US20230072729A1 - Method of manufacturing electronic device - Google Patents

Abstract

A method of manufacturing an electronic device includes providing a substrate, forming a solder on the substrate, and bonding a diode to the substrate through the solder, wherein the solder is formed by stacking a plurality of first conductive layers and a plurality of second conductive layers alternately, and the plurality of first conductive layers and the plurality of second conductive layers include different materials.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is a division of U.S. Application No. 16/860,040, filed on April 27th, 2020. The content of the application is incorporated herein by reference.
BACKGROUND OF THE DISCLOSURE1. Field of the Disclosure
• The present disclosure relates to an electronic device, more particularly to an electronic device in which the electronic component is bonded through the solder.
2. Description of the Prior Art
• The melting temperature or characteristics (including hardness) of the solder used in the bonding process of the electronic device may affect the yields of the device. Thus, improving the yields or reliability of the bonding process of the electronic device has become an important issue in this field.
SUMMARY OF THE DISCLOSURE
• A method of manufacturing an electronic device is provided in the present disclosure. The method of manufacturing an electronic device includes the following steps: providing a substrate, forming a solder on the substrate, and bonding a diode to the substrate through the solder. The solder is formed by stacking a plurality of first conductive layers and a plurality of second conductive layers alternately, and the plurality of first conductive layers and the plurality of second conductive layers include different materials.
• A method of manufacturing an electronic device is provided in the present disclosure. The method of manufacturing an electronic device includes the following steps: providing a diode, forming a solder on the diode, and bonding the diode to a substrate through the solder. The solder is formed by stacking a plurality of first conductive layers and a plurality of second conductive layers alternately, and the plurality of first conductive layers and the plurality of second conductive layers include different materials.
• These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG.1 schematically illustrates a side view of the electronic device before bonding according to the first embodiment of the present disclosure.
• FIG.2 schematically illustrates a side view of the electronic device after bonding according to the first embodiment of the present disclosure.
• FIG.3 schematically illustrates a side view of the electronic device before bonding according to the second embodiment of the present disclosure.
• FIG.4 schematically illustrates the solder before mixing according to the second embodiment of the present disclosure.
• FIG.5A schematically illustrates a side view of the electronic device after bonding according to the second embodiment of the present disclosure.
• FIG.5B schematically illustrates a side view of the electronic device after bonding according to the third embodiment of the present disclosure.
• FIG.6 schematically illustrates a side view of the electronic device before bonding according to the third embodiment of the present disclosure.
• FIG.7A schematically illustrates a side view of the electronic device measured by an energy dispersive spectrometer.
• FIG.7B schematically illustrates the analysis result of the solder alloy along the arrow shown inFIG.7A.
DETAILED DESCRIPTION
• The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings as described below. It is noted that, for purposes of illustrative clarity and being easily understood by the readers, various drawings of this disclosure show a portion of the electronic device, and certain elements in various drawings may not be drawn to scale. In addition, the number and dimension of each element shown in drawings are for illustrative and are not intended to limit the scope of the present disclosure.
• Certain terms are used throughout the description and following claims to refer to particular elements. As one skilled in the art will understand, electronic equipment manufacturers may refer to an element by different names. This document does not intend to distinguish between elements that differ in name but not function. In the following description and in the claims, the terms “include”, “comprise” and “have” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to...”.
• It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it may be directly on or directly connected to the other element or layer, or intervening elements or layers may be presented (indirectly). In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers presented.
• Although terms such as first, second, third, etc., may be used to describe diverse constituent elements, such constituent elements are not limited by the terms. The terms are used to discriminate a constituent element from other constituent elements in the specification. The claims may not use the same terms, but instead may use the terms first, second, third, etc. with respect to the order in which an element is claimed. Accordingly, in the following description, a first constituent element may be a second constituent element in a claim.
• It should be noted that the technical features in different embodiments described in the following can be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.
• The electronic device may include a substrate and electronic components disposed on the substrate. According to some embodiments, the electronic components may include light emitting elements, antenna, sensor, display element or other suitable electronic components, but not limited thereto.
• Referring toFIG.1 andFIG.2,FIG.1 schematically illustrates a side view of the electronic device before bonding according to the first embodiment of the present disclosure, andFIG.2 schematically illustrates a side view of the electronic device after bonding according to the first embodiment of the present disclosure. As shown inFIG.1, asubstrate102 and/or a light emitting diode (LED)104 are provided, and asolder112 is disposed on or form on thesubstrate102 and/or a light emitting diode (LED)104, and the light emitting diode may include quantum dot light emitting diode (QD-LED), micro light emitting diode (micro LED) or other suitable light emitting diodes, but not limited thereto. In some embodiments, a light converting material may be disposed on the light emitting diode, and the light converting material may include quantum dot (QD) material, fluorescence material, color filter (CF) material, phosphor material, other suitable light converting materials or the combinations of the above-mentioned materials, but not limited thereto. In some embodiments, the light converting material may cover the light emitting diode or be disposed corresponding to the light emitting diode. In some embodiments, thesubstrate102 may include rigid substrate, flexible substrate or the combinations of the above-mentioned substrate, but not limited thereto. In some embodiments, thesubstrate102 may include foldable substrate or deformable substrate such as plastic substrate, but not limited thereto. In some embodiments, the material of thesubstrate102 may include glass, quartz, organic polymer, metal, ceramic, other suitable materials or the combinations of the above-mentioned materials, but not limited thereto. If the material of thesubstrate102 includes organic polymer, the organic polymer may include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC) or the combinations of the above-mentioned materials, but not limited thereto.
• In some embodiments (as shown inFIG.1) , at least oneswitch element106 may be disposed on thesubstrate102, and thelight emitting diode104 may be electrically connected to theswitch element106, but not limited thereto. In some embodiments, thesubstrate102 is a thin film transistor substrate, theswitch element106 includes thin film transistor or other suitable components. In some embodiments (not shown), theswitch element106 and thelight emitting diode104 may be disposed on different surfaces of the substrate102 (such as opposite side surfaces), and thelight emitting diode104 may be electrically connected to theswitch element106. In some embodiments, other kinds of the electronic components (such as integrated circuit (IC), circuit, conductive pad or wire) may be disposed on thesubstrate102, but not limited thereto. In order to simplify or clarify the figures, some of the electronic components mentioned above or the protecting layer is omitted.
• In some embodiments, the electronic device may be an active matrix light emitting diode (AM-LED) or passive matrix light emitting diode (PM-LED). In some embodiments, asolder112 may be disposed on or formed on thesubstrate102, and thelight emitting diode104 bonded to thesubstrate102 through thesolder112. Thesolder112 may include metal, alloy, conductive materials or the combinations of the above-mentioned materials, but not limited thereto. For example, thesolder112 may include tin (Sn), indium (In), bismuth (Bi) or other suitable materials such as the alloy of tin and indium or the alloy of tin and bismuth, but not limited thereto. If the material of the solder only includes tin, higher temperature is needed during bonding process because the melting point of tin is higher (about 231.9° C.), the electronic component may be easily damaged or the reliability of the electronic component may be reduced. If the material of the solder only includes indium, although the melting point of indium is lower (about 157° C.) , the scratches may be easily produced because the hardness of indium is lower, abnormal situations may be occurred or the impedance may be increased during bonding process.
• In some embodiments of the present disclosure, thesolder112 may include tin and indium, such as the alloy or compound of tin and indium, but not limited thereto. In some embodiments, thesolder112 may include tin and metal element M, the metal element M is one of the indium and bismuth, and the atomic percentage of tin in thesolder112 ranges from 40% to 85%, which can reduce the melting point (about 120° C. to 200° C.) and increase the hardness of thesolder112, the possibility of damage or scratch of the electronic component may be reduced. For example, the atomic percentage of tin may be the atomic percentage of tin in the sum of tin and indium (Sn/ (Sn+In) ) when the metal element M in thesolder112 is indium, and the atomic percentage of tin may be designed to range from 40% to 85%.
• In another embodiment, the atomic percentage of tin may be the atomic percentage of tin in the sum of tin and bismuth (Sn/ (Sn+Bi) ) when the metal element M in thesolder112 is bismuth, and the atomic percentage of tin may be designed to range from 40% to 85%. In another embodiment, the atomic percentage of tin may be regarded as (Sn/(Sn+Bi)) or (Sn/(Sn+In)) when thesolder112 includes bismuth and indium, and the atomic percentage of tin may be in a range from 40% to 85%. In some embodiments, the atomic percentage of tin in thesolder112 may be in a range from 60% to 85%, that is, 60%≤ (Sn/ (Sn+In) )≤85% or 60%≤(Sn/ (Sn+Bi) )≤85%. In some embodiments, the atomic percentage of tin in thesolder112 may be in a range from 60% to 70%, that is, 60%≤(Sn/ (Sn+In) )≤70% or 60%≤ (Sn/ (Sn+Bi) )≤70%. In some embodiments, the atomic percentage of tin in thesolder112 may be in a range from 70% to 80%, that is, 70%≤ (Sn/ (Sn+In) )≤80% or 70%≤ ( Sn/ ( Sn+Bi ) ) ≤80%.
• In some embodiments, abonding layer110 may be disposed between thesubstrate102 and thesolder112. For example, thebonding layer110 may be an under bump metallurgy (UBM), but not limited thereto. In some embodiments, thebonding layer110 may be used to reduce diffusion of the material of thesolder112 to thesubstrate102, thebonding layer110 may be served as a barrier layer. In addition, thebonding layer110 may be used to increase the bonding strength or bonding adhesion between thesubstrate102 and thesolder112, that is, thebonding layer110 may be served as an adhesion layer. Moreover, thebonding layer110 may be used to reduce the impendence between the components or layers, such as the impendence between the conductive pad and thesolder112 on thesubstrate102, and the uniformity of current transfer may be improved, but not limited thereto. The material of thebonding layer110 may include titanium (Ti), platinum (Pt), nickel (Ni), tungsten (W), palladium (Pd), chromium (Cr), gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), oxides of the above-mentioned metals, transparent conductive oxides (such as indium tin oxide (ITO) or indium zinc oxide (IZO) ) or the combinations of the above-mentioned materials, but not limited thereto. In some embodiments, thebonding layer110 between thesubstrate102 and thesolder112 may be removed according to the demands.
• In some embodiments (as shown inFIG.1), a conductive structure108 may be disposed on thelight emitting diode104. In some embodiments, the material of the conductive structure108 may include gold, other suitable metals or the combinations of the above-mentioned materials, but not limited thereto. When the material of the conductive structure108 includes gold, for example, the conductive structure108 is a gold layer, bonding conditions may be enhanced because of the good corrosion resistance and a higher hardness of gold. In some embodiments, abonding layer114 may be disposed between thelight emitting diode104 and the conductive structure108. The material and/or function of thebonding layer114 may be the same or similar to thebonding layer110 mentioned above, but not limited thereto. In some embodiments, thebonding layer114 between thelight emitting diode104 and the conductive structure108 may be removed according to the demands.
• In some embodiments (not shown), the positions of the conductive structure108 and thesolder112 shown inFIG.1 may be exchanged, that is, the conductive structure108 may be disposed or formed on thesubstrate102 , and thesolder112 may be disposed or formed on thelight emitting diode104 . In details, thebonding layer110 and the conductive structure108 may be disposed on thesubstrate102 in sequence, thebonding layer114 and the conductive structure108 may be disposed on thelight emitting diode104 in sequence, and thelight emitting diode104 may be bonded to thesubstrate102 through thesolder112, but not limited thereto. Other suitable layers may be disposed between the above-mentioned components or layers according to the demands. In some embodiments, the bonding layer may be removed according to the demands.
• As shown inFIG.2, the conductive structure108 and thesolder112 may be mixed to form asolder alloy116 after the bonding process in some embodiments, and thesolder alloy116 may be an intermetallic compound (IMC), but not limited thereto. In some embodiments, thesolder alloy116 may be located between thebonding layer114 and thebonding layer110, thebonding layer110 is disposed between thesolder alloy116 and thesubstrate102 and/or thebonding layer116 is disposed between thesolder alloy116 and thelight emitting diode104, but not limited thereto. In some embodiments (not shown), when thebonding layer114 and thebonding layer110 are not included in the device, thesolder alloy116 may be located between thesubstrate102 and thelight emitting diode104. In details, the material of thesolder alloy116 may include the elements of the conductive structure108 and thesolder112. In some embodiments, thesolder alloy116 may include gold, tin, and a metal element M, and the metal element M may be one of the indium and bismuth, but not limited thereto. In thesolder alloy116, the atomic percentage of tin in the sum of tin and the metal element M is in a range from 60% to 90%. For example, when the metal element M is indium, the atomic percentage of tin in the sum of tin and indium (Sn/(Sn+In)) may be in a range from 60% to 90% or from 60% to 85% insolder alloy116, that is, 60%≤ (Sn/ (Sn+In) ) ≤90% or 60%≤ (Sn/ (Sn+In) )≤85%. In some embodiments, when the metal element M is bismuth, the atomic percentage of tin in the sum of tin and bismuth (Sn/(Sn+Bi)) may be in a range from 60% to 90% or from 60% to 80% in thesolder alloy116, that is, 60%≤(Sn/ (Sn+Bi) ) ≤90% or 60%≤(Sn/ (Sn+Bi))≤80%.
• The atomic percentage of the elements included in thesolder112 and/or thesolder alloy116 described in the present disclosure may be obtained by measurement and calculation conducted through energy dispersive spectrometer (EDS), X-ray analyzer or other suitable analyzers.
• Other embodiments of the present disclosure will be described in following paragraphs. In order to simplify the descriptions, the label of the same elements would be the same in the following description. In order to compare the differences between embodiments, the differences between different embodiments will be described in detail, and the repeated features will not be redundantly described.
• Referring toFIG.3,FIG.3 schematically illustrates a side view of the electronic device before bonding according to the second embodiment of the present disclosure. Different from the first embodiment (shown inFIG.1), thebonding layer114, theconductive structure1082, and thesolder1122 may be disposed or formed on thelight emitting diode104 in sequence, and thebonding layer110, theconductive structure1081, and thesolder1121 may be disposed or formed on thesubstrate102 in sequence in some embodiments (as shown inFIG.3), but not limited thereto. In some embodiments (as shown inFIG.3), theconductive structure1082 may be disposed between thesolder1122 and thelight emitting diode104, and theconductive structure1081 may be disposed between thesolder1121 and thesubstrate102, but not limited thereto. In some embodiments, when the conductive structure includes gold and is disposed between the solder and the bonding layer, the conductive structure may be used to increase the adhesion between the solder and the bonding layer. For example, theconductive structure1081 or theconductive structure1082 may be respectively used to increase the adhesion between thesolder1121, thesolder1122 and other components (such as thebonding layer110 and the bonding layer114), as shown inFIG.3.
• In some embodiments, the positions of theconductive structure1081 andsolder1121 shown inFIG.3 may be exchanged. In some embodiments, the positions of theconductive structure1082 andsolder1122 shown inFIG.3 may be exchanged. In some embodiments, thebonding layer114 and/or thebonding layer110 may be selectively removed. When theconductive structure1082 is disposed on the surface of thesolder1122 which is away from thelight emitting diode104 and the material of theconductive structure1082 includes gold, theconductive structure1082 may protect thesolder1122 or reduce the possibility of oxidation of thesolder1122. When theconductive structure1081 is disposed on the surface of thesolder1121 which is away from thesubstrate102 and the material of theconductive structure1081 includes gold, theconductive structure1081 may protect thesolder1121 or reduce the possibility of oxidation of thesolder1121.
• In some embodiments (as shown inFIG.3), the thickness of the conductive structure1081 (or the conductive structure1082) may be less than or equal to the thickness of the solder1121 (or the solder1122), but not limited thereto. It should be noted that, the thicknesses of the components (or layers) disposed on thesubstrate102 mentioned above or in the following description may be defined as the maximum thicknesses of the components (or layers) in a normal direction of thesubstrate102. Similarly, the thicknesses of the components (or layers) disposed on thelight emitting diode104 mentioned above or in the following description may be defined as the maximum thicknesses of the components (or layers) in a normal direction of thelight emitting diode104. The thicknesses of the above-mentioned components (or layers) may be measured through the picture of any cross-sectional view of the components or layers taken by the scanning electron microscope (SEM). For example, the layer A (analyte) is disposed between the layer B and the layer C, the picture taken by SEM should display at least a part of the layer A, at least a part of the layer B, and at least a part of the layer C, and the layer A having the entire thickness should be shown in the picture, and the maximum thickness of the layer A measured through the SEM picture may be regarded as the thickness of the layer A, but not limited thereto.
• In some embodiments (not shown), the solder1121 (as shown inFIG.3) formed in thesubstrate102 may be removed, that is, thebonding layer110 and theconductive structure1081 are formed or disposed on thesubstrate102 in sequence. In some embodiments (not shown), the solder1122 (as shown inFIG.3) formed on thelight emitting diode104 may be removed, thebonding layer114 and theconductive structure1082 are formed or disposed on thelight emitting diode104 in sequence.
• In some embodiments, thebonding layer110 and/or thebonding layer114 may be removed according to the demands. In some embodiments, one of thesolder1121 and theconductive structure1081 may be removed according to the demands. In some embodiments, one of thesolder1122 and theconductive structure1082 may be removed according to the demands.
• Referring toFIG.4,FIG.4 schematically illustrates the solder before mixing according to the second embodiment of the present disclosure. Different from the first embodiment, in some embodiments (shown inFIG.4),thesolder1121 and thesolder1122 may be a stacked layer formed of a plurality of firstconductive layers1181 and a plurality of secondconductive layers1182 which are alternately stacked. In other word, thesolder1121 or thesolder1122 is formed by stacking a plurality of firstconductive layers1181 and a plurality of secondconductive layers1182 alternately. The firstconductive layer1181 may include tin, and the secondconductive layer1182 may include indium, bismuth or other suitable materials, but not limited thereto. The firstconductive layers1181 and the secondconductive layers1182 include different materials. The alternately stacked firstconductive layers1181 and secondconductive layers1182 may form an alloy or compound (such as thesolder112 in the first embodiment) through the thermal bonding or annealing. In some embodiments, the thicknesses of different firstconductive layers1181 may be the same or different, and the thicknesses of different secondconductive layers1182 may be the same or different. The percentage of each of the elements in thesolder1121 and thesolder1122 may be adjusted by adjusting the number and/or the thicknesses of the firstconductive layers1181 and the number and/or the thicknesses of the secondconductive layers1182, but not limited thereto. In some embodiments, a firstconductive layer1181 and a secondconductive layer1182 may be stacked to form the solder, but not limited thereto.
• Referring toFIG.5A,FIG.5A schematically illustrates a side view of the electronic device after bonding according to the second embodiment of the present disclosure. Different from the first embodiment, at least a portion of the solder and at least a portion of the conductive structure (such as gold layer or the conductive layer including gold, but not limited thereto) may be mixed to form the solder alloy in some embodiments (as shown inFIG.5A) , that is, thesolder alloy116 may include gold, and the alloy having the atomic percentage of tin in the sum of tin and the metal element M in a range from 60% to 90% is defined as thesolder alloy116. In some embodiments, a portion of the solder which does not form thesolder alloy116 is alayer1201, a portion of the conductive structure which does not form thesolder alloy116 is a first layer1202 (such as gold layer or the layer including gold, but not limited thereto), and the thicknesses (and materials) of thelayer1201 and the thicknesses (and materials) thefirst layer1202 may be the same or different, but not limited thereto. In some embodiments (shown inFIG.5A) , thelayer1201 and thefirst layer1202 may be respectively located at two opposite sides of thesolder alloy116, which is shown in the left part of the stacked structure. In some embodiments (not shown) , thefirst layer1202 may be disposed between thesolder alloy116 and thesubstrate102, and thelayer1201 may be disposed between thesolder alloy116 and thelight emitting diode104, but not limited thereto. In some embodiments, the positions of thelayer1201 and thefirst layer1202 may be exchanged. In some embodiments (shown inFIG.5A), the first layers1202 (such as gold layers or the conductive layers including gold, but not limited thereto) may be located at two opposite sides of thesolder alloy116, which is shown in the right part of the stacked structure. For example, thefirst layer1202 may be disposed between thesolder alloy116 and thesubstrate102, anotherfirst layer1202 may be dispose between thesolder layer116 and thelight emitting diode104, and the materials and thicknesses of thesefirst layers1202 may be the same or different. In some embodiment (not shown), thelayers1201 may be disposed at two opposite sides of thesolder alloy116. For example, one of thelayers1201 may be disposed between thesolder alloy116 and thesubstrate102, the other one of thelayers1201 may be dispose between thesolder layer116 and thelight emitting diode104, and the materials and thicknesses of theselayers1201 may be the same or different. It should be noted that, the stacked structure in the left part and the stacked structure in the right part inFIG.5A are only illustrative in order to clarify different stacked conditions, and the stacked structure in the left part is not limited to be different from the stacked structure in the right part. In some embodiments, the stacked structure in the left part and the stacked structure in the right part may be the same.
• Referring toFIG.5B,FIG.5B schematically illustrates a side view of the electronic device after bonding according to the third embodiment of the present disclosure. Different from the first embodiment, theelectronic device10 may includelayer1201, but theelectronic device10 does not includefirst layers1202 after bonding in some embodiments (as shown inFIG.5B) . For example, theelectronic device10 may includelayer1201, and thelayer1201 may be disposed between thesolder alloy116 and thesubstrate102, or thelayer1201 may be disposed between thesolder alloy116 and thelight emitting diode104. In some embodiments (not shown), the electronic device may include thefirst layer1202, but the electronic device does not include thelayer1201, and the first layer1202 (such as gold layer or the layer including gold) may be disposed between thesolder alloy116 and thelight emitting diode104, or the first layer1202 (such as gold layer or the layer including gold) may be disposed between thesolder alloy116 and thesubstrate102. In some embodiments (not shown), the number of thelayer1201 may be greater than or equal to 1, the number of thefirst layer1202 may be greater than or equal to 1, and/or the number of thesolder alloy116 may be greater than or equal to 1, but not limited thereto. The relative positions of thelayer1201, thefirst layer1202, and thesolder alloy116 may be adjusted according to the bonding condition, and the present disclosure is not limited thereto.
• Referring toFIG.6,FIG.6 schematically illustrates a side view of the electronic device before bonding according to the third embodiment of the present disclosure. Different from the first embodiment, in some embodiments (as shown inFIG.6) thebonding layer114, theconductive structure1082, thesolder1122, and theconductive structure1084 may be formed or disposed on thelight emitting diode104 in sequence, and thebonding layer110, theconductive structure1081, thesolder1121 and the conductive structure1083 may be formed or disposed on thesubstrate102 in sequence, but not limited thereto. Other suitable layers (such as other conductive structures or other solders, but not limited thereto) may be intervened or added between the above-mentioned component or layers according to the demands, or the bonding layers or the metal layers may be removed according to the demands. In some embodiments (as shown inFIG.6), the thicknesses of theconductive structure1081, theconductive structure1082, the conductive structure1083, and/or theconductive structure1084 may be less than or equal to the thicknesses of thesolder1121, thesolder1122, thebonding layer110, and/or thebonding layer114, but not limited thereto. In some embodiments, the thicknesses of theconductive structure1081, theconductive structure1082, the conductive structure1083 and/or theconductive structure1084 may be the same or different. In some embodiments, the materials of theconductive structure1081, theconductive structure1082, the conductive structure1083, and/or theconductive structure1084 may be the same or different.
• According to the above-mentioned contents, in an embodiment of the present disclosure, the method of manufacturing an electronic device may include providing a substrate (such as the substrate102) , forming the solder (such as the solder1121) on the substrate, and bonding the light emitting diode (such as the light emitting diode104) to the substrate through the solder. The solder is formed by stacking a plurality of firstconductive layers1181 and a plurality of secondconductive layers1182 alternately, and as mentioned above, the plurality of firstconductive layers1181 and the plurality of secondconductive layers1182 include different materials.
• In another embodiment, the method of manufacturing an electronic device may include providing a light emitting diode (such as the light emitting diode104), forming the solder (such as the solder1122) on the light emitting diode, and bonding the substrate (such as the substrate102) to the light emitting diode through the solder. The solder is formed by stacking a plurality of firstconductive layers1181 and a plurality of secondconductive layers1182 alternately, and the firstconductive layers1181 and the secondconductive layers1182 include different materials.
• Referring toFIG.7A andFIG.7B,FIG.7A schematically illustrates a side view of the electronic device measured by an energy dispersive spectrometer,FIG.7B schematically illustrates the analysis result of the solder alloy along the arrow shown inFIG.7A. The measurement may be conducted along the direction of the arrow shown inFIG.7A, but not limited thereto. The location and direction of the measurement may be adjusted according to the demands.FIG.7B schematically illustrates a relation chart between the intensity (counts per second, cps) and the distance (µm) measured by EDS. In some embodiments (as shown inFIG.7A) , the measurement is performed from the layer (or component) nearest to the light emitting diode104 (such as the bonding layer114) to the layer (or component) nearest to the substrate102 (such as the bonding layer110). For example, the content or percentage of each of the elements in thebonding layer114, thefirst layer1202, thesolder alloy116, thelayer1201 and thebonding layer110 are measured in sequence to obtain the relation chart between the intensity (counts per second, cps) and the distance (shown inFIG.7B) . The alloy having the atomic percentage of tin in the sum of tin and the metal element M (such as one of indium and bismuth) ranging from 60% to 90% is defined as thesolder alloy116. For example, the line116-c1 and the line116-c2 inFIG.7B may be used to define the region of thesolder alloy116. In addition, although the present disclosure only illustrates one calculation method of the atomic percentage of tin in the sum of tin and metal element M, it is not limited thereto. For example(shown inFIG.7B), the calculation is performed on thesolder alloy116 in which the distance is 3 micrometers (µm), the intensity (counts per second, cps) of tin in this position is about 95, the intensity (counts per second, cps) of indium in this position is about 30, and the result of the atomic percentage of tin in the sum of tin and indium may be obtained after substituting the values into the equation, which is 76%, such as ( (Sn/ (Sn+In)=95/ (95+30)=0.76=76%) . In some embodiments, the compartment line between different layers may be defined by the intersection of the curves of two different elements, but not limited thereto. For example, as shown inFIG.7B, a line1202-c may be drawn through the intersection of the curves of two elements (such as nickel and tin), and a line1201-c may be drawn through the intersection of the curves of two elements (such as nickel and gold). The region between the line1202-c and the line116-c1 may be thefirst layer1202, the region between the line1201-c and the line116-c2 may be thelayer1201, another part (the part different from the first layer1202) using the line1202-c as the compartment line may represent thebonding layer114, and another part (the part different from the layer1201) using the line1201-c as the compartment line may represent thebonding layer110, but not limited thereto. In some embodiments, the comparison may be performed according to the materials of the bonding layers, the conductive structures, and the solder combined with the result of analysis, and the regions of thesolder alloy116, thelayer1201, thefirst layer1202, thebonding layer110, and/or thebonding layer114 may be defined by the above-mentioned method, but not limited thereto.
• In some embodiments (referring toFIG.7B), when the material of thebonding layer114 includes titanium and nickel, and the material of the solder includes tin and indium, the line1202-c may be drawn through the intersection of the curves of nickel and tin, but not limited thereto. In some embodiments (referring toFIG.7B), when the material of thebonding layer110 includes titanium and nickel, and the material of the conductive structure includes gold, the line1201-c may be drawn through the intersection of the curves of nickel and gold, but not limited thereto.
• It should be noted that the measuring method in the present disclosure is not limited to be performed along the direction of the arrow shown inFIG.7A. In some embodiments (not shown), the measurement may be performed from the layers (or components) nearest to thesubstrate102 to the layers (or components) nearest to the light emitting diode104 (such as the bonding layer114), or the measurement may be performed at any random position. It should be noted that, the corresponding distance of each of the layers shown inFIG.7B is only illustrative. In some embodiments, the thickness of thebonding layer110 or thebonding layer114 may be greater than the thicknesses of thesolder alloy116, thelayer1201, and/or thefirst layer1202. It should be noted that,FIG.7B only illustrates one of the possible results, and the percentage of the elements in different layers may be different according to the number, thickness, material, or bonding temperature of the bonding layer, the metal layer, and the solder, but not limited thereto. Similarly, the percentage of the elements in each of the layers (not limited to before bonding or after bonding) according to the embodiments may be analyzed by the similar way.
• In summary, the solder of the electronic device of the present disclosure may include alloy or compound which includes tin and indium (or tin and bismuth). The solder may be applied to the lower-temperature bonding process to reduce the possibility of damage of electronic components or increase hardness of the solder in order to reduce scratches because the melting point of the solder may be reduced, thereby improving the yields or reliability of the electronic device. In addition, the solder alloy may include tin and metal element M after bonding, the metal element M may be one of the indium and bismuth, and the atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.
• Although the embodiments and the advantages thereof are described above, it should be noted that any one skilled in the art can change, replace and modify the features of the present disclosure without departing from the spirit of the present disclosure. In addition, the scope of the present disclosure is not limited to the processes, equipment, fabrication, composition, device, methods, and steps described in the specification, and any one skilled in the art can realize the processes, equipment, fabrication, composition, device, methods, and steps in the present or the future from the present disclosure. As long as it can implement approximately the same function or obtain approximately the same result in the embodiments of the present disclosure, it can be applied according to the present disclosure.
• Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (10)

What is claimed is:

1. A method of manufacturing an electronic device, comprising:

providing a substrate;

forming a solder on the substrate; and

bonding a diode to the substrate through the solder;

wherein the solder is formed by stacking a plurality of first conductive layers and a plurality of second conductive layers alternately; and

wherein the plurality of first conductive layers and the plurality of second conductive layers include different materials.

2. The method of manufacturing an electronic device ofclaim 1, comprising:

forming a conductive structure on the substrate, wherein the conductive structure and the solder are mixed to form a solder alloy after a bonding process.

3. The method of manufacturing an electronic device ofclaim 2, wherein the solder alloy includes gold, tin and a metal element M.

4. The method of manufacturing an electronic device ofclaim 3, wherein the metal element M is indium or bismuth, and an atomic percentage of tin in sum of the tin and the metal element M is in a range from 60% to 90% in the solder alloy.

5. The method of manufacturing an electronic device ofclaim 2, wherein a portion of the solder does not form the solder alloy, and a portion of the conductive structure does not form the solder alloy.

6. The method of manufacturing an electronic device ofclaim 5, wherein the portion of the solder not forming the solder alloy is a layer, the portion of the conductive structure not forming the solder alloy is a first layer, and a thickness of the layer and a thickness of the first layer are different.

7. A method of manufacturing an electronic device, comprising:

providing a diode;

forming a solder on the diode; and

bonding the diode to a substrate through the solder;

wherein the solder is formed by stacking a plurality of first conductive layers and a plurality of second conductive layers alternately; and

wherein the plurality of first conductive layers and the plurality of second conductive layers include different materials.

8. The method of manufacturing an electronic device ofclaim 7, comprising:

forming a conductive structure on the substrate, wherein the conductive structure and the solder are mixed to form a solder alloy after a bonding process.

9. The method of manufacturing an electronic device ofclaim 8, wherein the solder alloy includes gold, tin and a metal element M.

10. The method of manufacturing an electronic device ofclaim 9, wherein the metal element M is indium or bismuth, and an atomic percentage of tin in sum of the tin and the metal element M is in a range from 60% to 90% in the solder alloy.

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