US20220271014A1

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Info

Publication number: US20220271014A1
Application number: US17/742,371
Authority: US
Inventors: Ying-Ju Chen; Hsien-Wei Chen; Ming-Fa Chen
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-03-26
Filing date: 2022-05-11
Publication date: 2022-08-25
Also published as: US20240379627A1; US11362066B2; US20210305209A1

Abstract

A semiconductor structure includes a bottom die, a top die bonded to the bottom die, an insulating layer disposed on the bottom die and laterally covering the top die, a first dual-damascene connector overlying the insulating layer and the top die. The bottom die is wider than the top die, and a bonding interface of the top and bottom dies is substantially flat. The first dual-damascene connector is inserted into the insulating layer to be in electrical and physical contact with the bottom die.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/831,776, filed on Mar. 26, 2020. The entirety of each of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area. Technological advances in integrated circuit (IC) design have produced generations of ICs where each generation has smaller and more complex circuit designs than the previous generation. There is continuous effort in developing new mechanisms of forming semiconductor structures having improved electrical performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A-1G are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments.

FIGS. 2A-2E are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments.

FIGS. 3A-3D are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments.

FIGS. 4A-4C are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments.

FIG. 5 is a schematic cross-sectional view showing an application of a semiconductor structure according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS. 1A-1G are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments. Referring toFIG. 1A, a semiconductor die120D is disposed on asemiconductor wafer110W. Thesemiconductor wafer110W may include different die regions that may be singulated in subsequent steps to form a plurality of semiconductor dies (e.g., first semiconductor die110 shown inFIG. 1G). Although only one die region is shown, it should be appreciated that multiple dies may be formed in thesemiconductor wafer110W, with each die region used to form one first semiconductor die110.

In some embodiments, thesemiconductor wafer110W includes afirst semiconductor substrate112, which may include a semiconductor material such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Thefirst semiconductor substrate112 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may be used.

Thefirst semiconductor substrate112 may have anactive surface112aand arear surface112bopposite to each other. A plurality offirst semiconductor devices113 may be formed in and/or on theactive surface112aof thefirst semiconductor substrate112. For example, thefirst semiconductor devices113 includes active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.), or other suitable electrical devices. Thesemiconductor wafer110W may include afirst interconnect structure114 formed over thefirst semiconductor substrate112 and thefirst semiconductor devices113. For example, thefirst interconnect structure114 include one or more dielectric layer(s)1141 and respective metallization pattern(s)1142 (e.g., metal lines, vias, pads, etc.). Themetallization patterns1142 may be embedded in the dielectric layers1141 and electrically coupled to thefirst semiconductor devices113. Thefirst semiconductor devices113 and themetallization patterns1142 may be interconnected to perform one or more functions including memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. For example, thesemiconductor wafer110W may include logic circuits, processing circuits, control circuits, I/O circuits, memory circuits, bias circuits, testing circuits, reference circuits, and/or the like.

The dielectric layer1141 of thefirst interconnect structure114 may be the inter-metallization dielectric (IMD) layer and may be formed of a dielectric material such as undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO_xC_y, spin-on-glass, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, compounds thereof, composites thereof, combinations thereof, and/or the like. Themetallization pattern1142 may route electrical signals between thefirst semiconductor devices113 by using vias and/or lines. The material of themetallization patterns1142 may be or may include tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. In some embodiments, thesemiconductor wafer110W is free of through substrate via (TSV). In alternative embodiments, thesemiconductor wafer110W includes at least one TSV that may penetrate through thefirst semiconductor substrate112 and further extend to thefirst interconnect structure114.

Thesemiconductor wafer110W may include a first inter-dielectric layer115 formed over thefirst interconnect structure114. The material of the first inter-dielectric layer115 may be made of the material same as or similar to that of the dielectric layer1141. In some embodiments, thesemiconductor wafer110W includes a plurality of first bonding vias116 penetrating through the first inter-dielectric layer115 to be in physical and electrical contact with themetallization patterns1142 of thefirst interconnect structure114. In some embodiments, thesemiconductor wafer110W includes at least one firstconductive pad117 formed over thefirst interconnect structure114 and embedded in the first inter-dielectric layer115. It is appreciated that only onepad117 is shown inFIG. 1A, but more than one firstconductive pad117 may be present. The material of the firstconductive pad117 may include aluminum, but other suitable conductive material (e.g., copper) may be used. In some embodiments, the firstconductive pad117 is the test pad for electrical testing. The electrical testing may include testing of the functionality of the various semiconductor devices, or testing for open or short circuits that may be expected based on the design. The firstconductive pad117 formed on themetallization patterns1142 and covered by the first inter-dielectric layer115 may be electrically floating in thesemiconductor wafer110W.

Thesemiconductor wafer110W may include afirst bonding structure118 formed over the first inter-dielectric layer115 and the first bonding vias116. For example, thefirst bonding structure118 includes abonding dielectric layer1181. A material of thebonding dielectric layer1181 may be or may include silicon oxide (e.g., TEOS formed oxide), silicon nitride, silicon oxynitride, or the like. The materials of thebonding dielectric layer1181 and the underlying first inter-dielectric layer115 may be the same or similar. In alternative embodiments, the materials of thebonding dielectric layer1181 and the underlying first inter-dielectric layer115 are different. Thefirst bonding structure118 may include a plurality offirst bonding pads1182 distributed within a die attaching region DR and at least onesecond bonding pad1183 located within a peripheral region PR connected to the die attaching region DR. Thefirst bonding pads1182 and thesecond bonding pad1183 may be electrically coupled to thefirst semiconductor devices113 through themetallization patterns1142 of thefirst interconnect structure114 and the first bonding vias116.

For example, at least one of thefirst bonding pads1182 is disposed on the bonding via116 in the die attaching region DR, and may be in physical and electrical contact with the bonding via116. Thesecond bonding pad1183 may be disposed on another bonding via116 in the peripheral region PR, and may be in physical and electrical contact with the bonding via116. It is appreciated that a singlesecond bonding pad1183 is shown inFIG. 1A, but more than one second bonding pad(s)1183 may be present. Thefirst bonding pads1182 may be formed of a metal that facilitates hybrid bonding, such as copper, a copper alloy, or other suitable conductive material. Thesecond bonding pad1183 may be made of the material same as or similar to that of thefirst bonding pads1182. In some embodiments, therespective bonding pad1182 and the underlying bonding via116 are collectively viewed as a bonding connector of thesemiconductor wafer110. Thefirst bonding pads1182 and thesecond bonding pad1183 may be laterally covered by thebonding dielectric layer1181. In some embodiments, thetop surfaces1182aof thefirst bonding pads1182 and thetop surface1183aof thesecond bonding pad1183 are substantially leveled with atop surface1181aof thebonding dielectric layer1181. In some embodiments, the top surface of thefirst bonding structure118 in the die attaching region DR including the

top surfaces

1181aand1182amay be viewed as abonding surface118afor the subsequent die bonding process. It is appreciated that the aforementioned examples are provided for illustrative purposes, and other elements may be used as appropriate for a given application.

Continue toFIG. 1A, the semiconductor die120D may be formed in a semiconductor wafer (not shown), which may include different die regions that are singulated to form a plurality of the semiconductor dies120D. The semiconductor die120D may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. The semiconductor die120D may perform the same function as or a different function than thesemiconductor wafer110W.

The semiconductor die120D may include asecond semiconductor substrate122 having anactive surface122aand arear surface122bopposite to each other. For example, thesecond semiconductor substrate122 is made of the material same as or similar to the material of thefirst semiconductor substrate112. The semiconductor die120D may includesecond semiconductor devices123, such as transistors, capacitors, resistors, diodes, and the like. Thesecond semiconductor devices123 may be formed in and/or on theactive surface122aof thesecond semiconductor substrate122. The semiconductor die120D may include asecond interconnect structure124 formed over theactive surface122aof thesecond semiconductor substrate122. For example, thesecond interconnect structure124 includes one or more dielectric layer(s)1241 andrespective metallization patterns1242 embedded in thedielectric layer1241. Themetallization patterns1242 may be electrically coupled to thesemiconductor devices123. In some embodiments, themetallization patterns1242 is viewed as an interconnecting circuitry of thesemiconductor die120D. The materials of thedielectric layer1241 and themetallization patterns1242 of thesecond interconnect structure124 may be the same as or similar to those of the dielectric layer1141 and themetallization patterns1142 of thefirst interconnect structure114.

The semiconductor die120D may include a secondinter-dielectric layer125 formed over thesecond interconnect structure124. The secondinter-dielectric layer125 may be made of the material same as or similar to that of the first inter-dielectric layer115. In some embodiments, the semiconductor die120D includes at least one second bonding via126 penetrating through the secondinter-dielectric layer125 to be in physical and electrical contact with themetallization patterns1242 of thesecond interconnect structure124. In some embodiments, the semiconductor die120D includes at least one secondconductive pad127 formed over thesecond interconnect structure124 and embedded in the secondinter-dielectric layer125. Although a single secondconductive pad127 is shown inFIG. 1A, multiple secondconductive pads117 may be present. The secondconductive pad127 may be similar to the firstconductive pad117. In some embodiments, the secondconductive pad127 is the test pad which allows electrical testing. The secondconductive pad127 may be formed on themetallization patterns1242, but electrically floating in thesemiconductor die120D.

The semiconductor die120D may include asecond bonding structure128 formed over the secondinter-dielectric layer125 and the second bonding via126. For example, thesecond bonding structure128 includes abonding dielectric layer1281 and a plurality ofbonding pads1282 covered by thebonding dielectric layer1281. In some embodiments,top surfaces1282aof thebonding pads1282 are substantially leveled with atop surface1281aof thebonding dielectric layer1281. Thetop surfaces1282aof thebonding pads1282 and thetop surface1281aof thebonding dielectric layer1281 may be viewed as abonding surface128aof thesecond bonding structure128. In some embodiments, at least one of thebonding pads1282 is in physical and electrical contact with the second bonding via126. The second bonding via126 and theoverlying bonding pad1282 may be collectively viewed as a bonding connector. The bonding connector may be electrically coupled to thesecond semiconductor devices123 through themetallization patterns1242 of thesecond interconnect structure124.

The semiconductor die120D may include at least oneTSV129 formed to connect themetallization patterns1242 and extend into thesecond semiconductor substrate122 from theactive surface122aof thesecond semiconductor substrate122. OneTSV129 is shown inFIG. 1A, but more than oneTSV129 may be present. In some embodiments, theTSV129 includes aconductive material129cwith a barrier layer129binterposed between theconductive material129cand thesecond semiconductor substrate122. Examples of the conductive material of theTSV129 include copper, tungsten, aluminum, silver, gold, a combination thereof, and/or the like, and examples of the material of the barrier layer of theTSV129 include an oxide, a nitride, or an oxynitride, a combination thereof, and/or the like. In some embodiments, theTSV129 is buried in thesecond semiconductor substrate122 and does not extend to therear surface122bof thesecond semiconductor substrate122 at this stage.

Still referring toFIG. 1A, the semiconductor die120D and thesemiconductor wafer110W may be separately fabricated, and then the semiconductor die120D may be positioned at the die attaching region DR of thesemiconductor wafer110W. Next, a bonding process may be performed on the semiconductor die120D and thesemiconductor wafer110W. For example, the semiconductor die120D and thesemiconductor wafer110W may be coupled in a face-to-face manner. For example, theactive surface122aof the semiconductor die120D faces theactive surface112aof thesemiconductor wafer110W, and thesecond bonding structure128 of the semiconductor die120D is boned to thefirst bonding structure118 of thesemiconductor wafer110W. The bonding process may include dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), any combinations thereof, and/or the like. In some embodiments, the semiconductor die120D and thesemiconductor wafer110W are bonded through a hybrid bonding process.

For example, to facilitate hybrid bonding, surface preparation for bonding surfaces (e.g., thebonding surface118aof thesemiconductor wafer110W and thebonding surface128aof the semiconductor die120D) is performed to remove particles thereon. The surface preparation may include surface cleaning and activation or other suitable process. In some embodiments, thetop surfaces1182aof thefirst bonding pads1182 and thetop surfaces1282aof thebonding pads1282 may be cleaned by wet cleaning before performing the bonding. For example, not only particles are removed, but also native oxide formed on thetop surfaces1182aof thefirst bonding pads1182 and thetop surfaces1282aof thebonding pads1282 are removed by chemicals used in the wet cleaning. After cleaning, activation of thetop surface1281aof thebonding dielectric layer1281 and at least a portion of thetop surface1181aof thebonding dielectric layer1181 corresponding to the die attaching region DR may be performed for development of high bonding strength. For example, plasma activation is performed to treat thetop surface1281aof thebonding dielectric layer1281 and thetop surface1181aof thebonding dielectric layer1181.

In some embodiments, the semiconductor die120D is aligned with thesemiconductor wafer110W and sub-micron alignment precision may be achieved. For example, eachbonding pad1282 of the semiconductor die120D may be substantially aligned with the correspondingfirst bonding pad1182 in the die attaching region DR of thesemiconductor wafer110W. Once the semiconductor die120D and thesemiconductor wafer110W are aligned precisely, the semiconductor die120D and thesemiconductor wafer110W may be placed on and in contact with one another. When the activatedtop surface1281aof thebonding dielectric layer1281 is in contact with the activatedtop surface1181aof thebonding dielectric layer1181, thebonding dielectric layer1281 of the semiconductor die120D and thebonding dielectric layer1181 of thesemiconductor wafer110W may be pre-bonded. For example, the semiconductor die120D and thesemiconductor wafer110W are pre-bonded through the pre-bonding of thebonding dielectric layer1181 and thebonding dielectric layer1281. After pre-bonding, thebonding pads1282 may respectively correspond to and may be in physical contact with thefirst bonding pads1182.

Referring toFIG. 1B and also with reference toFIG. 1A, an insulatingmaterial layer130A is formed on thesemiconductor wafer110W, and then the semiconductor die120D is thinned to accessibly reveal theTSV129. For example, an insulating material is formed on thesemiconductor wafer110W corresponding to the peripheral region PR to cover thesemiconductor die120D. The insulating material may be in physical contact with thetop surface1183aof thesecond bonding pad1183 and thetop surface1181aof thebonding dielectric layer1181 in the peripheral region PR. In some embodiments, the insulating material, when initially formed, may cover therear surface122bof thesecond semiconductor substrate122. The insulating material may be or may include silicon oxide, silicon nitride, tetraethoxysilane (TEOS), and/or the like. In some embodiments, the insulating material is formed through chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), or other suitable process.

In some embodiments, a plurality of the semiconductor dies120D are disposed side by side in an array on thesemiconductor wafer110W, and a gap (not shown) may be formed between neighboring semiconductor dies120D. The insulating material may be formed in the gap between the neighboring semiconductor dies120D. In some embodiments, the insulating material is referred to as “gap fill oxide”. In some other embodiments, the insulating material includes a molding compound, a molding underfill, a resin (such as epoxy), polymer, or the like. Other suitable insulating material that can provide a degree of protection for the second semiconductor die120 may be used.

Subsequently, a planarization process (e.g., chemical-mechanical polishing (CMP)) may be performed on the insulating material and the semiconductor die120D to form the insulatingmaterial layer130A and the second semiconductor die120, respectively. For example, after the planarization, the insulatingmaterial layer130A extends along thesidewalls120sof the second semiconductor die120. Thetop surface130tof the insulatingmaterial layer130A may be substantially leveled with therear surface122b′ of thesecond semiconductor substrate122′. After the planarization, theTSV129 may extend through thesecond semiconductor substrate122′ and may be accessibly revealed at therear surface122b′ of thesecond semiconductor substrate122′. In some embodiments, the exposedsurface129aof theTSV129 is substantially leveled with thetop surface130tof the insulatingmaterial layer130A.

In some embodiments, after the planarization process, a portion of theconductive material129cand a portion of the barrier layer129bare removed, so that theconductive material129claterally covered by the barrier layer129bis accessibly revealed. Thesecond semiconductor substrate122′ may be then slightly etched, so that a portion of theTSV129 may be protruded from therear surface122b′. Subsequently, an isolating liner IL is formed on therear surface122b′ of thesecond semiconductor substrate122′ to laterally cover the portion of theTSV129 that is protruded from therear surface122b′. In some embodiments, thetop surface130tof the insulatingmaterial layer130A may be substantially leveled with the top surface of the isolating liner IL. The isolating liner IL may separate thesecond semiconductor substrate122′ from the subsequently formed metal layer (e.g., the second die connector154). The material of the isolating liner IL may be or may include silicon nitride, an oxide, silicon oxynitride, silicon carbide, a polymer, the like, etc.

Referring toFIG. 1C, adielectric material layer140A is formed on the insulatingmaterial layer130A and the second semiconductor die120. For example, thedielectric material layer140A is in physical contact with the isolating liner IL, the exposedsurface129aof theTSV129, and thetop surface130tof the insulatingmaterial layer130A. The isolating liner IL may be interposed between thesecond semiconductor substrate122′ and the overlyingdielectric material layer140A. Thedielectric material layer140A may be formed of undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), TEOS, compounds thereof, composites thereof, combinations thereof, or the like. In some embodiments, thedielectric material layer140A and the underlying insulatingmaterial layer130A are formed of different materials. For example, thedielectric material layer140A has an etch selectivity different than that of the underlying insulatingmaterial layer130A. Thedielectric material layer140A may be formed by any suitable method such as spin-coating, CVD, PECVD, HDP-CVD, ALD, or the like.

Referring toFIG. 1D, a portion of thedielectric material layer140A and a portion of the insulatingmaterial layer130A may be removed to form thedielectric layer140 and the insulatinglayer130, respectively. For example, thedielectric layer140 includes a first trench TR1 and a second trench TR2. The first trench TR1 may accessibly expose at least a portion of thetop surface130tof the underlying insulatinglayer130 corresponding to the peripheral region PR of thesemiconductor wafer110W. In some embodiments, the first trench TR1 laterally extends to expose at least a portion of thesecond semiconductor substrate122′ corresponding to the die attaching region DR of thesemiconductor wafer110W. In some embodiments in which the isolating liner IL is formed on therear surface122b′ of thesecond semiconductor substrate122′, the first trench TR1 accessibly exposes thetop surface130tof the insulatinglayer130 and extends to reveal the top surface of the isolating liner IL. In some other embodiments, the first trench TR1 exposes at least a portion of another TSV (not shown) of the second semiconductor die120. In other embodiments, the first trench TR1 does not extend to expose the second semiconductor die120.

The second trench TR2 of thedielectric layer140 may accessibly reveal at least a portion of the exposedsurface129aof theTSV129. In some embodiments, the second trench TR2 is wide enough to expose the exposedsurface129aof theTSV129 and a portion of the isolating liner IL surrounding theTSV129. In some embodiments, the second trench TR2 further extends to expose at least a portion of thetop surface130tof the insulatinglayer130 corresponding to the peripheral region PR. It is noted that the widths of the first trench TR1 and the second trench TR2 of thedielectric layer140 may depend on the design requirements and construe no limitation in the disclosure. It is also appreciated that one first trench TR1 and one second trench TR2 are shown inFIG. 1D, but more than one first trench TR1 and/or more than one second trench TR2 may be present.

Continue toFIG. 1D, the insulatinglayer130 may have at least one first via opening OP1 in communication with the first trench TR1 of thedielectric layer140. For example, the first via opening OP1 accessibly exposes at least a portion of thetop surface1183aof thesecond bonding pad1183 of thesemiconductor wafer110W for further electrical connection. One via opening is shown inFIG. 1D, but more than one first via opening OP1 may be present. In some embodiments, the width (or diameter) W1 of the first via opening OP1 is smaller than the width (or diameter) of the corresponding first trench TR1. In some embodiments, the width W1 of the first via opening OP1 ranges from about 2 μm to about 5 μm. For example, the width W1 of the first via opening OP1 is less than the width (or diameter)1183wof thesecond bonding pad1183. Thewidth1183wof thesecond bonding pad1183 may be substantially equal to or less than that of the first trench TR1. Alternatively, thewidth1183wof thesecond bonding pad1183 is greater than that of the first trench TR1. In some embodiments, thewidth1183wof thesecond bonding pad1183 ranges from about 2 μm to about 5 μm. In some embodiments, a difference is between thewidth1183wof thesecond bonding pad1183 and the width W1 of the first via opening OP1. The difference of the widths (1183wand W1) is, for example, about 0.5 μm. Alternatively, the difference of the widths (1183wand W1) may be greater than or less than 0.5 μm. In some embodiments, an aspect ratio of the depth D1 over the width W1 is less than or substantially equal to 15. For example, the aspect ratio (D1/W1) ranges from about 1 to about 15.

Still referring toFIG. 1D, the removal of the portion of thedielectric material layer140A and the portion of the insulatingmaterial layer130A may be performed by lithography and etching or other suitable methods. For example, the first trench TR1 and the second trench TR2 of thedielectric layer140 are formed by photoresist patterning and by etching the patterns into thedielectric material layer140A. In some embodiments, the insulatingmaterial layer130A serves as an etch stop layer when patterning thedielectric material layer140A. Subsequently, the first via opening OP1 of the insulatinglayer130 is formed by via resist patterning and etching through the insulatingmaterial layer130A. In some embodiments, the etching is performed using thesecond bonding pad1183 as the etch stop layer. The first trench TR1, the second trench TR2, and the first via opening OP1 may be formed during the same step. It is appreciated that etch stop layer(s) (not shown) may be disposed between thedielectric material layer140A and the insulatingmaterial layer130A and/or between the insulatingmaterial layer130A and thesemiconductor wafer110W. The etch stop layer may have a high etching selectivity relative to the overlying layer (e.g., thedielectric material layer140A and/or the insulatingmaterial layer130A). In some embodiments, the etch stop layer is formed of silicon nitride, silicon carbon nitride, silicon carbo-oxide, combinations thereof, or the like.

In some embodiments, the etching process includes an anisotropic dry etch. The type of etchant applied for etching the first trench TR1, the second trench TR2, and the first via opening OP1 may be determined by the processing and functional application. A wet clean process is optionally performed after the etching process. In some embodiments,inner sidewalls130sof the insulatinglayer130 that define the first via opening OP1 are substantially vertical. For example, theinner sidewalls130sof the insulatinglayer130 are substantially perpendicular to thetop surface1183aof thesecond bonding pad1183. In some embodiments, thedielectric layer140 may haveinner sidewalls140sthat define the first trench TR1 and the second trench TR2. For example, theinner sidewalls140sare substantially vertical and may be substantially perpendicular to therear surface122b′ of thesecond semiconductor substrate122′ and/or thetop surface130tof the underlying insulatinglayer130.

Referring toFIGS. 1E-1F, afirst die connector152 is formed in the first trench TR1 and the first via opening OP1 in communication with the first trench TR1, and asecond die connector154 is formed in the second trench TR2. For example, a conductive liner CL is initially formed on the resulting structure as shown inFIG. 1E. For example, the conductive liner CL covers thetop surface140tof thedielectric layer140 and also conformally covers the surfaces that define the first trench TR1, the second trench TR2, and the first via opening OP1. In some embodiments, a portion of the conductive liner CL is in direct contact with the surfaces that define the first trench TR1 and the first via opening OP1 (e.g., thetop surface1183aof thesecond bonding pad1183, theinner sidewalls130sof the insulatinglayer130, and theinner sidewalls140sof the dielectric layer140). In some embodiments, another portion of the conductive liner CL may conformally cover surfaces that define the second trench TR2 (e.g., theinner sidewalls140sof thedielectric layer140, the exposedsurface129aof the TSV129). The portion of the conductive liner CL may be in physical and electrical contact with thesecond bonding pad1183, and the another portion of the conductive liner CL is in physical and electrical contact with theTSV129. Depending on the size of the second trench TR2, the another portion of the conductive liner CL may also be formed on therear surface122b′ of thesecond semiconductor substrate122′ and further extend to be in physical contact with thetop surface130tof the insulatinglayer130. In some embodiments in which the isolating liner IL is formed on therear surface122b′ of thesecond semiconductor substrate122′, the conductive liner CL is in physical contact with the portions of the isolating liner IL that are exposed by the first trench TR1 and the second trench TR2.

Continue toFIG. 1E, a deposition process (e.g., CVD, PVD, ALD, sputtering, combinations thereof, and/or the like) may be performed to form the conductive liner CL. In some embodiments, the conductive liner CL includes a barrier layer (not individually illustrated) formed of titanium, titanium nitride, titanium oxynitride, tantalum, tantalum nitride, tantalum oxynitride, tungsten, tungsten nitride, a combination thereof, and/or the like. In some embodiments, the barrier layer is conformally formed in the first trench TR1, the second trench TR2, and the first via opening OP1, so that the barrier layer is in direct contact with thesecond bonding pad1183, theTSV129, the insulatinglayer130, and thedielectric layer140. In some embodiments, the conductive liner CL includes a seed layer (not individually illustrated) that aids in the formation of a thicker conductive layer during subsequent processing steps. For example, the seed layer is a single metal layer or a composite metal layer including sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer formed over the titanium layer. In some embodiments, the conductive liner CL includes the seed layer conformally formed over the barrier layer, so that the barrier layer is interposed between the seed layer and thesecond bonding pad1183, and between the seed layer and theTSV129. Alternatively, the barrier layer is omitted.

Subsequently, a conductive material may be formed on the conductive liner CL and fill the first trench TR1, the second trench TR2, and the first via opening OP1. The conductive material may be formed by a plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of the conductive material include copper, tungsten, aluminum, silver, gold, combinations thereof, or the like. In some embodiments, excess conductive material and the underlying conductive liner CL may be removed from thetop surface140tof thedielectric layer140 to form thefirst die connector152 and thesecond die connector154. For example, a planarization process (e.g., CMP or the like) is performed to level the surface of the conductive liner CL and the conductive material, and to remove excess materials from thetop surface140tof thedielectric layer140. In some embodiments, after the planarization process, thetop surface152tof thefirst die connector152 and thetop surface154tof thesecond die connector154 are substantially leveled with thetop surface140tof thedielectric layer140.

Continue toFIG. 1F, thefirst die connector152 including theconductive material layer1522 and the underlyingconductive liner layer1521 may be electrically connected to thesecond bonding pad1183. Theconductive liner layer1521 may be physically interposed between and electrically connected to theconductive material layer1522 and thesecond bonding pad1183. Theconductive liner layer1521 may extend along the inner sidewalls (130sand140s) of the insulatinglayer130 and thedielectric layer140 to spatially separate theconductive material layer1522 from the insulatinglayer130 and thedielectric layer140. For example, in a top view, theconductive material layer1522 is encircled by theconductive liner layer1521, and thedielectric layer140 surrounds theconductive liner layer1521. In some embodiments in which the isolating liner IL is formed on therear surface122b′ of thesecond semiconductor substrate122′, theconductive liner layer1521 is physically interposed between theconductive material layer1522 and the isolating liner IL formed on thesecond semiconductor substrate122′.

Thesecond die connector154 including theconductive material layer1542 and the underlyingconductive liner layer1541 may be electrically connected to theTSV129. Theconductive liner layer1541 may be physically interposed between and electrically connected to theTSV129 and theconductive material layer1542. Theconductive liner layer1541 may extend along theinner sidewalls140sof thedielectric layer140 and therear surface122b′ of thesemiconductor substrate122′ to spatially separate theconductive material layer1542 from thedielectric layer140. For example, in the top view, theconductive material layer1542 is encircled by theconductive liner layer1541, and thedielectric layer140 surrounds theconductive liner layer1541. In some embodiments in which the isolating liner IL is formed on therear surface122b′ of thesecond semiconductor substrate122′, theconductive liner layer1541 is physically interposed between theconductive material layer1542 and the isolating liner IL formed on thesecond semiconductor substrate122′. In some other embodiments, thefirst die connector152 may be in contact with another TSV (not shown) so that thesemiconductor wafer110W may be electrically coupled to the second semiconductor die120 through the another TSV and thefirst die connector152.

Still referring toFIG. 1F, thefirst die connector152 may include afirst portion152aand asecond portion152bconnecting thefirst portion152ato thesecond bonding pad1183. For example, thefirst portion152aof thefirst die connector152 is laterally covered by thedielectric layer140, and thesecond portion152bof thefirst die connector152 is laterally covered by the insulatinglayer130. A portion of the insulatinglayer130 is interposed between thesecond portion152bof thefirst die connector152 and the second semiconductor die120. In some embodiments, thefirst portion152aof thefirst die connector152 and thesecond die connector154 spatially separated by thedielectric layer140 may be viewed as a conductive pattern. Thesecond portion152bof thefirst die connector152 penetrating through the insulatinglayer130 may be referred to as a through dielectric via (TDV). Since thefirst portion152aand thesecond portion152bare integratedly formed, no interface (e.g., a barrier layer, a seed layer, or the like) is between thefirst portion152aand thesecond portion152b. By such configuration, electrical resistance may be reduced and electrical performance may be improved.

Referring toFIG. 1G, aredistribution structure160 may be formed on thedielectric layer140, thefirst die connector152, and thesecond die connector154. Subsequently, a plurality ofconductive terminals170 may be formed on theredistribution structure160. For example, theredistribution structure160 includes at least one patterned dielectric layer (e.g.,1621 and1622) and at least one patterned conductive layer (e.g.,1641 and1642). The patterned conductive layer may be referred to as the redistribution layer or the redistribution lines. Two patterned dielectric layers and two patterned conductive layers are shown inFIG. 1G, but more or fewer patterned dielectric layers and patterned conductive layers may be present.

In some embodiments, the forming process of theredistribution structure160 includes at least the following steps. For example, a dielectric material is formed on thetop surface152tof thefirst die connector152, thetop surface154tof thesecond die connector154, and thetop surface140tof thedielectric layer140 by spin-coating, lamination, CVD, a combination thereof, and/or the like. The dielectric material may be or may include silicon oxide, silicon nitride, low-k dielectrics, combinations of these, and/or the like. In some other embodiments, the dielectric material includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like. The dielectric material is then patterned to form the patterneddielectric layer1621. For example, the patterning (e.g., lithography and etching, or the like) forms openings exposing portions of thefirst die connector152 and thesecond die connector154. Next, the patternedconductive layer1641 is formed on the patterneddielectric layer1621 and into the openings of the patterneddielectric layer1621. For example, the patternedconductive layer1641 includes conductive lines, conductive pads, and conductive vias. The conductive vias of the patternedconductive layer1641 may extend through the patterneddielectric layer1621 to physically and electrically couple the underlyingfirst die connector152 and the underlyingsecond die connector154 to subsequently formed structures. In some embodiments, the conductive vias of the patternedconductive layer1641 are tapered towards the underlying structure (e.g., thefirst die connector152 and the second die connector154). Alternatively, the conductive vias of the patternedconductive layer1641 may include vertical sidewalls.

In some embodiments, the patternedconductive layer1641 is formed by depositing a seed material layer, forming and patterning a photoresist layer on the seed material layer to expose portions of the seed material layer, forming a conductive material layer in the openings of the photoresist layer and on the exposed portions of the seed material layer, removing the photoresist layer, and removing portions of the seed material layer on which the conductive material layer is not formed. In some embodiments, an etching process may be performed to remove excess portions of the seed material layer which are not covered by the conductive material layer. The sidewalls of theconductive material layer1641band the underlyingseed material pattern1641amay be substantially leveled.

The combination of theconductive material layer1641band the underlyingseed material pattern1641aform the patternedconductive layer1641. For example, theseed material pattern1641amay be a titanium/copper bilayer, a copper layer, or other suitable metal layer. Theconductive material layer1641bmay include a metal, like copper, titanium, tungsten, aluminum, or the like. Theseed material pattern1641amay be interposed between theconductive material layer1641band thefirst die connector152, and between theconductive material layer1641band thesecond die connector154. In some embodiments, theseed material pattern1641ais in physical and electrical contact with thetop surface152tof thefirst die connector152 and thetop surface154tof thesecond die connector154, respectively. In some embodiments in which theseed material pattern1641aincludes titanium/copper bilayer, the titanium sublayer of theseed material pattern1641ais in direct contact with theconductive material layer1522 of thefirst die connector152 and theconductive material layer1542 of thesecond die connector154.

Continue toFIG. 1G, the patterneddielectric layer1622 is then formed on the patterneddielectric layer1621 to cover the patternedconductive layer1641. For example, the openings of the patterneddielectric layer1622 accessibly reveal at least a portion of the patternedconductive layer1641 for further electrical connection. Next, the patternedconductive layer1642 is formed on the patterneddielectric layer1622 and physically and electrically connected to the patternedconductive layer1641. The materials and the forming processes of the patterneddielectric layer1622 and the patternedconductive layer1642 may be similar to the patterneddielectric layer1621 and the patternedconductive layer1641, so the detailed descriptions are not repeated for the sake of brevity. In some embodiments in which fewer patterned dielectric layer and patterned conductive layer are to be formed, the forming processes discussed above may be omitted. In some embodiments in which more patterned dielectric layers and patterned conductive layers are to be formed, the forming processes discussed above may be repeated.

In some embodiments, the patternedconductive layer1642 may include under bump metallization (UBM) pads for providing electrical connections to the underlying structure upon which theconductive terminals170 may be formed. In some embodiments, the patternedconductive layer1642 includes aluminum pads, and theconductive terminals170 land thereon the aluminum pads. Other suitable conductive materials (e.g., copper) may be used to for the landing pads of the patternedconductive layer1642. For example, theconductive terminals170 may be or may include micro-bumps, controlled collapse chip connection (C4) bumps, metal pillars, solder balls, ball grid array (BGA) connectors, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, or the like. Theconductive terminals170 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. Theconductive terminals170 may include bump shapes or may have substantially vertical sidewalls. It is noted that the shape of theconductive terminal170 shown inFIG. 1G is provided for illustrative purposes, theconductive terminals170 may have various cross section depending on the design requirements.

Still referring toFIG. 1G, a singulation process (e.g., a sawing process or other dicing process) may be performed to separate the resulting structure into a plurality ofindividual semiconductor structures10. For example, a dicing tool (not shown) cuts through theredistribution structure160, the underlyingdielectric layer140, the underlying insulating layer, and theunderlying semiconductor wafer110W to form thesemiconductor structure10. Thesemiconductor wafer110W is cut to form the first semiconductor die110 after the singulation. In some embodiments, theredistribution structure160, the underlyingdielectric layer140, the underlying insulatinglayer130, and the first semiconductor die110 may have substantiallycoterminous sidewalls10safter the singulation. Thesemiconductor structure10 may be system-on-chip (SoC) or system-on-integrated-circuit (SoIC) devices. In such embodiments, the processing, memory, and/or electronic control functionality may be integrated on thesemiconductor structure10.

Thesemiconductor structure10 may include the first semiconductor die110, the second semiconductor die120 attached to the first semiconductor die110, the insulatinglayer130 disposed on the first semiconductor die110 and extending along thesidewalls120sof the second semiconductor die120, thedielectric layer140 disposed on the insulatinglayer130 and the second semiconductor die120, thefirst die connector152 having thefirst portion152alaterally covered by thedielectric layer140 and thesecond portion152blaterally covered by the insulatinglayer130, thesecond die connector154 laterally covered by thedielectric layer140 and directly connected to theTSV129, theredistribution structure160 disposed on thedielectric layer140, thefirst die connector152, and thesecond die connector154, and theconductive terminals170 disposed on theredistribution structure160.

Thefirst bonding pads1182 of the first semiconductor die110 may be physically and electrically connected to thebonding pads1282 of the second semiconductor die120. In some other embodiments, the first semiconductor die110 is electrically coupled to the second semiconductor die120 through thefirst die connector152 connected to another TSV (not shown) of the second semiconductor die120. In some embodiments, the first semiconductor die110 is electrically coupled to theredistribution structure160 through thefirst die connector152. Thefirst die connector152 may be viewed as a dual damascene connector. The second semiconductor die120 may be electrically coupled to theredistribution structure160 through thesecond die connector154. Thesecond die connector154 may be viewed as a single damascene connector. In some embodiments, the first semiconductor die110 is electrically coupled to theredistribution structure160 through the second semiconductor die120 and thesecond die connector154. Theconductive terminals170 may be electrically coupled to the first semiconductor die110 and the second semiconductor die120 through theredistribution structure160.

Thefirst portion152aof thefirst die connector152 may be physically and electrically connected toredistribution structure160, and thesecond portion152bof thefirst die connector152 may be physically and electrically connected to thesecond bonding pad1183 of the first semiconductor die110. Thefirst portion152aand thesecond portion152bof thefirst die connector152 may be formed in the same formation process, so that thefirst portion152amay form a continuous region with the underlyingsecond portion152b. There is no visible interface betweenfirst portion152aand thesecond portion152b. In this manner, the process steps and the processing cost of thesemiconductor structure10 may be reduced. The electrical interfaces between the first semiconductor die110 and theredistribution structure160 may be reduced by forming thefirst die connector152, and thus electrical performance and interconnect reliability of thesemiconductor structure10 may be improved.

FIGS. 2A-2E are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments. Throughout the various views and illustrative embodiments of the disclosure, like reference numbers are used to designate like elements. Unless specified otherwise, the materials and the formation methods of the elements described herein are essentially the same as the like elements described inFIGS. 1A-1G.

Referring toFIG. 2A, asemiconductor die220D is bonded to thesemiconductor wafer110W in the die attaching region DR. The semiconductor die220D is similar to the semiconductor die110D described inFIG. 1A, except that no TSV is formed in thesemiconductor die220D at this stage. The bonding process is similar to the process described inFIG. 1A, so the detailed descriptions are not repeated for the sake of brevity. After bonding the semiconductor die220D to thesemiconductor wafer110W, the insulatingmaterial layer130A may be formed on thesemiconductor wafer110W to laterally cover thesemiconductor die220D. A planarization process is optionally performed on the insulatingmaterial layer130A and the semiconductor die220D to level thetop surface130tof the insulatingmaterial layer130A and therear surface222bof thesemiconductor substrate222 of thesemiconductor die220D. Subsequently, thedielectric material layer140A may be formed on thetop surface130tof the insulatingmaterial layer130A and therear surface222bof thesemiconductor substrate222. The forming processes and the materials of the insulatingmaterial layer130A and thedielectric material layer140A may be similar to those of the insulatingmaterial layer130A and thedielectric material layer140A described inFIGS. 1B-1C, so the detailed descriptions are omitted for simplicity.

In some other embodiments, the isolating liner is formed on therear surface222bof thesemiconductor substrate222 prior to forming thedielectric material layer140A. For example, after planarizing the insulatingmaterial layer130A and the semiconductor die220D, thesemiconductor substrate222 may be slightly etched to form a recess, and then the isolating liner is formed in the recess of thesemiconductor substrate222. The isolating liner formed on thesemiconductor substrate222 may be substantially leveled with thetop surface130tof the insulatingmaterial layer130A. Subsequently, thedielectric material layer140A is formed on thetop surface130tof the insulatingmaterial layer130A and the isolating liner. In this manner, the isolating liner is interposed between thesemiconductor substrate222 and thedielectric material layer140A.

Referring toFIG. 2B, a portion of thedielectric material layer140A and a portion of the insulatingmaterial layer130A are removed to form thedielectric layer140 and the insulatinglayer130, respectively. Thedielectric layer140 may include the first trench TR1 and the second trench TR2, and the insulatinglayer130 may include the first via opening OP1 in communication with the first trench TR1 of thedielectric layer140 and exposing thesecond bonding pad1183 of thesemiconductor wafer110W. In some embodiments, a portion of the semiconductor die220D is removed to form the second semiconductor die220 having a second via opening OP2. For example, the second via opening OP2 is in communication with the second trench TR2. In some embodiments, the second via opening OP2 penetrates through thesemiconductor substrate222 and further extends into thesecond interconnect structure124. For example, a portion of thedielectric layer1241 is removed so that at least a portion of themetallization pattern1242 is accessibly exposed by the second via opening OP2. It is noted that the illustration of the second via opening OP2 is merely an example, the number of the second via opening OP2 construe no limitation in the disclosure, and the second via opening OP2 may expose any level of themetallization patterns1242 depending on the design requirements.

For example, the removal step may include one or more etching processes, such as wet etching, dry etching, or other etching techniques. In some embodiments, etching depths are controlled (e.g., by controlling the etching time) to obtain predetermined depths of the first via opening OP1 and the second via opening OP2. The etch stop layer (not shown) may be formed to provide a mechanism to stop the etching when forming the trenches and via openings. In some embodiments, one or more etch stop layers (not shown) are formed between adjacent layers, e.g., thedielectric material layer140A and the insulatingmaterial layer130A, thedielectric material layer140A and thesemiconductor substrate222, thesemiconductor substrate222 and thedielectric layer1241, and thedielectric layer1241 and themetallization patterns1242. The etch stop layers may be formed of a dielectric material having a different etch selectivity from the adjacent layers. The processes of forming the first trench TR1, the first via opening OP1, and the second trench TR2 may be similar to the processes described inFIG. 1D.

The process of forming the second via opening OP2 may be performed during the same step of forming the second trench TR2. In some alternative embodiments, the second via opening OP2 is formed after forming the second trench TR2. In some embodiments, the inner sidewalls of the second semiconductor die220 that define the second via opening OP2 are substantially vertical. Alternatively, the second via opening OP2 may be essentially tapered toward themetallization pattern1242 exposed by the second via opening OP2. The width W1 of the first via opening OP1 may be greater than the width W2 of the second via opening OP2. The depth D1 of the first via opening OP1 may also be greater than the depth D2 of the second via opening OP2. For example, an aspect ratio of depth D2 over the width W2 is less than or substantially equal to 10.

Continue toFIG. 2B, after forming the first trench TR1, the second trench TR2, the first via opening OP1, and the second via opening OP2, an isolatingliner230 is formed on portions of therear surface222bof thesemiconductor substrate222 that are exposed by the first trench TR1 and/or the second trench TR2. The material of the isolatingliner230 may be or may include silicon nitride, an oxide, silicon oxynitride, silicon carbide, or the like, and may be formed by any suitable method such as spin-coating, CVD, PECVD, HDP-CVD, ALD, or the like. Since the isolatingliner230 is formed after patterning thedielectric layer140, the sidewalls of the isolatingliner230 may be in direct contact with the inner sidewalls of thedielectric layer140.

The isolatingliner230 may be formed on therear surface222bof thesemiconductor substrate222 and continuously extend into the second via opening OP2 to line with theinner sidewalls222sof thesemiconductor substrate222 and theinner sidewalls1241sof thedielectric layer1241. At least a portion of thetop surface1242tof themetallization pattern1242 exposed by the second via opening OP2 may be exposed by the isolatingliner230. In some embodiments in which the first trench TR1 extends to expose therear surface222bof thesemiconductor substrate222, the isolatingliner230 may be formed on therear surface222bof thesemiconductor substrate222. In some other embodiments, the isolatingliner230 formed on therear surface222bof thesemiconductor substrate222 extends to cover thetop surface130tof the insulatinglayer130. The isolatingliner230 may further extend into the first via opening OP1 to line with theinner sidewalls130sof the insulatinglayer130. At least a portion of thesecond bonding pad1183 of thesemiconductor wafer110W corresponding to the first via opening OP1 may be exposed by the isolatingliner230.

Referring toFIGS. 2C-2D, thefirst die connector152 is formed in the first trench TR1 and the first via opening OP1 in communication with the first trench TR1, and asecond die connector254 is formed in the second trench TR2 and the second via opening OP2 in communication with the second trench TR2. For example, the conductive liner CL is conformally formed on thesemiconductor wafer110W, the second semiconductor die220, the insulatinglayer130, and thedielectric layer140. For example, the conductive liner CL covers thetop surface140tof thedielectric layer140 and also conformally covers the surfaces that define the first trench TR1, the second trench TR2, the first via opening OP1, and the second via opening OP2. The material and the forming process of the conductive liner CL may be similar to those of the conductive liner CL described inFIG. 1E, so the detailed descriptions are omitted for simplicity.

In some embodiments, the conductive liner CL is in physical contact with the surfaces that form the first trench TR1 and the first via opening OP1 (e.g., thetop surface1183aof thesecond bonding pad1183, theinner sidewalls130sof the insulatinglayer130, thetop surface130tof the insulatinglayer130, and theinner sidewalls140sof the dielectric layer140). In some embodiments, the conductive liner CL may also cover the isolatingliner230 formed on therear surface222bof thesemiconductor substrate222. In other embodiments in which the first trench TR1 doesn't expose therear surface222bof thesemiconductor substrate222, the conductive liner CL formed on thetop surface130tof the insulatinglayer130 does not extend to form on the second semiconductor die220.

In some embodiments, the conductive liner CL is in physical contact with the surfaces that form the second trench TR2 and the second via opening OP2 (e.g., theinner sidewalls140sof thedielectric layer140, thetop surface130tof the insulatinglayer130, theinner sidewalls222sof thesemiconductor substrate222, theinner sidewalls1241sof thedielectric layer1241, and thetop surface1242tof the metallization pattern1242). In some embodiments, the conductive liner CL may also cover the isolatingliner230 formed on therear surface222bof thesemiconductor substrate222. The isolatingliner230 may be physically interposed between thesemiconductor substrate222 and the conductive liner CL. The conductive liner CL may cover thetop surface1242tof themetallization pattern1242 on which the isolatingliner230 is not formed. In other embodiments in which the second trench TR1 doesn't expose thetop surface130tof the insulatinglayer130, the conductive liner CL formed over thesemiconductor substrate222 does not extend to cover the insulatinglayer130. It is appreciated that the illustration ofFIG. 2C is merely an example and more or fewer surfaces defining the trenches and via openings may be covered by the conductive liner CL.

Continue toFIG. 2D, after forming the conductive liner CL, the conductive material may be formed on the conductive liner CL and fill the openings (e.g., the first trench TR1, the second trench TR2, the first via opening OP1, and the second via opening OP2). The material and the forming process of the conductive material may be similar to the conductive material described related toFIG. 1F, so the detailed descriptions are omitted for simplicity. In some embodiments, excess conductive material and the underlying conductive liner CL are removed from thetop surface140tof thedielectric layer140 to form thefirst die connector152 and thesecond die connector254 by, for example, CMP or other suitable planarization techniques. In some embodiments, thetop surface152tof thefirst die connector152 and thetop surface254tof thesecond die connector254 are substantially leveled with thetop surface140tof thedielectric layer140.

Thefirst die connector152 including theconductive material layer1522 and the underlyingconductive liner layer1521 may be similar to thefirst die connector152 described inFIG. 1F. The isolatingliner230 may be physically interposed between therear surface222bof thesemiconductor substrate222 and theconductive liner layer1521 of thefirst die connector152, so that thefirst die connector152 is not in direct contact with thesemiconductor substrate222. Thesecond die connector254 including theconductive material layer2542 and the underlyingconductive liner layer2541 may be electrically connected to the second semiconductor die220. For example, theconductive liner layer2541 is physically interposed between and electrically connected to theconductive material layer2542 and themetallization pattern1242. Theconductive liner layer2541 may be physically interposed between the isolatingliner230 and theconductive material layer2542, so that thesecond die connector254 is not in direct contact with thesemiconductor substrate222. Theconductive liner layer2541 lining with theinner sidewalls140sof thedielectric layer120 may be physically interposed between thedielectric layer140 and theconductive material layer2542. In some embodiments, thesecond die connector254 includes afirst portion254aand asecond portion254bconnecting thefirst portion254ato themetallization pattern1242 of thesecond interconnect structure124.

Still referring toFIG. 2D, thefirst portion254aof thesecond die connector254 may be laterally covered by thedielectric layer140, and thesecond portion254bof thesecond die connector254 may be laterally covered by the isolatingliner230 formed in the second semiconductor die220. In some embodiments, thefirst portion152aof thefirst die connector152 and thefirst portion254aof thesecond die connector254 spatially separated by thedielectric layer140 may be viewed as a conductive pattern. In some embodiments, thesecond portion254bof thesecond die connector254 extends into the second semiconductor die220 from therear surface222bof thesemiconductor substrate222 to reach themetallization pattern1242 of thesecond interconnect structure124. The TSV of the second semiconductor die220 may be replaced with thesecond portion254bof thesecond die connector254. Thesecond die connector254 and thefirst die connector152 may be viewed as dual damascene connectors. In some embodiments, thefirst portion254aand thesecond portion254bof thesecond die connector254 actually form integrated regions, with no visible interfaces (e.g., a barrier layer, a seed layer, etc.) therebetween. By such configuration, electrical resistance may be reduced and electrical performance may be improved.

Referring toFIG. 2E, theredistribution structure160 including the patterned dielectric layer (e.g.,1621 and1622) and the patterned conductive layer (e.g.,1641 and1642) may be formed on thedielectric layer140, thefirst die connector152, and thesecond die connector254. For example, the patternedconductive layer1641 is in physical and electrical contact with thetop surface152tof thefirst die connector152 and thetop surface254tof thesecond die connector254. The patternedconductive layer1641 may include theseed material pattern1641aand the overlyingconductive material layer1641b. In some embodiments, theseed material pattern1641ais physically interposed between and electrically connected to theconductive material layer1641band thefirst portion254aof thesecond die connector254, and between theconductive material layer1641band thefirst portion152aof thefirst die connector152. Next, theconductive terminals170 may be formed on theredistribution structure160. Subsequently, the singulation process may be performed to separate the resulting structure into a plurality ofindividual semiconductor structures20. The materials and the forming processes of theredistribution structure160 and theconductive terminals170 may be similar to those of theredistribution structure160 and theconductive terminals170 described inFIG. 1G, so the detailed descriptions are omitted for simplicity.

As shown inFIG. 2E, after the singulation process, theredistribution structure160, the underlyingdielectric layer140, the underlying insulatinglayer130, and the first semiconductor die110 may have substantiallycoterminous sidewalls20s. Thesemiconductor structure20 may be similar to thesemiconductor structure10 described inFIG. 1G, except thesecond die connector254 and the isolatingliner230. For example, the isolatingliner230 is at least formed on a portion of therear surface222bof thesemiconductor substrate222 that is not covered by thedielectric layer140 to separate thefirst portion152aof thefirst die connector152 and thefirst portion254aof thesecond die connector254. The isolatingliner230 may extend into the second semiconductor die220 to separate thesecond portion254bof thesecond die connector254 from the second semiconductor die220. In some other embodiments, the isolatingliner230 is interposed between therear surface222bof thesemiconductor substrate222 and thedielectric layer140. Thefirst portion254aof thesecond die connector254 may be physically and electrically connected toredistribution structure160, and thesecond portion254bof thesecond die connector254 is physically and electrically connected to themetallization pattern1242 of thesecond interconnect structure124. Thefirst portion254aand thesecond portion254bof thesecond die connector254 may be formed in the same formation process, so that thefirst portion254amay form a continuous region with the underlyingsecond portion254b. Thus, no interface forms betweenfirst portion254aand thesecond portion254b. In this manner, the process steps and the processing cost of thesemiconductor structure20 may be reduced. The electrical interfaces between the second semiconductor die220 and theredistribution structure160 may be reduced by forming thesecond die connector254, and thus electrical performance and interconnect reliability may be improved.

FIGS. 3A-3D are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments. Throughout the various views and illustrative embodiments of the disclosure, like reference numbers are used to designate like elements. Unless specified otherwise, the materials and the formation methods of the elements described herein are essentially the same as the like elements described inFIGS. 1A-1G.

Referring toFIG. 3A, the second semiconductor die120 is bonded to thesemiconductor wafer110W, and then the insulatinglayer330 is formed on thesemiconductor wafer110W to laterally cover the second semiconductor die120. TheTSV129 of the second semiconductor die120 may be accessibly exposed by the insulatinglayer330. Thedielectric layer340 may be formed on the insulatinglayer330 and the second semiconductor die120. In some embodiments, at least a portion of thesecond bonding pad1183 of thesemiconductor wafer110W is accessibly exposed by the first via opening OP1′ of the insulatinglayer330 which is in communication with the first trench TR1′ of thedielectric layer340. In some embodiments, at least a portion of theTSV129 is accessibly exposed by the second trench TR2′ of thedielectric layer340.

In some embodiments, the insulatinglayer330 includes polymer materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using spin-on coating or the like. In some embodiments, the insulatinglayer330 is a molding compound, epoxy, or the like, and may be formed by compression molding, transfer molding, or the like. In some embodiments, the insulatinglayer330 may be a polymer with or without a silica-based or glass filler added. The planarization process is optionally performed to level thetop surface330tof the insulatinglayer330 and therear surface122b′ of thesemiconductor substrate122′ before forming thedielectric layer340. TheTSV129 of the second semiconductor die120 may be accessibly revealed after the planarization process. In some embodiments, thesecond semiconductor substrate122′ is slightly etched, and then the isolating liner IL′ is formed on therear surface122b′ of thesemiconductor substrate122′ to laterally cover theTSV129 before forming thedielectric layer340.

In some embodiments, thedielectric layer340 may be or may include polymer materials such as PBO, PI, BCB, a combination thereof, or the like. The materials of thedielectric layer340 and the underlying insulatinglayer330 may be the same or similar. In some alternative embodiments, thedielectric layer340 includes materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a combination thereof, or the like. In some embodiments, by forming thedielectric layer340 and/or the insulatinglayer330 as a low temperature cured polymer material, a thermal budget for the overall manufacture may be reduced.

Continue toFIG. 3A, in some embodiments, the dielectric material layer is formed on the insulating material layer, the isolating liner IL, and theTSV129. Next, the dielectric material layer and the insulating material layer may be patterned (e.g., using laser drilling) to form the first trench TR1′, the second trench TR2′, and the first via opening OP1′. In some embodiments in which the first trench TR1′, the second trench TR2′, and the first via opening OP1′ are formed by laser drilling, the surfaces that define the first trench TR1′, the second trench TR2′, and the first via opening OP1′ have significant roughness, compared with the surfaces formed by etching. As surface roughness is known that provides a measure of the unevenness of the surface height. In some embodiments, the surface roughness of the exposedsurface129aof theTSV129 is less than that of theinner sidewalls340sof thedielectric layer340. The surface roughness of the exposedsurface129aof theTSV129 may be less than that of the isolating liner IL′ formed on therear surface122b′ of thesemiconductor substrate122′ and exposed by the second trench TR2′. In some embodiments, the surface roughness of theinner sidewalls330sof the insulatinglayer330 is greater than that of thetop surface1183aof thesecond bonding pad1183.

In some embodiments in which the laser drilling is performed, the first trench TR1, the second trench TR2′ and the first via opening OP1 may be slightly tapered toward thesemiconductor wafer110W. The first trench TR1′, the second trench TR2′, and/or the first via opening OP1′ may have a wide top and narrow bottom profile. For example, theinner sidewalls330sof the insulatinglayer330 are inclined relative to thetop surface1183aof thesecond bonding pad1183. In some embodiments, a first angle θ1 formed between thetop surface1183aof thesecond bonding pad1183 and theinner sidewall330sof the insulatinglayer330 may be an obtuse angle. For example, theinner sidewalls340sof thedielectric layer340 are inclined relative to therear surface122b′ of thesemiconductor substrate122′ and/or thetop surface330tof the insulatinglayer330. Alternatively, the first angle θ1 may be close to a right angle. In some embodiments, a second angle θ2 formed between therear surface122b′ of thesemiconductor substrate122′ and theinner sidewall340sof thedielectric layer340 connected to therear surface122b′ (or between thetop surface330tof the insulatinglayer330 and theinner sidewall340sof thedielectric layer340 connected to thetop surface330t) may be an obtuse angle. Alternatively, the second angle θ2 may be substantially a right angle. The width (or diameter) W1′ of the first via opening OP1′ may be less than the width (or diameter)1183wof thesecond bonding pad1183. The width W1′ may be a maximum width of the first via opening OP1′ or a minimum width of the first via opening OP1′. For example, the width W1′ of the first via opening OP1′ ranges from about 2 μm to about 5 μm. In some embodiments, a difference is between thewidth1183wof thesecond bonding pad1183 and the width W1′ of the first via opening OP1′. Thewidth1183wof thesecond bonding pad1183 may range from about 4 μm to about 7 μm in accordance with some embodiments. The difference of the widths (1183wand W1′) is, for example, about 5 μm. Alternatively, the difference of the widths (1183wand W1′) may be greater than or less than 5 μm, depending on the accuracy of laser drilling.

Referring toFIG. 3B and also with reference toFIG. 3A, the conductive liner CL is formed on the resulting structure shown inFIG. 3A. For example, the conductive liner CL covers thetop surface340tof thedielectric layer340 and also conformally covers the surfaces that define the first trench TR1′, the second trench TR2′, and the first via opening OP1′. In some embodiments, the roughed inner sidewalls (330sand340s) of the insulatinglayer330 and thedielectric layer340 are covered by the conductive liner CL. In some embodiments, the conductive liner CL also covers the uneven topography of thetop surface330tof the insulatinglayer330. The conductive liner CL may further cover the uneven topography of the isolating liner IL′ formed on therear surface122b′ of thesemiconductor substrate122. The material and the forming process of the conductive liner CL may be similar to those of the conductive liner CL described inFIG. 1E, so the detailed descriptions are not repeated for simplicity.

Referring toFIG. 3C, the conductive material may be formed on the conductive liner CL and fill the first trench TR1′, the first via opening OP1′, and the second trench TR2′. Subsequently, excess conductive material and the underlying conductive liner CL may be removed from thetop surface340tof thedielectric layer340 to form thefirst die connector152 and thesecond die connector154. For example, the planarization process is performed to level thetop surface340tof thedielectric layer340, thetop surface152tof thefirst connector152, and thetop surface154tof thesecond die connector154. For example, thefirst die connector152 including theconductive material layer1522 and the underlyingconductive liner layer1521 may be electrically connected to thesecond bonding pad1183. Theconductive liner layer1521 may be physically interposed between and electrically connected to theconductive material layer1522 and thesecond bonding pad1183. Thesecond die connector154 including theconductive material layer1542 and the underlyingconductive liner layer1541 may be electrically connected to theTSV129. Theconductive liner layer1541 may be physically interposed between and electrically connected to theTSV129 and theconductive material layer1542. The forming processes and the materials of thefirst die connector152 and thesecond die connector154 may be similar to those of thefirst die connector152 and thesecond die connector154 described inFIG. 1F, so the detailed descriptions are omitted for the sake of brevity.

Referring toFIG. 3D, theredistribution structure160 including the patterned dielectric layer (e.g.,1621 and1622) and the patterned conductive layer (e.g.,1641 and1642) may be formed on thedielectric layer340, thefirst die connector152, and thesecond die connector154. For example, the patternedconductive layer1641 is in physical and electrical contact with thetop surface152tof thefirst die connector152 and thetop surface154tof thesecond die connector154. The patternedconductive layer1641 may include theseed material pattern1641aand the overlyingconductive material layer1641b. In some embodiments, theseed material pattern1641ais physically interposed between and electrically connected to theconductive material layer1641band thefirst portion152aof thefirst die connector152, and between theconductive material layer1641band thesecond die connector154.

Next, theconductive terminals170 may be formed on theredistribution structure160. Subsequently, the singulation process may be performed to separate the resulting structure into a plurality ofindividual semiconductor structures30. The materials and the forming processes of theredistribution structure160 and theconductive terminals170 may be similar to those of theredistribution structure160 and theconductive terminals170 described inFIG. 1G, so the detailed descriptions are omitted for simplicity. As shown inFIG. 3D, after the singulation process, theredistribution structure160, the underlyingdielectric layer340, the underlying insulatinglayer330, and the first semiconductor die110 may have substantiallycoterminous sidewalls30s.

FIGS. 4A-4C are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure according to some embodiments. Throughout the various views and illustrative embodiments of the disclosure, like reference numbers are used to designate like elements. Unless specified otherwise, the materials and the formation methods of the elements described herein are essentially the same as the like elements described inFIGS. 2A-2E and 3A-3D.

Referring toFIG. 4A, the structure shown inFIG. 4A may be similar to the structure shown inFIG. 2B, except that a different process is employed to form the trenches (e.g., TR1′ and TR2′) and the via openings (e.g., OP1′ and OP2′). For example, the semiconductor die is bonded to thesemiconductor wafer110W, and then the insulating material layer and the dielectric material layer are sequentially formed. The bonding process and the forming process may be similar to the processes described inFIG. 2A, so the detailed descriptions are not repeated for the sake of brevity. Subsequently, a removal process (e.g., laser drilling) is performed on the dielectric material layer, the insulating material layer, and the semiconductor die to respectively form thedielectric layer340 having the first trench TR1′ and the second trench TR2′, the insulatinglayer330 having the first via opening OP1′, and the second semiconductor die220 having the second via opening OP2′. The first via opening OP1′ of the insulatinglayer330 is in communication with the first trench TR1′ of thedielectric layer340 and may accessibly expose thesecond bonding pad1183 of thesemiconductor wafer110W. The second via opening OP2′ of the second semiconductor die220 is in communication with the second trench TR2′ of thedielectric layer340 and may accessibly expose themetallization pattern1242 of thesecond interconnect structure124.

Continue toFIG. 4A, the structure shown inFIG. 4A may be similar to the structure shown inFIG. 3A, except that the second semiconductor die220 is free of TSV and the second via opening OP2′ is formed during the step of forming the second trench TR2′. In some embodiments, thedielectric layer340, the insulatinglayer330, and the second semiconductor die220 may have roughed surfaces after the laser drilling process. For example, the surface roughness of theinner sidewalls222s′ of thesemiconductor substrate222 is greater than that of thetop surface1242tof themetallization pattern1242. In some embodiments, the second via opening OP2′ has a tapered profile. For example, theinner sidewalls222s′ of thesemiconductor substrate222 are sloped from therear surface222b′ of thesemiconductor substrate222 toward themetallization pattern1242. Alternatively, theinner sidewalls222s′ of thesemiconductor substrate222 are substantially vertical to therear surface222b′.

Still referring toFIG. 4A, the isolatingliner230 is formed on portions of therear surface222b′ of thesemiconductor substrate222 that are exposed by the first trench TR1′ and/or the second trench TR2′. The roughedrear surface222b′ of thesemiconductor substrate222 is then covered by the isolatingliner230. The isolatingliner230 may be formed on therear surface222b′ of thesemiconductor substrate222 and extend into the second via opening OP2′ to line with theinner sidewalls222s′ of thesemiconductor substrate222. In some embodiments in which the first trench TR1′ extends to expose therear surface222b′ of thesemiconductor substrate222, the isolatingliner230 is formed on therear surface222b′ of thesemiconductor substrate222. In some other embodiments, the isolatingliner230 formed on therear surface222b′ of thesemiconductor substrate222 extends to cover thetop surface330tof the insulatinglayer330. In some other embodiments, the isolatingliner230 may further extend into the first via opening OP1′ to line with theinner sidewalls130sof the insulatinglayer130. The material and the forming process of the isolatingliner230 may be similar to the isolatingliner230 described inFIG. 2B.

Referring toFIG. 4B, thefirst die connector152 including theconductive material layer1522 and the underlyingconductive liner layer1521, and thesecond die connector254 including theconductive material layer2542 and the underlyingconductive liner layer2541 are formed. Thefirst die connector152 and thesecond die connector254 may be formed during the same step, and may be similar to thefirst die connector152 and thesecond die connector254 described inFIG. 2D. For example, the conductive liner is conformally formed in the trenches and the via openings, and then the conductive material is formed on the conductive liner and fills the trenches and the via openings. Subsequently, the planarization process is optionally performed to remove excess conductive material and the conductive liner to level thetop surface340tof thedielectric layer340, thetop surface152tof thefirst die connector152, and thetop surface254tof thesecond die connector254. Theconductive liner layer1521 of thefirst die connector152 and theconductive liner layer2541 of thesecond die connector254 may cover the roughed surfaces caused by the laser drilling process. Theconductive liner layer1521 of thefirst die connector152 overlying thetop surface1183tof thesecond bonding pad1183 may be physically interposed between and electrically connected to thesecond bonding pad1183 and theconductive material layer1522. Theconductive liner layer2541 of thesecond die connector254 overlying thetop surface1242tof themetallization pattern1242 may be physically interposed between and electrically connected to themetallization pattern1242 and theconductive material layer2542.

Referring toFIG. 4C, theredistribution structure160 including the patterned dielectric layer (e.g.,1621 and1622) and the patterned conductive layer (e.g.,1641 and1642) may be formed on thedielectric layer340, thefirst die connector152, and thesecond die connector254. Next, theconductive terminals170 may be formed on theredistribution structure160. Subsequently, the singulation process may be performed to separate the resulting structure into a plurality ofindividual semiconductor structures40. The materials and the forming processes of theredistribution structure160 and theconductive terminals170 may be similar to those of theredistribution structure160 and theconductive terminals170 described inFIG. 1G, so the detailed descriptions are omitted for simplicity. As shown inFIG. 4C, after the singulation process, theredistribution structure160, the underlyingdielectric layer340, the underlying insulatinglayer330, and the first semiconductor die110 may have substantiallycoterminous sidewalls40s.

FIG. 5 is a schematic cross-sectional view showing an application of a semiconductor structure according to some embodiments. Referring toFIG. 5, apackage structure50 including afirst component52 and asecond component54 disposed over thefirst component52 is provided. Thefirst component52 may be or may include a printed circuit board (PCB), a printed wiring board, an interposer, a package substrate, and/or other carrier that is capable of carrying integrated circuits. Thesecond component54 mounted on thefirst component52 may be similar to any one of the semiconductor structures described inFIGS. 1G, 2E, 3D, and 4C. In some embodiments, more than one the semiconductor structures (e.g., any combination of the semiconductor structures described above) may be electrically coupled to thefirst component52 through a plurality ofterminals54a. In some embodiments, theterminals54aare theconductive terminals170 described above, and a reflow process may be performed on theconductive terminals170 to mount the semiconductor structure(s) on thefirst component52.

The semiconductor structure described above may be or may be a part of an Integrated-Fan-Out (InFO) package, a Chip-On-Wafer-On-Substrate (CoWoS) package, a Chip-On-Wafer (CoW) package, etc. For example, thesecond component54 mounted on thefirst component52 may be the InFO package including at least one semiconductor structure (e.g., any one or combination of the semiconductor structures described above) packaged therein. For example, thesecond component54 includes the semiconductor structures separately and laterally encapsulated by a molding layer (not shown). Thesecond component54 may further include a fan-out redistribution structure (not shown) formed on the molding layer and the semiconductor structures, and the fan-out redistribution structure may be electrically coupled to the semiconductor structures through theconductive terminals170. A plurality ofexternal terminals54aof thesecond component54 may be formed on the fan-out redistribution structure to be electrically coupled to thefirst component52 and the semiconductor structures. Other packaging techniques may be used to form thepackage structure50, which are not limited in the disclosure. Thepackage structure50 may be part of an electronic system for such as computers (e.g., high-performance computer), computational devices used in conjunction with an artificial intelligence system, wireless communication devices, computer-related peripherals, entertainment devices, etc. It should be noted that other electronic applications are also possible.

In accordance with some embodiments, a semiconductor structure includes a bottom die, a top die bonded to the bottom die, an insulating layer disposed on the bottom die and laterally covering the top die, a first dual-damascene connector overlying the insulating layer and the top die. The bottom die is wider than the top die, and a bonding interface of the top and bottom dies is substantially flat. The first dual-damascene connector is inserted into the insulating layer to be in electrical and physical contact with the bottom die.

In accordance with some embodiments, a semiconductor structure includes a bottom die, a top die stacked upon and fused to the bottom die, an insulating layer disposed on the bottom die and laterally covering the top die, a first die connector including a first via portion laterally covered by the insulating layer and landing on the bottom die, and a second die connector including a second via portion inserted into the top die.

In accordance with some embodiments, a semiconductor structure includes a bottom die, a top die bonded to the bottom die, an insulating layer disposed on the bottom die and laterally covering the top die, and a first dual-damascene connector including a via portion surrounded by the inner sidewall of the insulating layer and landing on the bottom die. The bottom die is wider than the top die, and a bonding interface of the top and bottom dies being substantially flat. A surface roughness of an inner sidewall of the insulating layer is greater than that of the bonding interface.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

What is claimed is:

1. A semiconductor structure, comprising:

a bottom die;

a top die bonded to the bottom die, the bottom die being wider than the top die, and a bonding interface of the top and bottom dies being substantially flat;

an insulating layer disposed on the bottom die and laterally covering the top die; and

a first dual-damascene connector overlying the insulating layer and the top die, and the first dual-damascene connector inserted into the insulating layer to be in electrical and physical contact with the bottom die.

2. The semiconductor structure ofclaim 1, wherein an inner sidewall of the insulating layer covering the first dual-damascene connector comprises a surface roughness greater than a surface roughness of the bonding interface.

3. The semiconductor structure ofclaim 1, further comprising:

a second dual-damascene connector comprising a pad portion overlying the top die and a via portion inserted into the top die.

4. The semiconductor structure ofclaim 3, wherein the second dual-damascene connector comprises:

a conductive liner layer lining with an inner sidewall of a semiconductor substrate of the top die, a rear surface of the semiconductor substrate connected to the inner sidewall of the semiconductor substrate; and

a conductive material layer overlying the conductive liner layer.

5. The semiconductor structure ofclaim 3, wherein a surface roughness of the inner sidewall of the semiconductor substrate of the top die is greater than that of an interconnect circuitry of the top die underlying the semiconductor substrate.

6. The semiconductor structure ofclaim 3, further comprising:

an isolating liner interposed between the semiconductor substrate of the top die and the second dual-damascene connector.

7. The semiconductor structure ofclaim 3, further comprising:

a dielectric layer disposed on the insulating layer and the top die to laterally cover a pad portion of the first dual-damascene connector and the pad portion of the second dual-damascene connector, wherein the dielectric layer and the insulating layer are of different materials.

8. A semiconductor structure, comprising:

a bottom die;

a top die stacked upon and fused to the bottom die;

an insulating layer disposed on the bottom die and laterally covering the top die;

a first die connector comprising a first via portion laterally covered by the insulating layer and landing on the bottom die; and

a second die connector comprising a second via portion inserted into the top die.

9. The semiconductor structure ofclaim 8, wherein a surface roughness of an inner sidewall of the insulating layer surrounding the first via portion of the first die connector is greater than that of a bonding surface of the bottom die.

10. The semiconductor structure ofclaim 9, wherein the second via portion of the second die connector extends through a semiconductor substrate of the top die and lands on an interconnect circuitry of the top die underlying the semiconductor substrate.

11. The semiconductor structure ofclaim 10, further comprising:

an isolating liner interposed between the semiconductor substrate of the top die and the second die connector.

12. The semiconductor structure ofclaim 11, wherein the isolating liner covers a surface of the semiconductor substrate of the top die that has a surface roughness greater than a surface roughness of the bonding surface of the bottom die.

13. The semiconductor structure ofclaim 8, wherein the second die connector comprises:

a conductive material layer; and

a conductive liner layer lining with a via opening of the top die and extending over a rear surface of the top die opposite to the bottom die, and the conductive liner layer interposed between the conductive material layer and the top die.

14. The semiconductor structure ofclaim 8, further comprising:

a polymer layer disposed on the insulating layer and the top die, the polymer layer separating a pad portion of the first die connector from a pad portion of the second die connector, and a surface roughness of an inner sidewall of the polymer layer being greater than a surface roughness of a bonding surface of the bottom die.

15. A semiconductor structure, comprising:

a bottom die;

an insulating layer disposed on the bottom die and laterally covering the top die, a surface roughness of an inner sidewall of the insulating layer being greater than that of the bonding interface; and

a first dual-damascene connector comprising a via portion surrounded by the inner sidewall of the insulating layer and landing on the bottom die.

16. The semiconductor structure ofclaim 15, further comprising:

a second dual-damascene connector comprising a via portion inserted into the top die.

17. The semiconductor structure ofclaim 16, wherein the via portion of the second dual-damascene connector passing through a semiconductor substrate of the top die and lands on an interconnect circuitry of the top die underlying the semiconductor substrate.

18. The semiconductor structure ofclaim 17, wherein a surface roughness of an inner sidewall of the semiconductor substrate of the top die surrounding the via portion of the second dual-damascene connector is greater than that of the bonding interface.

19. The semiconductor structure ofclaim 15, wherein the bonding interface comprises metal-to-metal bonds and dielectric-to-dielectric bonds.

20. The semiconductor structure ofclaim 15, wherein the first dual-damascene connector further comprises a pad portion connected to the via portion and overlying the insulating layer and the top die.