US20220045253A1 - Light emitting diode packages - Google Patents

Abstract

Solid-state lighting devices including light-emitting diodes (LEDs) and LED packages are disclosed. LED packages are provided with improved thermal and/or electrical coupling between LED chips and submounts or lead frames. Various configurations of submounts with via arrangements are disclosed to provide improved coupling between LED chips and submounts. LED chip contacts are disclosed with one or more openings that are registered with vias to provide more uniform mounting. Multiple LED chips may be arranged around a thermally conductive element on a submount, and a via in the submount may be registered with the thermally conductive element. Subassemblies are provided between LED chips and lead frames to improve electrical and thermal coupling. Underfill materials may be arranged between LED chips and lead frames to provide improved mechanical support.

Description

RELATED APPLICATIONS
• This application is a division of U.S. patent application Ser. No. 16/249,246, filed Jan. 16, 2019, the disclosure of which is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
• The present disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs) and more particularly to LED packages.
BACKGROUND
• Solid-state lighting devices such as light-emitting diodes (LEDs) are increasingly used in both consumer and commercial applications. Advancements in LED technology have resulted in highly efficient and mechanically robust light sources with a long service life. Accordingly, modern LEDs have enabled a variety of new display applications and are being increasingly utilized for general illumination applications, often replacing incandescent and fluorescent light sources.
• LEDs are solid-state devices that convert electrical energy to light and generally include one or more active layers of semiconductor material (or an active region) arranged between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into the one or more active layers where they recombine to generate emissions such as visible light or ultraviolet emissions. An LED chip typically includes an active region that may be fabricated, for example, from silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, gallium arsenide-based materials, and/or from organic semiconductor materials. LED packages are solid-state devices that incorporate one or more LED chips into a packaged device. An LED chip may be enclosed in a component package to provide environmental and/or mechanical protection, light focusing and the like.
• Typically, it is desirable to operate LED chips and LED packages at the highest light emission efficiencies possible, which can be measured by the emission intensity in relation to the input power (e.g., in lumens per watt). As light emission intensities of LED chips and LED components continue to increase, more heat can be generated from LED chips, which can adversely impact operating efficiencies. Additionally, challenges exist in manufacturing LED packages that incorporate LED chips mounted to die attach pads. The art continues to seek improved LEDs and solid-state lighting devices having increased light output and increased light emission efficiencies without impairing manufacturability and reliability of such devices, while providing desirable illumination characteristics capable of overcoming challenges associated with conventional lighting devices.
SUMMARY
• The present disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs), and more particularly to LED packages. LED packages as disclosed herein are configured to provide improved thermal and/or electrical coupling between LED chips and submounts or between LED chips and lead frames. In certain embodiments, LED packages include submounts incorporating electrically conductive vias, with such vias being configured to provide improved thermal contact between LED chips and submounts. LED chips may further include contacts with one or more openings that are registered with vias to provide more uniform mounting between LED chips and submounts. In certain embodiments, multiple LED chips are arranged around a thermally conductive element on a surface of a submount, and a via in the submount may be registered with the thermally conductive element. In certain embodiments, subassemblies are provided between LED chips and lead frames to improve electrical and thermal coupling. In certain embodiments, underfill materials are arranged between LED chips and lead frames to provide improved mechanical support. According to the embodiments disclosed herein, LED packages are provided with thermal capabilities that allow operation at higher powers with increased power densities.
• In one aspect, an LED package comprises: a submount comprising a first face, a second face that opposes the first face, a die attach pad on the first face, and at least one via that comprises an electrically conductive material and that extends between the first face and the second face, wherein the die attach pad is registered with the at least one via; and an LED chip comprising a contact pad that is coupled with the die attach pad, wherein the contact pad defines at least one opening that is registered with the at least one via. The die attach pad may be electrically coupled with the at least one via. In certain embodiments, each opening of the at least one opening comprises a recess having a maximum depth smaller than a thickness of the contact pad. In certain embodiments, each opening of the at least one opening comprises an aperture extending through an entire thickness of the contact pad. In certain embodiments, the at least one via comprises a plurality of vias, wherein the die attach pad is registered with the plurality of vias. In certain embodiments, the at least one opening comprises a plurality of openings that are registered with the plurality of vias. In certain embodiments, the at least one via comprises a plurality of vias that overlap with one another to form a trench via. In certain embodiments, the at least one opening comprises a trench opening that is registered with the trench via. In certain embodiments, the LED chip is one of a plurality of LED chips that are mounted on the submount; the at least one via comprises a plurality of vias; the die attach pad is one of a plurality of die attach pads on the first face; and each LED chip of the plurality of LED chips is coupled with a different die attach pad of the plurality of die attach pads, and each LED chip comprises a contact pad that defines an opening registered with a different via of the plurality of vias. The LED chip may comprise a multiple-junction LED chip that is mounted on the submount. In certain embodiments, the at least one via comprises three vias that are positioned relative to one another in the submount to form vertices of a triangle.
• In another aspect, an LED package comprises: a submount comprising a first face, a second face that opposes the first face, a first die attach pad on the first face, a second die attach pad on the first face, a first plurality of vias registered with the first die attach pad, and a second plurality of vias registered with the second die attach pad; and an LED chip comprising a primary light emitting face, a mounting face that opposes the primary light emitting face, an anode contact pad on the mounting face, and a cathode contact pad on the mounting face; wherein the anode contact pad is coupled with the first die attach pad, and the cathode contact pad is coupled with the second die attach pad. The LED package of claim B1, wherein the first plurality of vias is electrically coupled with the first die attach pad, and the second plurality of vias is electrically coupled with the second die attach pad. In certain embodiments, the anode contact pad comprises a plurality of openings, and openings of the plurality of openings are registered with vias of the first plurality of vias. In certain embodiments, the cathode contact pad comprises a plurality of openings, and openings of the plurality of openings are registered with vias of the second plurality of vias. In certain embodiments, the anode contact pad comprises a first plurality of openings, and openings of the first plurality of openings are registered with vias of the first plurality of vias; and the cathode contact pad comprises a second plurality of openings, and openings of the second plurality of openings are registered with vias of the second plurality of vias. The submount may comprise at least one additional via that is arranged outside of a mounting area defined by lateral boundaries of the LED chip. In certain embodiments, at least one via of the first plurality of vias extends into but not completely through the first die attach pad, and at least one via of the second plurality of vias extends into but not completely through the second die attach pad. The first plurality of vias and the second plurality of vias may be electrically isolated from the first die attach pad and the second die attach pad. In certain embodiments, at least one via of the first plurality of vias and/or at least one of the second plurality of vias extends in the submount at an oblique angle between the first face and the second face.
• In another aspect, an LED package comprise: a first submount comprising a first face and a second face that opposes the first face, the first submount further comprising a plurality of vias that extend between the first face and the second face; a second submount comprising a first die attach pad, wherein the first die attach pad is registered with the plurality of vias; and an LED chip comprising a first contact pad that is coupled with the first die attach pad. In certain embodiments, the second submount is arranged between the LED chip and the first submount. In certain embodiments, the plurality of vias extend less than an entire distance between the first face and the second face of the first submount. In certain embodiments, the plurality of vias extend completely through the first submount.
• In another aspect, an LED package comprises: a submount comprising a first face and a second face that opposes the first face, the submount further comprising a via that comprises a thermally conductive material and that extends between the first face and the second face; a thermally conductive element on the first face and registered with the via; and a plurality of LED chips on the first face, wherein each LED chip of the plurality of LED chips is arranged adjacent to a different lateral edge of the thermally conductive element. In certain embodiments, the via is configured with a same cross-sectional width or diameter as the thermally conductive element. In certain embodiments, the via is configured with a larger cross-sectional width or diameter than the thermally conductive element. The LED package may further comprise a package bond pad on the second face of the submount, wherein the package bond pad is registered with the via. In certain embodiments, a corner of each LED chip of the plurality of LED chips is arranged closest to a different corner of the thermally conductive element.
• In another aspect, an LED package comprises: an LED chip mounted to a lead frame; and a subassembly arranged between the LED chip and the lead frame, wherein the subassembly comprises a metal submount that is thermally coupled between the LED chip and the lead frame. In certain embodiments, the subassembly further comprises: a first die attach pad that is configured to be electrically coupled with a first contact pad of the LED chip; and a second die attach pad that is configured to be electrically coupled with a second contact pad of the LED chip. In certain embodiments, the first die attach pad and the second die attach pad are electrically coupled to different portions of the lead frame by wirebonds. In certain embodiments, the subassembly further comprises a dielectric layer arranged between the first die attach pad and the metal submount, and arranged between the second die attach pad and the metal submount. In certain embodiments, the LED chip is arranged in a flip-chip configuration on the first die attach pad and the second die attach pad. The LED package may further comprise an underfill material arranged between the subassembly and the lead frame.
• In another aspect, an LED package comprises: an LED chip mounted to a lead frame; a underfill material arranged between the LED chip and the lead frame; and an encapsulant material arranged on the LED chip and the underfill material. In certain embodiments, a first contact of the LED chip is electrically and mechanically coupled with a first lead frame portion, and a second contact of the LED chip is electrically and mechanically coupled with a second lead frame portion. In certain embodiments, the underfill material is arranged between the first lead frame portion and the second lead frame portion. In certain embodiments, the underfill material is arranged between the first contact of the LED chip and the second contact of the LED chip. In certain embodiments, the underfill material comprises light altering particles. In certain embodiments, the underfill material comprises a material with a higher durometer value on a Shore D hardness scale than the encapsulant material.
• In another aspect, an LED package comprises: a submount comprising a first face, a second face that opposes the first face, a die attach pad on the first face, and a plurality of vias registered with the die attach pad, wherein outermost vias of the plurality of vias are arranged to form vertices of a non-rectangular polygonal shape; and an LED chip comprising a primary light emitting face and a mounting face that opposes the primary light emitting face, and at least a portion of the mounting face is thermally coupled to the die attach pad. In certain embodiments, the plurality of vias are arranged in an asymmetric pattern. In certain embodiments, a spacing between adjacent vias of the plurality of vias is smaller near the center of the die attach pad than along a perimeter of the die attach pad. In certain embodiments, the plurality of vias comprises three vias that are positioned relative to one another in the submount to form vertices of a triangle.
• In another aspect, an LED package comprises: a submount comprising a first face, a second face that opposes the first face, a die attach pad on the first face, and a plurality of vias registered with the die attach pad, wherein a spacing between adjacent vias of the plurality of vias is smaller in certain areas of the die attach pad than in other areas the die attach pad; and an LED chip comprising a primary light emitting face and a mounting face that opposes the primary light emitting face, and at least a portion of the mounting face is thermally coupled to the die attach pad. In certain embodiments, the spacing between the adjacent vias of the plurality of vias is smaller near the center of the die attach pad than along a perimeter of the die attach pad. In certain embodiments, the spacing between the adjacent vias of the plurality of vias is smaller along a perimeter of the die attach pad. In certain embodiments, the plurality of vias form an array of closely spaced via clusters along the die attach pad. In certain embodiments, the die attach pad is electrically coupled with the plurality of vias. In certain embodiments, the die attach pad is electrically isolated with the plurality of vias.
• In another aspect, any one or more aspects or features described herein may be combined with any one or more other aspects or features for additional advantage.
• Other aspects and embodiments will be apparent from the detailed description and accompanying drawings.
• Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a cross-sectional view of a representative LED package that includes an LED chip mounted on a submount.
• FIG. 2A is a cross-sectional view of an LED package that includes one or more openings that are registered with vias according to embodiments disclosed herein.
• FIG. 2B is a top view of a portion of the first face of the submount ofFIG. 2A.
• FIG. 2C is a bottom view of the mounting face of the LED chip ofFIG. 2A.
• FIG. 3A is a top view of a portion of the first face of a submount that is configured for multiple LED chips or a multiple-junction LED chip.
• FIG. 3B is a bottom view of the mounting face of a multiple-junction LED chip that is configured to be mounted on the submount ofFIG. 3A.
• FIG. 4A is a top view of a portion of the first face of a submount that includes vias configured in a triangular arrangement.
• FIG. 4B is a bottom view of the mounting face of an LED chip that is configured to be mounted on the submount ofFIG. 4A.
• FIG. 5A is a cross-sectional view of an LED package that includes a plurality of vias arranged between particular die attach pads and package bond pads according to embodiments disclosed herein.
• FIG. 5B is a top view of a portion of the first face of the submount ofFIG. 5A.
• FIG. 5C is a bottom view of the mounting face of the LED chip ofFIG. 5A.
• FIG. 5D is a top view of a portion of the first face of the submount ofFIG. 5A with a different arrangement of vias.
• FIG. 5E is a top view of a portion of the first face of the submount ofFIG. 5A with a different arrangement of vias.
• FIG. 5F is a top view of a portion of the first face of the submount ofFIG. 5A with a different arrangement of vias.
• FIG. 6 is a cross-sectional view of an LED package that includes a plurality of vias arranged in a submount according to embodiments disclosed herein.
• FIG. 7A is a cross-sectional view of an LED package that includes a plurality of vias, at least some of which are arranged at oblique angles within a submount according to embodiments disclosed herein.
• FIG. 7B is a cross-sectional view of the LED package ofFIG. 7A where at least some of the plurality of vias are arranged at different oblique angles according to embodiments disclosed herein.
• FIG. 8 is a cross-sectional view of an LED package that includes a second submount arranged between an LED chip and a plurality of vias according to embodiments disclosed herein.
• FIG. 9 is a cross-sectional view of an LED package that includes die attach pads having thicknesses configured to prevent protruding vias from extending completely through the die attach pads according to embodiments disclosed herein.
• FIG. 10A is a top view of at least a portion of the first face of a submount that includes one or more trench vias according to embodiments disclosed herein.
• FIG. 10B is a bottom view of the mounting face of an LED chip that is configured to be mounted on the submount ofFIG. 10A.
• FIG. 11A is a top view of at least a portion of an LED package that includes a thermally conductive element arranged between a plurality of LED chips on a face of a submount according to embodiments disclosed herein.
• FIG. 11B is a cross-sectional view of the LED package ofFIG. 11A taken along the section line labeled11B inFIG. 11A.
• FIGS. 11C, 11D, and 11E are top views of at least portions of LED packages similar to the LED package ofFIG. 11A, but with different arrangements of LED chips on the submount.
• FIG. 12 is a cross-sectional view of an LED package that includes a lead frame according to embodiments disclosed herein.
• FIG. 13 is a cross-sectional view of an LED package that includes an underfill material configured to provide additional mechanical support between an LED chip and a lead frame.
DETAILED DESCRIPTION
• The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
• It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
• It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
• Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
• The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
• Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
• The present disclosure relates to solid-state lighting devices including light-emitting diodes (LEDs) and more particularly to LED packages. LED packages as disclosed herein are configured to provide improved thermal and/or electrical coupling between LED chips and submounts or between LED chips and lead frames. In certain embodiments, LED packages include submounts with via arrangements configured to provide improved thermal contact between LED chips and submounts. LED chips may further include contacts with one or more openings that are registered with vias to provide more uniform mounting between LED chips and submounts. In certain embodiments, multiple LED chips are arranged around a thermally conductive element on a surface of a submount, and a via in the submount may be registered with the thermally conductive element. In certain embodiments, subassemblies are provided between LED chips and lead frames to improve electrical and thermal coupling. In certain embodiments, underfill materials are arranged between LED chips and lead frames to provide improved mechanical support. According to the embodiments disclosed herein, LED packages are provided with thermal capabilities that allow operation at higher powers with increased power densities.
• An LED chip typically comprises an active LED structure or region that can have many different semiconductor layers arranged in different ways. The fabrication and operation of LEDs and their active structures are generally known in the art and are only briefly discussed herein. The layers of the active LED structure can be fabricated using known processes with a suitable process being fabrication using metal organic chemical vapor deposition. The layers of the active LED structure can comprise many different layers and generally comprise an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all of which are formed successively on a growth substrate. It is understood that additional layers and elements can also be included in the active LED structure, including, but not limited to, buffer layers, nucleation layers, super lattice structures, un-doped layers, cladding layers, contact layers, and current-spreading layers and light extraction layers and elements. The active layer can comprise a single quantum well, a multiple quantum well, a double heterostructure, or super lattice structures.
• The active LED structure can be fabricated from different material systems, with some material systems being Group III nitride-based material systems. Group III nitrides refer to those semiconductor compounds formed between nitrogen (N) and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). For Group III nitrides, silicon (Si) is a common n-type dopant and magnesium (Mg) is a common p-type dopant. Accordingly, the active layer, n-type layer, and p-type layer may include one or more layers of GaN, AlGaN, InGaN, and AlInGaN that are either undoped or doped with Si or Mg for a material system based on Group III nitrides. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other Group III-V systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.
• The active LED structure may be grown on a growth substrate that can include many materials, such as sapphire, SiC, aluminum nitride (AlN), GaN, with a suitable substrate being a 4H polytype of SiC, although other SiC polytypes can also be used including 3C, 6H, and 15R polytypes. SiC has certain advantages, such as a closer crystal lattice match to Group III nitrides than other substrates and results in Group III nitride films of high quality. SiC also has a very high thermal conductivity so that the total output power of Group III nitride devices on SiC is not limited by the thermal dissipation of the substrate. Sapphire is another common substrate for Group III nitrides and also has certain advantages, including being lower cost, having established manufacturing processes, and having good light transmissive optical properties.
• Different embodiments of the active LED structure can emit different wavelengths of light depending on the composition of the active layer and n-type and p-type layers. In some embodiments, the active LED structure emits blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm. In other embodiments, the active LED structure emits green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the active LED structure emits red light with a peak wavelength range of 600 nm to 650 nm.
• The LED chip can also be covered with one or more lumiphoric or other conversion materials, such as phosphors, such that at least some of the light from the LED chip is absorbed by the one or more phosphors and is converted to one or more different wavelength spectra according to the characteristic emission from the one or more phosphors. In some embodiments, the combination of the LED chip and the one or more phosphors emits a generally white combination of light. The one or more phosphors may include yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Ca_i-x-ySr_xEu_yAlSiN₃) emitting phosphors, and combinations thereof. Lumiphoric materials as described herein may be or include one or more of a phosphor, a scintillator, a lumiphoric ink, a quantum dot material, a day glow tape, and the like. Lumiphoric materials may be provided by any suitable means, for example, direct coating on one or more surfaces of an LED, dispersal in an encapsulant material configured to cover one or more LEDs, and/or coating on one or more optical or support elements (e.g., by powder coating, inkjet printing, or the like). In certain embodiments, lumiphoric materials may be downconverting or upconverting, and combinations of both downconverting and upconverting materials may be provided. In certain embodiments, multiple different (e.g., compositionally different) lumiphoric materials arranged to produce different peak wavelengths may be arranged to receive emissions from one or more LED chips. In some embodiments, one or more phosphors may include yellow phosphor (e.g., YAG:Ce), green phosphor (e.g., LuAg:Ce), and red phosphor (e.g., Ca_i-x-ySr_xEu_yAlSiN₃) and combinations thereof. One or more lumiphoric materials may be provided on one or more portions of an LED chip and/or a submount in various configurations. In certain embodiments, one or more surfaces of LED chips may be conformally coated with one or more lumiphoric materials, while other surfaces of such LED chips and/or associated submounts may be devoid of lumiphoric material. In certain embodiments, a top surface of an LED chip may include lumiphoric material, while one or more side surfaces of an LED chip may be devoid of lumiphoric material. In certain embodiments, all or substantially all outer surfaces of an LED chip (e.g., other than contact-defining or mounting surfaces) are coated or otherwise covered with one or more lumiphoric materials. In certain embodiments, one or more lumiphoric materials may be arranged on or over one or more surfaces of an LED chip in a substantially uniform manner. In other embodiments, one or more lumiphoric materials may be arranged on or over one or more surfaces of an LED chip in a manner that is non-uniform with respect to one or more of material composition, concentration, and thickness. In certain embodiments, the loading percentage of one or more lumiphoric materials may be varied on or among one or more outer surfaces of an LED chip. In certain embodiments, one or more lumiphoric materials may be patterned on portions of one or more surfaces of an LED chip to include one or more stripes, dots, curves, or polygonal shapes. In certain embodiments, multiple lumiphoric materials may be arranged in different discrete regions or discrete layers on or over an LED chip.
• Light emitted by the active layer or region of an LED chip is typically omnidirectional in character. For directional applications, internal mirrors or external reflective surfaces may be employed to redirect as much light as possible toward a desired emission direction. Internal mirrors may include single or multiple layers. Some multi-layer mirrors include a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is arranged between the metal reflector layer and a plurality of semiconductor layers. A passivation layer is arranged between the metal reflector layer and first and second electrical contacts, wherein the first electrical contact is arranged in conductive electrical communication with a first semiconductor layer, and the second electrical contact is arranged in conductive electrical communication with a second semiconductor layer. For single or multi-layer mirrors including surfaces exhibiting less than 100% reflectivity, some light may be absorbed by the mirror. Additionally, light that is redirected through the active LED structure may be absorbed by other layers or elements within the LED chip.
• As used herein, a layer or region of an LED is considered to be “reflective” or embody a “mirror” or a “reflector” when at least 80% of the emitted radiation that impinges on the layer or region is reflected. In some embodiments, the emitted radiation comprises visible light such as blue and/or green LEDs with or without lumiphoric materials. In other embodiments, the emitted radiation may comprise nonvisible light. For example, in the context of GaN-based blue and/or green LEDs, silver (Ag) may be considered a reflective material (e.g., at least 80% reflective). In the case of ultraviolet (UV) LEDs, appropriate materials may be selected to provide a desired, and in some embodiments high, reflectivity and/or a desired, and in some embodiments low, absorption.
• The present disclosure can be useful for LED chips having a variety of geometries, such as vertical geometry or lateral geometry. A vertical geometry LED chip typically includes anode and cathode connections on opposing sides or faces of the LED chip. A lateral geometry LED chip typically includes both anode and cathode connections on the same side of the LED chip that is opposite a substrate, such as a growth substrate. In some embodiments, a lateral geometry LED chip may be mounted on a submount of an LED package such that the anode and cathode connections are on a face of the LED chip that is opposite the submount. In this configuration, wirebonds may be used to provide electrical connections with the anode and cathode connections. In other embodiments, a lateral geometry LED chip may be flip-chip mounted on a surface of a submount of an LED package such that the anode and cathode connections are on a face of the active LED structure that is adjacent to the submount. In this configuration, electrical traces or patterns may be provided on the submount for providing electrical connections to the anode and cathode connections of the LED chip. In a flip-chip configuration, the active LED structure is configured between the substrate of the LED chip and the submount for the LED package. Accordingly, light emitted from the active LED structure may pass through the substrate in a desired emission direction. In some embodiments, the flip-chip LED chip may be configured as described in commonly-assigned U.S. Publication No. 2017/0098746, which is hereby incorporated by reference herein. In some embodiments, an LED package may be configured as set forth in the following commonly-assigned U.S. patents and U.S. publications, which are hereby incorporated by reference herein: U.S. Pat. Nos. 8,866,169; 9,070,850; 9,887,327; and U.S. Publication No. 2015/0179903.
• FIG. 1 is a cross-sectional view of arepresentative LED package10 that includes anLED chip12. TheLED chip12 includes a primarylight emitting face14 that is opposite a mountingface16. TheLED chip12 is mounted to asubmount18 such that the mountingface16 is arranged between the primarylight emitting face14 and thesubmount18. Thesubmount18 can be formed of many different materials, with a preferred material being electrically insulating. Suitable materials include, but are not limited to, ceramic materials such as aluminum oxide or alumina, AlN, or organic insulators like polyimide (PI) and polyphthalamide (PPA). In other embodiments thesubmount18 can comprise a printed circuit board (PCB), sapphire, Si, or any other suitable material. For PCB embodiments, different PCB types can be used such as standard FR-4 PCBs, metal core PCBs, or any other type of PCB. LED packages according to the present disclosure can be fabricated using a method that utilizes a submount panel sized to accommodate a plurality of submounts. Multiple LED packages can be formed on the panel, with individual packages being singulated from the panel. TheLED chip12 can be mounted to thesubmount18 using known methods and material mounting such as using conventional solder materials that may or may not contain a flux material or dispensed polymeric materials that may be thermally and electrically conductive, as well as other methods and material mounting such as solderless, direct attach, or other conventional attachment means.
• TheLED package10 further includes anencapsulant20 that may provide both environmental and/or mechanical protection for theLED chip12. Theencapsulant20 may also be referred to as an encapsulant layer. Many different materials can be used for theencapsulant20, including silicones, plastics, epoxies or glass, with a suitable material being compatible with molding processes. Silicone is suitable for molding and provides suitable optical transmission properties for light emitted from theLED chip12. In some embodiments, theencapsulant20 can be molded into the shape of alens20′. Different molding techniques may provide thelens20′ with many different shapes depending on the desired emission pattern for theLED package10. One suitable shape as shown inFIG. 1 is hemispheric, with some examples of alternative shapes being ellipsoid bullet, flat, hex-shaped and square. In certain embodiments, a suitable shape includes both curved and planar surfaces, such as a hemispheric top portion with planar side surfaces. It is understood that theencapsulant20 can also be textured to improve light extraction. In some embodiments, a portion of theencapsulant20 may form a protective layer that covers any portion of thesubmount18 that is not covered by the shape of thelens20′. For example, inFIG. 1, where the hemispherical shape of thelens20′ ends, a planar extension ofencapsulant20 material may be provided from thelens20′ to one or more perimeter edges of thesubmount18 to provide additional protection to elements on the top surface to reduce damage and contamination during subsequent processing steps and use. In certain embodiments, theencapsulant20 may include one or more lumiphoric materials or scattering particles. In other embodiments, one or more lumiphoric materials may be provided in a separate layer or layers between theLED chip12 and theencapsulant20.
• As illustrated inFIG. 1, theLED chip12 is arranged on thesubmount18 in a flip-chip configuration in certain embodiments. In this regard, theLED chip12 includes afirst contact pad22 and asecond contact pad24 on the mountingface16 that are configured to be mounted and electrically and thermally coupled to a first die attachpad26 and a second die attachpad28, respectively, that are arranged on thesubmount18. In certain embodiments, thefirst contact pad22 and thesecond contact pad24 comprise a thickness of in a range of about 1 micron (μm) to about 8 μm, or in range of about 3 μm to about 5 μm. Thefirst contact pad22 and thesecond contact pad24 may comprise different ones of an anode contact pad and a cathode contact pad for theLED chip12. In certain embodiments, the first die attachpad26 and the second die attachpad28 comprise a thickness in a range of about 1 μm to about 100 μm, or in a range of about 5 μm to about 90 μm, or in a range of about 40 μm to about 80 μm. The first die attachpad26 and the second die attachpad28 are arranged on afirst face30 of thesubmount18 that also may support theencapsulant20. Thesubmount18 includes asecond face32 that generally opposes thefirst face30. In certain embodiments, thesecond face32 of thesubmount18 includes a firstpackage bond pad34 and a secondpackage bond pad36 that are configured to receive an external electrical connection for theLED package10. For example, theLED package10 may be mounted on another board that includes electrical traces or leads that correspond with thepackage bond pads34,36.
• In order to electrically couple thepackage bond pads34,36 with theLED chip12, thesubmount18 comprises one ormore vias38 of electrically conductive material that extend between thefirst face30 and thesecond face32 of thesubmount18. In particular, thevias38 may be configured to be electrically and thermally coupled with the die attachpads26,28 and thepackage bond pads34,36. In certain embodiments, thevias38 extend completely through thesubmount18 to provide electrical connections between thepackage bond pads34,36 and the die attachpads26,28. In typical manufacturing processes, thevias38 may be formed by punching, cutting, drilling, laser cutting, or laser drilling of holes in thesubmount18, followed by plating or filling the holes with a conductive material such as copper or aluminum, among others. In certain embodiments, thevias38 may comprise a cross-sectional diameter in a range of about 20 μm to about 200 μm, or in a range of about 50 μm to about 160 μm, or in a range of about 80 μm to about 120 μm. Due to various manufacturing tolerances, the conductive material may include gaps or voids that can trap gas within thevias38. During subsequent assembly steps for theLED package10, thevias38 can be exposed to increased temperatures, such as those experienced during bonding or curing steps. Increased temperatures can cause somevias38, particularly those with the gaps or voids, to expand and push up or protrude from thesubmount18, thereby forming what may be referred to as blistered vias. As illustrated inFIG. 1, each via38 includes at least a viaportion38′ that protrudes out of thefirst face30 and through the die attachpads26,28. These protruding viaportions38′ can provide uneven surfaces for theLED chip12 to be mounted on. In this regard, the protruding viaportions38′ may prevent thecontact pads22,24 of theLED chip12 from making good bonds with the die attachpads26,28 of thesubmount18, thereby providing poor thermal and electrical coupling between theLED chip12 and thesubmount18. Additionally, gaps between thecontact pads22,24 and the die attachpads26,28 may allow material of theencapsulant20, e.g. silicone, to form between thecontact pads22,24 and the die attachpads26,28. The material of theencapsulant20 may expand during subsequent thermal cycling and can lead to theLED chip12 separating or popping off of thesubmount18.
• According to embodiments disclosed herein, an LED package may include one or more features configured to provide improved thermal and/or electrical coupling between LED chips and submounts. In certain embodiments, LED packages may be configured with one or more openings (e.g., recesses or apertures) that are registered with vias in submounts in a manner that allows the vias to expand without degrading thermal or electrical coupling. Accordingly, LED packages are provided with thermal capabilities that allow operation at higher powers with increased power densities. In certain embodiments, an LED package includes a submount comprising a first face and a second face that opposes the first face. The submount may further comprise a via that extends between the first face and the second face, and a die attach pad that is on the first face and registered with the via. An LED chip may comprise a contact pad that is coupled with the die attach pad, and the contact pad comprises an opening that is registered with the via. In this manner, the via may expand into the opening without degrading thermal or electrical coupling between the contact pad of the LED chip and the die attach pad of the submount.
• FIG. 2A is a cross-sectional view of anLED package40 that includes one ormore openings42 that are registered withvias38 according to embodiments disclosed herein. TheLED package40 includes theLED chip12 with thecontact pads22,24 coupled with the die attachpads26,28 of thesubmount18 as previously described. TheLED package40 may further include theencapsulant20, the one ormore vias38 that extend between thefirst face30 and thesecond face32 of thesubmount18, and thepackage bond pads34,36 as previously described. As illustrated inFIG. 2A, thecontact pads22,24 include theopenings42 that are registered with thevias38. In this manner, when theLED chip12 is mounted to thesubmount18, thevias38 have room to expand within theopenings42 without compromising thermal or electrical coupling between thecontact pads22,24 and the die attachpads26,28. Theopenings42 may be formed in thecontact pads22,24 by selectively removing portions of thecontact pads22,24 after they have been formed. Alternatively, theopenings42 may be formed concurrently with thecontact pads22,24 by way of selective deposition, such as deposition through a patterned mask. In certain embodiments, theopenings42 embody recesses that extend through less than an entire thickness of thecontact pads22,24, with each opening having a maximum depth smaller than a thickness of thecorresponding contact pad22,24. In other embodiments, theopenings42 may embody apertures that extend through an entire thickness of thecontact pads22,24. Theopenings42 may be configured to have a same size or a larger size than a maximum width or diameter of thevias38. In certain embodiments, theopenings42 may comprise a similar cross-sectional shape as thevias38, such as circles, ovals, squares, or rectangles, among others. In other embodiments, theopenings42 may comprise cross-sectional shapes that are different than thevias38, such as larger square or rectangular shapedopenings42 that are registered withcircular vias38.
• FIG. 2B is a top view of a portion of thefirst face30 of thesubmount18 ofFIG. 2A. As illustrated, thesubmount18 includes the first die attachpad26 that is registered with one of thevias38 and a second die attachpad28 that is registered with a different one of thevias38.FIG. 2C is a bottom view of the mountingface16 of theLED chip12 ofFIG. 2A. The first die attachpad26 and the second die attachpad28 collectively form a die attach area for theLED chip12. In particular, thefirst contact pad22 of theLED chip12 is configured for mounting with the first die attachpad26 of thesubmount18, and thesecond contact pad24 of theLED chip12 is configured for mounting with the second die attachpad28 of thesubmount18. Thecontact pads22,24 include theopenings42 as previously described. Theopenings42 are configured to be registered or aligned with thevias38 of thesubmount18 when theLED chip12 is mounted on thesubmount18. In certain embodiments, theLED chip12 may include different numbers of contact pads. For example, theLED chip12 may include a single contact pad that is registered with a single die attach pad on thesubmount18.
• According to embodiments disclosed herein, an LED package may include multiple LED chips or a multiple-junction LED chip mounted to a common submount. The multiple LED chips or the multiple-junction LED chip may include contact pads with openings that are registered with vias in the submount. In particular, each LED chip or each LED junction of a multiple-junction LED chip may include a separate contact pad that comprises an opening that is registered with a different via of the submount.
• FIG. 3A is a top view of a portion of thefirst face30 of asubmount46 that is configured for multiple LED chips or a multiple-junction LED chip. As illustrated, thesubmount46 includes a plurality of first die attach pads26-1 to26-4 and a plurality of second die attach pads28-1 to28-4. At least one via of the plurality ofvias38 may be registered with each of the first die attach pads26-1 to26-4 and each of the second die attach pads28-1 to28-4. Individual pairs of the first and second die attach pads26-1 to26-4,28-1 to28-4 (e.g., a first pair formed by the first die attach pad26-1 and the second die attach pad28-1) collectively form separate die attach areas for multiple LED chips or a multiple-junction LED chip.FIG. 3B is a bottom view of the mountingface16 of a multiple-junction LED chip50 that is configured to be mounted on thesubmount46 ofFIG. 3A. The mountingface16 includes a plurality of first contact pads22-1 to22-4 and a plurality of second contact pads24-1 to24-4. Each pair of first and second contact pads22-1 to22-4,24-1 to24-4 (e.g., a first pair formed by the first contact pad22-1 and the second contact pad24-1) is arranged to be electrically coupled with a different junction of the multiple-junction LED chip50. Different junctions may be formed by isolating separate active layers or active layer regions of the multiple-junction LED chip50. Theopenings42 are configured as previously described to be registered or aligned with thevias38 of thesubmount46. In other embodiments, multiple LED chips can be individually mounted on thesubmount46 ofFIG. 3A. Multiple LED chips may have similar structures as described for the multiple-junction LED chip50, but with separate LED chips formed along the dashed lines ofFIG. 3B. In certain embodiments, each LED chip of a plurality of LED chips comprises a separate contact pad with anopening42 that is registered with a different via38 of thesubmount46.
• According to embodiments disclosed herein, an LED package may include a submount with multiple vias configured in arrangements that allow improved mounting surfaces for LED chips. In certain embodiments, a submount for an LED package comprises vias configured in a triangular arrangement. In particular, a submount may include three vias in a triangular arrangement. As previously described, vias can sometimes expand and protrude from a surface of a submount, thereby creating uneven mounting surfaces for LED chips. By having three vias in a triangular arrangement, the vias will form an arbitrary plane such that the LED chip may be evenly supported by the three vias, regardless of any protruding height differences between the vias.
• FIG. 4A is a top view of a portion of thefirst face30 of asubmount54 that includes a plurality of vias38-1 to38-3 arranged in thesubmount54 as previously described and configured in a triangular arrangement (as indicated by the dashed lines inFIG. 4A). InFIG. 4A, one via38-1 is registered with the first die attachpad26, and the other vias38-2,38-3 are registered with the second die attachpad28. In other embodiments, the order may be reversed such that two vias38-2,38-3 are registered with the first die attachpad26 and the one via38-1 is registered with the second die attachpad28. In still other embodiments, thesubmount54 may include a single die attach pad for receiving an LED chip and the single die attach pad may be registered with the plurality of vias38-1 to38-3. As illustrated inFIG. 4A, three vias38-1 to38-3 are positioned relative to one another in thesubmount54 to form vertices of a triangle.FIG. 4B is a bottom view of the mountingface16 of anLED chip58 that is configured to be mounted on thesubmount54 ofFIG. 4A. As illustrated, thefirst contact pad22 and thesecond contact pad24 do not have theopenings42 as previously described. In this manner, thefirst contact pad22 and thesecond contact pad24 form a generally planar surface that is configured to be mounted on thesubmount54 ofFIG. 4A. If any of the vias38-1 to38-3 protrude to different heights above thesubmount54, the generally planar surface formed by thefirst contact pad22 and thesecond contact pad24 will self-level across the triangular plane formed by the heights of the three vias38-1 to38-3. In certain embodiments, thefirst contact pad22 and thesecond contact pad24 may further comprise openings that are registered with the vias38-1 to38-3 as previously described.
• According to certain embodiments disclosed herein, an LED package may include a plurality of vias in a submount that are registered between a particular die attach pad and a particular package bond pad. In certain embodiments, the plurality of vias are electrically and thermally coupled between the particular die attach pad and the particular package bond pad to form a plurality of electrically and thermally conductive paths. Additionally, the plurality of vias may be arranged in close proximity to one another and, accordingly, the vias will experience similar manufacturing conditions. In this manner, if the plurality of vias protrude out of the submount as previously described, the vias may protrude with similar heights, thereby reducing unevenness with an LED chip after mounting.
• FIG. 5A is a cross-sectional view of anLED package60 that includes a plurality ofvias38 arranged between particular die attach pads and package bond pads according to embodiments disclosed herein. TheLED package60 includes theLED chip12 with thecontact pads22,24 mounted on thesubmount18 with the die attachpads26,28 and thepackage bond pads34,36 as previously described. The encapsulant (20 ofFIG. 2A) may also be provided on theLED chip12 and thesubmount18 as previously described. Thesubmount18 further includes the plurality ofvias38 that extend between thefirst face30 and thesecond face32 of thesubmount18. Notably, an increased amount ofvias38 are provided between the second die attachpad28 and the secondpackage bond pad36. In this regard, thevias38 between thesecond contact pad24 and the secondpackage bond pad36 may be in close proximity to one another and may experience similar manufacturing conditions. Accordingly, if any of thevias38 expand or protrude from thefirst face30, the likelihood is that all of thevias38 may expand or protrude in a similar manner, thereby providing a more uniform support and contact for theLED chip12. Additionally, the increased amount ofvias38 also provides additional thermal and electrical paths for theLED chip12, thereby allowing theLED chip12 to be operated with higher powers and increased power densities. In certain embodiments, an increased amount ofvias38 may also be arranged between thefirst contact pad22 and the first die attachpad26.FIG. 5B is a top view of a portion of thefirst face30 of thesubmount18 ofFIG. 5A. As illustrated, a first plurality ofvias38aare registered with the first die attachpad26 and a second plurality ofvias38bare registered with the second die attachpad28. In certain embodiments, the second plurality ofvias38bare arranged with a shape that is the same or similar to the second die attachpad28. For example, inFIG. 5B, the second die attachpad28 is configured as a rectangular polygonal shape andoutermost vias38bof the second plurality ofvias38bare arranged to form vertices of a rectangular polygonal shape. In this regard, uniform support for the LED chip (12 ofFIG. 5A) may be provided across the second die attachpad28.FIG. 5C is a bottom view of the mountingface16 of theLED chip12 ofFIG. 5A. As with previous embodiments, thefirst contact pad22 of theLED chip12 is configured for mounting with the first die attachpad26 of thesubmount18, and thesecond contact pad24 of theLED chip12 is configured for mounting with the second die attachpad28 of thesubmount18. In certain embodiments, thefirst contact pad22 and thesecond contact pad24 form a generally planar surface that can be evenly mounted over thesubmount18. In other embodiments, thecontact pads22,24 may include a first plurality ofopenings42aand a second plurality ofopenings42b, respectively, as previously described and indicated by dashed lines inFIG. 5C. In certain embodiments, theopenings42a,42bare configured to be registered or aligned respectively with the vias38a,38bof thesubmount18 when theLED chip12 is mounted on thesubmount18.
• FIGS. 5D and 5E are various top views of a portion of thefirst face30 of thesubmount18 ofFIG. 5A with different arrangements of the second plurality ofvias38bthat are registered with the second die attachpad28. As illustrated, the first plurality ofvias38aare registered with the first die attachpad26 as previously described. In certain embodiments,outermost vias38bof the second plurality ofvias38bare arranged to form vertices of a non-rectangular polygonal shape. InFIG. 5D,outermost vias38bof the second plurality ofvias38bare arranged to form vertices of a trapezoidal shape. InFIG. 5E,outermost vias38bof the second plurality ofvias38bare arranged to form vertices of a parallelogram. While trapezoid and parallelogram shapes are illustrated inFIGS. 5D and 5E,outermost vias38bof the second plurality ofvias38bmay form other non-rectangular shapes. In this regard, the second plurality ofvias38bmay be arranged with non-rectangular polygonal shapes to provide various mounting planes for the LED chip (12 ofFIG. 5A). In certain embodiments, theoutermost vias38bof the second plurality ofvias38bcomprise three vias that are positioned relative to one another in thesubmount18 to form vertices of a triangle. In certain embodiments, the second plurality ofvias38bmay be arranged in an asymmetric pattern. As previously described, the second plurality ofvias38bmay be configured to provide electrical coupling and/or thermal coupling between the second die attachpad28 and the second package bond pad (36 ofFIG. 5A). As shown inFIG. 5F, spacing betweenadjacent vias38bof the second plurality ofvias38bis smaller near the center of the second die attachpad28 than along a perimeter of the die attachpad28. The smaller spacing of theadjacent vias38bof the second plurality ofvias38bmay provide localized areas with increased thermal dissipation capabilities. InFIG. 5F, the smaller spacing is provided near the center of the second die attachpad28, where heat may tend to concentrate in higher amounts during operation. Depending on the particular application and heat profile of a particular LED package, smaller spacing betweenadjacent vias38bof the second plurality ofvias38bmay be arranged in other locations, such as along the perimeter of the second die attachpad28, or an array of closely spaced via clusters arranged across the second die attachpad28.
• According to certain embodiments disclosed herein, an LED package may include a submount with vias configured in arrangements that provide improved thermal dissipation for LED chips. In certain embodiments, at least some of the vias may be electrically isolated from LED chips mounted on the submount. In this regard, electrical connections may be provided to the LED chips by other arrangements, such as wire bonds or other die attach pads that have electrically coupled vias. The electrically isolated vias may be provided in the submount in areas that experience high amounts of heat during operation, such as below an LED chip mounted thereon. The vias may be arranged to extend less than an entire distance through the submount. The vias may be arranged perpendicular to a first face of the submount, or the vias may be arranged at oblique angles within the submount to dissipate heat in more lateral directions. In certain embodiments, a second submount may be arranged between an LED chip and a first submount that includes a plurality of vias.
• FIG. 6 is a cross-sectional view of anLED package62 that includes a plurality ofvias38a,38barranged in thesubmount18 according to embodiments disclosed herein. TheLED package62 includes theLED chip12 with thecontact pads22,24 mounted on thesubmount18 with the die attachpads26,28 and thepackage bond pads34,36 as previously described. The encapsulant (20 ofFIG. 2A) may also be provided on theLED chip12 and thesubmount18 as previously described. Thesubmount18 further includes a first plurality ofvias38athat are registered with the first die attachpad26 and a second plurality ofvias38bthat are registered with the second die attachpad28. Notably, the vias38a,38bare configured to extend less than an entire distance between thefirst face30 and thesecond face32 of thesubmount18. In certain embodiments, the first plurality ofvias38aand the second plurality ofvias38bare electrically isolated from the first die attachpad26 and the second die attachpad28. In this manner, while not electrically coupled to theLED chip12, the vias38a,38bare configured to dissipate heat that radiates into thesubmount18 away from theLED chip12. In particular, the vias38a,38bmay be configured to dissipate heat through thesubmount18 and to athermal pad61. Thethermal pad61 may be arranged on thesecond face32 of thesubmount18. Thethermal pad61 may comprise one or more metal layers, similar to thepackage bond pads34,36. In certain embodiments, thepackage bond pads34,36 are electrically coupled with the die attachpads26,28 by way of electrically conductive vias orpaths63a,63bthrough thesubmount18. The die attachpads26,28 may be configured to extend on thefirst face30 to lateral edges of thesubmount18 to provide increased surface area for thermal dissipation on thefirst face30. As illustrated, the vias38a,38bare configured in a direction perpendicular to thefirst face30 of thesubmount18. Accordingly, heat may be dissipated through a shorter path through thesubmount18, where in turn, the heat may be dissipated laterally through thethermal pad61 or into another material on which theLED package62 may be mounted, such as a fixture housing, a heat sink, or the like.
• FIG. 7A is a cross-sectional view of anLED package64 that includes a plurality ofvias38, at least some of which are arranged at oblique angles within thesubmount18 according to embodiments disclosed herein. TheLED package64 includes theLED chip12 with thecontact pads22,24 mounted on thesubmount18 with the die attachpads26,28, thepackage bond pads34,36, and the electrically conductive vias orpaths63a,63bas previously described. The encapsulant (20 ofFIG. 2A) may also be provided on theLED chip12 and thesubmount18 as previously described. Notably, at least one of the plurality ofvias38 extends in thesubmount18 at an oblique angle from thefirst face30 to thesecond face32. In this manner heat may be dissipated away from theLED chip12 in multiple directions through thesubmount18, including along thermal paths with oblique angles where heat dissipates laterally away from theLED chip12 as it dissipates through thesubmount18. The plurality ofvias38 may be thermally coupled with thethermal pad61 as previously described. In this regard, heat that may be concentrated directly under theLED chip12 may be distributed to thethermal pad61 with increased lateral spreading.
• FIG. 7B is a cross-sectional view of theLED package64 ofFIG. 7A where at least some of the plurality ofvias38 are arranged at different oblique angles within thesubmount18 according to embodiments disclosed herein. TheLED package64 includes theLED chip12 with thecontact pads22,24 mounted on thesubmount18 with the die attachpads26,28, thepackage bond pads34,36, and the electrically conductive vias orpaths63a,63bas previously described. The encapsulant (20 ofFIG. 2A) may also be provided on theLED chip12 and thesubmount18 as previously described. Notably, at least one of the plurality ofvias38 extends in thesubmount18 at an oblique angle from thefirst face30 to thesecond face32. In this manner heat may be dissipated in multiple directions through thesubmount18, including along thermal paths at oblique angles where heat dissipates laterally toward thethermal pad61 as it dissipates through thesubmount18. In this regard, heat that may spread laterally along thefirst face30 may be directed through thesubmount18 and to thethermal pad61.
• FIG. 8 is a cross-sectional view of anLED package66 that includes asecond submount68 arranged between theLED chip12 and the plurality ofvias38a,38baccording to embodiments disclosed herein. TheLED package66 includes theLED chip12 with thecontact pads22,24 and thesubmount18, also referred to as afirst submount18, with thepackage bond pads34,36 as previously described. The encapsulant (20 ofFIG. 2A) may also be provided on theLED chip12 and thesecond submount68 as previously described. Thesecond submount68 is arranged between theLED chip12 and thefirst submount18, and thesecond submount68 accordingly includes the die attachpads26,28 as previously described. Thefirst submount18 includes the first plurality ofvias38athat are registered with the first die attachpad26 and the second plurality ofvias38bthat are registered with the second die attachpad28 as previously described. In certain embodiments, the vias38a,38bextend less than an entire distance between thefirst face30 and thesecond face32 of thefirst submount18. In other embodiments, the vias38a,38bmay extend completely through thefirst submount18. Notably, thesecond submount68 provides mechanical and electrical isolation between the vias38a,38band the die attachpads26,28. In this regard, the die attachpads26,28 and theLED chip12 are buffered from any expanding or protruding of the vias38a,38bthat may occur. Additionally, the vias38a,38bare still configured to dissipate heat from theLED chip12 to thethermal pad61. InFIG. 8, the electricallyconductive paths63a,63bmay be arranged through both of thefirst submount18 and thesecond submount68 between the die attachpads26,28 and thepackage bond pads34,36.
• FIG. 9 is a cross-sectional view of anLED package70 that includes first and second die attachpads26,28 having thicknesses configured to prevent protruding vias from extending completely through the die attachpads26,28 according to embodiments disclosed herein. TheLED package70 includes theLED chip12 with thecontact pads22,24 mounted on thesubmount18 with the die attachpads26,28 and thepackage bond pads34,36 as previously described. The encapsulant (20 ofFIG. 2A) may also be provided on theLED chip12 and thesubmount18 as previously described. The first plurality ofvias38aare registered with the first die attachpad26 and the second plurality ofvias38bare registered with the second die attachpad28 as previously described. InFIG. 9, the die attachpads26,28 comprise increased thicknesses such that any expanding or protruding of the vias38a,38bmay extend less than an entire distance through either of the die attachpads26,28. In this manner, good thermal and electrical contact between thecontact pads22,24 and the die attachpads26,28 is maintained. In certain embodiments, the first die attachpad26 and the second die attachpad28 comprise a thickness that is at least twice as high as previously described. For example, in certain embodiments, the thickness of the die attachpads26,28 can be up to about 200 μm, or in a range of about 10 μm to about 180 μm, or in a range of about 80 μm to about 160 μm. In certain embodiments, thesubmount18 comprises one or moreadditional vias38cthat are arranged outside of a mounting area defined by lateral boundaries of theLED chip12. In this regard, additional thermally conductive paths are provided so heat that may dissipate laterally in the die attachpads26,28 can in turn dissipate through thesubmount18 outside of the mounting area of theLED chip12.
• According to certain embodiments disclosed herein, an LED package may include a submount with vias configured in arrangements that provide improved thermal dissipation for LED chips. In certain embodiments, at least some of the vias may be arranged in close proximity to one another in a manner that certain vias overlap with one another to form a trench via in the submount. In this manner, a trench via provides a larger area for heat that may be dissipated in localized areas of the submount. In certain embodiments, a submount may include combinations of individual vias and trench vias. For example, one or more trench vias may be arranged in a submount underneath a mounting area for an LED chip and other individual vias may be arranged in other areas of the submount. Accordingly, positions of vias and trench vias may be tailored within submounts to accommodate different heat profiles generated by different LED packages.
• FIG. 10A is a top view of a portion of thefirst face30 of asubmount74 that includes one or more trench vias76 according to embodiments disclosed herein. The trench vias76 may be formed by arranging multiple vias in close proximity to one another in a manner that certain vias overlap with one another to form the one or more trench vias76 in the submount. By way of example, the trench vias76 illustrated inFIG. 10A are formed by arranging five vias in close proximity to one another such that diameters or widths of the five vias overlap, thereby forming each trench via76 that is continuous in thesubmount74. As illustrated, each trench via76 may comprise multiple curved edges corresponding to the five vias that overlap. While the trench vias76 are illustrated as linear inFIG. 10A, in certain embodiments trench vias76 may comprise one or more arcs or bends to form various nonlinear shapes in thesubmount74. Trench vias76 with nonlinear shapes may be formed by arranging multiple vias in close proximity to one another in nonlinear configurations. In certain embodiments, the trench vias76 may be formed by other techniques, including continuously cutting or drilling a desired shape, e.g. linear or nonlinear, in thesubmount74. In this manner, the trench vias76 may be configured with edges that are different than the edges formed by overlapping vias as illustrated inFIG. 10A. For example, trench vias76 may include elongated ovals, elongated rectangles, linear shapes, and nonlinear shapes with linear or nonlinear edges. The trench vias76 provide localized areas with increased thermally conductive material for heat dissipation. InFIG. 10A, one of the trench vias76 is registered with the first die attachpad26, and another one oftrench vias76 is registered with the second die attachpad28 of thesubmount74.FIG. 10B is a bottom view of the mountingface16 of anLED chip78 that is configured to be mounted on thesubmount74 ofFIG. 10A. In certain embodiments, thefirst contact pad22 and thesecond contact pad24 of theLED chip78 comprise correspondingtrench openings80. Thetrench openings80 may be formed by overlapping openings or by a single continuous opening. When theLED chip78 is mounted on thesubmount74 ofFIG. 10A, thetrench openings80 are configured to be registered with the trench vias76 ofFIG. 10A.
• According to certain embodiments disclosed herein, LED packages with multiple LED chips may include one or more features configured to provide improved thermal and/or electrical coupling between the multiple LED chips and submounts. In certain embodiments, it is desirable for multiple LED chips to be mounted on a submount in close proximity to one another. In this manner, when the multiple LED chips are electrically activated, the multiple LED chips may appear as a larger emitting area for an LED package that is configured to operate at high output powers with increase power densities. The multiple LED chips may be configured to all generate the same color, or one or more of the LED chips may be configured to generate different colors. For LED packages with LEDs configured to generate different colors, having the multiple LEDs in close proximity to one another may additionally provide improved color mixing or provide an emitting area or a pixel that is capable of emitting different colors. When multiple LED chips are arranged in close proximity to one another, heat tends to cluster in areas of the submount that are central to the LED chips, thereby limiting operating powers and efficiencies of the LED chips. In certain embodiments, at least one thermally conductive element may be arranged between the multiple LED chips on a submount. The thermally conductive element may be positioned centrally to the multiple LED chips in areas where heat generation is the highest. In certain embodiments, the submount may further comprise a thermally conductive via that is registered with the thermally conductive element. In this manner, heat that tends to cluster between multiple LED chips may have a thermally conductive path away from the multiple LED chips.
• FIG. 11A is a top view of at least a portion of anLED package82 that includes a thermallyconductive element84 arranged between a plurality of LED chips86-1 to86-4 on a face of asubmount88 according to embodiments disclosed herein. As illustrated, the plurality of LED chips86-1 to86-4 are arranged on thefirst face30 of thesubmount88 in close proximity to one another. The LED chips86-1 to86-4 may all be configured to generate the same color of light, such as a white, or the LED chips86-1 to86-4 may be separately configured to generate different colors of light, such as different combinations of white, red, blue, and green light. The thermallyconductive element84 is arranged on thefirst face30 and centrally positioned with regard to the LED chips86-1 to86-4. In certain embodiments, each LED chip of the LED chips86-1 to86-4 is arranged adjacent to a different lateral edge of the thermallyconductive element84. In this manner, heat generated by each of the LED chips86-1 to86-4 may conduct into the thermallyconductive element84. As illustrated inFIG. 11A, in order for all of the LED chips86-1 to86-4 to be arranged adjacent a different lateral edge of the thermallyconductive element84, the LED chips86-1 to86-4 are arranged in a pinwheel configuration where a corner of each of the LED chip86-1 to86-4 is arranged closest to a different corner of the thermallyconductive element84. In certain embodiments, thesubmount88 comprises a via90 that is thermally conductive and registered with the thermallyconductive element84. InFIG. 11A, the via90 is illustrated with dashed lines to indicate it may not be visible in the top view. In certain embodiments, the via90 is configured with a same cross-sectional width or diameter as the thermallyconductive element84. In other embodiments, the via90 may be configured with a cross-sectional width or diameter that is larger or smaller than the thermallyconductive element84. InFIG. 11A, the dashed lines indicate the via90 has a larger cross-sectional width or diameter and may accordingly provide increased heat dissipation for the LED chips86-1 to86-4. In certain embodiments, the configuration of the LED chips86-1 to86-4, the thermallyconductive element84, and the via90 illustrated inFIG. 11A may be replicated and repeated across a larger area of thesubmount88 to form an LED array.
• FIG. 11B is a cross-sectional view of theLED package82 taken along the section line labeled11B inFIG. 11A. The LED chips86-1 and86-3 are visible in this cross-sectional view and are arranged adjacent to different lateral edges of the thermallyconductive element84. As illustrated, the via90 extends between thefirst face30 and thesecond face32 of thesubmount88. Apackage bond pad92 is configured on thesecond face32 of thesubmount88 and registered with the via90. In this manner, a thermally conductive path is provided from the LED chips86-1,86-3, through the thermallyconductive element84 and the via90, and to thepackage bond pad92. As previously described and indicated by the dashed lines inFIG. 11B, the via90 may comprise a cross-sectional width or diameter that is the larger than a cross-sectional width or diameter of the thermallyconductive element84.
• FIGS. 11C, 11D, and 11E are top views ofLED packages82 similar to theLED package82 ofFIG. 11A, but with different arrangements of LED chips on thesubmount88. InFIG. 11C, the plurality of LED chips86-1 to86-4 are arranged such that a corner of each of the LED chips86-1 to86-4 is arranged closest to a different corner of the thermallyconductive element84. Rather than the pinwheel arrangement illustrated inFIG. 11A, the LED chips86-1 to86-4 are arranged outwardly from the thermallyconductive element84 and away from lateral edges of the thermallyconductive element84. In this configuration, the LED chips86-1 to86-4 are spaced further from one another around the thermallyconductive element84. In this manner, heat from each LED chip86-1 to86-4 has a further distance to travel to reach a different one of the LED chips86-1 to86-4. Heat may still tend to concentrate in positions central to the LED chips86-1 to86-4 and, accordingly, the thermallyconductive element84 and the via90 are configured to provide a thermally conductive path away from the LED chips86-1 to86-4 and through thesubmount88. InFIG. 11D, three LED chips86-1 to86-3 are arranged along or adjacent to three different lateral edges of the thermallyconductive element84. InFIG. 11E, two LED chips86-1,86-2 are arranged along or adjacent to two different lateral edges of the thermallyconductive element84. In certain embodiments, the two LED chips86-1,86-2 are arranged along or adjacent to two opposing lateral edges of the thermallyconductive element84. InFIG. 11D andFIG. 11E, the thermallyconductive element84 and the via90 are configured to provide thermally conductive paths as previously described.
• According to certain embodiments disclosed herein, LED packages are configured to provide improved thermal and/or electrical coupling between LED chips and lead frames. In certain embodiments, an LED chip is arranged in a flip-chip configuration on a subassembly that is then mounted to a lead frame in an LED package. The subassembly may comprise one or more die attach pads for the LED chip, one or more dielectric layers, and one or more thermally conductive layers. The subassembly may provide a planar surface for mounting with the lead frame, thereby providing improved thermal coupling between the LED chip and the lead frame. In certain embodiments, an underfill material may be arranged between the lead frame and the LED chip or the subassembly to provide improved mechanical support between the LED chip and the lead frame.
• FIG. 12 is a cross-sectional view of anLED package94 that includes alead frame96a,96baccording to embodiments disclosed herein. TheLED package94 includes theLED chip12 withcontact pads22,24 as previously described. TheLED chip12 is mounted over thelead frame96a,96b. A firstlead frame portion96amay comprise an anode or a cathode for theLED package94, and a secondlead frame portion96bmay comprise the other of an anode or a cathode of theLED package94. The firstlead frame portion96ais electrically isolated from the secondlead frame portion96b. Thelead frame96a,96bis a structure typically formed of metal, such as copper, copper alloys, or other conductive metals. Thelead frame96a,96bmay initially be part of a larger metal structure that is singulated during manufacturing of LED packages. In certain embodiments of theLED package94, an insulatingmaterial98 is formed to surround portions of thelead frame96a,96b. In certain embodiments, the insulatingmaterial98 is formed on thelead frame96a,96bbefore singulation so that the individuallead frame portions96a,96bmay be electrically isolated from one another and mechanically supported in theLED package94. The insulatingmaterial98 may form reflective sidewalls of a cup or a recess in theLED package94 where theLED chip12 is mounted to thelead frame96a,96b. Thelead frame portions96a,96b, which may respectively form the anode and cathode for theLED package94, may be configured to protrude or be accessible outside of the insulatingmaterial98 to provide external electrical connections for theLED package94. Anencapsulant material100, such as silicone or epoxy, may fill the cup or recess to encapsulate theLED chip12. In certain embodiments, asubassembly102 is arranged between theLED chip12 and thelead frame96a,96b. Thesubassembly102 may comprise first and second die attachpads104,106 that are configured to be electrically coupled to different ones of thecontact pads22,24 of theLED chip12. In this manner, theLED chip12 may be arranged in a flip-chip configuration on the first die attachpad104 and the second die attachpad106. Thesubassembly102 may further comprise asubmount108 that is mounted to at least onelead frame portion96b. In certain embodiments, thesubmount108 comprises a thermally conductive material that is configured to provide a thermally conductive path from theLED chip12 to the at least onelead frame portion96b. In certain embodiments, thesubmount108 comprises a metal with a thermal conductivity that is higher than other submount materials, such as aluminum oxide, alumina, AlN, PCBs, sapphire, Si, or SiC. One or moredielectric layers110 may be provided between the die attachpads104,106 and thesubmount108 to provide electrical insulation. Thesubassembly102 may further provide a uniform mounting surface that may be mounted to at least one of thelead frame portions96a,96b(96binFIG. 12). Without thesubassembly102, theLED chip12 may be flip-chip mounted directly to thelead frame96a,96bsuch that thefirst contact pad22 is electrically and mechanically coupled to the firstlead frame portion96a, and thesecond contact pad24 is electrically and mechanically coupled to the secondlead frame portion96b. Due to manufacturing variances common to lead frames, the firstlead frame portion96amay not be completely planar with the secondlead frame portion96b. In this manner, if theLED chip12 is directly flip-chip mounted, uneven surfaces of thelead frame portions96a,96bmay prevent theLED chip12 from making sufficient electrical and thermal contact. In order to provide electrical connections with theLED chip12,different wire bonds112 may electrically couple the firstlead frame portion96ato the first die attachpad104 and the secondlead frame portion96bto the second die attachpad106.
• FIG. 13 is a cross-sectional view of anLED package114 that includes anunderfill material116 configured to provide additional mechanical support between theLED chip12 and thelead frame96a,96b. As illustrated, theLED chip12 is flip-chip mounted to thelead frame96a,96bsuch that thefirst contact pad22 is electrically and mechanically coupled to the firstlead frame portion96a, and thesecond contact pad24 is electrically and mechanically coupled to the secondlead frame portion96b. Theunderfill material116 is arranged between theLED chip12 and thelead frame96a,96bto provide additional mechanical support for theLED chip12 to reduce the likelihood theLED chip12 becomes separated from thelead frame96a,96bduring operation. In certain embodiments, theunderfill material116 is arranged between the firstlead frame portion96aand the secondlead frame portion96b. Theunderfill material116 may also be arranged between thefirst contact pad22 and thesecond contact pad24 of theLED chip12 and between lateral edges of theLED chip12 and thelead frame96a,96b. After forming theunderfill material116, theencapsulant material100 as previously described may be arranged between sidewalls formed by the insulatingmaterial98. In certain embodiments, theunderfill material116 comprises a material with a high durometer value on a Shore hardness scale (e.g., a high durometer silicone material). A material with a high durometer value, or hardness, in theunderfill material116 provides mechanical stability or anchoring for theLED chip12. For example, theunderfill material116 may comprise a material, such as silicone, with a Shore D hardness scale durometer value of at least 40. In further embodiments, theunderfill material116 may comprise a material with a Shore D hardness scale durometer value in a range of from about 40 to about 100 or in a range from about 60 to about 80. In certain embodiments, theunderfill material116 includes a silicone material with a hardness that is higher than a silicone material of theencapsulant material100. In other embodiments, theunderfill material116 comprises epoxy. In still further embodiments, theunderfill material116 comprises light altering particles, such as titanium dioxide (TiO₂) particles suspended in a silicone binder. In this manner, light generated by theLED chip12 that travels in directions toward thelead frame96a,96bmay be redirected out of theLED package114.
• Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (21)

1. A light emitting diode (LED) package comprising:

an LED chip mounted to a lead frame;

a underfill material arranged between the LED chip and the lead frame; and

an encapsulant material arranged on the LED chip and the underfill material.

2. The LED package ofclaim 1, wherein a first contact of the LED chip is electrically and mechanically coupled with a first lead frame portion, and a second contact of the LED chip is electrically and mechanically coupled with a second lead frame portion.

3. The LED package ofclaim 2, wherein the underfill material is arranged between the first lead frame portion and the second lead frame portion.

4. The LED package ofclaim 2, wherein the underfill material is arranged between the first contact of the LED chip and the second contact of the LED chip.

5. The LED package ofclaim 1, wherein the underfill material is arranged between lateral edges of the LED chip and the lead frame.

6. The LED package ofclaim 1, wherein the underfill material comprises light-altering particles.

7. The LED package ofclaim 6, wherein the light-altering particles comprise titanium dioxide (TiO₂) particles that are suspended in a binder.

8. The LED package ofclaim 7, wherein the binder comprises silicone.

9. The LED package ofclaim 1, wherein the underfill material comprises epoxy.

10. The LED package ofclaim 1, wherein the underfill material comprises a material with a higher durometer value on a Shore D hardness scale than the encapsulant material.

11. The LED package ofclaim 1, wherein the underfill material comprises a material with a durometer value on a Shore D hardness scale of at least 40.

12. The LED package ofclaim 11, wherein the durometer value is in a range from 40 to 100.

13. The LED package ofclaim 1, further comprising an insulating material on the lead frame, wherein the insulating material forms sidewalls of a cup in which the LED chip is arranged, and wherein the underfill material is arranged between the sidewalls of the cup.

14. A light emitting diode (LED) package comprising:

an LED chip mounted to a lead frame; and

a subassembly arranged between the LED chip and the lead frame, wherein the subassembly comprises a metal submount that is thermally coupled between the LED chip and the lead frame.

15. The LED package ofclaim 14, wherein the subassembly further comprises:

a first die attach pad that is configured to be electrically coupled with a first contact pad of the LED chip; and

a second die attach pad that is configured to be electrically coupled with a second contact pad of the LED chip.

16. The LED package ofclaim 15, wherein the first die attach pad and the second die attach pad are electrically coupled to different portions of the lead frame by wirebonds.

17. The LED package ofclaim 15, wherein the subassembly further comprises a dielectric layer arranged between the first die attach pad and the metal submount and arranged between the second die attach pad and the metal submount.

18. The LED package ofclaim 15, wherein the LED chip is arranged in a flip-chip configuration on the first die attach pad and the second die attach pad.

19. The LED package ofclaim 14, further comprising an underfill material arranged between the subassembly and the lead frame.

20. The LED package ofclaim 14, further comprising an insulating material on the lead frame, wherein the insulating material forms sidewalls of a cup in which the LED chip and the subassembly are arranged.

21-39. (canceled)

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