US20220020705A1 - Semiconductor wafer thinned by stealth lasing - Google Patents

Abstract

A semiconductor wafer thinned by a stealth lasing process, and semiconductor dies formed therefrom. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by focusing a laser at discrete points in the wafer substrate beneath the surface of the wafer. Upon completion of stealth lasing in one or more planar layers in the substrate, a portion of the substrate may be removed, leaving the wafer thinned to a desired final thickness.

Description

BACKGROUND
• The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, cellular telephones and solid-state drives.
• Wafers currently are shipped from the wafer fab with a typical thickness of 760 microns to prevent damage during transport, and then thinned once the individual semiconductor dies are defined within the wafer. In order to maximize storage capacity for a given form factor storage device, storage device semiconductor dies, and the wafers from which they are made, are being fabricated to ever-decreasing thicknesses. Currently, wafers are being thinned for example to 36 microns, 25 microns and thinner.
• A popular method of thinning semiconductor wafers involves a backgrinding process where the back, inactive surface of the wafer is thinned using a number of grinding wheels while the front, active surface of the wafer is covered by protective tape and supported on a chuck. Conventional backgrinding processes have several disadvantages, including for example exerting forces on the wafer that may generate cracks, especially given the current fragile thicknesses of semiconductor wafers. Cracked dies have to be discarded, thus reducing yield. Moreover, detection of cracks also requires an additional screening/inspection step, adding to fabrication costs and processing time. Conventional backgrinding processes further generate debris and foreign materials that can also cause cracks and otherwise impair the dies on the wafers.
DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a flowchart for forming a semiconductor wafer and semiconductor dies according to embodiments of the present technology.
• FIG. 2 is a front view of a semiconductor wafer showing a first major surface of the wafer.
• FIG. 3 is an enlarged cross-sectional edge view showing the circuit layer within a semiconductor die.
• FIG. 4 is a perspective view of a stealth lasing process for thinning a semiconductor wafer according to embodiments of the present technology.
• FIG. 5 is a cross-sectional view a stealth lasing process for thinning a semiconductor wafer according to embodiments of the present technology.
• FIG. 6 is an enlarged cross-sectional view of a section of a wafer undergoing a stealth lasing process for thinning a semiconductor wafer according to embodiments of the present technology.
• FIG. 7 is a perspective view of a single laser focus zone created by a stealth lasing process for thinning a semiconductor wafer according to embodiments of the present technology.
• FIG. 8 is an edge view of a wafer after a stealth lasing process according to embodiments of the present technology.
• FIG. 9 is an edge view of thinned wafer and removal of a substrate layer of the wafer according to embodiments of the present technology.
• FIG. 10 is a perspective view of a die cut from a wafer thinned by a stealth lasing process according to embodiments of the present technology.
DETAILED DESCRIPTION
• The present technology will now be described with reference to the figures, which in general, relate to a semiconductor wafer thinned by a stealth lasing process, and semiconductor dies cut therefrom. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by focusing a laser at discrete points in the wafer substrate beneath the surface of the wafer. The discrete focal points of the laser are provided in one or more planes parallel to the front and back surfaces of the wafer. Upon completion of stealth lasing in one or more planar layers in the substrate, a portion of the substrate may be removed, leaving the wafer thinned to a desired final thickness. In embodiments, the wafer may then undergo a polishing step, and may thereafter be diced into individual semiconductor dies.
• It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.
• The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal,” and forms thereof, as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±5 um
• An embodiment of the present technology will now be explained with reference to the flowchart ofFIG. 1, and the views ofFIGS. 2-10. Referring initially to the flowchart ofFIG. 1, asemiconductor wafer100 may start as an ingot of wafer material, which may be formed instep200. In one example, the ingot from which thewafers100 are formed may be monocrystalline silicon grown according to either a Czochralski (CZ) or floating zone (FZ) process. However,wafer100 may be formed of other materials and by other processes in further embodiments.
• Instep204, thesemiconductor wafer100 may be cut from an ingot and polished on both the first major surface102 (FIG. 2), and second major surface104 (FIG. 4)opposite surface102, to provide smooth surfaces. Instep206, the firstmajor surface102 may undergo various processing steps to divide thewafer100 into respective semiconductor dies106 (one of which is numbered inFIG. 2), and to form integrated circuits of the respective semiconductor dies106 on and/or in the firstmajor surface102.
• FIG. 3 is a cross-sectional side view of an exemplary semiconductor die106 of thewafer100 showing theintegrated circuit layer110 formed in asilicon substrate112.Integrated circuit layer110 may in general include integratedcircuits114 electrically coupled to surfacedie bond pads116 bymetallization layers118. The integratedcircuits114 may be formed by various processes including for example deposition, patterning and doping of metals, metal oxides and silicon.
• After formation of the integratedcircuits114,metallization layers118 may be defined includingmetal interconnects120 andvias124 layered sequentially in adielectric film128. As is known in the art, themetal interconnects120,vias124 anddielectric film128 may be formed for example by damascene processes a layer at a time using photolithography and thin-film deposition. Themetal interconnects120 andvias124 may be used to form conductive nodes for transferring signals and voltages between thedie bond pads116 and integratedcircuits114. Apassivation layer130 may be formed on top of the upperdielectric film layer128. Thepassivation layer130 may be etched to expose the diebond pads116.
• In embodiments, the semiconductor dies106 may for example be flash memory dies such as 2D NAND flash memory or 3D BiCS (Bit Cost Scaling), V-NAND or other 3D flash memory, but other types ofdies106 may be used. These other types of semiconductor dies include but are not limited to RAM, a controller, an SOC (system on a chip), a processor or other types of semiconductor dies.
• It is known to create a single integrated memory die module comprised of a first semiconductor die including the memory array, and a second semiconductor die including the logic circuit such as CMOS integrated circuits. An example of such an integrated memory die module is disclosed in Published U.S. Patent Application No. U.S. 2019/0341375, entitled “Bifurcated Memory Die Module Semiconductor Device.”Dies106 may further be from a wafer of such bifurcated memory array semiconductor dies, or from a wafer of such bifurcated CMOS logic circuit dies.
• The number ofdies106 shown onwafer100 inFIG. 2 is for illustrative purposes, andwafer100 may include more semiconductor dies106 than are shown in further embodiments. Similarly, the number ofbond pads116 on eachsemiconductor die106 is shown for illustrative purposes, and each die106 may include more die bond pads than are shown in further embodiments.
• After formation of theintegrated circuit layer110 instep206, a layer of tape may be laminated onto the active,major surface102 instep210. Thewafer100 may then be turned over and thinned instep212. In accordance with aspects of the present technology, the second surface may be lased by performing a stealth lasing step to thin the wafer as will now be explained with reference toFIGS. 4-9. Referring to the perspective view ofFIG. 4, thewafer100 may be supported on a chuck or other support surface (not shown) with the laminatedactive surface102 facing the chuck and the secondmajor surface104 facing upward. Alaser150 may then emit apulsed laser beam152 at a wavelength that transmits through the secondmajor surface104 of thewafer100, for example at infrared or near-infrared wavelengths. The pulsed laser beam may be focused to a point beneath the wafer'ssurface104 using an optical system, for example including one or morecollimating lenses156.
• Referring now to the cross-sectional edge view ofFIG. 5, when thelaser beam152 hits the secondmajor surface104, the beam refracts due to light in the laser beam slowing as it passes into thesilicon substrate112. The amount of refraction may vary depending on the refractive index of thesubstrate112 material.FIG. 6 is an enlarged view of a section ofsubstrate112 within the dashed oval ofFIG. 5. As shown inFIGS. 5 and 6, the collimating lens154 causes thebeam152 to converge to afocal point160 where the energy of thelaser beam152 is most concentrated. When thelaser beam152 hits a peak power density at thefocal point160, thesubstrate112 absorbs the energy, and the area around the focal point is vaporized, creating avoid162 around the focal point.
• In particular, as thebeam152 converges above thefocal point160, and diverges below thefocal point160, the beam will be sufficiently concentrated, and the energy high enough, above and below the focal point to vaporize the substrate material along a predefined height. That height is shown by H in the perspective view of asingle void162 inFIG. 7. In thelaser beam152 above and below thevoid162, the energy of thelaser beam152 is sufficiently defocused so as to leave thesubstrate112 intact. The void162 will also have a diameter, D, which is a function of the void height, H, and the convergence angle of thelaser beam152 in thesubstrate112, after refraction.
• The dimensions H and D of a void162 may be controlled by a variety of factors, includinglaser150 peak power intensity,laser beam152 diameter, the convergence angle created by thecollimating lens156 and the angle of refraction of thesubstrate112. The peak power and beam area together define the peak power density of laser150:
• 
  Peak power density W/m²=peak power (W)/beam area (m²).
• In one example, the peak power oflaser150 may be 2 W, and the beam diameter 2-4 μm. These values are by way of example only, and may vary in further embodiments.
• In one example, thecollimating lens156 may create an angle of convergence, Θ, oflaser beam152 of ˜50°. This angle may change upon entering thesubstrate112 to a refractive angle, ϕ, of ˜80°. The angle of refraction will depend on the incoming collimating lens angle Θ, and the relative permittivity, εr, of thesubstrate112. In embodiments, thesubstrate112 may have a relative permittivity, εr, of between 11.0 and 12.0. These angles and relative permittivity values are by way of example only, and may vary in further embodiments.
• With such parameters, the void162 may have a height, H, of 1.4˜2 μm, and a diameter, D, of 2˜4 μm. Again, these dimensions are by way of example only. Moreover, while thevoid162 is shown as being generally cylindrical inFIG. 7, thevoids162 may have other shapes in further embodiments, including ovoid, spherical, or a combination of cylindrical, ovoid and/or spherical.
• Referring again toFIG. 5, thevoids162 may be formed in one or moreplanar layers164. The one or more planar layers of voids define a modifiedzone166 in thewafer substrate112 where the wafer will separate upon completion of the stealth lasing process. Theplanar layers164 in the modifiedzone166 may be parallel to each other and the first and secondmajor surfaces102,104 of thewafer100. In one example, there may be fourlayers164 ofvoids162 formed, but there may be 1 layer, 2 layers, 3 layers or more than 4 layers in further embodiments. A higher number of layers facilitates easier separation of thesubstrate112.
• The position of eachlayer164 relative to the secondplanar surface104 may be controlled by a variety of parameters, including the peak power density of thelaser150, the height of thecollimating lens156 abovesurface104, and the collimator and refractive angles, Θ and ϕ. Examples of the laser peak power density, collimator angle and refractive angle are provided above. With the above parameters being constant, the height of eachlayer164 beneath thesurface104 of wafer100 (also referred to as the defocus height) may vary by changing a position of thecollimating lens156 above the surface. In examples, thecollimating lens156 may move between 181 μm and 186 μm above thesurface104 ofwafer100 to create thedifferent layers164.
• Another parameter which may be controlled when performing thestealth lasing step212 is the spacing betweenvoids162 in alayer164. A pattern ofhigher density voids162 will remove more material from the modifiedzone166 where the voids are formed making it easier to separate thesubstrate112. Spacing betweenvoids162, also referred to as pulse interval, is given by:
• 
  Pulse interval (μm)=laser feed rate (mm/s)/laser pulse frequency (kHz).
• In one example, thelaser150 may move at a rate of 300 mm/s relative to thesurface104 ofwafer100, and the pulse frequency may be 90 kHz. Thus:
• 
  Pulse interval≈3.3 μm.
• It is understood that the feed rate may be other values, such as for example 250 mm/s, and the pulse frequency may be other values, in further examples.
• FIG. 8 is an edge view showing thewafer100 after thelaser150 has formed themultiple layers164 of the modifiedzone166 in thesubstrate112. In one example, the wafer may have a total thickness of 760 μm. The modifiedzone166 may be about 20-25 μm thick. In one example, the thickness, Tw, of the finished wafer may be 32 μm. Thus, the thickness, Ts, of the removedsubstrate112 may be between 703 μm and 708 μm. Again, these values are by way of example only and each may vary in further embodiments. For example, the thickness of thefinished wafer100 may be 25 μm or thinner Where thefinished wafer100 is 25 μm, the thickness of the removed substrate, Ts, may be between 710 μm and 715 μm.
• FIG. 9 is an edge view showing removal of a portion of thesubstrate112, specificallyportion112a,at the modifiedzone166 after thestealth lasing step212. A portion of thesubstrate112, specificallysubstrate112b,remains as part of thewafer100. Theportion112athat was severed may be discarded. The new second major (back)surface104 is the surface ofsubstrate112adefined by removal of theportion112b.
• In embodiments, afterstealth lasing step212, theback surface104 may undergo a polishingstep214, using for example a Z3 polishing wheel rotating against the back surface. In further embodiments, it is conceivable that the parameters ofstealth lasing step212 be controlled such that polishingstep214 may be omitted.
• After completion of thestealth lasing step212 and polishing step214 (where included), a layer of die attach film (DAF) adhered to a flexible dicing tape may be applied onto the secondmajor surface104 of thewafer100 instep218. Thewafer100 may then be turned over and supported on a chuck or other support surface, and the lamination tape on the active, firstmajor surface102 of thewafer100 may be removed instep220.
• Thereafter, thewafer100 may be diced instep222. Dicing of the wafer may be performed for example using a known cutting blade. It is also known to dice wafers using a stealth dicing process in which a laser forms layers of voids in vertical planes (orthogonal tosurfaces102,104) around the outline of each semiconductor die106 inwafer100. The stealth dicing process is distinguishable from the stealth lasing process of the present technology to thin the wafer in several respects. For example, stealth dicing may use a narrow diameter beam which forms impact points in vertical planes of the wafer. The stealth dicing impact points do not cut the wafer. Instead, after creation of the impact points, stresses on the wafer are generated which propagate the impact points along vertical crystalline planes to sever the individual semiconductor dies. Other dicing methods may be used.
• After dicingstep222, the flexible dicing tape may be stretched along orthogonal axes to separate the individual semiconductor dies106 instep224. Thereafter, instep226, individual semiconductor dies106 may be removed by a pick and place robot for inclusion in a semiconductor package.
• Stealth lasing to thin thewafer100 as described above provides several advantages. As noted in the Background, conventional backgrinding processes may generate cracks in semiconductor wafers, especially those that are currently made at thin, fragile thicknesses. Stealth dicing according to the present technology eliminates wafer cracking due to the backgrinding processes. Elimination of such cracks improves wafer and die yields, and does away with the need for additional screening/inspection steps. Additionally, conventional backgrinding processes generate debris and foreign materials that can cause cracks and otherwise impair the assembly process. Elimination of the backgrinding process prevents the generation of this debris and foreign material, thus further improving yield and die quality. Moreover, the multiple backgrinding wheels needed for conventional wafer thinning add significant time, expense and complexity to the packaging process. Omission of the backgrinding wheels in accordance with the present technology improves each of these packaging parameters.
• It is a further advantage of the present technology that thelaser beam152 has sufficiently diverged, or defocused, by the time it reaches theintegrated circuit layer110. Thus, the stealth lasing may be provided to thin the wafer without damaging theintegrated circuit layer110.
• FIG. 10 shows an exemplary semiconductor die106 after separation fromwafer100. Thedie106 includes diebond pads116 at the firstmajor surface102 of thedie106. Thedie106 includes a lased, second major surface formed by the stealth lasing process described above. ADAF layer176 is also shown on the secondmajor surface104.
• In summary, an example of the present technology relates to a semiconductor die, comprising: a first major surface; a plurality of integrated circuits formed in the first major surface of the wafer; a lased, second major surface opposed to the first major surface; a die attach film layer covering the lased, second major surface.
• In another example, the present technology relates to a semiconductor wafer, comprising: a first major surface; a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer; and a lased, second major surface opposed to the first major surface.
• In a further example, the present technology relates to a semiconductor wafer, comprising: a first major surface; a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer; a second major surface opposed to the first major surface; wherein the second major surface is defined by means for severing a first portion of the wafer from a second portion of the wafer.
• The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (20)

We claim:

1. A semiconductor die, comprising:

a first major surface;

a plurality of integrated circuits formed in the first major surface of the wafer;

a lased, second major surface opposed to the first major surface; and

a die attach film (DAF) layer covering the lased, second major surface.

2. The semiconductor die ofclaim 1, wherein the lased, second major surface comprises a first portion of a semiconductor die substrate that was severed from a second portion of the semiconductor die substrate by a stealth lasing process.

3. The semiconductor die ofclaim 1, wherein the lased, second major surface is formed by application of a laser focused in between surfaces of a wafer from which the semiconductor die is formed.

4. The semiconductor die ofclaim 1, wherein the lased, second major surface is formed by application of a laser focused in a pattern of discrete points at one or more planar layers of the semiconductor die.

5. The semiconductor die ofclaim 4, wherein the one or more planar layers comprise four planar layers.

6. The semiconductor die ofclaim 1, wherein the lased, second major surface is also polished.

7. The semiconductor die ofclaim 1, wherein the semiconductor die has a thickness between the first and second major surfaces of between 25 microns and 36 microns.

8. The semiconductor die ofclaim 1, wherein the semiconductor die is a flash memory semiconductor die.

9. The semiconductor die ofclaim 1, wherein the DAF layer has been removed, thereby exposing the second major surface.

10. A semiconductor wafer, comprising:

a first major surface;

a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer; and

a lased, second major surface opposed to the first major surface.

11. The semiconductor wafer ofclaim 10, wherein the lased, second major surface comprises a first portion of a semiconductor wafer substrate that was severed from a second portion of the semiconductor wafer substrate by a stealth lasing process.

12. The semiconductor wafer ofclaim 10, wherein the lased, second major surface is formed by application of a laser beam from a laser, focused in between surfaces of the wafer.

13. The semiconductor wafer ofclaim 12, wherein the laser is cycled off and on to a peak power density at a predetermined frequency as the laser beam is moved relative to the semiconductor wafer.

14. The semiconductor wafer ofclaim 13, wherein voids in the wafer are created at and around a focal point of the laser beam when the laser is cycled at its peak power density.

15. The semiconductor wafer ofclaim 14, wherein a height and width of a void of the voids is controlled by a predetermined laser beam width and a predetermined power intensity of the laser.

16. The semiconductor wafer ofclaim 14, wherein the laser beam is defocused and does not modify the wafer at predetermined distances above and below the focal point of the laser beam.

17. The semiconductor wafer ofclaim 14, wherein the voids are formed in a pattern defining one or more planar layers within the wafer, the one or more planar layers of voids defining a modified zone in the wafer allowing separation of the wafer substrate above and below the modified zone.

18. The semiconductor wafer ofclaim 17, wherein a density of the voids in a planar layer of the one or more planar layers of voids is controlled by a predetermined peak intensity cycle time of the laser and a predetermined rate of movement of the laser beam across the semiconductor wafer.

19. The semiconductor wafer ofclaim 10, wherein the lased, second major surface is also polished.

20. A semiconductor wafer, comprising:

a first major surface;

a plurality of semiconductor dies, the plurality of semiconductor dies comprising integrated circuits formed in the first major surface of the wafer;

a second major surface opposed to the first major surface;

wherein the second major surface is defined by means for severing a first portion of the wafer from a second portion of the wafer.

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