US20220012105A1 - Technologies for allocating resources across data centers - Google Patents

Abstract

Technologies for allocating resources across data centers include a compute device to obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload. The compute device is also to determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data. Additionally, the compute device is to allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node. The supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located. Other embodiments are also described and claimed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application claims the benefit of priority to U.S. Non-Provisional application Ser. No. 15/858,286, filed Dec. 29, 2017, which in turn claims the benefit of and priority to U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017, and Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017, the entire contents of which are incorporated herein by reference in their entirety.
BACKGROUND
• Typically, in a group of compute devices assigned to collectively execute a workload (e.g., an application) in a data center, the resource utilization of the workload changes over time. For example, a workload may operate in a phase of relatively high memory usage and low processor usage, followed by a phase of relatively low memory usage and high processor usage. As such, an orchestrator server or other computer device that monitors the resource utilization of the workload may selectively allocate and deallocate resources (e.g., memory, data storage, processors, accelerator devices, etc.) to the group of compute devices as the workload transitions through the various phases. As such, the set of resources available to the workload may “burst” (e.g., increase) and decrease on an as-needed basis. However, in a data center in which multiple workloads are being executed concurrently, it is possible for a workload to encounter a phase that needs a particular amount of resources in order to execute at a speed specified in a service level agreement (e.g., an agreement between a customer of the data center and the data center operator) that are unavailable, such as when those resources are presently allocated to the execution of another workload in the data center.
BRIEF DESCRIPTION OF THE DRAWINGS
• The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
• FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources;
• FIG. 2 is a simplified diagram of at least one embodiment of a pod of the data center ofFIG. 1;
• FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod ofFIG. 2;
• FIG. 4 is a side plan elevation view of the rack ofFIG. 3;
• FIG. 5 is a perspective view of the rack ofFIG. 3 having a sled mounted therein;
• FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled ofFIG. 5;
• FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled ofFIG. 6;
• FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center ofFIG. 1;
• FIG. 9 is a top perspective view of at least one embodiment of the compute sled ofFIG. 8;
• FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center ofFIG. 1;
• FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled ofFIG. 10;
• FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center ofFIG. 1;
• FIG. 13 is a top perspective view of at least one embodiment of the storage sled ofFIG. 12;
• FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center ofFIG. 1; and
• FIG. 15 is a simplified block diagram of a system that may be established within the data center ofFIG. 1 to execute workloads with managed nodes composed of disaggregated resources.
• FIG. 16 is a simplified block diagram of at least one embodiment of a system for allocating resources across data centers;
• FIG. 17 is a simplified block diagram of at least one embodiment of an orchestrator server of the system ofFIG. 16;
• FIG. 18 is a simplified block diagram of at least one embodiment of an environment that may be established by the orchestrator server ofFIGS. 16 and 17; and
• FIGS. 19-21 are a simplified flow diagram of at least one embodiment of a method for allocating resources across data centers that may be performed by the orchestrator server ofFIGS. 16 and 17.
DETAILED DESCRIPTION OF THE DRAWINGS
• While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
• References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
• The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
• In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
• Referring now toFIG. 1, a data center100 in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includesmultiple pods110,120,130,140, each of which includes one or more rows of racks. As described in more detail herein, each rack houses multiple sleds, which each may be embodied as a compute device, such as a server, that is primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors). In the illustrative embodiment, the sleds in eachpod110,120,130,140 are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod). The pod switches, in turn, connect with spine switches150 that switch communications among pods (e.g., thepods110,120,130,140) in the data center100. In some embodiments, the sleds may be connected with a fabric using Intel Omni-Path technology. As described in more detail herein, resources within sleds in the data center100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more other sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may even belong to sleds belonging to different racks, and even todifferent pods110,120,130,140. Some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node). By disaggregating resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and selectively allocating and deallocating the disaggregated resources to form a managed node assigned to execute a workload, the data center100 provides more efficient resource usage over typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources). As such, the data center100 may provide greater performance (e.g., throughput, operations per second, latency, etc.) than a typical data center that has the same number of resources.
• Referring now toFIG. 2, thepod110, in the illustrative embodiment, includes a set ofrows200,210,220,230 ofracks240. Eachrack240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in eachrow200,210,220,230 are connected to multiple pod switches250,260. The pod switch250 includes a set ofports252 to which the sleds of the racks of thepod110 are connected and another set ofports254 that connect thepod110 to the spine switches150 to provide connectivity to other pods in the data center100. Similarly, the pod switch260 includes a set of ports262 to which the sleds of the racks of thepod110 are connected and a set of ports264 that connect thepod110 to the spine switches150. As such, the use of the pair of switches250,260 provides an amount of redundancy to thepod110. For example, if either of the switches250,260 fails, the sleds in thepod110 may still maintain data communication with the remainder of the data center100 (e.g., sleds of other pods) through the other switch250,260. Furthermore, in the illustrative embodiment, the switches150,250,260 may be embodied as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link-layer protocol (e.g., Intel's Omni-Path Architecture's, Infiniband) via optical signaling media of an optical fabric.
• It should be appreciated that each of the other pods120,130,140 (as well as any additional pods of the data center100) may be similarly structured as, and have components similar to, thepod110 shown in and described in regard toFIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches250,260 are shown, it should be understood that in other embodiments, eachpod110,120,130,140 may be connected to different number of pod switches (e.g., providing even more failover capacity).
• Referring now toFIGS. 3-5, eachillustrative rack240 of the data center100 includes two elongated support posts302,304, which are arranged vertically. For example, the elongated support posts302,304 may extend upwardly from a floor of the data center100 when deployed. Therack240 also includes one or morehorizontal pairs310 of elongated support arms312 (identified inFIG. 3 via a dashed ellipse) configured to support a sled of the data center100 as discussed below. Oneelongated support arm312 of the pair ofelongated support arms312 extends outwardly from theelongated support post302 and the otherelongated support arm312 extends outwardly from theelongated support post304.
• In the illustrative embodiments, each sled of the data center100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, therack240 is configured to receive the chassis-less sleds. For example, eachpair310 ofelongated support arms312 defines asled slot320 of therack240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrativeelongated support arm312 includes acircuit board guide330 configured to receive the chassis-less circuit board substrate of the sled. Eachcircuit board guide330 is secured to, or otherwise mounted to, atop side332 of the correspondingelongated support arm312. For example, in the illustrative embodiment, eachcircuit board guide330 is mounted at a distal end of the correspondingelongated support arm312 relative to the correspondingelongated support post302,304. For clarity of the Figures, not everycircuit board guide330 may be referenced in each Figure.
• Eachcircuit board guide330 includes an inner wall that defines a circuit board slot380 configured to receive the chassis-less circuit board substrate of asled400 when thesled400 is received in thecorresponding sled slot320 of therack240. To do so, as shown inFIG. 4, a user (or robot) aligns the chassis-less circuit board substrate of anillustrative chassis-less sled400 to asled slot320. The user, or robot, may then slide the chassis-less circuit board substrate forward into thesled slot320 such that eachside edge414 of the chassis-less circuit board substrate is received in a corresponding circuit board slot380 of the circuit board guides330 of thepair310 ofelongated support arms312 that define thecorresponding sled slot320 as shown inFIG. 4. By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in eachrack240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, the data center100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in the data center100.
• It should be appreciated that eachcircuit board guide330 is dual sided. That is, eachcircuit board guide330 includes an inner wall that defines a circuit board slot380 on each side of thecircuit board guide330. In this way, eachcircuit board guide330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to therack240 to turn therack240 into a two-rack solution that can hold twice asmany sled slots320 as shown inFIG. 3. Theillustrative rack240 includes sevenpairs310 ofelongated support arms312 that define a corresponding sevensled slots320, each configured to receive and support acorresponding sled400 as discussed above. Of course, in other embodiments, therack240 may include additional orfewer pairs310 of elongated support arms312 (i.e., additional or fewer sled slots320). It should be appreciated that because thesled400 is chassis-less, thesled400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of eachsled slot320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1U”). That is, the vertical distance between eachpair310 ofelongated support arms312 may be less than a standard rack unit “1U.” Additionally, due to the relative decrease in height of thesled slots320, the overall height of therack240 in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts302,304 may have a length of six feet or less. Again, in other embodiments, therack240 may have different dimensions. Further, it should be appreciated that therack240 does not include any walls, enclosures, or the like. Rather, therack240 is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts302,304 in those situations in which therack240 forms an end-of-row rack in the data center100.
• In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts302,304. To facilitate such routing, eachelongated support post302,304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts302,304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to eachsled slot320, power interconnects to provide power to eachsled slot320, and/or other types of interconnects.
• Therack240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with acorresponding sled slot320 and is configured to mate with an optical data connector of acorresponding sled400 when thesled400 is received in thecorresponding sled slot320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
• Theillustrative rack240 also includes afan array370 coupled to the cross-support arms of therack240. Thefan array370 includes one or more rows of coolingfans372, which are aligned in a horizontal line between the elongated support posts302,304. In the illustrative embodiment, thefan array370 includes a row of coolingfans372 for eachsled slot320 of therack240. As discussed above, eachsled400 does not include any on-board cooling system in the illustrative embodiment and, as such, thefan array370 provides cooling for eachsled400 received in therack240. Eachrack240, in the illustrative embodiment, also includes a power supply associated with eachsled slot320. Each power supply is secured to one of theelongated support arms312 of thepair310 ofelongated support arms312 that define thecorresponding sled slot320. For example, therack240 may include a power supply coupled or secured to eachelongated support arm312 extending from theelongated support post302. Each power supply includes a power connector configured to mate with a power connector of thesled400 when thesled400 is received in thecorresponding sled slot320. In the illustrative embodiment, thesled400 does not include any on-board power supply and, as such, the power supplies provided in therack240 supply power to correspondingsleds400 when mounted to therack240.
• Referring now toFIG. 6, thesled400, in the illustrative embodiment, is configured to be mounted in acorresponding rack240 of the data center100 as discussed above. In some embodiments, eachsled400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, thesled400 may be embodied as acompute sled800 as discussed below in regard toFIGS. 8-9, anaccelerator sled1000 as discussed below in regard toFIGS. 10-11, a storage sled1200 as discussed below in regard toFIGS. 12-13, or as a sled optimized or otherwise configured to perform other specialized tasks, such as amemory sled1400, discussed below in regard toFIG. 14.
• As discussed above, theillustrative sled400 includes a chassis-lesscircuit board substrate602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that thecircuit board substrate602 is “chassis-less” in that thesled400 does not include a housing or enclosure. Rather, the chassis-lesscircuit board substrate602 is open to the local environment. The chassis-lesscircuit board substrate602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-lesscircuit board substrate602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-lesscircuit board substrate602 in other embodiments.
• As discussed in more detail below, the chassis-lesscircuit board substrate602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-lesscircuit board substrate602. As discussed, the chassis-lesscircuit board substrate602 does not include a housing or enclosure, which may improve the airflow over the electrical components of thesled400 by reducing those structures that may inhibit air flow. For example, because the chassis-lesscircuit board substrate602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-lesscircuit board substrate602, which could inhibit air flow across the electrical components. Additionally, the chassis-lesscircuit board substrate602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-lesscircuit board substrate602. For example, the illustrative chassis-lesscircuit board substrate602 has awidth604 that is greater than adepth606 of the chassis-lesscircuit board substrate602. In one particular embodiment, for example, the chassis-lesscircuit board substrate602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, anairflow path608 that extends from afront edge610 of the chassis-lesscircuit board substrate602 toward arear edge612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of thesled400. Furthermore, although not illustrated inFIG. 6, the various physical resources mounted to the chassis-lesscircuit board substrate602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-lesscircuit board substrate602 linearly in-line with each other along the direction of the airflow path608 (i.e., along a direction extending from thefront edge610 toward therear edge612 of the chassis-less circuit board substrate602).
• As discussed above, theillustrative sled400 includes one or morephysical resources620 mounted to atop side650 of the chassis-lesscircuit board substrate602. Although twophysical resources620 are shown inFIG. 6, it should be appreciated that thesled400 may include one, two, or morephysical resources620 in other embodiments. Thephysical resources620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of thesled400 depending on, for example, the type or intended functionality of thesled400. For example, as discussed in more detail below, thephysical resources620 may be embodied as high-performance processors in embodiments in which thesled400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which thesled400 is embodied as an accelerator sled, storage controllers in embodiments in which thesled400 is embodied as a storage sled, or a set of memory devices in embodiments in which thesled400 is embodied as a memory sled.
• Thesled400 also includes one or more additionalphysical resources630 mounted to thetop side650 of the chassis-lesscircuit board substrate602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of thesled400, thephysical resources630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
• Thephysical resources620 are communicatively coupled to thephysical resources630 via an input/output (I/O)subsystem622. The I/O subsystem622 may be embodied as circuitry and/or components to facilitate input/output operations with thephysical resources620, thephysical resources630, and/or other components of thesled400. For example, the I/O subsystem622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.
• In some embodiments, thesled400 may also include a resource-to-resource interconnect624. The resource-to-resource interconnect624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the resource-to-resource interconnect624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
• Thesled400 also includes apower connector640 configured to mate with a corresponding power connector of therack240 when thesled400 is mounted in thecorresponding rack240. Thesled400 receives power from a power supply of therack240 via thepower connector640 to supply power to the various electrical components of thesled400. That is, thesled400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of thesled400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-lesscircuit board substrate602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-lesscircuit board substrate602 as discussed above. In some embodiments, power is provided to theprocessors820 through vias directly under the processors820 (e.g., through thebottom side750 of the chassis-less circuit board substrate602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
• In some embodiments, thesled400 may also include mountingfeatures642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled600 in arack240 by the robot. The mounting features642 may be embodied as any type of physical structures that allow the robot to grasp thesled400 without damaging the chassis-lesscircuit board substrate602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features642 may be embodied as non-conductive pads attached to the chassis-lesscircuit board substrate602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-lesscircuit board substrate602. The particular number, shape, size, and/or make-up of the mountingfeature642 may depend on the design of the robot configured to manage thesled400.
• Referring now toFIG. 7, in addition to thephysical resources630 mounted on thetop side650 of the chassis-lesscircuit board substrate602, thesled400 also includes one ormore memory devices720 mounted to abottom side750 of the chassis-lesscircuit board substrate602. That is, the chassis-lesscircuit board substrate602 is embodied as a double-sided circuit board. Thephysical resources620 are communicatively coupled to thememory devices720 via the I/O subsystem622. For example, thephysical resources620 and thememory devices720 may be communicatively coupled by one or more vias extending through the chassis-lesscircuit board substrate602. Eachphysical resource620 may be communicatively coupled to a different set of one ormore memory devices720 in some embodiments. Alternatively, in other embodiments, eachphysical resource620 may be communicatively coupled to eachmemory devices720.
• Thememory devices720 may be embodied as any type of memory device capable of storing data for thephysical resources620 during operation of thesled400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
• In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
• Referring now toFIG. 8, in some embodiments, thesled400 may be embodied as acompute sled800. Thecompute sled800 is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, thecompute sled800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. Thecompute sled800 includes various physical resources (e.g., electrical components) similar to the physical resources of thesled400, which have been identified inFIG. 8 using the same reference numbers. The description of such components provided above in regard toFIGS. 6 and 7 applies to the corresponding components of thecompute sled800 and is not repeated herein for clarity of the description of thecompute sled800.
• In theillustrative compute sled800, thephysical resources620 are embodied asprocessors820. Although only twoprocessors820 are shown inFIG. 8, it should be appreciated that thecompute sled800 may includeadditional processors820 in other embodiments. Illustratively, theprocessors820 are embodied as high-performance processors820 and may be configured to operate at a relatively high power rating. Although theprocessors820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-lesscircuit board substrate602 discussed above facilitate the higher power operation. For example, in the illustrative embodiment, theprocessors820 are configured to operate at a power rating of at least 250 W. In some embodiments, theprocessors820 may be configured to operate at a power rating of at least 350 W.
• In some embodiments, thecompute sled800 may also include a processor-to-processor interconnect842. Similar to the resource-to-resource interconnect624 of thesled400 discussed above, the processor-to-processor interconnect842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect842 communications. In the illustrative embodiment, the processor-to-processor interconnect842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the processor-to-processor interconnect842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
• Thecompute sled800 also includes acommunication circuit830. Theillustrative communication circuit830 includes a network interface controller (NIC)832, which may also be referred to as a host fabric interface (HFI). TheNIC832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by thecompute sled800 to connect with another compute device (e.g., with other sleds400). In some embodiments, theNIC832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, theNIC832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to theNIC832. In such embodiments, the local processor of theNIC832 may be capable of performing one or more of the functions of theprocessors820. Additionally or alternatively, in such embodiments, the local memory of theNIC832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
• Thecommunication circuit830 is communicatively coupled to anoptical data connector834. Theoptical data connector834 is configured to mate with a corresponding optical data connector of therack240 when thecompute sled800 is mounted in therack240. Illustratively, theoptical data connector834 includes a plurality of optical fibers which lead from a mating surface of theoptical data connector834 to anoptical transceiver836. Theoptical transceiver836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of theoptical data connector834 in the illustrative embodiment, theoptical transceiver836 may form a portion of thecommunication circuit830 in other embodiments.
• In some embodiments, thecompute sled800 may also include anexpansion connector840. In such embodiments, theexpansion connector840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to thecompute sled800. The additional physical resources may be used, for example, by theprocessors820 during operation of thecompute sled800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-lesscircuit board substrate602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
• Referring now toFIG. 9, an illustrative embodiment of thecompute sled800 is shown. As shown, theprocessors820,communication circuit830, andoptical data connector834 are mounted to thetop side650 of the chassis-lesscircuit board substrate602. Any suitable attachment or mounting technology may be used to mount the physical resources of thecompute sled800 to the chassis-lesscircuit board substrate602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-lesscircuit board substrate602 via soldering or similar techniques.
• As discussed above, theindividual processors820 andcommunication circuit830 are mounted to thetop side650 of the chassis-lesscircuit board substrate602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, theprocessors820 andcommunication circuit830 are mounted in corresponding locations on thetop side650 of the chassis-lesscircuit board substrate602 such that no two of those physical resources are linearly in-line with others along the direction of theairflow path608. It should be appreciated that, although theoptical data connector834 is in-line with thecommunication circuit830, theoptical data connector834 produces no or nominal heat during operation.
• Thememory devices720 of thecompute sled800 are mounted to thebottom side750 of the of the chassis-lesscircuit board substrate602 as discussed above in regard to thesled400. Although mounted to thebottom side750, thememory devices720 are communicatively coupled to theprocessors820 located on thetop side650 via the I/O subsystem622. Because the chassis-lesscircuit board substrate602 is embodied as a double-sided circuit board, thememory devices720 and theprocessors820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-lesscircuit board substrate602. Of course, eachprocessor820 may be communicatively coupled to a different set of one ormore memory devices720 in some embodiments. Alternatively, in other embodiments, eachprocessor820 may be communicatively coupled to eachmemory device720. In some embodiments, thememory devices720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-lesscircuit board substrate602 and may interconnect with acorresponding processor820 through a ball-grid array.
• Each of theprocessors820 includes a heatsink850 secured thereto. Due to the mounting of thememory devices720 to thebottom side750 of the chassis-less circuit board substrate602 (as well as the vertical spacing of thesleds400 in the corresponding rack240), thetop side650 of the chassis-lesscircuit board substrate602 includes additional “free” area or space that facilitates the use of heatsinks850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-lesscircuit board substrate602, none of the processor heatsinks850 include cooling fans attached thereto. That is, each of the heatsinks850 is embodied as a fan-less heatsinks.
• Referring now toFIG. 10, in some embodiments, thesled400 may be embodied as anaccelerator sled1000. Theaccelerator sled1000 is optimized, or otherwise configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, acompute sled800 may offload tasks to theaccelerator sled1000 during operation. Theaccelerator sled1000 includes various components similar to components of thesled400 and/or computesled800, which have been identified inFIG. 10 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of theaccelerator sled1000 and is not repeated herein for clarity of the description of theaccelerator sled1000.
• In theillustrative accelerator sled1000, thephysical resources620 are embodied asaccelerator circuits1020. Although only twoaccelerator circuits1020 are shown inFIG. 10, it should be appreciated that theaccelerator sled1000 may includeadditional accelerator circuits1020 in other embodiments. For example, as shown inFIG. 11, theaccelerator sled1000 may include fouraccelerator circuits1020 in some embodiments. Theaccelerator circuits1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, theaccelerator circuits1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
• In some embodiments, theaccelerator sled1000 may also include an accelerator-to-accelerator interconnect1042. Similar to the resource-to-resource interconnect624 of the sled600 discussed above, the accelerator-to-accelerator interconnect1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the accelerator-to-accelerator interconnect1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, theaccelerator circuits1020 may be daisy-chained with aprimary accelerator circuit1020 connected to theNIC832 andmemory720 through the I/O subsystem622 and asecondary accelerator circuit1020 connected to theNIC832 andmemory720 through aprimary accelerator circuit1020.
• Referring now toFIG. 11, an illustrative embodiment of theaccelerator sled1000 is shown. As discussed above, theaccelerator circuits1020,communication circuit830, andoptical data connector834 are mounted to thetop side650 of the chassis-lesscircuit board substrate602. Again, theindividual accelerator circuits1020 andcommunication circuit830 are mounted to thetop side650 of the chassis-lesscircuit board substrate602 such that no two heat-producing, electrical components shadow each other as discussed above. Thememory devices720 of theaccelerator sled1000 are mounted to thebottom side750 of the of the chassis-lesscircuit board substrate602 as discussed above in regard to the sled600. Although mounted to thebottom side750, thememory devices720 are communicatively coupled to theaccelerator circuits1020 located on thetop side650 via the I/O subsystem622 (e.g., through vias). Further, each of theaccelerator circuits1020 may include a heatsink1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks870, the heatsinks1070 may be larger than tradition heatsinks because of the “free” area provided by thememory devices750 being located on thebottom side750 of the chassis-lesscircuit board substrate602 rather than on thetop side650.
• Referring now toFIG. 12, in some embodiments, thesled400 may be embodied as a storage sled1200. The storage sled1200 is optimized, or otherwise configured, to store data in adata storage1250 local to the storage sled1200. For example, during operation, acompute sled800 or anaccelerator sled1000 may store and retrieve data from thedata storage1250 of the storage sled1200. The storage sled1200 includes various components similar to components of thesled400 and/or thecompute sled800, which have been identified inFIG. 12 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and8 apply to the corresponding components of the storage sled1200 and is not repeated herein for clarity of the description of the storage sled1200.
• In the illustrative storage sled1200, thephysical resources620 are embodied asstorage controllers1220. Although only twostorage controllers1220 are shown inFIG. 12, it should be appreciated that the storage sled1200 may includeadditional storage controllers1220 in other embodiments. Thestorage controllers1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into thedata storage1250 based on requests received via thecommunication circuit830. In the illustrative embodiment, thestorage controllers1220 are embodied as relatively low-power processors or controllers. For example, in some embodiments, thestorage controllers1220 may be configured to operate at a power rating of about 75 watts.
• In some embodiments, the storage sled1200 may also include a controller-to-controller interconnect1242. Similar to the resource-to-resource interconnect624 of thesled400 discussed above, the controller-to-controller interconnect1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the controller-to-controller interconnect1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
• Referring now toFIG. 13, an illustrative embodiment of the storage sled1200 is shown. In the illustrative embodiment, thedata storage1250 is embodied as, or otherwise includes, astorage cage1252 configured to house one or more solid state drives (SSDs)1254. To do so, thestorage cage1252 includes a number of mountingslots1256, each of which is configured to receive a correspondingsolid state drive1254. Each of the mountingslots1256 includes a number of drive guides1258 that cooperate to define anaccess opening1260 of thecorresponding mounting slot1256. Thestorage cage1252 is secured to the chassis-lesscircuit board substrate602 such that the access openings face away from (i.e., toward the front of) the chassis-lesscircuit board substrate602. As such, solid state drives1254 are accessible while the storage sled1200 is mounted in a corresponding rack204. For example, asolid state drive1254 may be swapped out of a rack240 (e.g., via a robot) while the storage sled1200 remains mounted in thecorresponding rack240.
• Thestorage cage1252 illustratively includes sixteen mountingslots1256 and is capable of mounting and storing sixteen solid state drives1254. Of course, thestorage cage1252 may be configured to store additional or fewer solid state drives1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in thestorage cage1252, but may be mounted in thestorage cage1252 in a different orientation in other embodiments. Eachsolid state drive1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives1254 may include volatile and non-volatile memory devices discussed above.
• As shown inFIG. 13, thestorage controllers1220, thecommunication circuit830, and theoptical data connector834 are illustratively mounted to thetop side650 of the chassis-lesscircuit board substrate602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled1200 to the chassis-lesscircuit board substrate602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.
• As discussed above, theindividual storage controllers1220 and thecommunication circuit830 are mounted to thetop side650 of the chassis-lesscircuit board substrate602 such that no two heat-producing, electrical components shadow each other. For example, thestorage controllers1220 and thecommunication circuit830 are mounted in corresponding locations on thetop side650 of the chassis-lesscircuit board substrate602 such that no two of those electrical components are linearly in-line with other along the direction of theairflow path608.
• Thememory devices720 of the storage sled1200 are mounted to thebottom side750 of the of the chassis-lesscircuit board substrate602 as discussed above in regard to thesled400. Although mounted to thebottom side750, thememory devices720 are communicatively coupled to thestorage controllers1220 located on thetop side650 via the I/O subsystem622. Again, because the chassis-lesscircuit board substrate602 is embodied as a double-sided circuit board, thememory devices720 and thestorage controllers1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-lesscircuit board substrate602. Each of thestorage controllers1220 includes a heatsink1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-lesscircuit board substrate602 of the storage sled1200, none of the heatsinks1270 include cooling fans attached thereto. That is, each of the heatsinks1270 is embodied as a fan-less heatsink.
• Referring now toFIG. 14, in some embodiments, thesled400 may be embodied as amemory sled1400. Thestorage sled1400 is optimized, or otherwise configured, to provide other sleds400 (e.g., compute sleds800, accelerator sleds1000, etc.) with access to a pool of memory (e.g., in two ormore sets1430,1432 of memory devices720) local to the memory sled1200. For example, during operation, acompute sled800 or anaccelerator sled1000 may remotely write to and/or read from one or more of the memory sets1430,1432 of the memory sled1200 using a logical address space that maps to physical addresses in the memory sets1430,1432. Thememory sled1400 includes various components similar to components of thesled400 and/or thecompute sled800, which have been identified inFIG. 14 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of thememory sled1400 and is not repeated herein for clarity of the description of thememory sled1400.
• In theillustrative memory sled1400, thephysical resources620 are embodied asmemory controllers1420. Although only twomemory controllers1420 are shown inFIG. 14, it should be appreciated that thememory sled1400 may includeadditional memory controllers1420 in other embodiments. Thememory controllers1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets1430,1432 based on requests received via thecommunication circuit830. In the illustrative embodiment, eachstorage controller1220 is connected to acorresponding memory set1430,1432 to write to and read frommemory devices720 within the correspondingmemory set1430,1432 and enforce any permissions (e.g., read, write, etc.) associated withsled400 that has sent a request to thememory sled1400 to perform a memory access operation (e.g., read or write).
• In some embodiments, thememory sled1400 may also include a controller-to-controller interconnect1442. Similar to the resource-to-resource interconnect624 of thesled400 discussed above, the controller-to-controller interconnect1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the controller-to-controller interconnect1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, amemory controller1420 may access, through the controller-to-controller interconnect1442, memory that is within the memory set1432 associated with anothermemory controller1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, thememory controllers1420 may implement a memory interleave (e.g., one memory address is mapped to thememory set1430, the next memory address is mapped to thememory set1432, and the third address is mapped to thememory set1430, etc.). The interleaving may be managed within thememory controllers1420, or from CPU sockets (e.g., of the compute sled800) across network links to the memory sets1430,1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
• Further, in some embodiments, thememory sled1400 may be connected to one or more other sleds400 (e.g., in thesame rack240 or an adjacent rack240) through a waveguide, using thewaveguide connector1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets1430,1432) to another sled (e.g., asled400 in thesame rack240 or anadjacent rack240 as the memory sled1400) without adding to the load on theoptical data connector834.
• Referring now toFIG. 15, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center100. In the illustrative embodiment, thesystem1510 includes anorchestrator server1520, which may be embodied as a managed node comprising a compute device (e.g., a compute sled800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled tomultiple sleds400 including a large number of compute sleds1530 (e.g., each similar to the compute sled800), memory sleds1540 (e.g., each similar to the memory sled1400), accelerator sleds1550 (e.g., each similar to the memory sled1000), and storage sleds1560 (e.g., each similar to the storage sled1200). One or more of thesleds1530,1540,1550,1560 may be grouped into a managednode1570, such as by theorchestrator server1520, to collectively perform a workload (e.g., anapplication1532 executed in a virtual machine or in a container). The managednode1570 may be embodied as an assembly ofphysical resources620, such asprocessors820,memory resources720,accelerator circuits1020, ordata storage1250, from the same ordifferent sleds400. Further, the managed node may be established, defined, or “spun up” by theorchestrator server1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, theorchestrator server1520 may selectively allocate and/or deallocatephysical resources620 from thesleds400 and/or add or remove one ormore sleds400 from the managednode1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application1532). In doing so, theorchestrator server1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in eachsled400 of the managednode1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. If the so, theorchestrator server1520 may additionally determine whether one or more physical resources may be deallocated from the managednode1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, theorchestrator server1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application1532) while the workload is executing
• Additionally, in some embodiments, theorchestrator server1520 may identify trends in the resource utilization of the workload (e.g., the application1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application1532) and pre-emptively identifying available resources in the data center100 and allocating them to the managed node1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, theorchestrator server1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center100. For example, theorchestrator server1520 may utilize a model that accounts for the performance of resources on the sleds400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, theorchestrator server1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and thesled400 on which the resource is located).
• In some embodiments, theorchestrator server1520 may generate a map of heat generation in the data center100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from thesleds400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center100. Additionally or alternatively, in some embodiments, theorchestrator server1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. Theorchestrator server1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center100.
• To reduce the computational load on theorchestrator server1520 and the data transfer load on the network, in some embodiments, theorchestrator server1520 may send self-test information to thesleds400 to enable eachsled400 to locally (e.g., on the sled400) determine whether telemetry data generated by thesled400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Eachsled400 may then report back a simplified result (e.g., yes or no) to theorchestrator server1520, which theorchestrator server1520 may utilize in determining the allocation of resources to managed nodes.
• Referring now toFIG. 16, asystem1610 for allocating resources across data centers may be implemented in accordance with the data center100 described above with reference toFIG. 1. In the illustrative embodiment, thesystem1610 includes anorchestrator server1620 communicatively coupled to multiple sleds including one ormore compute sleds1630, one ormore accelerator sleds1640, one or more data storage sleds1650, and one or more memory sleds1660. The compute sled(s)1630 includecompute resources1632, in operation, execute an application1638 (e.g., a workload). The accelerator sled(s)1640 includeaccelerator resources1642. Additionally, the data storage sled(s)1650 includedata storage resource1652, and the memory sled(s)1660 includememory resources1662. One or more of thesleds1630,1640,1650,1660 may be grouped into a managed node, such as by theorchestrator server1620, to collectively perform a workload (e.g., the application1638). A managed node may be embodied as an assembly of resources, such as compute resources, memory resources, storage resources, or other resources, from the same or different sleds or racks. Further, a managed node may be established, defined, or “spun up” by theorchestrator server1620 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. Thesystem1610 may be located in a data center and provide storage and compute services (e.g., cloud services) to a client device (not shown) that is in communication with thesystem1610 through anetwork1612. Theorchestrator server1620 may support a cloud operating environment, such as OpenStack, and managed nodes established by theorchestrator server1620 may execute one or more applications or processes (i.e., workloads), such as in virtual machines or containers, on behalf of a user of a client device (not shown).
• In the illustrative embodiment, theorchestrator server1620 determines whether an amount of resources to be used in the execution of an workload (e.g., the application1638) by a managed node exceeds the amount of resources available in thedata center1614 in which theorchestrator server1620 and the sleds of the managed node are located and, if so, communicates with one or moreother data centers1670,1680 (e.g., through the network1612) that are located off-premises to allocateresources1672,1682 to the managed node. Theresources1672 in thedata center1670 includecompute resources1634, similar to thecompute resources1632,accelerator resources1644, similar to theaccelerator resources1642,data storage resources1654, similar to thedata storage resources1652, andmemory resources1664, similar to thememory resources1662. Further, theresources1682 includecompute resources1636, similar to thecompute resources1632, accelerator resources1646, similar to theaccelerator resources1642,data storage resources1656, similar to thedata storage resources1652, andmemory resources1666, similar to thememory resources1662. In allocating the resources, theorchestrator server1620 may determine the availability and cost of using the resources at eachdata center1670,1680 and select the resources for use by the managed node as a function of the availability and cost. Further, theorchestrator server1620 may, in communicating with thedata centers1670,1680, utilize an application programming interface (API) to format requests and queries pursuant to a format specific to eachdata center1670,1680. Additionally, in the illustrative embodiment, theorchestrator server1620 obtains address information from thedata centers1670,1680 that is usable by the managed node to access the resources as if they were local (e.g., in the data center1614) such as through non-volatile memory express over fabric (NVMe-oF) or other local data bus protocols that are mapped onto a fabric (e.g., a network topology). Theorchestrator server1620 may subsequently deallocate the resources when the resource utilization needs of the managed node decrease (e.g., when the workload enters into a less resource-intensive phase). As such, unlike typical systems in which a managed node is limited to the resources available in a particular data center, thesystem1610 enables flexible bursting of the infrastructure (e.g., resources) beyond the particular data center1614 (e.g., to other data centers) to accommodate the changing resource needs of a workload when the resources are unavailable in thedata center1614.
• Referring now toFIG. 17, theorchestrator server1620 may be embodied as any type of compute device capable of performing the functions described herein, including obtaining resource utilization data indicative of a utilization of resources for a managed node to execute a workload, determining whether a set of resources presently available to the managed node in a data center in which theorchestrator server1620 is located satisfies the resource utilization data, and allocating, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node from an off-premises data center. As shown inFIG. 17, theillustrative orchestrator server1620 includes acompute engine1702, an input/output (I/O)subsystem1708,communication circuitry1710, and one or moredata storage devices1714. Of course, in other embodiments, theorchestrator server1620 may include other or additional components, such as those commonly found in a computer (e.g., display, peripheral devices, etc.). Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.
• Thecompute engine1702 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, thecompute engine1702 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. In the illustrative embodiment, thecompute engine1702 includes or is embodied as aprocessor1704 and a memory1706. Theprocessor1704 may be embodied as any type of processor capable of performing the functions described herein. For example, theprocessor1704 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, theprocessor1704 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.
• The memory1706 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
• In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
• In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory1706 may be integrated into theprocessor1704. In operation, the memory1706 may store various software and data used during operation such as resource utilization data, resource availability data, application programming interface (API) data, applications, programs, and libraries.
• Thecompute engine1702 is communicatively coupled to other components of thesled1630 via the I/O subsystem1708, which may be embodied as circuitry and/or components to facilitate input/output operations with the compute engine1702 (e.g., with theprocessor1704 and/or the memory1706) and other components of theorchestrator server1620. For example, the I/O subsystem1708 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem1708 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of theprocessor1704, the memory1706, and other components of theorchestrator server1620, into thecompute engine1702.
• Thecommunication circuitry1710 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over thenetwork1612 between theorchestrator server1620 and another compute device (e.g., thesleds1630,1640,1650,1660, and/or compute devices of theother data centers1670,1680, etc.). Thecommunication circuitry1710 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.
• Thecommunication circuitry1710 may include a network interface controller (NIC)1712 (e.g., as an add-in device), which may also be referred to as a host fabric interface (HFI). The NIC1712 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by theorchestrator server1620 to connect with another compute device (e.g., thesleds1630,1640,1650,1660, and/or compute devices of theother data centers1670,1680, etc.). In some embodiments, the NIC1712 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC1712 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC1712. In such embodiments, the local processor of the NIC1712 may be capable of performing one or more of the functions of thecompute engine1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC1712 may be integrated into one or more components of theorchestrator server1620 at the board level, socket level, chip level, and/or other levels.
• The one or more illustrativedata storage devices1714 may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Eachdata storage device1714 may include a system partition that stores data and firmware code for thedata storage device1714. Eachdata storage device1714 may also include one or more operating system partitions that store data files and executables for operating systems.
• Thesleds1630,1640,1650,1660 may have components similar to those described inFIG. 17. The description of those components of theorchestrator server1620 is equally applicable to the description of components of those devices and is not repeated herein for clarity of the description. Further, it should be appreciated that any of theorchestrator server1620, and thesleds1630,1640,1650,1660 may include other components, sub-components, and devices commonly found in a computing device, which are not discussed above in reference to theorchestrator server1620 and not discussed herein for clarity of the description.
• As described above, theorchestrator server1620, thesleds1630,1640,1650,1660 and thedata centers1670,1680 are illustratively in communication via thenetwork1612, which may be embodied as any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), etc.), digital subscriber line (DSL) networks, cable networks (e.g., coaxial networks, fiber networks, etc.), or any combination thereof.
• Referring now toFIG. 18, theorchestrator server1620 may establish anenvironment1800 during operation. Theillustrative environment1800 includes anetwork communicator1820 and aburst manager1830. Each of the components of theenvironment1800 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of theenvironment1800 may be embodied as circuitry or a collection of electrical devices (e.g.,network communicator circuitry1820, burstmanager circuitry1830, etc.). It should be appreciated that, in such embodiments, one or more of thenetwork communicator circuitry1820 or burstmanager circuitry1830 may form a portion of one or more of thecompute engine1702, the I/O subsystem1708, thecommunication circuitry1710 and/or other components of theorchestrator server1620. In the illustrative embodiment, theenvironment1800 includesresource utilization data1802 which may be embodied as any data indicative of present and/or predicted amounts and types (e.g., compute, accelerator, data storage, memory) of resources to be utilized by a managed node to execute a workload (e.g., the application1638). As such, theresource utilization data1802 may include telemetry data indicative of performance conditions in eachsled1630,1640,1650,1660 in the managed node associated with the workload, such as the present load on each resource of each sled (e.g., the percentage of the resource presently utilized by the workload), fingerprint data indicative of resource utilization profiles of different phases of operation of a workload (e.g., phase A characterized by relatively high compute usage and relative low memory usage, followed by phase B characterized by relatively high accelerator usage, relatively high memory usage, and relatively low data storage usage, etc.) and the lengths of time (e.g., residencies) that each phase typically lasts. Additionally, theresource utilization data1802 may include target thresholds to which the measured resource utilizations (e.g., loads) are to be compared to and/or target throughput and/or latency (e.g., quality of service (QoS) metrics), pursuant to a service level agreement (SLA) with a customer for whom the workload is executed. Theenvironment1800, in the illustrative embodiment, also includesresource availability data1804 which may be embodied as any data indicative of the availability ofresources1672,1682 at the off-premises data centers1670,1680 and the costs of using them (e.g., dollars per unit of compute capacity per second, dollars for gigabyte of storage per second, costs of utilizing a network to access theresources1672,1682, etc.). Theresource availability data1804, in the illustrative embodiment, also includes data indicative of the amount and types of presently unallocated resources in the data center1614 (e.g., on-premises). Additionally, theillustrative environment1800 includes application programming interface (API)data1806, which may be embodied as any data indicative of instructions usable to format requests and queries and otherwise communicate with eachdata center1670,1680. In some embodiments, eachdata center1670,1680 may communicate using a different protocol, and as such, theAPI data1806 may include libraries or other instructions unique to eachdata center1670,1680.
• In theillustrative environment1800, thenetwork communicator1820, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from theorchestrator server1620, respectively. To do so, thenetwork communicator1820 is configured to receive and process data packets from one system or computing device (e.g., one or more of thesleds1630,1640,1650,1660) and to prepare and send data packets to another computing device or system (e.g., resources of one or more of thedata centers1670,1680). Accordingly, in some embodiments, at least a portion of the functionality of thenetwork communicator1820 may be performed by thecommunication circuitry1710, and, in the illustrative embodiment, by the NIC1712.
• Theburst manager1830, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to obtain theresource utilization data1802, determine whether a set of resources presently available to the managed node in thedata center1614 satisfies theresource utilization data1802, and allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set ofresources1672,1682 to the managed node from an off-premises data center1670,1680. To do so, in the illustrative embodiment, theburst manager1830 includes aresource utilization determiner1832 and anallocation manager1834.
• Theresource utilization determiner1832, in the illustrative embodiment, is configured to obtain theresource utilization data1802, such as by collecting telemetry data indicative of the performance conditions of the resources allocated to the managed node executing the workload, determining patterns in the resource utilizations of the workload over time (e.g., fingerprint data), and predicting the upcoming resource utilization of the workload (e.g., within a predefined amount of time) based on the patterns.
• Theallocation manager1834, in the illustrative embodiment, is configured to selectively allocate and/or deallocate resources from the managed node as the workload is executed, from thedata center1614 and/or from off-premises data centers1670,1680, to satisfy the resource needs of the managed node, as determined by theresource utilization determiner1832. To do so, in the illustrative embodiment, theallocation manager1834 includes an on-premises allocator1836 and an off-premises allocator1838. The on-premises allocator1836, in the illustrative embodiment, is configured to allocate resources (e.g., computeresources1632,accelerator resources1642,data storage resources1652, memory resources1662) that are presently available in thedata center1614 to the managed node, such as by sending notifications of their assignment to the correspondingsleds1630,1640,1650,1660 on which the resources are located and/or by providing information usable by thecompute sled1630 to access the resources (e.g., address information). The off-premises allocator1838, in the illustrative embodiment, is configured to communicate with one or more off-premises data centers (e.g., thedata centers1670,1680) to determine the amounts and types of resources available and selectively allocate or deallocate the resources on an as-needed basis (e.g., when the resources are not available in the data center1614). In doing so, the off-premises allocator may compare the cost of each resource (e.g., a price charged by the operator of the off-premises data center1670,1680) and select the lowest-cost resources for allocation. Additionally, the off-premises allocator1838 may utilize one or more APIs in theAPI data1806 to communicate with the off-premises data centers1670,1680.
• It should be appreciated that each of theresource utilization determiner1832, theallocation manager1834, the on-premises allocator1836, and the off-premises allocator1838 may be separately embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. For example, theresource utilization determiner1832 may be embodied as a hardware component, while theallocation manager1834, the on-premises allocator1836, and the off-premises allocator1838 are embodied as virtualized hardware components or as some other combination of hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof.
• Referring now toFIG. 19, theorchestrator server1620, in operation, may execute amethod1900 for allocating resources across data centers. Themethod1900 begins with block1902 in which theorchestrator server1620 obtains resource utilization data indicative of resource utilization of a managed node associated with a workload (e.g., a utilization of resources needed to execute theapplication1638 at a predefined quality of service). In doing so, theorchestrator server1620 may receive a managed node composition request associated with a workload (e.g., from acompute sled1630 that is to execute theapplication1638 or from a client device (not shown)), as indicated inblock1904. As indicated inblock1906, theorchestrator server1620, in receiving the managed node composition request, may receive a service level agreement indicative of one or more quality of service metrics associated with the workload (e.g., a target latency, a target throughput, a target number of input/output operations per second, a target number of instructions executed per second, etc.). Additionally or alternatively, theorchestrator server1620 may receive telemetry data from a presently-executing managed node (e.g., a managed node presently executing the workload, such as the application1638), as indicated inblock1908. In the illustrative embodiment, theorchestrator server1620 determines a predicted resource utilization of the managed node (e.g., the resource utilization predicted in a predefined period of time in the future, such as one second) from workload fingerprint data (e.g., resource utilization phases, patterns of the phases exhibited over time, and the residencies of the phases), as indicated inblock1910.
• Subsequently, inblock1912, theorchestrator server1620 determines whether resources allocated to the managed node satisfy the obtained resource utilization data. In doing so, and as indicated inblock1914, theorchestrator server1620 may determine whether the present resources are within a predefined range (e.g., 1%) of the obtained utilization data (e.g., within 1% of the amount of resources that are needed by the managed node or are predicted to be needed by the managed node). The predefined range may be defined in the service level agreement as an acceptable variance in the quality of service or may be defined by another source (e.g., in a configuration file). In the illustrative embodiment, theorchestrator server1620 compares the available resources in thepresent data center1614 to the obtained resource utilization data, as indicated inblock1916. In doing so, theorchestrator server1620 may allocate resources available in the present data center to the managed node (e.g., if the resource utilization data indicates a shortfall between the amount of resources allocated and the amount needed, and those resources are not presently allocated to any other managed nodes in the data center1614), as indicated inblock1918. Theorchestrator server1620 may also compare the amounts and types of any off-premises resources (e.g.,resources1672,1682 located in thedata centers1670,1680) presently allocated to the managed node to the resource utilization data, as indicated in block1920. Subsequently, inblock1922, theorchestrator server1620 determines a course of action to take as a function of whether the present resources (e.g., from thedata center1614 and any off-premises data centers1670,1680) allocated to the managed node satisfy (e.g., are within the predefined range of) the resource utilization data. If so, themethod1900 advances to block1924, in which theorchestrator server1620 monitors further execution of the workload (e.g., the application1638) and obtains additional (e.g., subsequent) resource utilization data in block1902, described above. Otherwise, themethod1900 advances to block1926 ofFIG. 20, in which theorchestrator server1620 determines whether the presently allocated resources exceed the resource utilization data (e.g., in excess of the predefined range of resources).
• Referring now toFIG. 20, in response to a determination that the present resources allocated to the managed node exceed the resource utilization data, themethod1900 advances to block1928 in which theorchestrator server1620 deallocates resources from the managed node. In doing so and as indicated inblock1930, theorchestrator server1620 determines the amount of resources to deallocate. Theorchestrator server1620, in the illustrative embodiment, does so by determining the difference between the presently allocated resources and the resource utilization data, as indicated inblock1932. As indicated inblock1934, in deallocating the resources, theorchestrator server1620 may deallocate off-premises resources before deallocating resources in the present data center1614 (e.g., the data center in which theorchestrator server1620 is located). In other words, theorchestrator server1620 prioritizes deallocating off-premises resources over deallocating resources present in thedata center1614. As indicated inblock1936, theorchestrator server1620 may deallocate more expensive resources before deallocating less expensive resources (e.g., as a function of fees charged by operators of thedata centers1670,1680 for use of the off-premises resources). In deallocating the off-premises resources, theorchestrator server1620, in the illustrative embodiment, sends, through thenetwork1612, one or more deallocation requests to each off-premises data center1670,1680 from which resources are to be deallocated, as indicated inblock1938. As eachdata center1670,1680 may communicate using a different protocol, theorchestrator server1620 may send the deallocation request(s) using an API associated with each off-premises data center1670,1680 (e.g., the API data1806), as indicated inblock1940. Subsequently, themethod1900 loops back to block1924 ofFIG. 19, in which execution of the workload continues.
• Referring back to block1926 ofFIG. 20, if theorchestrator server1620 instead determines that the present resources do not exceed the resource utilization data1802 (e.g., the present resources are less than the resource utilization data1802), themethod1900 advances to block1942 in which theorchestrator server1620 determines the availability of supplemental resources from one or more off-premises data centers (e.g., theresources1672,1682 atdata centers1670,1680). In doing so, theorchestrator server1620 may query each off-premises data center1670,1680 for the availability of resources at thosedata centers1670,1680, as indicated inblock1944. In the illustrative embodiment, theorchestrator server1620 may query for the availability of specific types of resources to satisfy the resource utilization data1802 (e.g., if theresource utilization data1802 indicates a deficiency in available accelerator resources, the query may request information indicative of the availability of accelerator resources at the correspondingdata center1670,1680), as indicated inblock1946. As indicated inblock1948, theorchestrator server1620 may additionally query for the financial cost of each resource available at the off-premises data center1670,1680 (e.g., a financial cost per unit of time on a specific FPGA, a financial cost per number of gigabytes allocated from a particular type of data storage device, etc.). Further, as indicated in block1950, theorchestrator server1620 may send the queries using an API associated with each off-premises data center1670,1680. Subsequently, themethod1900 advances to block1952 ofFIG. 21, in which theorchestrator server1620 selects one or more of the off-premises data centers1670,1680 from which to allocate the supplemental resources.
• Referring now toFIG. 21, in selecting one or more off-premises data centers1670,1680, theorchestrator server1620 may determine a cost per unit of eachresource1672,1682, as indicated inblock1954. For example, theorchestrator server1620 may determine that one class of accelerator resource available at thedata center1670 performs a greater number of operations per second than another class of accelerator resource available at thedata center1680. Similarly, one class of memory or data storage device available at thedata center1670 may provide a greater read and/or write throughput than another class of memory or data storage device available at thedata center1680. As such, and as indicated inblock1956, theorchestrator server1620, in the illustrative embodiment, adjusts the costs (e.g., fromblock1948 ofFIG. 20) as a function of performance differences between classes of resources provided by each off-premises data center1670,1680. For example, theorchestrator server1620 may determine a unit by which to measure each class of resource (e.g., operations per second), determine the amount of the units provided by each class of resources, and divide the cost associated with the resource by the amount of the units provided the resource (e.g., cents per operation per second). Additionally, theorchestrator server1620 may adjust the cost as a function of characteristics of each off-premises data center1670,1680, as indicated inblock1958. In doing so, theorchestrator server1620 may adjust the cost as a function of the reliability of eachdata center1670,1680 (e.g., decreasing the cost for a more reliable data center and increasing the cost for a less reliable data center), as indicated inblock1960. As indicated inblock1962, theorchestrator server1620 may adjust the cost as a function of the responsiveness of eachdata center1670,1680 (e.g., decreasing the cost for a data center that generally has a lower latency and increasing the cost for a data center that generally has a higher latency). Inblock1964, theorchestrator server1620 may prioritize (e.g., rank for selection) thedata centers1670,1680 in order from lowest cost to highest cost. Theorchestrator server1620 may also compare the lowest available cost of allocating off-premises resources1672,1682 (e.g., in accordance with the prioritization from block1964) to a cost of not satisfying quality of service metrics associated with the workload (e.g., as specified in a service level agreement for the workload) and determine whether the cost of allocating the off-premises resources is less than or equal to the cost of not satisfying the QoS metric(s), as indicated inblock1966. In the illustrative embodiment, if the cost of allocating the off-premises resources is less than or equal to the cost of not satisfying the QoS metric(s), theorchestrator server1620 selects one or more of the off-premises data centers1670,1680 for allocation of off-premises (e.g., supplemental) resources.
• Inblock1968, theorchestrator server1620 determines the subsequent course of action as a function of whether one or more off-premises data centers1670,1680 have been selected. If not, themethod1900 loops back to block1924 ofFIG. 19, in which the managed node continues execution of the workload. Otherwise, themethod1900 advances to block1970, in which theorchestrator server1620 allocates the supplemental off-premises resource(s) to the managed node associated with the workload (e.g., the application1638). In doing so, theorchestrator server1620 may send a request to each selected off-premises data center to allocate the corresponding resource(s), as indicated inblock1972. Theorchestrator server1620 may send each request using an API associated with the correspondingdata center1670,1680, as indicated inblock1974. Further, and as indicated inblock1976, theorchestrator server1620 receives data usable to utilize the allocated resource(s). In doing so, theorchestrator server1620 may receive address data (e.g., a unique identifier such as an Internet Protocol (IP) address, a media access control (MAC) address, etc.) for each resource, as indicated inblock1978. Further, in the illustrative embodiment, theorchestrator server1620 maps each off-premises resource as a local resource (e.g., to appear to sleds of the managed node in thedata center1614 as if those off-premises resources1672,1682 are also located in the data center1614), as indicated in block1980. For example, and as indicated inblock1982, theorchestrator server1620 may map one or more resource(s) for access via non-volatile memory express over fabric (NVMe-oF). Subsequently, themethod1900 loops back to block1924 ofFIG. 19 in which execution of the workload continues.
Examples
• Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
• Example 1 includes a compute device comprising a compute engine to (i) obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload, (ii) determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data, and (iii) allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node, wherein the supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located.
• Example 2 includes the subject matter of Example 1, and wherein to allocate the supplemental set of resources comprises to map the supplemental set of resources to be accessible as being located in the data center in which the compute device is located.
• Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the compute engine is further to determine an availability of the supplemental set of resources prior to the allocation of the supplemental set of resources.
• Example 4 includes the subject matter of any of Examples 1-3, and wherein to determine the availability of the supplemental set of resources comprises to query the off-premises data center for an availability of the supplemental set of resources.
• Example 5 includes the subject matter of any of Examples 1-4, and wherein to query the off-premises data center comprises to query the off-premises data center with an application programming interface associated with the off-premises data center.
• Example 6 includes the subject matter of any of Examples 1-5, and wherein to determine the availability of the supplemental set of resources comprises to query the off-premises data center for a cost of the supplemental set of resources.
• Example 7 includes the subject matter of any of Examples 1-6, and wherein the off-premises data center is one of a plurality of off-premises data centers, and the compute engine is further to select the off-premises data center for allocation of the supplemental set of resources as a function of the determined availability and cost of the supplemental set of resources.
• Example 8 includes the subject matter of any of Examples 1-7, and wherein the compute engine is further to deallocate, in response to a determination that the set of resources presently allocated to the managed node exceeds the resource utilization data, one or more of the resources from the managed node.
• Example 9 includes the subject matter of any of Examples 1-8, and wherein to deallocate the one or more of the resources comprises to prioritize deallocation of resources located in the off-premises data center over deallocation of resources located in the data center in which the compute device is located.
• Example 10 includes the subject matter of any of Examples 1-9, and wherein to deallocate the one or more of the resources comprises to prioritize deallocations of resources as a function of a cost of each resource.
• Example 11 includes the subject matter of any of Examples 1-10, and wherein the compute engine is further to determine whether a cost of not satisfying a service level agreement associated with the workload exceeds a cost of allocating the supplemental set of resources; and to allocate the supplemental set of resources comprises to allocate, in response to a determination that that the cost of not satisfying the service level agreement exceeds the cost of allocating the supplemental set of resources, the supplemental set of resources.
• Example 12 includes the subject matter of any of Examples 1-11, and wherein to allocate the supplemental set of resources comprises to allocate at least one of accelerator resources, data storage resources, compute resources, or memory resources.
• Example 13 includes a method comprising obtaining, by a compute device, resource utilization data indicative of a utilization of resources for a managed node to execute a workload; determining, by the compute device, whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data; allocating, by the compute device and in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node, wherein the supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located.
• Example 14 includes the subject matter of Example 13, and wherein allocating the supplemental set of resources comprises mapping the supplemental set of resources to be accessible as being located in the data center in which the compute device is located.
• Example 15 includes the subject matter of any of Examples 13 and 14, and further including determining, by the compute device, an availability of the supplemental set of resources prior to the allocation of the supplemental set of resources.
• Example 16 includes the subject matter of any of Examples 13-15, and wherein determining the availability of the supplemental set of resources comprises querying the off-premises data center for an availability of the supplemental set of resources.
• Example 17 includes the subject matter of any of Examples 13-16, and wherein querying the off-premises data center comprises querying the off-premises data center with an application programming interface associated with the off-premises data center.
• Example 18 includes the subject matter of any of Examples 13-17, and wherein determining the availability of the supplemental set of resources comprises querying the off-premises data center for a cost of the supplemental set of resources.
• Example 19 includes the subject matter of any of Examples 13-18, and wherein the off-premises data center is one of a plurality of off-premises data centers, the method further comprising selecting, by the compute device, the off-premises data center for allocation of the supplemental set of resources as a function of the determined availability and cost of the supplemental set of resources.
• Example 20 includes the subject matter of any of Examples 13-19, and further including deallocating, by the compute device and in response to a determination that the set of resources presently allocated to the managed node exceeds the resource utilization data, one or more of the resources from the managed node.
• Example 21 includes the subject matter of any of Examples 13-20, and wherein deallocating the one or more of the resources comprises prioritizing deallocation of resources located in the off-premises data center over deallocation of resources located in the data center in which the compute device is located.
• Example 22 includes the subject matter of any of Examples 13-21, and wherein deallocating the one or more of the resources comprises prioritizing deallocations of resources as a function of a cost of each resource.
• Example 23 includes the subject matter of any of Examples 13-22, and further including determining, by the compute device, whether a cost of not satisfying a service level agreement associated with the workload exceeds a cost of allocating the supplemental set of resources; and allocating the supplemental set of resources comprises allocating, in response to a determination that that the cost of not satisfying the service level agreement exceeds the cost of allocating the supplemental set of resources, the supplemental set of resources.
• Example 24 includes the subject matter of any of Examples 13-23, and wherein allocating the supplemental set of resources comprises allocating at least one of accelerator resources, data storage resources, compute resources, or memory resources.
• Example 25 includes a compute device comprising means for performing the method of any of Examples 13-24.
• Example 26 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute engine to perform the method of any of Examples 13-24.
• Example 27 includes a compute device comprising a compute engine to perform the method of any of Examples 13-24.
• Example 28 includes a compute device comprising burst manager circuitry to (i) obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload, (ii) determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data, and (iii) allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node, wherein the supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located.
• Example 29 includes the subject matter of Example 28, and wherein to allocate the supplemental set of resources comprises to map the supplemental set of resources to be accessible as being located in the data center in which the compute device is located.
• Example 30 includes the subject matter of any of Examples 28 and 29, and wherein the burst manager circuitry is further to determine an availability of the supplemental set of resources prior to the allocation of the supplemental set of resources.
• Example 31 includes the subject matter of any of Examples 28-30, and wherein to determine the availability of the supplemental set of resources comprises to query the off-premises data center for an availability of the supplemental set of resources.
• Example 32 includes the subject matter of any of Examples 28-31, and wherein to query the off-premises data center comprises to query the off-premises data center with an application programming interface associated with the off-premises data center.
• Example 33 includes the subject matter of any of Examples 28-32, and wherein to determine the availability of the supplemental set of resources comprises to query the off-premises data center for a cost of the supplemental set of resources.
• Example 34 includes the subject matter of any of Examples 28-33, and wherein the off-premises data center is one of a plurality of off-premises data centers, and the burst manager circuitry is further to select the off-premises data center for allocation of the supplemental set of resources as a function of the determined availability and cost of the supplemental set of resources.
• Example 35 includes the subject matter of any of Examples 28-34, and wherein the burst manager circuitry is further to deallocate, in response to a determination that the set of resources presently allocated to the managed node exceeds the resource utilization data, one or more of the resources from the managed node.
• Example 36 includes the subject matter of any of Examples 28-35, and wherein to deallocate the one or more of the resources comprises to prioritize deallocation of resources located in the off-premises data center over deallocation of resources located in the data center in which the compute device is located.
• Example 37 includes the subject matter of any of Examples 28-36, and wherein to deallocate the one or more of the resources comprises to prioritize deallocations of resources as a function of a cost of each resource.
• Example 38 includes the subject matter of any of Examples 28-37, and wherein the burst manager circuitry is further to determine whether a cost of not satisfying a service level agreement associated with the workload exceeds a cost of allocating the supplemental set of resources; and to allocate the supplemental set of resources comprises to allocate, in response to a determination that that the cost of not satisfying the service level agreement exceeds the cost of allocating the supplemental set of resources, the supplemental set of resources.
• Example 39 includes the subject matter of any of Examples 28-38, and wherein to allocate the supplemental set of resources comprises to allocate at least one of accelerator resources, data storage resources, compute resources, or memory resources.
• Example 40 includes a compute device comprising circuitry for obtaining resource utilization data indicative of a utilization of resources for a managed node to execute a workload; circuitry for determining whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data; means for allocating, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node, wherein the supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located.
• Example 41 includes the subject matter of Example 40, and wherein the means for allocating the supplemental set of resources comprises means for mapping the supplemental set of resources to be accessible as being located in the data center in which the compute device is located.
• Example 42 includes the subject matter of any of Examples 40 and 41, and further including circuitry for determining an availability of the supplemental set of resources prior to the allocation of the supplemental set of resources.
• Example 43 includes the subject matter of any of Examples 40-42, and wherein the circuitry for determining the availability of the supplemental set of resources comprises circuitry for querying the off-premises data center for an availability of the supplemental set of resources.
• Example 44 includes the subject matter of any of Examples 40-43, and wherein the circuitry for querying the off-premises data center comprises circuitry for querying the off-premises data center with an application programming interface associated with the off-premises data center.
• Example 45 includes the subject matter of any of Examples 40-44, and wherein the circuitry for determining the availability of the supplemental set of resources comprises circuitry for querying the off-premises data center for a cost of the supplemental set of resources.
• Example 46 includes the subject matter of any of Examples 40-45, and wherein the off-premises data center is one of a plurality of off-premises data centers, and the compute device further comprises means for selecting the off-premises data center for allocation of the supplemental set of resources as a function of the determined availability and cost of the supplemental set of resources.
• Example 47 includes the subject matter of any of Examples 40-46, and further including circuitry for deallocating, in response to a determination that the set of resources presently allocated to the managed node exceeds the resource utilization data, one or more of the resources from the managed node.
• Example 48 includes the subject matter of any of Examples 40-47, and wherein the circuitry for deallocating the one or more of the resources comprises circuitry for prioritizing deallocation of resources located in the off-premises data center over deallocation of resources located in the data center in which the compute device is located.
• Example 49 includes the subject matter of any of Examples 40-48, and wherein the circuitry for deallocating the one or more of the resources comprises circuitry for prioritizing deallocations of resources as a function of a cost of each resource.
• Example 50 includes the subject matter of any of Examples 40-49, and further including circuitry for determining whether a cost of not satisfying a service level agreement associated with the workload exceeds a cost of allocating the supplemental set of resources; and wherein the means for allocating the supplemental set of resources comprises means for allocating, in response to a determination that that the cost of not satisfying the service level agreement exceeds the cost of allocating the supplemental set of resources, the supplemental set of resources.
• Example 51 includes the subject matter of any of Examples 40-50, and wherein the means for allocating the supplemental set of resources comprises circuitry for allocating at least one of accelerator resources, data storage resources, compute resources, or memory resources.

Claims (21)

1. A server comprising:

a node, the node comprising resources, the resources including:

a compute resource to execute an application;

a data storage resource;

an accelerator resource; and

a memory resource; and

one or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause the server to:

communicate with a remote server via a public cloud service to allocate a remote resource in the remote server to the node based on the resources available in the server; and

obtain address information from the remote server for use by the node to access the remote resource as if the remote resource was in the server.

2. The server ofclaim 1, wherein the server to select the remote resource as a function of availability and cost.

3. The server ofclaim 1, wherein the server to utilize an application programming interface to communicate with the remote server in a format specific to the remote server.

4. The server ofclaim 1, wherein the server to communicate with the remote resource using a non-volatile memory express over fabric (NVMe-oF) bus protocol.

5. The server ofclaim 1, wherein the server to communicate with the remote server via the public cloud service to deallocate the remote resource in the remote server to the node if the resources to be used in an execution of a workload by the node decrease below the resources available in the server.

6. The server ofclaim 1, wherein the remote resource is a remote accelerator resource.

7. The server ofclaim 1, wherein the remote resource is a remote storage resource.

8. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a server to:

communicate with a remote server via a public cloud service to allocate a remote resource in the remote server to a node based on resources available in the server, the node comprising the resources, the resources including a compute resource to execute an application, a data storage resource, an accelerator resource, and a memory resource; and

obtain address information from the remote server for use by the node to access the remote resource as if the remote resource was in the server.

9. The one or more non-transitory machine-readable storage media ofclaim 8, wherein the server to select the remote resource as a function of availability and cost.

10. The one or more non-transitory machine-readable storage media ofclaim 8, wherein the server to utilize an application programming interface to communicate with the remote server in a format specific to the remote server.

11. The one or more non-transitory machine-readable storage media ofclaim 8, wherein the server to communicate with the remote resource using a non-volatile memory express over fabric (NVMe-oF) bus protocol.

12. The one or more non-transitory machine-readable storage media ofclaim 8, wherein the server to communicate with the remote server via the public cloud service to deallocate the remote resource in the remote server to the node if the resources to be used in an execution of a workload by the node decrease below the resources available in the server.

13. The one or more non-transitory machine-readable storage media ofclaim 8, wherein the remote resource is a remote accelerator resource.

14. The one or more non-transitory machine-readable storage media ofclaim 8, wherein the remote resource is a remote storage resource.

15. A method comprising:

communicating, by a server, with a remote server via a public cloud service to allocate a remote resource in the remote server to a node based on resources available in the server, the node comprising the resources, the resources including a compute resource to execute an application, a data storage resource, an accelerator resource and a memory resource; and

obtaining, by the server, address information from the remote server for use by the node to access the remote resource as if the remote resource was in the server.

16. The method ofclaim 15, wherein the server to select the remote resource as a function of availability and cost.

17. The method ofclaim 15, wherein the server to utilize an application programming interface to communicate with the remote server in a format specific to the remote server.

18. The method ofclaim 15, wherein the server to communicate with the remote resource using a non-volatile memory express over fabric (NVMe-oF) bus protocol.

19. The method ofclaim 15, wherein the server to communicate with the remote server via the public cloud service to deallocate the remote resource in the remote server to the node if the resources to be used in an execution of a workload by the node decrease below the resources available in the server.

20. The method ofclaim 15, wherein the remote resource is a remote accelerator resource.

21. The method ofclaim 15, wherein the remote resource is a remote storage resource.

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