US20210027826A1 - Methods and apparatus for synchronizing communication with a memory controller - Google Patents

Abstract

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Description

TECHNICAL FIELD
• The present invention relates to the field of signal communications and more particularly to high-speed transfer of information within and between integrated circuit devices using electrical signaling.
BACKGROUND
• In modern electronic systems, data and control information are transferred between various subsystems using extremely short-lived electrical signals. For example, in high-speed memory systems, a data signal from a memory controller to a memory device may be valid at the input of the memory device for only a nanosecond or less; less time, in some cases, than the propagation time of the data signal on the signaling path between the memory controller and the memory device. In any such high-speed signaling system, the ability of the receiving device to sample the data signal at a precise instant within the valid data interval (the “data eye”) is often a critical factor in determining how brief the data eye may be and, consequently, the overall data transfer rate of the system. Accordingly, any technique for more accurately controlling the sampling instant within the data eye generally permits faster data transfer and therefore higher signaling bandwidth.
• FIG. 1 illustrates a prior art high-speed signaling system in which a strobe signal is transmitted on strobe line DQS to control the sampling of data signals transmitted on data lines, DQO-DQN. Because the strobe signal is edge-aligned with the data signals when transmitted (i.e., the strobe signal transition coincides with the opening of the data eye) and the DQS line introduces nominally the same propagation delay as the DQ0-DQn lines, the strobe signal and data signals arrive at the receiving device at nearly the same time. A variable delay circuit15 then delays the strobe signal by half the nominal duration of the data eye so that the delayed strobe signal transitions at the midpoint of the data eye.
• In order to prevent the delayed strobe signal from drifting away from the midpoint of the data eye (e.g., due to changes in voltage and temperature), a delay-locked loop circuit (DLL)12 is provided to adjust the delay applied by the variable delay circuit over time. Avariable delay circuit21 within the DLL is formed by coarse and fine delay elements that correspond to coarse and fine delay elements within the variable delay circuit15 in the strobe signal path. As the output of thevariable delay circuit21 within the DLL drifts out of phase with a reference clock signal (e.g., due to changes in voltage and temperature), the phase difference is detected by aphase detector18 which outputs a signal to adelay control circuit20 to adjust the delay control value applied to thevariable delay circuit21. The adjustment to the delay control value results in adjustment in the number of coarse and/or fine delay elements in the signal path of thevariable delay circuit21 so as to drive the output of thevariable delay circuit21 back toward phase lock with the reference clock signal. As shown inFIG. 1, the delay control value is also provided, after translation in a ratio circuit22 according to the ratio between the reference clock period and one half the data eye duration, to the variable delay circuit15 in the strobe signal path. By this arrangement, the delay applied to the data strobe signal is automatically adjusted to compensate for variations in voltage and temperature. Other relatively constant sources of error (e.g., process variations, mismatches in the DQS and DQ paths, etc.) may be compensated by the initial selection of coarse and fine delay elements within thevariable delay circuit21.
• Unfortunately, because a delayed version of the data strobe signal is ultimately used to control the sampling of the DQ lines (a technique referred to herein as direct strobing), any transient sources of timing error in the data strobe signal such as intersymbol interference (ISI) and cross-talk, or data-dependent timing errors resulting from mismatched rising and falling edge rates are not significantly compensated by the variable delay circuit15 and instead appear as timing jitter at the sample control inputs of the data receiver. This phenomenon is illustrated inFIG. 2. As shown, astrobe signal31 is delayed by an amount of time, T_EYE/2, to produce adelayed strobe signal33 that transitions at the midpoint of the data eye. Slightly advanced and delayed versions of thestrobe signal31 resulting from transient sources of timing error are illustrated by dashedlines34 and35, respectively. Because the transient sources of timing error are passed through to the output of the variable delay circuit15 ofFIG. 1, thedelayed strobe signal33 is likewise advanced or delayed, resulting in a sampling point that is offset from the ideal sampling point as shown. As discussed above, such inaccuracy in the sampling point translates to lost timing margin and ultimately to reduced data transfer rates.
SUMMARY
• In accordance with an aspect of the present invention, an apparatus is disclosed that can reduce sampling errors for data communicated between devices. The apparatus uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty-percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.
BRIEF DESCRIPTION OF THE FIGURES
• FIG. 1 is a diagram of a prior art signaling system that samples data signals with a strobe signal that is phase-adjusted with a delay-locked loop circuit.
• FIG. 2 is a diagram of the phase-adjusted strobe signals ofFIG. 1 used to sample data during a valid data interval represented by a data eye.
• FIG. 3 is a diagram of an apparatus that samples data signals with a data-sampling signal that is generated by adjustably delaying a clock signal in accordance with phase information acquired from a strobe signal.
• FIG. 4 is a diagram of an apparatus that samples data signals with a duty cycle corrected data-sampling signal that is generated by adjustably delaying a clock signal with a delay-locked loop that is phase-locked to a strobe signal.
• FIG. 5 is a diagram of a portion of the apparatus ofFIG. 4, including elements of a phase control device and interpolator.
• FIG. 6 is a diagram of a system for communicating data including a controller and a plurality of memory devices.
• FIG. 7 is a diagram of a system for transmitting data using a transmit state derived from a received state of the apparatus ofFIG. 4.
• FIG. 8 is a phase diagram of the data-sampling signal relative to a master clock domain.
• FIG. 9 is a diagram of a mechanism that can be used for data sampled by the data-sampling signal and read with the master clock signal.
• FIG. 10 is a diagram of an implementation of the present invention in an information storage and transfer system having a multi-drop bus with plural devices coupled to the bus.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• FIG. 3 shows a diagram of a data-sampling apparatus50 that creates a data-sampling signal on data-sampling line DSS for sampling data signals received on data lines DQ1-DQN withreceivers60,64 and66. The data-sampling signal is output by aDLL52 that adjusts the phase of a clock signal on clock line CLK in accordance with phase information acquired from a strobe signal received on strobe line DQS. The phase information is acquired by comparing, at aphase detector55, the strobe signal received on strobe line DQS with the signal output byDLL52 on phase-lock line58. Thus, unlike the direct strobing of the prior art, in which the strobe signal is used for sampling data signals, in accordance with the present invention the strobe signal is used to adjust the phase of a data-sampling signal, and the data-sampling signal is instead employed to sample data signals.
• As discussed below, embodiments of the present invention may be used with timing reference signals other than strobe signals, including without limitation, clock signals, and pseudo-random signals. Herein, the expression “strobe signal” refers to a signal that transitions between valid logic levels (e.g., logic high and logic low) when a valid signal is present on a corresponding data, control or address line. Except for calibration transitions and other overhead signaling associated with establishing or maintaining the timing accuracy of the strobe signal, the strobe signal is generally idle (often in a precharged state midway between valid logic levels) when no valid signal is present or is being output on the corresponding data, control or address line. By contrast, a clock signal transitions between logic levels in a periodic fashion regardless of whether control, data or address signals are present on other lines. Note that, in the case of a strobe signal that is precharged to a state midway between valid logic levels when idle, a transition from the precharged level to a valid logic level (sometimes called a preamble) typically precedes any transition between valid logic levels.
• The strobe signal has been sent along with the data signals by a device that is transmitting data, not shown in this figure, whereas the clock signal is generally available to all devices in a data signaling system during system operation. In one embodiment, the strobe signal is in phase with the data signals when transmitted from the remote device. In this case, theDLL52 is configured to output a data-sampling signal on line DSS that is 90° out of phase with the strobe signal received on line DQS, for sampling the received data signals with transitions of the data-sampling signal at the midpoint of the data eyes. In another embodiment, the strobe signal is 90° out of phase with the data signals when transmitted from the remote device. In this case, theDLL52 is configured to output a data-sampling signal on line DSS that is in phase with the strobe signal received on line DQS, for sampling the received data signals with transitions of the data-sampling signal at the midpoint of the data eyes.
• For a memory system implementation in which data and accompanying strobe signals are transmitted between a memory controller and one or more DRAM devices, a data-sampling apparatus such asapparatus50 may be disposed only on the memory controller to keep the DRAM cost effective. In this case, the strobe signal is phase aligned with data signals transmitted by the DRAM, so the data-sampling signal output byDLL52 is 90° out of phase with the data signals received on lines DQ1-DQN.
• The strobe signal and data signals may be transmitted by similar output drivers, such as CMOS transistors, and over similar paths, such as conductive traces having substantially matched transmission characteristics. For certain implementations, both the strobe signal and the data signals may have different slopes for rising transitions versus falling transitions, for example due to inherent differences between PMOS and NMOS output driver transistors that may be used to drive the strobe signal and data signals high and low. This can cause the percentage of time that the strobe signal is high versus low to vary from an ideal 50% duty cycle.
• Since the data signals have differences in rising and falling transitions that match those of the strobe signal, one might expect that imperfections in the strobe signal would cancel those in the data signals. However, a rising strobe signal transition may correspond to a rising or a falling data signal transition, and a falling strobe signal transition may correspond to a rising or falling data signal transition. Thus, although strobe signal imperfections may be cancelled by certain data signal imperfections, they may be magnified by other data signal imperfections. Other imperfections that can degrade the strobe signal include intersymbol interference, cross talk and signal dispersion.
• In contrast, the data-sampling signal output on line DSS may be created with a desired waveform, for example having a fifty percent duty cycle and sharp transitions, compared to the strobe signal. TheDLL52 may also smooth jitter of the strobe signal so that in addition to providing an improved waveform, the data-sampling signal DSS has a more stable phase than the strobe signal DQS. Thus, instead of the direct strobing of the prior art, which is subject to imperfections of the strobe signal DQS, a high quality data-sampling signal DSS is used to sample data.
• FIG. 4 shows another embodiment of a data-sampling apparatus100 that creates a data-sampling signal for sampling data signals received on lines DQ1-DQN, with the phase of the data-sampling signal derived from a strobe signal or timing reference signal received on line DQS. Thesystem100 uses a two-stage delay-lock loop (DLL) similar to that disclosed in U.S. Pat. No. 6,125,157, assigned to Rambus Inc. and incorporated by reference herein.
• In a first stage, aDLL reference loop102 uses a clock signal on line CLK, which is duty cycle corrected by a first dutycycle correction circuit105, to produce a set ofsignals110 that are sequentially delayed replications of the corrected clock signal, termed phase vectors. In a second stage, an adjacent pair ofphase vectors110 are selected and weighted by aninterpolator112 to output a zero-degree signal at an output labeled 0°. At an output labeled 90°, another adjacent pair ofphase vectors110 are selected and weighted byinterpolator112 to output a ninety-degree signal that is phase-adjusted according to the zero-degree signal.DLL reference loop102 andinterpolator112 thus provide a variable delay circuit to the clock signal.
• TheDLL reference loop102 includes a series of delay elements arranged in a chain, the chain receiving the clock signal and generating, from the delay elements, thephase vectors110, each of thephase vectors110 shifted a unit delay from an adjacent phase vector. TheDLL reference loop102 may adjust the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase length of the clock signal. Although fourphase vectors110 are shown inFIG. 4, more or less phase vectors can be employed, such as two, three, six, eight or twelve. The phase difference betweenadjacent phase vectors110 in the embodiment ofapparatus100 is 180°/N and so, for the four signals shown, eachphase vector110 is spaced from the next by 45°.
• Theinterpolator112 receives thephase vectors110 fromreference loop102 and outputs the zero-degree signal and the ninety-degree signal, based upon a phase-control signal from a phase-control circuit122. A selection circuit in phase-control circuit122 orinterpolator112 causes interpolator112 to select twoadjacent phase vectors110 and create the zero-degree signal from a weighted combination of thosesignals110. The zero-degree signal resulting from the mathematical combination ofphase vectors110 byinterpolator112 is designed to be in phase, after subsequent processing, with the strobe signal received on line DQS. An embodiment of selection circuitry ininterpolator112 that may be employed in the present invention is disclosed in the above-referenced U.S. Pat. No. 6,125,157.
• The clock signal on line CLK is a master clock signal for an information transfer system that includessystem100 and can also be used, for example, to synchronize transmission of the strobe signal and data signals to a remote device, not shown in this figure. The strobe signal received on line DQS has substantially the same frequency in this embodiment as the clock signal received on line CLK. The ninety-degree signal results from a mathematical combination ofreference signals110 byinterpolator112 that is designed in this embodiment to be out of phase with the zero-degree signal by 90°.
• The zero-degree signal is fed through a dutycycle correction circuit115, which is configured to output a phase-lock signal PL online128 having a substantially 50% duty cycle regardless of imperfections in the duty cycle of the zero-degree signal. The ninety-degree signal is fed through a similar dutycycle correction circuit118, which is configured to output a data-sampling signal online129 having a substantially 50% duty cycle regardless of imperfections in the duty cycle of the ninety-degree signal. An embodiment of a duty cycle correction circuit that may be employed in the present invention is disclosed in the above-referenced U.S. Pat. No. 6,125,157.
• A zerophase detector120 receives the strobe signal on line DQS and the phase-lock signal on line PL from dutycycle correction circuit115, and compares the two signals to generate an early or late signal to the phase-control circuit122. The phase-control circuit122 uses the early or late signal to causeinterpolator112 to move the zero-degree signal forward or backward in time until the phase-lock signal is in phase with DQS.
• Phase-control circuit122, which is shown in more detail inFIG. 5, includes acounter150 that has a digital state determined by a history of early or late signals received from zerophase detector120, the digital state stored in afirst register155 of amemory152 and maintained in the absence of the input strobe signal. Alternatively, the digital state of thecounter150 may drive theinterpolator112 directly, without storage of the state in a register.
• Thememory152 has M registers, includingsecond register157 throughMTH register159, for storing M states of phase-control circuit122. As discussed further below,second register157 throughMTH register159, which may alternatively be disposed outside phase-control circuit122, store states that may be used to control the output ofinterpolator112 or other interpolators, not shown in this figure, to provide additional data-sampling signals. The additional data-sampling signals may be used for transmitting strobe or timing reference signals to the remote device rather than receiving strobe or timing reference signals from the remote device, for synchronization of the received data signals with the local clock signal CLK, or for communication with different remote devices, for example.
• In order to avoid instability, phase-control circuit122 may act as a digital filter by requiring two or more consecutive early or late signals before changing the signal output tointerpolator112. The phase-control circuit122 can also be caused to hold the signal output tointerpolator112 constant, ignoring the signal from the zerophase detector120. This can be used, for example, to lock the phase position of the ninety-degree signal for sampling data even when strobe signal DQS is nonexistent or suspected to have errors.
• Phase-control circuit122 also communicates to a digital-to-analog converter (DAC)160 withininterpolator112, which converts a digital state such as a six-bit word stored in thefirst register155 into a pair ofcontrol signals164 and166 that is applied to control the weighting of thephase vectors110 selected by the selection circuitry, interpolating between those phase vectors. This weighting of thephase vectors110 can be achieved by controlling the current drawn by sources connected to the selected phase vectors, and integrating that current with corresponding capacitors, as described in above-referenced U.S. Pat. No. 6,125,157. For the situation in which other digital states are stored in phase-control circuit122, astate selection circuit162 is provided that selects whether the state stored infirst register155 or other registers157-159 is provided toDAC160. The state selection circuitry also selects the twoadjacent phase vectors110 that are interpolated bysignals164 and166 fromDAC160.
• The 90° output signal, after passing through dutycycle correction circuit118, provides a data-sampling signal having a predetermined quadrature phase relationship to a data signal received on line DQ1 for sampling with aconventional receiver130. Thusreceiver130 can sample the data signal on line DQ1 with an accurately aligned quadrature signal on line DSS1 that has a substantially 50% duty cycle, instead of direct strobing the data signal on line DQ1 with the strobe signal, which may have jitter, imperfections in duty cycle, reduced edge slopes due to dispersion during transmission, and transient errors such as intersymbol errors and crosstalk errors. The data-sampling signal may also provide a free running clock signal, as opposed to a strobe signal that may only exist concomitant with receiving data.
• Additional receivers, such asNth receiver133, can sample other data signals on lines such as data line DQN, with the data-sampling signal produced byapparatus100. Thusapparatus100 can be used for data signals transmitted over a multi-bit wide bus.System100 can employ phase information of strobe signal DQS to synchronize a virtually ideal, free running quadrature clock signal having a 50% duty cycle and sharp rising and falling edges for sampling received data signal DQ.
• An offsetcontrol circuit140 can be coupled to either the zerophase detector120 or the phase-control circuit122 to adjust the phase of 0° output so that the zero clock signal is slightly out of phase with strobe signal DQS. Alternatively, 90° output may be adjusted slightly byinterpolator112 to not be exactly 90° out of phase with 0° output. This may be used, for example, to better align the signal output from dutycycle correction circuit118 with the quadrature of data signals DQ and DQX. Thus, for a common situation in which a number of data bits, such as a byte, are received in parallel by a number of receivers associated with a strobe signal, such asreceiver130 andreceiver133, offsetcontrol circuit140 offers a per-byte adjustment of the phase of the data-sampling signal. Similar per-byte calibration of the data-sampling signals can be accomplished bymultiplexer170, which may also be controlled by offset control, and which can select how many delayelements144, such as inverters, are in the path of the phase-lock signal.
• Further adjustment of the data-sampling signal can be achieved by providing another series ofdelay elements146, such as inverters, to the data-sampling signal.Multiplexer172 is provided for selecting the number ofdelay elements146 that the data-sampling signal DSS1 encounters compared to the number ofdelay elements144 that phase-lock signal PL encounters.Multiplexer175 is provided for selecting the number ofdelay elements146 that the data-sampling signal DSSN encounters compared to the number ofdelay elements144 that phase-lock signal encounters. This selection ofdelay elements146 offers a per-bit calibration of the data-sampling signals DSS1-DSSN. In this fashion, early, normal or late data-sampling clock signals can be selectively provided to each of the various receivers sampling data signals from a byte-wide or multi-byte wide bus.
• The zerophase detector120 may be configured to compare the falling edges of the DQS and the phase-lock signals, since such falling edges are commonly produced by N-MOS drivers that drive faster transitions than P-MOS drivers that are commonly used to produce rising edges. Anoptional edge selector125, which may be a part of zerophase detector120, includes circuitry such as a configurable register that can be programmed to cause zerophase detector120 to look at rising edges of the DQS and the phase-lock signals, instead of or in addition to comparing the falling edges of those signals.
• Although asingle interpolator112 is shown in this figure, other interpolators may also receive the output signals110 fromreference loop102. Moreover, provided that the traces that carryoutput signals110 have matched lengths and impedances, interpolators such asinterpolator112 may be located a relatively long distance fromreference loop102. Thus many such interpolators may be located on the same electronic circuit, each of which usessignals110 fromreference loop102 as phase vectors.
• For example, as discussed further below,apparatus100 may be part of a memory controller formed on an integrated circuit chip that communicates with plural DRAM devices disposed on other integrated circuit chips. In this case, another interpolator may receiveoutput signals110 for controlling transmission of data and strobe or timing reference signals to those DRAM devices. For the situation, also described in further detail below, in which plural devices such as DRAMs share transmission lines such as a memory bus, a separate interpolator may be provided on the memory controller for communicating with each of the DRAM devices, with each interpolator controlled by a signal specific to the corresponding DRAM device.
• FIG. 6 shows thetiming system100 employed as part of amemory controller200 that communicates withmemory devices RAM202 andRAM212 to read and write data for amemory system220. Data signals DQ are sent on abus204 having multiple parallel conductive traces between a first group of input/output (I/O)units205 and a second group of I/O units207. Each of the I/O units205 and207 have a conventional data transmit circuit and a conventional data receive circuit corresponding to each of the traces. Strobe signals DQS can be communicated betweensystem100 and an I/O unit208 ofRAM202 overtrace206. That is, strobe signals DQS are received bysystem100 as discussed above, and can be sent by a conventional strobe transmit circuit ortransmitter209 that is coupled tosystem100.
• Memory controller200 also contains anothertiming system210 that is similar tosystem100.Timing system210 receives strobe signals DQS2 from I/O unit218 viatrace216. Asecond strobe transmitter219 is coupled totiming system210 for sending strobe signals DQS2 fromcontroller200 to I/O unit218. A group of I/O units215 communicates data signals DQ2 with I/O units217 ofRAM212 overbus214. Since the I/O units207 ofRAM202 and I/O units217 ofRAM212 are the only I/O units directly connected to respective I/O units205 and215 ofcontroller200, strobe signals DQS and DQS2 are sent according to point-to-point communication.
• Clock, command and address signals are sent fromcontroller200 tomemory devices RAM202 andRAM212 alongcontrol line230. Alternatively, clock signals may be generated by an external clock chip.Control line230 is coupled toreceivers244 and246 in a multi-drop configuration, although a point-to-point configuration is also possible. Associated data and strobe traces204 and206 are designed to be closely matched with each other, and associated data and strobe traces214 and216 are also designed to be closely matched with each other, however,control line230 may have a substantially different path length and delay than any of the traces.
• Conventional clock transmitter240 sends a clock signal CLK torespective clock receivers244 and246. The data signals DQ and DQ2 and strobe signals DQS and DQS2 that are sent bymemory devices RAM202 and212 tomemory controller200 are transmitted according to the clock signals CLK received by those memory devices. Similarly, the data signals DQ and DQ2 and strobe signals DQS and DQS2 that are sent bymemory controller200 tomemory devices RAM202 and212 are, after being received, written to memory addresses according to the clock signals CLK received by those memory devices.
• AlthoughFIG. 6 depicts timingsystems100 and210 implemented in the context of amemory system220, note that such timing systems can be employed in a variety of other applications, including digital, analog, chip-to-chip, logic-to-logic, peripheral device communications, network communications or any other system where signals are transmitted between a transmitter and a receiver. Also note that timing systems such assystems100 and210 may be included inmemory devices RAM202 andRAM212, instead of or in addition to being included incontroller200, and may be provided in one or more communicating devices of the applications and systems listed above.
• Controller200 andmemory devices RAM202 andRAM212 may be formed within the same integrated circuit, in a system-on-chip embodiment. Alternatively,controller200 andmemory devices RAM202 andRAM212 may each be formed as a separate integrated circuit, which may be connected by printed circuit board (PCB) traces on a single PCB as a multi-chip package or separate PCBs coupled to a motherboard. In another embodiment,controller200 andmemory devices RAM202 andRAM212, or other communication devices, may be interconnected by transmission lines such as network channels.
• For the situation in which a phase providing signal such as strobe signal DQS is intermittent, additional mechanisms can be employed to improve the data-sampling signal. As mentioned above, phase-control circuit122 can be set to hold its state during time periods in which the strobe signal is not received. In addition, phase state maintenance operations can be conducted which convey process, voltage or temperature induced phase differences to the phase-control circuit122 in the absence of data requests. Such maintenance operations may involve at least a minimal number of strobe signal reads from a device such asmemory device RAM202, in which a strobe signal is sent tosystem100 to acquire phase information.
• Various types of maintenance operations can be used to acquire phase information, including the following examples. A power-up type of maintenance operation may occur shortly after power is initially provided to devices such ascontroller200 and/ormemory devices RAM202 andRAM212. A power state change type of maintenance operation may occur during run-time power state transitions of the devices. For instance, such a power state change maintenance operation can occur during transitions into and out of low power sleep, nap, standby or other power saving modes. A periodic type of maintenance operation may be triggered by a clock, counter or interrupt mechanism whereby either a fixed or programmable minimum time duration is specified that causes the maintenance operation to be run. For the implementation oftiming system100 in a memory system, a hidden-refresh type of maintenance operation may be performed in parallel with a DRAM refresh operation.
• Maintenance operations may not be needed for systems communicating intermittent strobe signals that have a minimal number of pre-amble or post-amble strobe cycles for acquiring phase information by phase-control circuit122. Also, depending upon the number of strobe cycles accompanying a data signal read, an intermittent strobe signal may provide sufficient phase information fortiming system100, especially if the data signal is read after a delay.
• The phase information gleaned from a strobe signal DQS received bymemory controller200 fromRAM202 can also be used to synchronize transmission of data signals DQ frommemory controller200 toRAM202, so that the data signal DQ received byRAM202 is aligned with the clock signal CLK at thatRAM202. That is, the digital state of the phase-control circuit122 controls phase-adjustment of the reference clock signal CLK relative to received strobe signal DQS, and thus provides an indication of transmission differences betweenbus204 andcontrol line230. The digital state for received signals can be used to create a digital state for transmit signals that compensates for those transmission differences in writing data.
• The transmit state of the phase-control circuit122 may be the complement of the received state of that circuit, causing the interpolator to output a transmit strobe signal that is phase-shifted from CLK an opposite amount as the phase difference between the received strobe signal DQS and reference clock CLK. Since the state of phase-control circuit122 is a digital number, reversing the phase-adjustment to transmit DQS instead of receive DQS may simply involve subtracting the received state from unity to obtain the transmit state, which is output to the interpolator. The interpolator may also output a transmit data signal DQ that is 90° out of phase with the transmit strobe signal DQS, which can be accomplished via another simple transformation of the transmit state settings, to provide data and strobe signals having a quadrature relationship tomemory device RAM202. Also note that because the transmit data signal DQ can, by this mechanism, be aligned with the clock signal CLK at a remote device such asRAM202, transmission of a strobe signal for sampling that data signal DQ at the remote device may not be necessary.
• For example, if the phase-control circuit122 has a state acquired from DQS signals received from I/O unit208 that causesinterpolator112 to output a 0° signal that is advanced by ten degrees relative to clock signal CLK, then a DQS signal transmitted fromtransmitter209 to I/O unit208 can be delayed by ten degrees relative to clock signal CLK, in addition to an optional quadrature offset. Various states of phase-control circuit122 may be stored bycontroller200 and applied as desired to control interpolator to output data-sampling signals as needed.
• Note that while the phase of a transmitted data or strobe signal can be derived from the phase of a received data or strobe signal, as described above, it is also possible to have the transmit phase determined irrespective of the received phase, for example by programming a register with a phase control state. In this case, separate transmit phase vectors can be used to generate the transmitted data or strobe signal or the same phase vectors used for generating received data-sampling signals can be used to generate transmitted data or strobe signals.
• FIG. 7 illustrates asystem300 for transmitting data using a transmitstate303 derived from a received state of the phase-control circuit122. Although the DLL interpolator112 described above in the context of receiving data may also be employed for transmitting data, the embodiment illustrated inFIG. 7 includes an additional and substantiallysimilar DLL interpolator312 to that described above.Interpolator312 outputs a transmit data signal T° and a transmit strobe signal (T+90)° that is offset from the transmit data signal T° by approximately ninety degrees, in accordance with the transmitstate303.
• The data to be transmitted is provided to aconventional data transmitter305 along with the transmit data signal T° that has been duty cycle corrected by dutycycle correction circuit308.Data transmitter305 transmits data signal DQ alongbus204, the data signal DQ having a predetermined phase relationship with the clock signal CLK so that the data arrives atRAM202 at a desired phase relationship to the clock signal CLK atRAM202. Other transmitters, not shown, may also transmit other data signals onbus204 using transmit data signal T° . At the same time, after passing through dutycycle correction circuit318, a quadrature transmit clock signal may be provided to conventionaldata strobe transmitter310, which transmits strobe signal DQS onbus206 so that strobe signal DQS has a predetermined phase relationship with the clock signal CLK upon arrival atRAM202.
• Another use of the phase information acquired bysystem100 and quantified as a received state of phase-control circuit122 is shown inFIG. 8 andFIG. 9. As described above, for example with reference toFIG. 4, data signals DQ received bysystem100 andreceiver130 are sampled by a quadrature signal that is phase spaced relative to the received strobe signal DQS, and so received data may be said to be in a data-sampling clock domain DCLK.Controller200, however, manipulates data, control signals and logic according to master clock signals CLK, and may be said to be in a master clock domain.Controller200 may be an application specific integrated circuit (ASIC), so logic and data manipulation by the controller may be said to be in the ASIC domain. Because the received state of phase-control circuit122 includes information relating DQS and CLK signals, the received state can be used to transfer received data from the DQS domain to the master clock or ASIC domain with minimal latency and adequate setup and hold time, thus avoiding any meta-stability risks.
• FIG. 8 is a phase diagram400 of the phase of the data-sampling clock DCLK in the master clock domain, i.e., with master clock CLK phase defined as 0°. The phase diagram is divided into eight octants, labeledOCT1 throughOCT8, which can be used to illustrate a general phase relationship of data-sampling clock DCLK relative to the master clock CLK signal. Note that the receive state of phase-control circuit122 controls an interpolation between reference vectors ofreference loop102 that defines in which octant the phase of DCLK signal is found relative to CLK.
• FIG. 9 shows amechanism500 that can be used for data that may be sampled by data-sampling signal DCLK as described above, in order to read that data by CLK.Interpolator112 in this embodiment includes an auxiliary output signal labeled X°, which outputs to a dutycycle correction circuit502 that in turn outputs an auxiliary clock signal XCLK to anauxiliary receiver505.Receiver505 also receives data signal DQ' that is output byreceiver130 tomultiplexer510, andreceiver505 outputs data signal DQ″ tomultiplexer510.Multiplexer510 outputs either DQ' or DQ″ toreceiver515, which uses clock signal CLK to read the data in the master clock domain.
• In order to read the data with CLK, DCLK should be in the left-hand side of phase diagram400 to avoid potential setup and hold time conflicts between CLK and DCLK. If the state of phase-control circuit122 indicates that DCLK is inOCT4 orOCT5 for example, as shown byarrow404, themultiplexer510 may be set to select DQ′, which is then clocked with CLK byreceiver515. If, however, the state of phase-control circuit122 indicates that DCLK is in the right hand side of phase diagram400, as shown byarrow408, phase-control circuit122 can cause auxiliary output X° to output the inverse of DCLK, shown byarrow410.Receiver505 then reads data DQ′ with XCLK and outputs DQ″ in phase with XCLK. Phase-control circuit122 also in this case signals tomultiplexer510 to select DQ″, which is then clocked with CLK byreceiver515. Since the phase of DQS relative to CLK is represented as a digital state of phase-control circuit122, inverting the phase output byinterpolator112 involves a simple manipulation of that state.
• If the state of phase-control circuit122 instead indicates that DCLK is inOCT6, as shown by arrow414, phase-control circuit122 can cause auxiliary output X° to output XCLK having one-half the phase shift from CLK as that of DCLK, as shown byarrow418. Changing the phase state to output a signal having one-half the phase shift from CLK is also an easy operation. In this case also phase-control circuit122 signals tomultiplexer510 to select DQ″, which is then clocked with CLK byreceiver515. Thus, working with the phase octant of the data-sampling clock DCLK relative to the master clock CLK,system500 can transfer data between the data strobe domain DQS and the master clock CLK domain with minimal latency. Although described in terms of phase octants, other divisions of phase diagram400 may be employed, as well as more or less frequency reference vectors.
• The data-timing systems described above can also be used to receive and transmit data for the situation in which a strobe signal DQS has a different frequency than a master clock signal CLK. For example, the clock frequency CLK may be an integer multiple of the data strobe DQS frequency, for receiving or transmitting the data with one rather than both clock CLK edges. In this case, duty cycle correction of the CLK signals may not be needed, but phase information of the received data strobe DQS is used to generate a data-sampling clock DCLK. The double-frequency DCLK signal may be 180° out of phase with a 0° output that is in phase with DQS, to read the received data signal DQ with one edge of DCLK that is approximately 90° out of phase with DQ.
• While the above-described mechanisms and methods are useful for point-to-point data transfer between two devices of a system that transfers information, in systems such as a memory system the number of pins available at the controller limit additional DRAM connections tocontroller200.FIG. 10 illustrates an implementation of the present invention in an information storage andtransfer system600 having a multi-drop bus that allows more than one memory device to be coupled to the bus. Acontroller602 includes a conventionalmaster clock generator604 and a plurality of data-timingsystems606 and608. An I/O unit or group of I/O units610 are coupled to data-timing system606 and another I/O unit or group of I/O units612 are coupled to data-timing system608. Afirst bus614couples memory devices616,618 and620 tocontroller602 via I/O group610. Asecond bus624couples memory devices626,628 and630 tocontroller602 via I/O group612.Buses614 and624 may each include data, strobe, clock and control channels. Data, strobe and control signals may be routed tocontroller602 and the memory devices based upon their addresses withinsystem600.
• Data-timing system606 and608 may be similar to timingsystems100 and500 described above. In thismulti-drop system600, however, data-timingsystems606 and608 each store different phase-control states specific to each of the coupled memory devices. That is, data-timing system606 acquires phase information from a strobe signal sent bymemory device616, the phase information quantified as a digital state of a phase-control circuit ofsystem606 and used to create a data-sampling signal for clocking data received from thatmemory device616. Similarly, data-timing system606 separately acquires phase information from a strobe signal sent bymemory device618, and also separately acquires phase information from a strobe signal sent bymemory device620, the phase information stored as digital states of a phase-control circuit ofsystem606.Controller602 not only stores the plural received phase-control states of data-timing system606 but also stores plural received phase-control states of data-timing system608.
• In addition,controller602 may store various other phase-control states of data-timingsystems606 and608, such as individual transmit timing states for transmitting data to each of the memory devices, and individual auxiliary states for transferring received data into the clock domain ofmaster clock generator604. Each of these states may include information regarding per-byte offsets as well as per-bit offsets, as described above with reference toFIG. 4. Thuscontroller602 may select for a particular communication (e.g., data read or data write) with a particular device (e.g.,RAM616,RAM618 or RAM620), a digital state corresponding to the device and to the communication, the selected state being employed to provide phase adjustment on a per-bit as well as per-byte basis, the phase adjustment used for sampling received data, transmitting data in a phase for sampling, or aligning data with a selected clock domain.
• Although described above as a master-slave system,multi-drop system600 can be implemented as a system having plural controllers, each of which has a data-timing system similar to that described above. Moreover, the strobe signals need not be sent by the same device that transmits data signals. For example, another clock may be provided on an opposite end ofbus614 that transmits clock-to-master signals that are used bymemory devices616,618 and620 in transmitting data tocontroller602, with those clock-to-master signals processed by data-timing system606 to receive the data. In this case, a duty cycle corrected master clock can be phase-adjusted by the received clock-to-master signals to create a data-sampling signal for receiving the data and shifting the received data to the master clock domain.
• Although we have focused on teaching the preferred embodiments of improved data-timing systems, other embodiments and modifications of this invention will be apparent to persons of ordinary skill in the art in view of these teachings. Therefore, this invention is limited only by the following claims, which include all such embodiments, modifications and equivalents when viewed in conjunction with the above specification and accompanying drawings.

Claims (21)

1. (canceled)

2. A memory controller comprising:

an interface circuit to couple to a first memory device and a second memory device, the interface circuit including a first receiver circuit to receive a first read signal of a first phase from the first memory device and second read signal of a second phase from the second memory device;

a first register to store a first receive state corresponding to the first memory device, the first receive state derived from the first phase; and

a second register to store a second receive state corresponding to the second memory device, the second receive state derived from the second phase.

3. The memory controller ofclaim 2, wherein the first receive state represents a first offset from a clock signal and the second receive state represents a second offset from the clock signal.

4. The memory controller ofclaim 3, the interface circuit comprising a delay-locked loop to derive the first offset from and the second offset from the clock signal.

5. The memory controller ofclaim 2, wherein at least one of the first read signal and the second read signal comprises a strobe signal.

6. The memory controller ofclaim 2, wherein the interface circuit further includes transmitter circuits for transmitting first write data signals to the first memory device and second write data signals to the second memory device, the first register stores a first transmitting timing state for the first write data signals, and the second register stores a second transmitting timing state for the second write data signals.

7. A method performed by a memory controller, the method comprising:

receiving a first timing-reference signal and a first data signal from a first memory device;

deriving first phase information from the first timing-reference signal;

generating a first data-sampling signal from a clock signal based on the first phase information;

sampling the first data signal with the first data-sampling signal;

receiving a second timing-reference signal and a second data signal from a second memory device;

deriving second phase information from the second timing-reference signal;

generating a second data-sampling signal from the clock signal based on the second phase information; and

sampling the second data signal with the second data-sampling signal.

8. The method ofclaim 7, wherein generating the first data-sampling signal phase aligns the first data-sampling signal with the first data signal responsive to a phase offset between the first timing-reference signal and the clock signal.

9. The method ofclaim 7, wherein at least one of the first timing-reference signal and the second timing-reference signal transitions irregularly between high and low logic levels.

10. The method ofclaim 9, wherein the first timing-reference signal is a pseudo-random signal.

11. The method ofclaim 7, wherein the first timing-reference signal is not a clock signal.

12. The method ofclaim 7, further comprising maintaining a phase offset between the first data-sampling signal and the clock signal absent the first timing-reference signal.

13. The method ofclaim 12, further comprising storing a representation of the phase offset in a register.

14. A memory controller comprising:

a first lock circuit to phase adjust a first data-sampling signal relative to a clock signal responsive to a first phase-adjust signal;

a first phase detector to receive a first timing-reference signal of a first phase from a first memory device and to provide the first phase-adjust signal responsive to the first phase;

a first receiver to sample a first data signal from the first memory device with the first timing-reference signal;

a second lock circuit to phase adjust a second data-sampling signal relative to the clock signal responsive to a second phase-adjust signal;

a second phase detector to receive a second timing-reference signal of a second phase from a second memory device and to provide the second phase-adjust signal responsive to the second phase; and

a second receiver to sample a second data signal from the second memory device with the second timing-reference signal.

15. The memory controller ofclaim 14, wherein each of the first timing-reference signal and the second timing-reference signal transitions irregularly between high and low logic levels.

16. The memory controller ofclaim 15, wherein each of the first timing-reference signal and the second timing-reference signal is a pseudo-random signal.

17. The memory controller ofclaim 14, further comprising registers to store representations of the first phase and the second phase.

18. The memory controller ofclaim 17, wherein the registers store the representations absent the clock signal.

19. The memory controller ofclaim 14, supporting first and second modes, the memory controller establishing a phase offset between the first data-sampling signal and the clock signal responsive to the first timing-reference signal in the first mode and sampling the first data signal with the first data-sampling signal in the second mode.

20. The memory controller ofclaim 19, wherein the first mode supports a maintenance operation for the memory controller.

21. The memory controller ofclaim 14, further comprising a transmitter to transmit a third data signal to the first memory device, the third data signal being timed based on the first phase.

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