US20210004178A1 - Multi-Die System Capable of Sharing Non-volatile Memory - Google Patents

Abstract

A multi-die system includes a non-volatile memory, a first die having a first operational clock, a second die having a second operational clock, and an arbiter. The first die includes a first bus, a first bus filter coupled to the first bus and the arbiter for controlling access signals, a first access controller coupled to the first bus filter, and a first input/output (I/O) filter coupled to the first access controller, the arbiter and the non-volatile memory for controlling access to the non-volatile memory. The second die includes a second bus, a second bus filter coupled to the second bus and the arbiter, a second access controller coupled to the second bus filter, and a second I/O filter coupled to the second access controller, the arbiter and the non-volatile memory. The first and second operational clocks are independent.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention
• The present invention is related to a multi-die system, and particularly to a multi-die system capable of sharing non-volatile memory.
2. Description of the Prior Art
• In order to improve system performance and the system complexity cannot be met with a single die, a system with multiple dies becomes a choice. Traditionally, a die with central processing unit (CPU) has a dedicated non-volatile memory (e.g. ROM, non-volatile memory) for instruction, data storage and execute-in-place (XIP) support. Moreover, each die has its own independent operation. Therefore, the power domain and the clock (frequency) domain of each die are completely independent, that is, the power domain and/or the clock domain of each die are not identical, resulting in different levels or/and frequencies of signals within each chip. Moreover, since each chip has its own independent operation, operational clock signals within the respective chips are not synchronized with each other. That is, even if the frequencies of the operation clock signals in the respective chips are the same, the operation clock signals in the respective chips are not synchronized with each other. Thus multiple dedicated non-volatile memories are required for a multi-die system. However the traditional system of dedicated non-volatile memory can incur higher cost and the bandwidth of each non-volatile memory is not used to its maximum capacity.
• Therefore, there needs a solution to have a single non-volatile memory shared by multiple dies in order to reduce packaging complexity and cost while maximizing the bandwidth utilization.
SUMMARY OF THE INVENTION
• An embodiment provides a multi-die system including a non-volatile memory, a first die having a first operational clock, a second die having a second operational clock and an arbiter. The first die includes a first processor for generating a first control signal, a first access controller coupled to the first processor via a first bus for generating a first access signal to access the non-volatile memory according to the first control signal, a first bus filter coupled between the first processor and the first access controller for controlling the first access control signal to the first access controller, and a first input/output (I/O) filter coupled between the first access controller and the non-volatile memory for controlling the first access signal to the non-volatile memory. The second die having a second operational clock, the second die includes a second processor for generating a second control signal, a second access controller coupled to the second processor via a second bus for generating a second access signal to access the non-volatile memory according to the second control signal; a second bus filter coupled between the second processor and the second access controller, and for controlling the second control signal to the second access controller, and a second I/O filter coupled between the second access controller and the non-volatile memory for controlling the second access signal to the non-volatile memory. The arbiter is located in one of the first die and the second die for generating an arbitration signal according to the first and the second control signals. The first and the second bus filters, and the first and the second I/O filters are controlled according to the arbitration signal. The first and second operational clocks are independent.
• An embodiment provides a method of operating a multi-die system in a chip. The chip includes a first die, a second die and an arbiter. The method includes generating, by a first processor in the first die, a first control signal to a first access controller of the first die via a first path, generating, by the first access controller in the first die, a first access signal according to the first control signal to access a non-volatile memory via a second path, generating, by a second processor in the second die, a second control signal to a second access controller of the second die via a third path, generating, by the second access controller in the second die, a second access signal according to the second control signal to access the non-volatile memory via a fourth path, generating, by an arbiter, an arbitration signal according to the first and the second control signals, and controlling the first, the second, the third, and the fourth paths according to the arbitration signal.
• An embodiment provides a method of operating a multi-die system in a chip. The multi-die system includes a non-volatile memory, a first die and a second die. The first die includes an arbiter coupled to the second die. The method includes the arbiter granting access for the first die to access the non-volatile memory by default, the first die accessing the non-volatile memory, after an access of the first die, a request signal being de-asserted for one cycle for the arbiter to perform arbitration, and the arbiter granting access for the first die or the second die to access the non-volatile memory according to an arbitration result. The first die and the second die are independent operations.
• These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a diagram of a multi-die system of an embodiment of present invention.
• FIG. 2 is a diagram of the operating signals of the arbitration process of the multi-die system inFIG. 1.
• FIG. 3 is a state diagram further explaining the arbitration process inFIG. 2.
• FIG. 4 is a flowchart of a method of operating a multi-die system ofFIG. 1.
DETAILED DESCRIPTION
• FIG. 1 is a diagram of amulti-die system100 of an embodiment of present invention. Themulti-die system100 includes anon-volatile memory10, afirst die20 and asecond die30. Thefirst die20 includes afirst processor26, afirst bus21, anarbiter22 for arbitrating the multi-dies (20,30) to access thenon-volatile memory10, a first bus filter23 coupled to thefirst processor26 and thearbiter22 for monitoring and controlling access signals from thefirst processor26, afirst access controller24 coupled to the first bus filter23 for accessing thenon-volatile memory10 according to control signals of thearbiter22, and a first input/output (I/O)filter25 coupled to non-volatile thearbiter22 non-volatile for controlling access to thenon-volatile memory10. The second die30 includes asecond processor36, asecond bus31, asecond bus filter33 coupled to thesecond processor36 and thearbiter22 for monitoring and controlling non-volatile access signals from thesecond processor36, asecond access controller34 coupled to thesecond bus filter33 for non-volatile accessing thenon-volatile memory10 according to control signals of thearbiter22, and a second I/O filter35 coupled to thesecond access controller34, thearbiter22 and thenon-volatile memory10 for controlling access to thenon-volatile memory10. In one embodiment, thearbiter22 is disposed outside of thefirst die20 and thesecond die30. In an embodiment, the power settings (e.g., operate in one of normal mode, sleep mode, suspend mode, and power off) of thefirst die20 and thesecond die30 are different. In one embodiment, if the performances of thefirst die20 and thesecond die30 are not the same, thearbiter22 is disposed in a higher performance die. For example, the first die20 has a faster clock, higher bandwidth, higher structure, configuration, etc. than thesecond die30. For examples, compared to thesecond die30, thefirst die20 has a faster clock, longer operation in normal mode, higher bandwidth, greater processing power (structure, configuration), and the like.
• In an embodiment, thefirst die20 and thesecond die30 each have a priority to access thenon-volatile memory10. In one embodiment, when the priorities of the dies are the same, thearbiter22 can use a round-robin scheme to determine which dies can access thenon-volatile memory10. In one embodiment, the level of priority is related to what functions the dies perform. In one embodiment, the priority level is related to the performance of the dies. In the embodiment, thefirst die20 has a higher priority than thesecond die30 to access thenon-volatile memory10. Also, thefirst die20 and the second die30 may have different clocks, bandwidth, structures, configurations and/or power. Thus thefirst bus21 and thesecond bus31 may have different clocks, bandwidth, bus structures and/or configurations and thefirst die20 may have a faster system clock than thesecond die30. Thefirst bus21 and thebus31 may be AHB, AXI or one of any types of buses. Thenon-volatile memory10 may have an interface such as QSPI or other types of interfaces. In addition, thearbiter22 would grant access to a request of highest priority if more than one request is issued.
• The first bus filter23 and thesecond bus filter33 generate request signals ReqA and ReqB to thearbiter22 when thenon-volatile memory10 needs to be accessed. The first bus filter23 passes access signals from thefirst bus21 and tofirst access controller24 when a grant signal GntA from thearbiter22 is asserted to thefirst die20. Similarly, thesecond bus filter33 passes access signals from thesecond bus31 and tosecond access controller34 when a grant signal GntB from thearbiter22 is asserted to thesecond die30. In contrast, the first bus filter23 blocks access signals and responds to thefirst bus21 and tofirst access controller24 accordingly when the grant signal GntA is de-asserted to thefirst die20. Thesecond bus filter33 blocks access signals and responds to thesecond bus31 and tosecond access controller34 accordingly when the grant signal GntB is de-asserted to thesecond die30.
• The first I/O filter25 passes interface signals from thefirst access controller24 to thenon-volatile memory10 when the grant signal GntA is asserted to thefirst die20. Similarly, the second I/O filter35 passes interface signals from thesecond access controller34 to thenon-volatile memory10 when the grant signal GntB is asserted to thesecond die30. In contrast, the first I/O filter25 stops interface signals from thefirst access controller24 to thenon-volatile memory10 when the grant signal GntA is de-asserted to thefirst die20. The second I/O filter35 stops interface signals from thesecond access controller34 to thenon-volatile memory10 when the grant signal GntB is de-asserted to thesecond die30.
• FIG. 2 is a diagram of the operating signals of the arbitration process by thearbiter22. The diagram shows a clock signal ClkA for thefirst die20, the grant signal GntA for thefirst die20, the request signal ReqA for thefirst die20, the grant signal GntB for thesecond die30, and the request signal ReqB for thesecond die30.
• Initially, thearbiter22 grants access for thefirst die20 to access thenon-volatile memory10 by default and by sending the grant signal GntA to the first bus filter23 and the I/O filter25. At this time, thefirst die20 can access to thenon-volatile memory10. After an access of thefirst die20, the request signal ReqA would be de-asserted for one cycle for thearbiter22 to perform arbitration. If thefirst die20 continues to send the request signal ReqA in the de-asserted cycle, thearbiter22 would continue to grant access to thefirst die20 by maintaining the grant signal GntA to thefirst die20. In some embodiments, When thefirst die20 has completed a certain number of accesses and thesecond die30 has sent the request signal ReqB to thearbiter22, thearbiter22 would grant access to thesecond die30 by sending the grant signal GntB to thesecond die30 regardless thefirst die20 has a pending request or not.
• When thefirst die20 no longer asserts the request signal ReqA in the de-asserted cycle, it means thefirst die20 has no more pending request. At this time, if thesecond die30 asserts a request signal ReqB to thearbiter22, thearbiter22 would send a grant signal GntB to thesecond die30. Specifically, thesecond bus filter33 asserts the request signal ReqB to thearbiter22 and thearbiter22 asserts the grant signal GntB back to thesecond bus filter33 and the second I/O filter35 to allow thesecond die30 to access thenon-volatile memory10. After an access of thesecond die30, the request signal ReqB would be de-asserted for one cycle for thearbiter22 to perform arbitration to indicate current access has been started. Thearbiter22 also can start arbitration next cycle for next access. If thesecond die30 continues to send the request signal ReqB in the de-asserted cycle, thearbiter22 would continue to grant access to thesecond die30 by maintaining the grant signal GntB to thesecond die30. Asserts the request signal ReqB after the de-asserted cycle,arbiter22 would base on priority setting to do arbitration if ReqA is also asserted. When thesecond die30 completes configured number of accesses or no more pending accesses. Then, thearbiter22 would then grant access for thefirst die20 if thefirst die20 has a pending request. In some embodiments, When thesecond die30 has completed a certain number of accesses and thefirst die20 has sent the request signal ReqB to thearbiter22, thearbiter22 would grant access to thefirst die20 by sending the grant signal GntA to thefirst die20 regardless thesecond die30 has a pending request or not. In some embodiments, different arbitration priority settings can be supported, e.g. fixing priority or number of accesses to be configured. For the fixed priority, assume die20 has higher priority, GntA will be asserted as long as ReqA is asserted regardless of ReqB status. For number of accesses to be configured, once GntA is asserted, GntA will be de-asserted only when die20 has completed the number of accesses or no more pending accesses.
• FIG. 3 is a state diagram further explaining the arbitration process. The diagram shows a round-robin arbitration process. Thearbiter22 makes arbitration based on priority setting. Initially a reset signal sets grant to thefirst die20 by default. If thefirst die20 has completed a certain number of accesses and/or has no more pending request, and a request has been sent from thesecond die30, thearbiter22 would switch the grant from thefirst die20 to thesecond die30. If thesecond die30 has completed a certain number of accesses and/or has no more pending access, and a request has been sent from thefirst die20, thearbiter22 would switch the grant from thesecond die30 to thefirst die20. If no request has been sent from either thefirst die20 or thesecond die30, thearbiter22 could leave the grant at the last state for the following cycles until receiving a new request.
• FIG. 4 is a flowchart of amethod400 of operating amulti-die system100. The method may include the following steps:
• S400: Generate, by thefirst processor26 in thefirst die20, a first control signal to afirst access controller24 of thefirst die20 via a first path;
• S402: Generate, by thefirst access controller24 in thefirst die20, a first access signal according to the first control signal to access thenon-volatile memory10 via a second path;
• S404: Generate, by thesecond processor36 in thesecond die30, a second control signal to thesecond access controller34 of thesecond die30 via a third path;
• S406: Generate, by thesecond access controller34 in thesecond die30, a second access signal according to the second control signal to access thenon-volatile memory10 via a fourth path;
• S408: Generate, by thearbiter22, an arbitration signal according to the first and the second control signals; and
• S410: Control the first, the second, the third, and the fourth paths according to the arbitration signal.
• In summary, with the aforementioned implementation, the multi-die system can share a single non-volatile memory to execute instruction in place, store data, program and erase the non-volatile memory to update data and instruction, thus increasing bandwidth utilization of the non-volatile memory. The implementation can reduce the complexity and cost of the system package thus reducing manufacturing cost.
• Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

What is claimed is:

1. A multi-die system comprising:

a non-volatile memory;

a first die having a first operational clock, the first die comprising:

a first processor, configured to generate a first control signal;

a first access controller, coupled to the first processor via a first bus, and configured to generate a first access signal to access the non-volatile memory according to the first control signal;

a first bus filter coupled between the first processor and the first access controller, and configured to control the first access control signal to the first access controller;

and

a first input/output (I/O) filter coupled between the first access controller and the non-volatile memory, configured to control the first access signal to the non-volatile memory;

a second die having a second operational clock, the second die comprising:

a second processor, configured to generate a second control signal;

a second access controller coupled to the second processor via a second bus, configured to generate a second access signal to access the non-volatile memory according to the second control signal;

a second bus filter coupled between the second processor and the second access controller, and configured to control the second control signal to the second access controller; and

a second I/O filter coupled between the second access controller and the non-volatile memory, configured to control the second access signal to the non-volatile memory;

an arbiter, located in one of the first die and the second die, configured to generate an arbitration signal according to the first and the second control signals;

wherein the first and the second bus filters, and the first and the second I/O filters are controlled according to the arbitration signal;

wherein the first and second operational clocks are independent.

2. The multi-die system ofclaim 1 wherein the first die has a higher priority than the second die to access the non-volatile memory.

3. The multi-die system ofclaim 1, wherein priorities of the first die and the second die are determined according to performances of the first and the second dies.

4. The multi-die system ofclaim 1 wherein a priority the first die and that of the second die are the same.

5. The multi-die system ofclaim 1 wherein the first and the second operational clocks are different.

6. The multi-die system ofclaim 1 wherein at least one of bus clock, bus bandwidth, bus structure, and bus configuration between the first and the second buses are different.

7. The multi-die system ofclaim 1 wherein power setting of the first die and that of the second die are different.

8. The multi-die system ofclaim 1 wherein the first and the second bus filters, and the first and the second I/O filters are controlled according to the arbitration signal such that the operational clocks in the first and the second dies are not synchronized with each other is overcome.

9. A method of operating a multi-die system in a chip, the chip comprising a first die, a second die and an arbiter, the method comprising:

generating, by a first processor in the first die, a first control signal to a first access controller of the first die via a first path;

generating, by the first access controller in the first die, a first access signal according to the first control signal to access a non-volatile memory via a second path;

generating, by a second processor in the second die, a second control signal to a second access controller of the second die via a third path;

generating, by the second access controller in the second die, a second access signal according to the second control signal to access the non-volatile memory via a fourth path;

generating, by an arbiter, an arbitration signal according to the first and the second control signals; and

controlling the first, the second, the third, and the fourth paths according to the arbitration signal;

wherein the first die having a first power and a first operational clock and the second die having a second power and a second operational clock are independently operation.

10. The method ofclaim 9, wherein the first and the second operational clocks are different.

11. The method ofclaim 9, wherein the first and the second operational clocks are unsynchronized.

12. The method ofclaim 9, wherein at least one of bus clock, bus bandwidth, bus structure, and bus configuration of the first and the second dies are different.

13. The method ofclaim 9, wherein the first, the second, the third, and the fourth paths are controlled according to the arbitration signal such that the operational clocks in the first and the second dies are not synchronized is overcome.

14. A method of operating a multi-die system in a chip, the multi-die system comprising a first die and a second die, the first die comprising an arbiter coupled to the second die, the method comprising:

the arbiter granting access for the first die to access a non-volatile memory by default;

the first die accessing the non-volatile memory;

after an access of the first die, a request signal being de-asserted for one cycle for the arbiter to perform arbitration; and

the arbiter granting access for the first die or the second die to access the non-volatile memory according to an arbitration result;

wherein the first die and the second die are independent operations.

15. The method ofclaim 14 wherein the arbiter granting access for the first die to access the non-volatile memory if the first die has a pending request and/or has not completed a certain number of accesses.

16. The method ofclaim 14 wherein the arbiter granting access for the second die to access the non-volatile memory if the first die has no pending request or has completed a certain number of accesses and the second die has a pending request.

17. The method ofclaim 16 further comprising:

the second die accessing the non-volatile memory; and

after an access of the second die, a request signal being de-asserted for one cycle to indicate the current access has started for the arbiter to keep tracking of number of accesses has already been taken.

18. The method ofclaim 17 wherein the arbiter granting access for the first die to access the non-volatile memory if the second die has no pending request or has completed a certain number of accesses and the first die has a pending request or the first die has higher priority and the first die has a pending request.

19. The method ofclaim 17 further comprising:

the arbiter granting access for the second die to access the non-volatile memory if the second die has a pending request and has not completed a certain number of accesses.

20. The method ofclaim 14 wherein the first die has a higher priority than the second die to access the non-volatile memory.

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