US20200075547A1 - Double-sided integrated circuit module having an exposed semiconductor die - Google Patents
Double-sided integrated circuit module having an exposed semiconductor dieDownload PDFInfo
- Publication number
- US20200075547A1 US20200075547A1US16/119,554US201816119554AUS2020075547A1US 20200075547 A1US20200075547 A1US 20200075547A1US 201816119554 AUS201816119554 AUS 201816119554AUS 2020075547 A1US2020075547 A1US 2020075547A1
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- Prior art keywords
- module
- semiconductor die
- mold compound
- coupled
- electronic component
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present disclosurerelates to integrated circuit (IC) modules for electronic devices, and more particularly to double-sided IC modules for radio frequency (RF) applications.
- ICintegrated circuit
- RFradio frequency
- ICintegrated circuit
- a double-sided IC modulemounts IC components to both of a top side and a bottom side of the module's substrate.
- electronic devicescontinue to drive further reductions in IC module size.
- the present disclosurerelates to a double-sided integrated circuit (IC) module having an exposed semiconductor die.
- the double-sided IC moduleincludes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side is removed, exposing a semiconductor die surface of at least one of the electronic components.
- Exposing the semiconductor diereduces an overall thickness of the double-sided IC module.
- exposing the semiconductor diecan provide additional advantages, such as by providing a surface to which a heat exchange device can be coupled (e.g., to transfer heat away from the semiconductor die).
- electrical, magnetic, or other connectionscan be formed between the semiconductor die and other electronic components through the exposed surface.
- a radio frequency (RF) modulein an exemplary aspect, includes a module substrate defining a top side and a bottom side. A plurality of electronic components is coupled to the top side and a semiconductor die coupled to the bottom side. The RF module also includes a first mold compound coupled to the semiconductor die and exposing a surface of the semiconductor die.
- RFradio frequency
- Another exemplary aspectrelates to a method for assembling a RF module.
- the methodincludes the operations of coupling an electronic component to a top side of a module substrate and coupling a semiconductor die to a bottom side of the module substrate.
- the methodalso includes encapsulating the semiconductor die in a mold compound such that the mold compound at least partially surrounds the semiconductor die and removing a portion of the mold compound to expose a surface of the semiconductor die.
- the electronic deviceincludes a circuit board on which a plurality of electronic components is mounted and an IC module coupled to the circuit board.
- the IC moduleincludes a module substrate having a top side and a bottom side adjacent the circuit board.
- the IC modulealso includes a first electronic component coupled to the top side and a second electronic component coupled to the bottom side.
- the IC modulealso includes a mold compound at least partially surrounding the second electronic component and exposing a surface of the second electronic component.
- FIG. 1illustrates an electronic device, which includes an integrated circuit (IC) module coupled to a circuit board.
- ICintegrated circuit
- FIG. 2illustrates the electronic device of FIG. 1 having a portion of the first mold compound on a bottom side of the IC module removed, exposing a semiconductor die surface of at least one bottom electronic component.
- FIG. 3Aillustrates an exemplary bottom view of the IC module of FIG. 2 prior to encapsulating the bottom electronic components in the first mold compound.
- FIG. 3Billustrates another exemplary bottom view of the IC module of FIG. 2 with the bottom electronic components encapsulated in the first mold compound.
- FIG. 3Cillustrates another exemplary bottom view of the IC module of FIG. 2 after a portion of the first mold compound is removed to expose the semiconductor die surface.
- FIG. 4Aillustrates an exemplary electronic device as in FIG. 2 , having a device mounted to the exposed semiconductor die surface.
- FIG. 4Billustrates an exemplary electronic device as in FIG. 2 , having another device mounted to the exposed semiconductor die surface.
- FIG. 4Cillustrates an exemplary electronic device as in FIG. 2 , having another device mounted to the exposed semiconductor die surface.
- FIG. 4Dillustrates an exemplary electronic device as in FIG. 2 , having a connection formed between the exposed semiconductor die surface and the circuit board.
- FIG. 4Eillustrates an exemplary electronic device as in FIG. 2 , having another connection formed between the exposed semiconductor die surface and the circuit board.
- FIG. 4Fillustrates an exemplary electronic device as in FIG. 2 , having variations in its components.
- the present disclosurerelates to a double-sided integrated circuit (IC) module having an exposed semiconductor die.
- the double-sided IC moduleincludes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side is removed, exposing a semiconductor die surface of at least one of the electronic components.
- Exposing the semiconductor diereduces an overall thickness of the double-sided IC module.
- exposing the semiconductor diecan provide additional advantages, such as by providing a surface to which a heat exchange device can be coupled (e.g., to transfer heat away from the semiconductor die).
- electrical, magnetic, or other connectionscan be formed between the semiconductor die and other electronic components through the exposed surface.
- FIG. 1illustrates an electronic device 10 , which includes an IC module 12 coupled to a circuit board 14 .
- the IC module 12is a shielded double-sided IC module, which includes a module substrate 16 , a first top electronic component 18 , a second top electronic component 20 , a third top electronic component 22 , a first bottom electronic component 24 , and a second bottom electronic component 26 .
- Each of the bottom electronic components 24 , 26is encapsulated by a first mold compound 28
- each of the top electronic components 18 , 20 , 22is encapsulated by a second mold compound 30 .
- a shielding structure 32can at least partially surround the IC module 12 , and module contacts 34 couple the IC module 12 to the circuit board 14 .
- the first bottom electronic component 24 , the second bottom electronic component 26 , and the module contacts 34are attached to a bottom side 36 of the module substrate 16 .
- the IC module 12may include fewer or more bottom electronic components 24 , 26 .
- Each of the bottom electronic components 24 , 26may be a flip-chip die, a wire-bonding die, a surface mounted device (SMD), an inductor, or other active or passive component.
- SMDsurface mounted device
- at least one of the bottom electronic components 24 , 26includes a semiconductor die.
- the module contacts 34are conductive and may be solder bumps or copper pillars forming an electrical connection with the circuit board 14 (e.g., connecting the top electronic components 18 , 20 , 22 and/or the bottom electronic components 24 , 26 to other devices mounted on the circuit board 14 ). Each of the module contacts 34 can be used for grounded signals or non-grounded signals, and at least some of the module contacts 34 may be electrically isolated from other module contacts 34 .
- the first mold compound 28resides over the bottom side 36 of the module substrate 16 and encapsulates the first bottom electronic component 24 and the second bottom electronic component 26 . Each module contact 34 is taller than the bottom electronic components 24 , 26 and exposed through the first mold compound 28 .
- the first mold compound 28may be an organic epoxy resin or similar material. In an exemplary aspect, the first mold compound 28 is a 20 micron ( ⁇ m) top cut material.
- the first top electronic component 18 and the second top electronic component 20are attached to a top side 38 of the module substrate 16 .
- the IC module 12may include fewer or more top electronic components 18 , 20 .
- Each of the first top electronic component 18 and the second top electronic component 20may be a flip-chip die, a wire-bonding die, a SMD, an inductor, or other active or passive component.
- the second mold compound 30resides over the top side 38 of the module substrate 16 and encapsulates the first top electronic component 18 and the second top electronic component 20 .
- the second mold compound 30may be formed from a same or different material as the first mold compound 28 .
- a top surface 40 of the IC module 12is defined by a top surface of the second mold compound 30 (e.g., a surface opposite the module substrate 16 ).
- a side surface 42 of the IC module 12is defined by a side surface of the second mold compound 30 , a side surface of the module substrate 16 , and a side surface of the first mold compound 28 .
- the shielding structure 32(e.g., shield layer) entirely covers the top surface 40 of the IC module 12 and entirely or almost entirely covers the side surface 42 of the IC module 12 .
- the shielding structure 32does not cover a bottom side of the IC module 12 , which couples to the circuit board 14 .
- entirely covering a surfacerefers to covering at least 99% of the surface, while almost entirely covering a surface refers to covering at least 90% of the surface.
- the shielding structure 32can include a single layer of material, or it can include multiple layers of the same or different materials.
- an interior layere.g., covering the top surface 40 and the side surface 42 of the IC module 12
- An exterior layermay reside over the interior layer, and may be formed of nickel with a thickness between 1 ⁇ m and 3 ⁇ m.
- the module substrate 16may be a laminate having a number of layers 44 . These layers 44 of the module substrate 16 may include prepreg material.
- the module substrate 16can also include conductive elements 46 and via structures 48 , which may be formed of an appropriate conductive material. Generally, the conductive elements 46 and the via structures 48 form electrical connections between one or more of the electronic components 18 , 20 , 22 , 24 , 26 and the circuit board 14 .
- a portion of the first mold compound 28 on a bottom side of the IC module 12is removed, exposing a semiconductor die surface 50 , 52 of at least one of the bottom electronic components 24 , 26 .
- the exposed semiconductor die surface 50 , 52is a bottom surface of the bottom electronic component 24 , 26 facing opposite the module substrate 16 .
- a bottom surface 54 of the IC module 12is defined by the semiconductor die surface(s) 50 , 52 and a bottom surface of the first mold compound 28 .
- one of the semiconductor die surfaces 50 , 52is exposed (e.g., the semiconductor die surface 50 , 52 further below the module substrate 16 ), while in other examples two or more semiconductor die surfaces 50 , 52 are exposed.
- the IC module 12may be a radio frequency (RF) module, providing processing, signal conditioning, controls, and/or similar functions for RF signals of the electronic device 10 .
- the top electronic components 18 , 20 , 22 and bottom electronic components 24 , 26 of the RF module 12may be configured for RF operation.
- Each of the electronic components 18 , 20 , 22 , 24 , 26 and the module contacts 34are mounted to the module substrate 16 through an appropriate technique.
- the first top electronic component 18 and the third top electronic component 22are each a SMD which is mounted by solder, reflow, an adhesive, or similar technique.
- the second top electronic component 20 , the first bottom electronic component 24 , and the second bottom electronic component 26are each a semiconductor die (e.g., a flip-chip die or a wire-bonding die) mounted to the module substrate 16 through a set of solder bumps 56 or similar conductive elements (e.g., through a reflow process). It should be understood that the mounting of the electronic components 18 , 20 , 22 , 24 , 26 is shown for illustrative purposes, and each component may be mounted differently in different applications.
- the first mold compound 28is applied over the bottom side 36 of the module substrate 16 to encapsulate each bottom electronic component 24 , 26 as depicted in FIG. 1 , and removed to expose at least one semiconductor die surface 50 , 52 as depicted in FIG. 2 .
- the first mold compound 28may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, or screen print encapsulation. In an exemplary aspect, if there is space between the bottom side 36 of the module substrate 16 and a bottom electronic component 24 , 26 , the first mold compound 28 fills the space. A curing process hardens the first mold compound 28 .
- the second mold compound 30is applied over the top side 38 of the module substrate 16 to encapsulate each top electronic component 18 , 20 , 22 .
- the second mold compound 30may be the same or a different material as the first mold compound 28 , and may be applied through the same or a different technique. In some cases, both the first mold compound 28 and the second mold compound 30 are applied in a same process, and in other cases the first mold compound 28 and the second mold compound 30 are applied in separate processes.
- a height H of the module contacts 34can be reduced.
- an overall thickness T of the IC module 12is reduced.
- a thickness of each bottom electronic component 24 , 26is between 40 ⁇ m and 150 ⁇ m thick
- a thickness of the first mold compound 28e.g., a distance between the bottom surface 54 of the IC module 12 and the bottom side 36 of the module substrate 16
- the height H of the module contacts 34is between 100 and 300 ⁇ m prior to attachment to the circuit board 14 .
- exposing the semiconductor die surface 50 , 52is further illustrated in FIGS. 3A-3C .
- exposing the semiconductor die surface 50 , 52can provide additional advantages, such as by providing a surface for coupling a device to the bottom electronic component 24 , 26 or by facilitating connections between the bottom electronic component 24 , 26 and the circuit board 14 , as discussed further with respect to FIGS. 4A-4E . It should be understood that variations in components of the IC module 12 are contemplated, as depicted in FIG. 4F .
- FIGS. 3A-3Cprovide exemplary steps that illustrate a process to fabricate the IC module 12 shown in FIG. 2 having the exposed semiconductor die surface 50 , 52 .
- the exemplary stepsare illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 3A-3C .
- FIG. 3Aillustrates an exemplary bottom view of the IC module 12 of FIG. 2 prior to encapsulating the bottom electronic components 24 , 26 in the first mold compound 28 .
- FIG. 3Billustrates another exemplary bottom view of the IC module 12 of FIG. 2 with the bottom electronic components 24 , 26 encapsulated in the first mold compound 28 .
- FIG. 3Cillustrates another exemplary bottom view of the IC module 12 of FIG. 2 after a portion of the mold compound 28 is removed to expose the semiconductor die surface 50 , 52 .
- the first bottom electronic component 24 , the second bottom electronic component 26 , and the module contacts 34are attached at the bottom side 36 of the module substrate 16 as depicted in FIG. 3A .
- Some module contacts 34may be used for grounded signals, and may be electrically isolated from other module contacts 34 which are used for non-grounded signals.
- the module contacts 34are taller than the first bottom electronic component 24 and the second bottom electronic component 26 .
- the first mold compound 28is applied to the IC module 12 as depicted in FIG. 3B .
- the first mold compound 28resides over the bottom side 36 of the module substrate 16 to encapsulate each bottom electronic component 24 , 26 and each module contact 34 .
- the bottom electronic components 24 , 26 and the module contacts 34are entirely encapsulated, and in other embodiments, the module contacts 34 are only partially encapsulated.
- the first mold compound 28may be applied by various procedures.
- the first mold compound 28is overmolded. A curing process hardens the first mold compound 28 .
- the first mold compound 28is applied and cured, a portion of the first mold compound 28 is removed to expose the at least one semiconductor die surface 50 , 52 of the bottom electronic components 24 , 26 as depicted in FIG. 3C .
- the removal of the portion of the first mold compound 28may be done with a mechanical grinding process, a chemical removal process, a laser ablation, or other appropriate technique.
- the bottom surface 54 of the IC module 12is defined by the semiconductor die surface(s) 50 , 52 and a bottom surface of the first mold compound 28 . In some applications, the bottom surface 54 is a common plane at and around the semiconductor die surface(s) 50 , 52 .
- Exposure of the semiconductor die surface 50 , 52can provide additional advantages, such as by providing a surface for coupling a device to one or more of the bottom electronic components 24 , 26 as depicted in FIGS. 4A-4C .
- the exposed semiconductor die surface 50 , 52can also facilitate connections between at least one of the bottom electronic components 24 , 26 and the circuit board 14 , as depicted in FIGS. 4D and 4E .
- Variations in the components of the IC module 12are contemplated, such as depicted in FIG. 4F .
- FIG. 4Aillustrates an exemplary electronic device 10 as in FIG. 2 , having a device mounted to the exposed semiconductor die surface 50 , 52 .
- one or more of the bottom electronic components 24 , 26may benefit from direct heat transfer, such as heat dissipation.
- a heat exchanger 58may be coupled to the exposed semiconductor die surface(s) 50 , 52 of the bottom electronic component(s) 24 , 26 . This can improve the performance of the bottom electronic component(s) 24 , 26 and/or prevent damage to the bottom electronic component(s) 24 , 26 during operation.
- the heat exchanger 58may be mounted to the bottom electronic component(s) 24 , 26 and/or the first mold compound 28 through an adhesive material (e.g., a thermal adhesive) or another appropriate technique.
- one or more of the bottom electronic components 24 , 26may include a sensor (e.g., a temperature sensor, a pressure sensor, and so on) or other device, as depicted in FIGS. 4B and 4C .
- a separate sensor substrate 60e.g., a conductive material, an optical material, and so on
- the sensor substrate 60can be coupled to more than one bottom electronic component 24 , 26 as depicted in FIG. 4C .
- the sensor substrate 60can facilitate operation of the sensor.
- the sensor substrate 60may be omitted and the sensor in the bottom electronic component 24 , 26 can perform its operations directly.
- FIG. 4Dillustrates an exemplary electronic device 10 as in FIG. 2 , having a connection formed between the exposed semiconductor die surface 50 , 52 and the circuit board 14 .
- a conductive pad 62is coupled to the semiconductor die surface 50 , 52 and a corresponding conductive pad 64 is coupled to the circuit board 14 .
- the conductive pad 62 and/or the corresponding conductive pad 64can be an exposed or insulated trace, pad, coil, or another shape.
- the conductive pad 62 and the corresponding conductive pad 64can exchange signals and/or power through an indirect electromagnetic technique, such as inducing electrical signals through electrical, magnetic, capacitive, or inductive techniques.
- the conductive pad 62can be included within the bottom electronic component 24 , 26 rather than coupled to the semiconductor die surface 50 , 52 .
- a direct electrical connectionmay be formed between one or more of the bottom electronic components 24 , 26 and the circuit board 14 through the exposed semiconductor die surface 50 , 52 as illustrated in FIG. 4E .
- one or more conductors 66can be coupled between the semiconductor die surface 50 , 52 and the circuit board 14 .
- the conductors 66can be deposited on or coupled to each of the semiconductor die surface 50 , 52 and the circuit board 14 through soldering, an adhesive (e.g., a conductive adhesive), vapor deposition, printing, and similar techniques.
- the conductors 66can facilitate an exchange of power and/or signals between the bottom electronic component(s) 24 , 26 and one or more devices coupled to the circuit board 14 (not shown).
- FIG. 4Fillustrates an exemplary electronic device 10 as in FIG. 2 , having variations in its components.
- the IC module 12may include modules contacts 34 a , 34 b having different shapes.
- one or more of the module contacts 34 amay have a substantially planar surface attached to the bottom side 36 of the module substrate 16 .
- one or more of the module contacts 34 bmay include a notched or otherwise irregular surface attached to the bottom side 36 of the module substrate 16 .
- the module contacts 34 a , 34 bmay be solder bumps or copper pillars forming an electrical connection with the circuit board 14 .
- the surfaces of the module contacts 34 a , 34 b attached to the bottom side 36 of the module substrate 16may be machined, molded, or otherwise formed as depicted in FIG. 4F . It should be understood that other variations and modifications of the IC module 12 and its components are also contemplated herein.
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Abstract
Description
- The present disclosure relates to integrated circuit (IC) modules for electronic devices, and more particularly to double-sided IC modules for radio frequency (RF) applications.
- Many electronic devices include multiple components, including integrated circuit (IC) modules. Such components are often mounted to circuit boards in order to provide various functionalities. Traditional IC modules include a substrate on which multiple IC components (e.g., semiconductor dice) are mounted. As electronic devices have become smaller, demand for more compact IC modules has increased.
- One solution to forming compact electronic devices has been to form double-sided IC modules. A double-sided IC module mounts IC components to both of a top side and a bottom side of the module's substrate. However, electronic devices continue to drive further reductions in IC module size.
- The present disclosure relates to a double-sided integrated circuit (IC) module having an exposed semiconductor die. The double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side is removed, exposing a semiconductor die surface of at least one of the electronic components.
- Exposing the semiconductor die reduces an overall thickness of the double-sided IC module. In addition, exposing the semiconductor die can provide additional advantages, such as by providing a surface to which a heat exchange device can be coupled (e.g., to transfer heat away from the semiconductor die). In other examples, electrical, magnetic, or other connections can be formed between the semiconductor die and other electronic components through the exposed surface.
- In an exemplary aspect, a radio frequency (RF) module is provided. The RF module includes a module substrate defining a top side and a bottom side. A plurality of electronic components is coupled to the top side and a semiconductor die coupled to the bottom side. The RF module also includes a first mold compound coupled to the semiconductor die and exposing a surface of the semiconductor die.
- Another exemplary aspect relates to a method for assembling a RF module. The method includes the operations of coupling an electronic component to a top side of a module substrate and coupling a semiconductor die to a bottom side of the module substrate. The method also includes encapsulating the semiconductor die in a mold compound such that the mold compound at least partially surrounds the semiconductor die and removing a portion of the mold compound to expose a surface of the semiconductor die.
- Another exemplary aspect relates to an electronic device. The electronic device includes a circuit board on which a plurality of electronic components is mounted and an IC module coupled to the circuit board. The IC module includes a module substrate having a top side and a bottom side adjacent the circuit board. The IC module also includes a first electronic component coupled to the top side and a second electronic component coupled to the bottom side. The IC module also includes a mold compound at least partially surrounding the second electronic component and exposing a surface of the second electronic component.
- Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
- The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
FIG. 1 illustrates an electronic device, which includes an integrated circuit (IC) module coupled to a circuit board.FIG. 2 illustrates the electronic device ofFIG. 1 having a portion of the first mold compound on a bottom side of the IC module removed, exposing a semiconductor die surface of at least one bottom electronic component.FIG. 3A illustrates an exemplary bottom view of the IC module ofFIG. 2 prior to encapsulating the bottom electronic components in the first mold compound.FIG. 3B illustrates another exemplary bottom view of the IC module ofFIG. 2 with the bottom electronic components encapsulated in the first mold compound.FIG. 3C illustrates another exemplary bottom view of the IC module ofFIG. 2 after a portion of the first mold compound is removed to expose the semiconductor die surface.FIG. 4A illustrates an exemplary electronic device as inFIG. 2 , having a device mounted to the exposed semiconductor die surface.FIG. 4B illustrates an exemplary electronic device as inFIG. 2 , having another device mounted to the exposed semiconductor die surface.FIG. 4C illustrates an exemplary electronic device as inFIG. 2 , having another device mounted to the exposed semiconductor die surface.FIG. 4D illustrates an exemplary electronic device as inFIG. 2 , having a connection formed between the exposed semiconductor die surface and the circuit board.FIG. 4E illustrates an exemplary electronic device as inFIG. 2 , having another connection formed between the exposed semiconductor die surface and the circuit board.FIG. 4F illustrates an exemplary electronic device as inFIG. 2 , having variations in its components.- The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
- It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
- Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- The present disclosure relates to a double-sided integrated circuit (IC) module having an exposed semiconductor die. The double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side is removed, exposing a semiconductor die surface of at least one of the electronic components.
- Exposing the semiconductor die reduces an overall thickness of the double-sided IC module. In addition, exposing the semiconductor die can provide additional advantages, such as by providing a surface to which a heat exchange device can be coupled (e.g., to transfer heat away from the semiconductor die). In other examples, electrical, magnetic, or other connections can be formed between the semiconductor die and other electronic components through the exposed surface.
- In this regard,
FIG. 1 illustrates anelectronic device 10, which includes anIC module 12 coupled to acircuit board 14. For the purpose of this illustration, theIC module 12 is a shielded double-sided IC module, which includes amodule substrate 16, a first topelectronic component 18, a second topelectronic component 20, a third topelectronic component 22, a first bottomelectronic component 24, and a second bottomelectronic component 26. Each of the bottomelectronic components first mold compound 28, and each of the topelectronic components second mold compound 30. As depicted, a shieldingstructure 32 can at least partially surround theIC module 12, andmodule contacts 34 couple theIC module 12 to thecircuit board 14. - In further detail, the first bottom
electronic component 24, the second bottomelectronic component 26, and themodule contacts 34 are attached to abottom side 36 of themodule substrate 16. In different applications, theIC module 12 may include fewer or more bottomelectronic components electronic components electronic components - The
module contacts 34 are conductive and may be solder bumps or copper pillars forming an electrical connection with the circuit board14 (e.g., connecting the topelectronic components electronic components module contacts 34 can be used for grounded signals or non-grounded signals, and at least some of themodule contacts 34 may be electrically isolated fromother module contacts 34. Thefirst mold compound 28 resides over thebottom side 36 of themodule substrate 16 and encapsulates the first bottomelectronic component 24 and the second bottomelectronic component 26. Eachmodule contact 34 is taller than the bottomelectronic components first mold compound 28. Thefirst mold compound 28 may be an organic epoxy resin or similar material. In an exemplary aspect, thefirst mold compound 28 is a 20 micron (μm) top cut material. - The first top
electronic component 18 and the second topelectronic component 20 are attached to atop side 38 of themodule substrate 16. In different applications, theIC module 12 may include fewer or more topelectronic components electronic component 18 and the second topelectronic component 20 may be a flip-chip die, a wire-bonding die, a SMD, an inductor, or other active or passive component. Thesecond mold compound 30 resides over thetop side 38 of themodule substrate 16 and encapsulates the first topelectronic component 18 and the second topelectronic component 20. Thesecond mold compound 30 may be formed from a same or different material as thefirst mold compound 28. - As shown in
FIG. 1 , atop surface 40 of theIC module 12 is defined by a top surface of the second mold compound30 (e.g., a surface opposite the module substrate16). Aside surface 42 of theIC module 12 is defined by a side surface of thesecond mold compound 30, a side surface of themodule substrate 16, and a side surface of thefirst mold compound 28. The shielding structure32 (e.g., shield layer) entirely covers thetop surface 40 of theIC module 12 and entirely or almost entirely covers theside surface 42 of theIC module 12. The shieldingstructure 32 does not cover a bottom side of theIC module 12, which couples to thecircuit board 14. Herein and hereafter, entirely covering a surface refers to covering at least 99% of the surface, while almost entirely covering a surface refers to covering at least 90% of the surface. - The shielding
structure 32 can include a single layer of material, or it can include multiple layers of the same or different materials. For example, an interior layer (e.g., covering thetop surface 40 and theside surface 42 of the IC module12) may be formed of copper, aluminum, silver, gold, or other conductive materials with a thickness between 3 μm and 16 μm. An exterior layer may reside over the interior layer, and may be formed of nickel with a thickness between 1 μm and 3 μm. - Further, the
module substrate 16 may be a laminate having a number oflayers 44. Theselayers 44 of themodule substrate 16 may include prepreg material. Themodule substrate 16 can also includeconductive elements 46 and viastructures 48, which may be formed of an appropriate conductive material. Generally, theconductive elements 46 and the viastructures 48 form electrical connections between one or more of theelectronic components circuit board 14. - In an exemplary aspect, shown in
FIG. 2 , a portion of thefirst mold compound 28 on a bottom side of theIC module 12 is removed, exposing asemiconductor die surface electronic components surface electronic component module substrate 16. Thus abottom surface 54 of theIC module 12 is defined by the semiconductor die surface(s)50,52 and a bottom surface of thefirst mold compound 28. In some examples, one of the semiconductor die surfaces50,52 is exposed (e.g., the semiconductor diesurface surfaces - In detail, the
IC module 12 may be a radio frequency (RF) module, providing processing, signal conditioning, controls, and/or similar functions for RF signals of theelectronic device 10. Accordingly, the topelectronic components electronic components RF module 12 may be configured for RF operation. Each of theelectronic components module contacts 34 are mounted to themodule substrate 16 through an appropriate technique. For example, the first topelectronic component 18 and the third topelectronic component 22 are each a SMD which is mounted by solder, reflow, an adhesive, or similar technique. The second topelectronic component 20, the first bottomelectronic component 24, and the second bottomelectronic component 26 are each a semiconductor die (e.g., a flip-chip die or a wire-bonding die) mounted to themodule substrate 16 through a set of solder bumps56 or similar conductive elements (e.g., through a reflow process). It should be understood that the mounting of theelectronic components - The
first mold compound 28 is applied over thebottom side 36 of themodule substrate 16 to encapsulate each bottomelectronic component FIG. 1 , and removed to expose at least one semiconductor diesurface FIG. 2 . Thefirst mold compound 28 may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, or screen print encapsulation. In an exemplary aspect, if there is space between thebottom side 36 of themodule substrate 16 and a bottomelectronic component first mold compound 28 fills the space. A curing process hardens thefirst mold compound 28. - Similarly, the
second mold compound 30 is applied over thetop side 38 of themodule substrate 16 to encapsulate each topelectronic component second mold compound 30 may be the same or a different material as thefirst mold compound 28, and may be applied through the same or a different technique. In some cases, both thefirst mold compound 28 and thesecond mold compound 30 are applied in a same process, and in other cases thefirst mold compound 28 and thesecond mold compound 30 are applied in separate processes. - By removing a portion of the
first mold compound 28 to expose at least one semiconductor diesurface module contacts 34 can be reduced. In addition, an overall thickness T of theIC module 12 is reduced. In an exemplary aspect, a thickness of each bottomelectronic component bottom surface 54 of theIC module 12 and thebottom side 36 of the module substrate16) is between 80 μm and 200 μm. In addition, the height H of themodule contacts 34 is between 100 and 300 μm prior to attachment to thecircuit board 14. - The process of exposing the semiconductor die
surface FIGS. 3A-3C . In addition, exposing the semiconductor diesurface electronic component electronic component circuit board 14, as discussed further with respect toFIGS. 4A-4E . It should be understood that variations in components of theIC module 12 are contemplated, as depicted inFIG. 4F . FIGS. 3A-3C provide exemplary steps that illustrate a process to fabricate theIC module 12 shown inFIG. 2 having the exposed semiconductor diesurface FIGS. 3A-3C .FIG. 3A illustrates an exemplary bottom view of theIC module 12 ofFIG. 2 prior to encapsulating the bottomelectronic components first mold compound 28.FIG. 3B illustrates another exemplary bottom view of theIC module 12 ofFIG. 2 with the bottomelectronic components first mold compound 28.FIG. 3C illustrates another exemplary bottom view of theIC module 12 ofFIG. 2 after a portion of themold compound 28 is removed to expose the semiconductor diesurface - The first bottom
electronic component 24, the second bottomelectronic component 26, and themodule contacts 34 are attached at thebottom side 36 of themodule substrate 16 as depicted inFIG. 3A . In different applications, there may be more or fewer bottomelectronic components fewer module contacts 34 attached to themodule substrate 16. Somemodule contacts 34 may be used for grounded signals, and may be electrically isolated fromother module contacts 34 which are used for non-grounded signals. Herein, themodule contacts 34 are taller than the first bottomelectronic component 24 and the second bottomelectronic component 26. - After the first bottom
electronic component 24, the second bottomelectronic component 26, and themodule contacts 34 are attached, thefirst mold compound 28 is applied to theIC module 12 as depicted inFIG. 3B . Thefirst mold compound 28 resides over thebottom side 36 of themodule substrate 16 to encapsulate each bottomelectronic component module contact 34. In some examples, the bottomelectronic components module contacts 34 are entirely encapsulated, and in other embodiments, themodule contacts 34 are only partially encapsulated. As described above, thefirst mold compound 28 may be applied by various procedures. In an exemplary aspect, thefirst mold compound 28 is overmolded. A curing process hardens thefirst mold compound 28. - After the
first mold compound 28 is applied and cured, a portion of thefirst mold compound 28 is removed to expose the at least one semiconductor diesurface electronic components FIG. 3C . The removal of the portion of thefirst mold compound 28 may be done with a mechanical grinding process, a chemical removal process, a laser ablation, or other appropriate technique. After the removal process, thebottom surface 54 of theIC module 12 is defined by the semiconductor die surface(s)50,52 and a bottom surface of thefirst mold compound 28. In some applications, thebottom surface 54 is a common plane at and around the semiconductor die surface(s)50,52. - Exposure of the semiconductor die
surface electronic components FIGS. 4A-4C . The exposed semiconductor diesurface electronic components circuit board 14, as depicted inFIGS. 4D and 4E . Variations in the components of theIC module 12 are contemplated, such as depicted inFIG. 4F . FIG. 4A illustrates an exemplaryelectronic device 10 as inFIG. 2 , having a device mounted to the exposed semiconductor diesurface electronic components heat exchanger 58 may be coupled to the exposed semiconductor die surface(s)50,52 of the bottom electronic component(s)24,26. This can improve the performance of the bottom electronic component(s)24,26 and/or prevent damage to the bottom electronic component(s)24,26 during operation. Theheat exchanger 58 may be mounted to the bottom electronic component(s)24,26 and/or thefirst mold compound 28 through an adhesive material (e.g., a thermal adhesive) or another appropriate technique.- In other examples, one or more of the bottom
electronic components FIGS. 4B and 4C . In an exemplary aspect, a separate sensor substrate60 (e.g., a conductive material, an optical material, and so on) can be coupled to each bottomelectronic component FIG. 4B . In another aspect, thesensor substrate 60 can be coupled to more than one bottomelectronic component FIG. 4C . Thesensor substrate 60 can facilitate operation of the sensor. In some examples, thesensor substrate 60 may be omitted and the sensor in the bottomelectronic component FIG. 4D illustrates an exemplaryelectronic device 10 as inFIG. 2 , having a connection formed between the exposed semiconductor diesurface circuit board 14. In some examples, aconductive pad 62 is coupled to the semiconductor diesurface conductive pad 64 is coupled to thecircuit board 14. Theconductive pad 62 and/or the correspondingconductive pad 64 can be an exposed or insulated trace, pad, coil, or another shape. Theconductive pad 62 and the correspondingconductive pad 64 can exchange signals and/or power through an indirect electromagnetic technique, such as inducing electrical signals through electrical, magnetic, capacitive, or inductive techniques. In some examples, theconductive pad 62 can be included within the bottomelectronic component surface - In other examples, a direct electrical connection may be formed between one or more of the bottom
electronic components circuit board 14 through the exposed semiconductor diesurface FIG. 4E . For example, one ormore conductors 66 can be coupled between the semiconductor diesurface circuit board 14. Theconductors 66 can be deposited on or coupled to each of the semiconductor diesurface circuit board 14 through soldering, an adhesive (e.g., a conductive adhesive), vapor deposition, printing, and similar techniques. Theconductors 66 can facilitate an exchange of power and/or signals between the bottom electronic component(s)24,26 and one or more devices coupled to the circuit board14 (not shown). - Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
- For example,
FIG. 4F illustrates an exemplaryelectronic device 10 as inFIG. 2 , having variations in its components. In particular, theIC module 12 may includemodules contacts module contacts 34amay have a substantially planar surface attached to thebottom side 36 of themodule substrate 16. In other examples, one or more of themodule contacts 34bmay include a notched or otherwise irregular surface attached to thebottom side 36 of themodule substrate 16. As described above, themodule contacts circuit board 14. The surfaces of themodule contacts bottom side 36 of themodule substrate 16 may be machined, molded, or otherwise formed as depicted inFIG. 4F . It should be understood that other variations and modifications of theIC module 12 and its components are also contemplated herein.
Claims (20)
1. A radio frequency (RF) module, comprising:
a module substrate defining a top side and a bottom side;
a plurality of electronic components coupled to the top side;
a semiconductor die coupled to the bottom side; and
a first mold compound coupled to the semiconductor die and exposing a surface of the semiconductor die.
2. The RF module ofclaim 1 , wherein the surface of the semiconductor die is a bottom surface of the semiconductor die facing opposite the module substrate.
3. The RF module ofclaim 1 , wherein the semiconductor die is coupled to the module substrate via a plurality of conductive elements.
4. The RF module ofclaim 3 , wherein the first mold compound surrounds each of the plurality of conductive elements.
5. The RF module ofclaim 1 , wherein the first mold compound and the surface of the semiconductor die define a common plane.
6. The RF module ofclaim 5 , further comprising a plurality of module contacts extending below the common plane, wherein at least one of the plurality of module contacts is configured to provide an electrical connection between the module substrate and a secondary substrate.
7. The RF module ofclaim 5 , wherein a distance between the common plane and the bottom side of the module substrate is between 80 μm and 200 μm.
8. The RF module ofclaim 1 , further comprising a second mold compound coupled to the top side and encapsulating the plurality of electronic components.
9. The RF module ofclaim 8 , further comprising a shield layer at least partially surrounding the second mold compound.
10. The RF module ofclaim 1 , further comprising a heat exchanger coupled to the surface of the semiconductor die and configured to exchange heat with the semiconductor die.
11. A method for assembling a radio frequency (RF) module, comprising:
coupling an electronic component to a top side of a module substrate;
coupling a semiconductor die to a bottom side of the module substrate;
encapsulating the semiconductor die in a mold compound such that the mold compound at least partially surrounds the semiconductor die; and
removing a portion of the mold compound to expose a surface of the semiconductor die.
12. The method ofclaim 11 , wherein removing the portion of the mold compound exposes a bottom surface of the semiconductor die facing opposite the module substrate.
13. The method ofclaim 11 , wherein coupling the semiconductor die to the bottom side of the module substrate further comprises coupling a plurality of conductive elements between the semiconductor die and the bottom side of the module substrate.
14. The method ofclaim 13 , wherein encapsulating the semiconductor die in the mold compound comprises at least partially surrounding each of the plurality of conductive elements.
15. The method ofclaim 11 , wherein removing the portion of the mold compound forms a planar bottom module surface defined by the mold compound and the surface of the semiconductor die.
16. The method ofclaim 15 , wherein:
removing the portion of the mold compound further exposes a plurality of module contacts extending below the planar bottom module surface; and
the method further comprises coupling the plurality of module contacts to a secondary substrate.
17. The method ofclaim 15 , further comprising coupling a heat exchanger to the planar bottom module surface such that the heat exchanger is configured to exchange heat with the semiconductor die.
18. An electronic device, comprising:
a circuit board on which a plurality of electronic components is mounted; and
an integrated circuit (IC) module coupled to the circuit board, comprising:
a module substrate having a top side and a bottom side adjacent the circuit board;
a first electronic component coupled to the top side;
a second electronic component coupled to the bottom side; and
a mold compound at least partially surrounding the second electronic component and exposing a surface of the second electronic component.
19. The electronic device ofclaim 18 , wherein:
the mold compound and the surface of the second electronic component define a common plane facing the circuit board;
the electronic device further comprises a plurality of module contacts extending below the common plane and coupled to the circuit board; and
at least one of the plurality of module contacts provides an electrical connection between the module substrate and an electronic component of the plurality of electronic components.
20. The electronic device ofclaim 19 , wherein a distance between the common plane and the bottom side of the module substrate is between 80 μm and 200 μm.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/119,554US20200075547A1 (en) | 2018-08-31 | 2018-08-31 | Double-sided integrated circuit module having an exposed semiconductor die |
| US17/498,577US12021065B2 (en) | 2018-08-31 | 2021-10-11 | Double-sided integrated circuit module having an exposed semiconductor die |
| US18/657,968US20240387464A1 (en) | 2018-08-31 | 2024-05-08 | Double-sided integrated circuit module having an exposed semiconductor die |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/119,554US20200075547A1 (en) | 2018-08-31 | 2018-08-31 | Double-sided integrated circuit module having an exposed semiconductor die |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US17/498,577DivisionUS12021065B2 (en) | 2018-08-31 | 2021-10-11 | Double-sided integrated circuit module having an exposed semiconductor die |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20200075547A1true US20200075547A1 (en) | 2020-03-05 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US16/119,554AbandonedUS20200075547A1 (en) | 2018-08-31 | 2018-08-31 | Double-sided integrated circuit module having an exposed semiconductor die |
| US17/498,577ActiveUS12021065B2 (en) | 2018-08-31 | 2021-10-11 | Double-sided integrated circuit module having an exposed semiconductor die |
| US18/657,968PendingUS20240387464A1 (en) | 2018-08-31 | 2024-05-08 | Double-sided integrated circuit module having an exposed semiconductor die |
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| US17/498,577ActiveUS12021065B2 (en) | 2018-08-31 | 2021-10-11 | Double-sided integrated circuit module having an exposed semiconductor die |
| US18/657,968PendingUS20240387464A1 (en) | 2018-08-31 | 2024-05-08 | Double-sided integrated circuit module having an exposed semiconductor die |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20240387464A1 (en) | 2024-11-21 |
| US12021065B2 (en) | 2024-06-25 |
| US20220028838A1 (en) | 2022-01-27 |
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