US20200013807A1

Movatterモバイル変換

Info

Publication number: US20200013807A1
Application number: US16/571,928
Authority: US
Inventors: Kuan-Feng LEE; Chandra LIUS; Nai-Fang HSU
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2016-04-08
Filing date: 2019-09-16
Publication date: 2020-01-09
Anticipated expiration: 2037-02-17
Also published as: TW201803095A; US11984451B2; CN113013180A; US10468434B2; US20170294456A1; TWI631693B; CN107452749A; US20210335837A1; US20240258324A1; CN107452749B; US20250151409A1; US12356723B2; US11088173B2

Abstract

A display device, and method for manufacture, having a substrate; a first thin film transistor (TFT) on the substrate, the first TFT having a first active layer, a first gate insulator, and a first gate electrode; a second TFT on the substrate, the second TFT having a second active layer, a second gate insulator and a second gate electrode. The first gate insulator is disposed between the first gate electrode and the first active layer, and the first gate insulator is in contact with the first active layer. The second gate insulator is disposed between the second gate electrode and the second active layer, and the second gate insulator is in contact with the second active layer. The first active layer is a different material than said second active layer, and a hydrogen concentration of the second gate insulator is less than a hydrogen concentration of the first gate insulator.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of application Ser. No. 15/436,073, filed on Feb. 17, 2017 and entitled “HYBRID THIN FILM TRANSISTOR STRUCTURE, DISPLAY DEVICE, AND METHOD OF MAKING THE SAME”, the entirety of which is incorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to displays having a thin film transistor (TFT) disposed on a substrate and methods for manufacturing the same, and more particularly to hybrid TFT structures having active layers with different semiconducting materials, and methods for manufacturing the same.

BACKGROUND

Metal oxide semiconductors have been used for such device fabrication due to their high carrier mobility, low processing temperatures, and optical transparency. However, thin film transistors (TFTs) made from metal oxide semiconductors are sensitive to hydrogen content, where hydrogen between layers can act as an amphoteric impurity, e.g., acts as a donor or acceptor, and can induce a high threshold voltage shift under voltage/light bias conditions.

Therefore, the present disclosure resulted from the recognition that there is a need for a TFT and manufacturing process that is less susceptible to the hydrogen impurity problems of the prior art.

SUMMARY

The present disclosure relates to, in one embodiment, to TFTs for use in electronic devices having a display, e.g., TVs, mobile phones, etc., using LED and OLED technology. As the display resolution for such a display requires to be higher, which requires smaller and stable transistors with lower power and lower mura defects.

Accordingly, the present disclosure relates to displays having the hybrid TFT structure and the manufacturing process thereof. The advantages and features of the disclosure are set forth in the description which follows or resulting thereof.

To achieve one of the advantages of the present disclosure, a display device utilizing the hybrid TFT structure comprises: a substrate; a first thin film transistor (TFT) on said substrate, the first thin film transistor comprising a first active layer, a first gate insulator, and a first gate electrode; a second thin film transistor (TFT) on said substrate, the second thin film transistor comprising a second active layer, a second gate insulator, and a second gate electrode; wherein said first gate insulator is disposed between said first gate electrode and said first active layer, and said first gate insulator is in contact with said first active layer; wherein said second gate insulator is disposed between said second gate electrode and said second active layer, and said second gate insulator is in contact with said second active layer; wherein said first active layer is a different material than said second active layer; and wherein a hydrogen concentration of said second gate insulator is less than a hydrogen concentration of said first gate insulator.

In a second embodiment of a display device of the present disclosure, a display device utilizing a hybrid TFT structure comprises: a substrate; a first thin film transistor (TFT) on said substrate, the first thin film transistor comprising a first active layer, a first source electrode, a first drain electrode, a first gate insulator and a first gate electrode; a second thin film transistor (TFT) on said substrate; the second thin film transistor comprising a second active layer, a second source electrode, a second drain electrode, a second gate insulator and a second gate electrode; wherein said first gate insulator is disposed between said first gate electrode and said first active layer, and said first gate insulator is in contact with said first active layer; wherein said second gate insulator is disposed between said second gate electrode and said second active layer, and said second gate insulator is in contact with said second active layer; wherein a material of said first active layer is different from a material of said second active layer, and a material of said first gate insulator is different from a material of said second gate insulator; wherein said second active layer contains a metal oxide semiconductor and said second gate insulator contains silicon oxide.

In a preferred embodiment, the second gate insulator is a material having a lower hydrogen concentration than that of the first gate insulator, such as a silicon oxide material having a hydrogen concentration between about 0-5 atomic percent, and preferably between about 1-3 atomic percent.

In one of the embodiments, the first gate insulator layer contains at least one of silicon oxide, silicon nitride, or silicon oxynitride, and the second gate insulator layer contains at least one of silicon oxide or silicon oxynitride.

In another embodiment, the first gate insulator and the second gate insulator are formed on different layers and/or formed of different materials.

Inyet another embodiment of the disclosure, the first gate insulator has a hydrogen concentration greater than 5 percent and less than 10 percent, and the second gate insulator has a hydrogen concentration less than or equal to 5 percent and greater than or equal to 0 percent.

The display device can also include a blanking layer disposed between the second active layer and the substrate or below any of the TFTs.

In another aspect of this disclosure, the method for manufacturing a hybrid TFT structure for a display, comprises the steps of: depositing a first active layer over a portion of a substrate; depositing a second active layer over another portion of the substrate; depositing a first gate insulator over the first active layer; depositing a second gate insulator over the second active layer; depositing a first gate electrode over the first gate insulator so that the first gate insulator is disposed between said first gate electrode and said first active layer, wherein said first gate insulator is in contact with said first active layer, and wherein said first active layer, first gate insulator, and first gate electrode form a first thin film transistor; depositing a second gate electrode over the second gate insulator so that the second gate insulator is disposed between said second gate electrode and said second active layer, wherein said second gate insulator is in contact with said second active layer, and wherein said second active layer, second gate insulator, and second gate electrode form a second thin film transistor; wherein said first active layer is a different material than said second active layer, and wherein a hydrogen concentration of said second gate insulator is less than a hydrogen concentration of said first gate insulator.

It is to be understood that the above description and description in the specification are exemplary and explanatory and are not intended to limit the scope of the disclosure, where different embodiments of the disclosure can be combined without changing the scope of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of a display device having hybrid thin film transistor structures and methods of manufacturing the same according to different embodiments of the disclosure will now be explained in more detail with reference to the drawings, wherein:

FIG. 1 is a cross-sectional view illustrating the hybrid TFT structure according to a first embodiment of the disclosure.

FIGS. 2A-2F illustrate an exemplary process flow showing the deposition and formation of a display device according to the first embodiment of the disclosure.

FIG. 3 is a process flow diagram illustrating a method for manufacturing the hybrid TFT structure according to the first embodiment of the disclosure.

FIG. 4 is a cross-sectional view illustrating the hybrid TFT structure according to a second embodiment of the disclosure.

FIGS. 5A-5D illustrate an exemplary process flow for forming the hybrid TFT structure for the second embodiment of the disclosure.

FIG. 6 is a cross-sectional view illustrating the structure of the hybrid TFT structure according to a third embodiment of the disclosure.

FIG. 7 is a process flow diagram illustrating a method for manufacturing the hybrid TFT structure according to the third embodiment of the disclosure.

FIGS. 8A-8D illustrate the process flow for forming the hybrid TFT structure according to the third embodiment of the disclosure.

FIG. 9 is a cross-sectional view illustrating the structure of the hybrid TFT structure according to a fourth embodiment of the disclosure.

FIGS. 10 and 11 show cross-sectional views illustrating the structure of the hybrid TFT structure according to a variant of the third embodiment of the disclosure.

FIGS. 12A-12L show cross-sectional views illustrating a fourth embodiment of the disclosure.

FIGS. 13A-13L illustrate the process flow for forming one of the embodiments of the fourth embodiment of the disclosure.

FIGS. 14A-14L illustrate the process flow for forming another of the embodiments of the fourth embodiment of the disclosure.

FIGS. 15A-15M illustrate the process flow for forming another of the embodiments of the fourth embodiment of the disclosure.

In the various figures, similar elements may be provided with similar reference numbers. It should be noted that the drawing figures are not necessarily drawn to any scale, or proportion, but instead are drawn to provide an understanding of the method according to the disclosure and the resulting hybrid TFT structure and components. Thus, the illustrations are not intended to be limiting as to the scope of the disclosure described herein, but rather to provide exemplary illustrations thereof.

DETAILED DESCRIPTION

A. Discussion of Various Embodiments

As used in the different embodiments of the present disclosure, the term “over” or “on” broadly encompasses a layer being “directly on or over,” e.g., contacting, or “indirectly on or over,” e.g., not contacting, another layer. Also, unless otherwise specified, the term “under” broadly encompasses “directly under” and “indirectly under.”

Although the terms “first,” “second,” etc. may be used to describe various layers and steps, these features should not be limited by these designations, since such designations are only being used to distinguish one feature from another. It is to be understood that the skilled person would appreciate that any combination of steps or features can be combined in any of the embodiments described below to reach the desired effects of this disclosure.

As generally discussed above, the electron mobility in TFTs needs to be enhanced to increase response speed and require lower amounts of power (or current) while maintaining a small size. For example, hydrogen concentration is important, since hydrogen ion is a component of the reactant gases used in fabrication, e.g., in SiOx layer production, and may be responsible for fixed charge in the active layer and the creation of trap generation in the layer. To overcome this deficiency, the present disclosure was developed for manufacturing a hybrid TFT structure for a display device, having at least a first thin film transistor and at least a second thin film transistor, where the second thin film transistor has an active layer, e.g., a metal oxide semiconductor material layer, contacting a gate insulator having a concentration of hydrogen that is lower than a concentration of hydrogen in a gate insulator associated with the first thin film transistors. For example, in one of the embodiments the display device comprises a first TFT comprising a first gate insulator disposed between a first gate electrode and a first active layer, and a second TFT comprising a second gate insulator disposed between a second gate electrode and a second active layer, where the first gate insulator is in contact with the first active layer, the second gate insulator is in contact with the second active layer, and the second gate insulator has a lower hydrogen concentration than the first gate insulator. For example, the second gate insulator may have a concentration of hydrogen less than 5 atomic percent and greater than or equal to 0 (or practically thereof), and less than 3 atomic percent and greater than or equal to 1 according to another embodiment, while the first gate insulator may have a hydrogen concentration greater than 5 atomic percent.

In some embodiments of the disclosure, the active layer of the second TFT is a metal oxide semiconductor (OXIDE) material layer, and the active layer of the first TFT is a low temperature polycrystalline semiconductor (LTPS) material layer, resulting in an OXIDE TFT and an LTPS TFT. More particularly, in some embodiments of the disclosure the active layer of the second TFT is an Indium Gallium Zinc Oxide (IGZO) material, resulting in an IGZO TFT. The substrate may include a display area and a non-display area located outside and adjacent to the display area, where the display area includes a plurality of pixels arranged in a matrix for producing a display using light emitting diodes (LED) or organic LED (OLED) technology, and the non-display area includes the driving circuits and elements for driving the pixels. The IGZO TFT and the LTPS TFT can be included in the display area or the non-display area, or combinations thereof, where the IGZO TFT and the LTPS TFT may be positioned apart or close, e.g., adjacent, to each other along the substrate. In another embodiment, at least parts of the IGZO TFT and the LTPS TFT may overlap.

The TFT substrate can be any of the substrates known in the art, including, but not limited to glass, polycrystalline silicon, microcrystalline silicon, amorphous silicon, cadmium selenide, metal oxides, such as tin and zinc, organic materials (OTFT), such as polymers, e.g., poly(methyl-methacrylate) (PMMA), polythiophenes, polyfluorene, polydiacetylene, and the like, rubrene, tetracene, pentacene, diindenoperylene, perylenediimides, tetracyanoquinodimethane (TCNQ), etc., where the semiconductor substrate can be a rigid or flexible layer.

The hybrid TFT structure may optionally include a blanking layer for blocking light from passing through the glass substrate to improve the overall contrast and performance of the display. Or the blanking layer can also protect TFT from back light and prevent light leakage current. The blanking layer can be a single layer structure or a multilayer structure. In some embodiments the blanking layer may be provided as a black matrix layer on or above the substrate, below the IGZO TFT and/or the LTPS TFT, as a non-conductive type or a conductive type layer. The blanking layer, or black matrix layer, can comprise a blanking material including metal layers, such as chromium, aluminum, or chromium oxide, light absorbing material, such as a polymer or an oxide, black pigments particles, such as carbon black, or other materials known in the art or other materials that act to block light, such as a combination of a gate electrode and gate insulator.

Additionally, the hybrid TFT structure may also include one or more of the following: at least one buffer layer provided over the substrate to at least protect the several layers from deterioration caused by ambient air and the mounting process, promote electron mobility, prevent particles from diffusing from/to the active layer, or improve thermal conductivity; at least one interlayer dielectric layer formed over the at least one of the buffer layers, where the source and drain electrodes are formed therein, e.g., using a masking process to form contact holes in the different layers; at least one passivation layer formed over the drain and source electrodes to passivate the layers and improve bias stability.

The buffer layer can include at least one inorganic or organic layer and/or a light shield layer, for example, an oxide layer, e.g., silicon oxide (SiOx), a nitride layer, e.g., silicon nitride (SiNx), polymer layers, etc. The interlayer dielectric layer and the passivation layer can be formed from various combinations of metal oxides, e.g., AlOx, SrOx, etc., SiOx, or SiNx, or other suitable materials, where the passivation layer can also be formed from compounds of group II and a halogen element. The organic layer can be formed from a polymer, such as polyethylene terephthalate (PET), polyimide, polycarbonate, epoxy, polyethylene, and/or a polyacrylate and can include an inorganic layer, such as SiNx, Al₂O₃, SiOx, and TiO₂. Any of the above described layers can include a single layer or multiple layers according to different embodiments of this disclosure as desired.

Turning to the TFTs, the first and second TFTs are TFTs having an active layer, e.g., semiconductor material layer. In one specific embodiment, the first TFT is a LTPS TFT and the second TFT is an IGZO TFT, both of which are multilayer TFTs. The IGZO TFT includes an indium gallium zinc oxide (IGZO) active layer and the LTPS TFT includes a low temperature polycrystalline silicon (LTPS) active layer. The IGZO TFT and the LTPS TFT also include a gate electrode and may include a gate insulator, which is/are disposed over or under (e.g., above, below, and/or around) the active layer, e.g., the LTPS or IGZO semiconductor material layer. That is, the gate insulator is an insulating layer between the gate electrode and the active layer, in a top gate or a bottom gate TFT structure. Additionally, at least one of the TFTs include a source electrode and a drain electrode that are connected to a circuit or pixel, where the source and drain areas of the active layer are formed by doping, e.g., using doping impurities, and/or created during a conductorization process, e.g., using plasma treatment, or etching, or depositing additional metals to form the source and drain areas. In so doing, the TFT active layers can be doped to form n-channel and/or p-channel TFTs. The gate electrodes can be formed from a variety metals, such as Ga, In, Sn, Tn, Al, Zn, or the like, while the gate insulator can be formed from an insulating material, such as SiOx, SiNx or a high-K material, e.g., Si₃N₄, Al₂O₃, or HfO₂, etc. The gate electrodes can include a single layer or multiple layers according to different embodiments of this disclosure as desired. To be noted that the insulating layers with different density may be regarded as different material layers. For example, SiOx material layers with different density e.g. functioned as a gate insulator, a buffer layer or an interlayer dielectric layer, could be regarded as different layers. The different material layers may have different etching rates when etching with same etchant.

The inventors note that although specific embodiments described herein discuss a gate insulator that is in contact with the active layer, it is understood that any layer between (above or below) the active layer of the TFT and the gate electrode may act as a gate insulator, where the benefits of the disclosure will be understood herein. And in another embodiments with bottom gate TFT structure (not shown), the gate insulator might be disposed over the gate electrode but still disposed between the gate electrode and the active layer, it should not be limited thereto.

Although not discussed in detail, the TFTs can be formed by a variety of techniques, as well known in the art, including but not limited to vacuum deposition (including chemical vapor deposition and plasma enhanced chemical vapor deposition), dip coating, spin coating, printing, spray coating, roll coating, sputtering, lithography, masking, photoresist, etc.

In one embodiment, one of the characteristics of the present disclosure is that the gate insulator contacting the active layer of the IGZO TFT is a SiOx layer having a lower hydrogen concentration than that of other SiOx or SiNx layers in the hybrid TFT structure. For example, the hydrogen concentration of the SiOx (gate insulator) layer contacting the active layer of the IGZO TFT is less than or equal to about 5 atomic percent and greater than or equal to 0 percent (and, in another embodiment, greater than or equal to 0 and less than or equal to about 3 atomic percent), whereas other SiOx or SiNx layers in the hybrid TFT structure may have a hydrogen concentration greater than or equal to about 5 atomic percent, as discussed further below. By using a gate insulator having a lower hydrogen concentration in contact with the IGZO active layer, electron mobility can be increased and the amount of power (or current) needed for control of a pixel decreased.

First Embodiment

As seen inFIG. 1, a first embodiment of the disclosure is illustrated, whereFIG. 1 is a cross sectional view illustrating ahybrid TFT structure10 for a display that includes at least one LTPS TFT and at least one IGZO TFT on the substrate, but it's not limited to. In this embodiment, thehybrid TFT structure10 comprises asubstrate layer100, e.g., glass, PI or PET, anIGZO TFT110 and anLTPS TFT120, which are disposed on the substrate. TheIGZO TFT120 comprises a metal oxideactive layer114, e.g., a layer of IGZO semiconductor material, agate insulator116, agate electrode117, and a source electrode anddrain electrode119. TheLTPS TFT120 comprises anactive layer124, e.g., a layer of LTPS semiconductor material, agate insulator126, agate electrode127, and a source electrode and adrain electrode129. In this embodiment, a blanking layer is included as ablack matrix layer130, where theblack matrix layer130 is disposed on thesubstrate layer100 below theIGZO TFT110 and theLTPS TFT120, where the IGZOactive layer114 is disposed over theblack matrix layer130 in theIGZO TFT110.

In this embodiment, a buffer layer140 is disposed over thesubstrate layer100, below theLTPS TFT120, and disposed on and over the IGZOactive layer114 in theIGZO TFT110. In this case, not only does theIGZO TFT110 have agate insulator116, the buffer layer140, over the IGZOactive layer114 and below thegate electrode117, also acts as a gate insulator. The buffer layer140 can comprise a single layer of SiOx, or a plurality of layers comprising different layers of silicon oxide, silicon nitride, and/or silicon oxynitride. For example, in one embodiment afirst sublayer141 comprises silicon oxide SiOx, a second sublayer142 comprises silicon nitride SiNx, and athird sublayer143 comprises silicon oxide SiOx. As discussed above, one of the important characteristics of the present disclosure is that the layer contacting, e.g., directly adjacent on or over the active layer, e.g., the IGZOactive layer114, that is, thefirst sublayer141, is a SiOx layer having a lower hydrogen concentration than that of other SiOx or SiNx layers in the hybrid TFT structure. For example, the hydrogen concentration of thefirst sublayer141 is less than or equal to about 5 atomic percent and greater than or equal to 0 percent (and, in another embodiment, greater than or equal to 0 and less than or equal to about 3 atomic percent), whereas other SiOx or SiNx layers in the hybrid TFT structure may have a hydrogen concentration greater than or equal to about 5 atomic percent.

More particularly, in this embodiment, the hydrogen concentration of thefirst sublayer141 contacting the IGZOactive layer114 is lower than a hydrogen concentration of thegate insulator126 contacting the firstactive layer124, e.g., the LTPS semiconductor material.

On the buffer layer140, the LTPSactive layer124 is formed or deposited to form theLTPS TFT120. TheLTPS TFT120 has gate andsource electrodes129 connected to a source area (or region) and adrain area128 on the LTPS active layer, which are formed by doping, e.g., to form an n-type or p-type TFT, where thegate insulator126 and thegate electrode127 are formed or deposited over the LTPSactive layer124. In theIGZO TFT110, thegate insulator116 andgate electrode117 are formed on the buffer layer140 above the IGZOactive layer114. The hybrid TFT structure also includes aninterlayer dielectric layer150 formed or deposited over the buffer layer140, theIGZO TFT110, and theLTPS TFT120. Theinterlayer dielectric layer150 can be a single layer or a multilayer structure, where the layer(s) can comprise SiOx and/or SiNx.

The source and drain electrodes are formed on or disposed in/through theinterlayer dielectric layer150, e.g., through contact holes, where the source and drainelectrodes119 are provided for theIGZO TFT110 and the source and drainelectrodes129 are provided for theLTPS TFT120 which contact the source and drainareas128. In this embodiment, theLTPS TFT120 is an n-channel TFT or a p-channel TFT, and wherein when at least two LTPS TFTs are provided, the pair of LTPS TFTs define an n-channel TFT and a p-channel TFT. As further seen inFIG. 1, the IGZOactive layer114 is not on the same plane as the LTPSactive layer124, it means the LTPS active layer and the IGZO active layer are disposed at different sides of the buffer layer140. As discussed above, one of the advantages of the disclosure, is that the gate insulator of the IGZO TFT has a hydrogen concentration less than a hydrogen concentration of the gate insulator of the LTPS TFT.

The hybrid TFT structure also includes over or on theinterlayer dielectric layer150 and source and drain

electrodes

119,129, a first passivation layer160, where the passivation layer is formed from silicon nitride, SiNx, or any other layer as known in the art.

In an embodiment, ex. an LCD display, after the hybrid TFT structure is provided, additionally, an insulating layer170 can be provided on the first passivation layer160. The insulating layer170 could be an organic layer or an inorganic layer. A common electrode190 (or pixel electrode) can be provided on or over the insulating layer170. Lastly, asecond passivation layer180 is provided over the insulating layer170 and common electrode190 (or pixel electrode), where pixel electrode (or common electrode)195 is provide on or above thesecond passivation layer180 and connected to the source (or drain)electrode119 of theIGZO TFT110.

In another embodiment, ex. an LED display, after the hybrid TFT structure is provided, where a pixel (or anode electrode) electrode and a common electrode (or cathode electrode) can be provided on or over the insulating layer170. Another insulating layer could be provided between the pixel electrode and the common electrode. A display medium layer, not shown on the figures, also be provide between the pixel electrode and the common electrode, the display medium layer is disposed apart by the insulating layer, and the display medium layer could be organic light emitting layer, an inorganic light emitting layer or and quantum dot light emitting layer.

As discussed further with reference toFIGS. 2A-2F, an exemplary method for manufacturing the hybrid TFT structure with top gate TFT structure is described. In a first step, as seen inFIG. 2A, a blanking material is optionally deposited on asubstrate layer100 to form ablack matrix layer130, and the IGZOactive layer114 is deposited over theblack matrix layer130, where each layer has a thickness between 50 and 5000 Angstroms. In a second step, as illustrated inFIG. 2B, a first mask process, e.g., a photoresist process, is used to form patterned coatings, e.g., photo resist102, on thesubstrate layer100, IGZOactive layer114, andblack matrix layer130, where the LTPS TFT areas, e.g., where theLTPS TFT120 will be formed, are exposed using amask101 having at least one half tone region, while the IGZO TFT area, e.g., where theIGZO TFT110 will be formed, is exposed using an obstacle region. As seen inFIG. 2C, the IGZO active layer and the black matrix layer are then etched to be formed in the IGZO TFT area and the LTPS TFT areas. The photoresist is then ashed, as seen inFIG. 2D, to remove the photo resist, where since theIGZO TFT110 was exposed using an obstacle region, theIGZO TFT110 has a remainder of photoresist. The IGZO active layer is then etched, so that the IGZOactive layer114 is removed from the LTPS TFT areas and etched in the IGZO TFT area so that the IGZOactive layer114 is patterned on theblack matrix layer130 to form theIGZO TFT110. Finally, the remainder of the photoresist is removed, e.g., via stripping.

In a second manufacturing step, as seen inFIG. 3, the buffer layer is deposited over the substrate, IGZO TFT area, and the LPTS TFT area, by depositing at least one sublayer, e.g., a first sublayer, atstep300 having a thickness between 50 and 5000 Angstroms. The first sublayer comprises an oxide material, such as SiOx, having a lower hydrogen concentration than other oxide layers in the hybrid TFT structure. For example, the first sublayer may have a hydrogen concentration of less than or equal to 5 atomic percent and greater than or equal to 0, and in another embodiment, less than or equal to 3 atomic percent and greater than or equal to 1, comparison to, for example, a hydrogen concentration of between 5 and 10 atomic percent in other SiOx layers, and a hydrogen concentration of between 10 and 20 atomic percent in SiNx layers in the hybrid TFT structure. The first sublayer may be formed by SiOx growing/deposition methods, e.g., RF plasma hydrogenated silicon, but not limited to. For example, in a SiOx deposition method, a substrate layer is positioned in a plasma processing chamber under vacuum, where plasma is introduced into the plasma processing chamber by introducing one or more process gases that are excited with an electrical field to cause the dissociation of the gases into radicals and other ions. The radicals and other ions diffuse to the surface of the substrate layer, where a chemical reaction occurs on the surface of the substrate layer. The reaction product diffuses and is deposited on the surface of the substrate layer, where the byproducts diffuse through the interface boundary layer and leave the deposition system via the main stream along with unused reactants.

The plasma may be produced inductively using RF coils, capacitively using plate electrodes, or using microwave energy, where the plasma and reactant gas are used to deposit the particles on the substrate. For example, the SiOx layer having the lower hydrogen concentration can be deposited using high RF power, e.g., between 7700-10,000 W, with a reactant gas having a silicon containing precursor, such as silane or silicon tetrafluoride, etc., and/or by annealing the SiOx layer at temperatures between 450-500° C. The first sublayer having the lower hydrogen concentration is directly adjacent, e.g., contacts, the IGZO TFT semiconductor material to promote higher electron mobility, as discussed above. The buffer layer can also include additional sublayers, such as second and third sublayers, which may be silicon oxide or silicon nitride layers having a higher hydrogen concentration than the first sublayer.

It is appreciated that the control of at least one of the RF power, glass temperature, chamber pressure, gas flow rate, and the distance between glass and plate (spacing) can be used to produce the different layers of the TFTs having varying hydrogen concentrations. For example, the gate insulator for the IGZO TFT (GI SiOx-IGZO), the gate insulator for the LTPS TFT (GI SiOx-LTPS), and the interlayer dielectric layer (ILD SiNx) can be formed according to the following parameters:


Item/Parameter	GI SiOx-IGZO	GI SiOx-LTPS	ILD SiNx

Hydrogen Concentration	0%~3%	5%~10%	10%~20%

PECVD	Reactant gases	N₂O(g) + SiH₄(g)	SiH₄(g) + NH₃(g) +
Parameters			N₂(g)
	Temperature	340° C.~360° C.	200° C.~220° C.

Power (@	7700 W~10000 W	5000 W~8500 W	5000 W~13000 W
13.56 MHz
RF)
N₂O/SiH₄ratio	75~125	50~75
(N₂O = 43200 sccm)
Spacing	400~800 mils	800~1200mils	600~1300mils
Pressure
700~100mTorr	1000~1200mTorr	1000~2000 mTorr

In some embodiments, the PECVD deposition conditions are inter-correlated, e.g., power is set at 8000 W N₂O/SiH₄ratio at 90, and spacing at 650 mils to obtain a silicon oxide film with hydrogen concentration lower than 3% (at %). Additionally, to quantify the hydrogen concentration, SIMS (Secondary Ion Mass Spectrometer) and/or RBS (Rutherford Back-Scattering Spectrometry) equipment and processes can be used to measure such hydrogen concentration in the layers.

In the next manufacturing step (step310), the LTPS active layer is deposited and/or formed over the buffer layer in the LTPS TFT areas using a masking process and a known deposition method in the art, such as, laser annealing, plasma enhanced chemical vapor deposition, chemical vapor deposition, expanding thermal plasma, crystallization step, or similar methods using a Si-precursor material, where the LTPS active layer comprises low temperature polycrystalline silicon semiconductor material. During or after the depositing of the LTPS active layer on the buffer layer, a doping process is used to form source and drain areas (or regions) so that a channel area (not shown) is formed in the LTPS active layer. In so doing, the LTPS TFTs can define an n-channel TFT or a p-channel TFT accordingly. Then, instep320, a gate insulator is formed in the LTPS TFT area and the IGZO TFT area, where the gate insulator is formed on, over, or around the LTPS active layer and formed over the IGZO active layer, respectively. The gate insulator can be formed from a silicon oxide or a silicon nitride material. A gate electrode is then formed on or over each gate insulator in the LTPS TFT and the IGZO TFT over the active layer, e.g., the semiconductor material. In another embodiment, a TFT structure with bottom gate (not shown on the figures), depositing a gate electrode before depositing a gate insulator, and then depositing an active layer on the gate insulator. An interlayer dielectric layer is then deposited atstep330 over the entire structure using one of the known masking and/or deposition processes. Each of these layers has a thickness between having a thickness between 50 and 5000 Angstroms.

As discussed above, one of the important aspects of one of the embodiments of the disclosure, is that the gate insulator over the IGZO active layer is formed to have a lower hydrogen concentration than the gate insulator over the LTPS active layer.

Then, the source and drain electrodes are formed in the LTPS TFT area and the IGZO TFT area instep340, e.g., by forming channels through the interlayer dielectric layer, such as, through contact holes that were patterned by masking and etching after or during the deposition process of the layers. Atstep350, a first passivation layer can then be deposited over the entire structure, e.g., the source and drain electrodes and the interlayer dielectric layer. Such layers can be deposited using a deposition process known in the art and/or can also include a masking process for patterning the layers to include contact holes for exposing the source and drain electrodes in the LTPS TFT area and the IGZO TFT area. In so doing, the IGZO TFT is defined in the IGZO TFT area and the LTPS TFT is defined in the LTPS TFT area.

In addition to the above identified layers, an optional step360, an insulating layer can be deposited over the first passivation layer. The insulating layer could be an organic layer or an inorganic layer. And an optional step370, a second passivation layer can be deposited over the insulating layer using one of the known deposition methods, where holes and areas can also be defined using a patterning process for connecting a pixel electrode (or an anode electrode) of the display to the drain electrode of at least one of the IGZO TFT or the LTPS TFTs and to include a common electrode.

In view of such steps, a hybrid TFT structure is formed where a gate insulator of IGZO TFT is in contact with the IGZO semiconductor material layer, where the second insulator of IGZO TFT has a lower hydrogen concentration than the gate insulator of LTPS TFT.

Second Embodiment

As seen inFIG. 4, a second embodiment of the disclosure is illustrated, which is similar to the first embodiment. In this embodiment, however, the buffer layer includes three sublayers and the IGZO active layer is deposited and formed on one of the sublayers of the buffer layer above the blanking layer, e.g., the black matrix layer, as opposed to being formed directly on the blanking layer as in the first embodiment.

For example, as shown inFIG. 4, thehybrid TFT structure40 includes asubstrate layer400 having anIGZO TFT410 andLTPS TFT420, which are disposed on the same substrate. In this embodiment, a blanking material is disposed on thesubstrate layer400 below theIGZO TFT410 and theLTPS TFT420 to form ablack matrix layer430. Abuffer layer440 is disposed over theblack matrix layer430 and thesubstrate layer400, where thebuffer layer440 comprises afirst sublayer441, asecond sublayer442, and athird sublayer443. The first and

second sublayers

441,442 are provided over theblack matrix layer430 and thesubstrate layer400, where the first and second sublayers can comprise SiOx and/or SiNx layers, and exemplary thefirst sublayer441 being a SiNx layer and thesecond sublayer442 being a SiOx layer. The IGZOactive layer414 is then disposed on or over thesecond sublayer442, and thethird sublayer443 is then formed or deposited over thesecond sublayer442 and over (and/or around) the IGZOactive layer414. In this embodiment,buffer layer440 acts as a gate insulator since it is between thegate electrode417 and the IGZOactive layer414, and thethird sublayer443 in contact with the IGZOactive layer414 is a SiOx layer that has a lower hydrogen concentration than other SiOx or SiNx layers in thehybrid TFT structure40.

TheLTPS TFT420 includes the LTPSactive layer424 formed or deposited on thebuffer layer440, where portions of the LTPS active layer have been doped with impurities to form a source area and adrain area428, and thegate insulator426 and thegate electrode427 have been formed or deposited over theactive layer424, e.g., the LTPS semiconductor material. TheIGZO TFT410 includes thegate insulator416 andgate electrode417 formed on thebuffer layer440 over theactive layer414, e.g., the IGZO semiconductor material. Thehybrid TFT structure40 also includes aninterlayer dielectric layer450 that has been formed or deposited over the entire structure. Theinterlayer dielectric layer450 can be a single layer or a multilayer structure, where one layer comprises SiOx and another layer comprises SiNx. Each of theLTPS TFTs420 and theIGZO TFT410 includes the source and drain electrodes that have been formed on or disposed in or through theinterlayer dielectric layer450, e.g., through contact holes, where source and drainelectrodes419 are provided for theIGZO TFT410 and source and drainelectrodes429 are provided for theLTPS TFT420 to contact the source and drain areas of the active layer. TheLTPS TFT420 can define an n-channel TFT or a p-channel TFT based on the doping impurities used for doping the source and drain areas, while the source and drain areas of the IGZO active layer are formed by conductorization, plasma treatment, dry etching, or made from aluminum, titanium, molybdenum, copper, copper-manganese alloy, or a combination thereof. As in the first embodiment, the LTPSactive layer424 is not on the same plane as the IGZOactive layer414, it means the LTPS active layer and the IGZO active layer are disposed at different sides of thethird sublayer443.

The hybrid TFT structure also includes over or on theinterlayer dielectric layer450 and source and drain

electrodes

419,429, afirst passivation layer460, where the passivation layer is formed from silicon nitride, SiNx. Additionally, an insulating layer470 can be provided on thefirst passivation layer460, where common electrode490 (or pixel electrode) can be disposed on or over the insulating layer470. The insulating layer470 could be an organic layer or an inorganic layer. Lastly, asecond passivation layer480 is provided over the insulating layer470 andcommon electrode490, where pixel electrode (or common electrode)495 is provide on or above thesecond passivation layer480 and connected to the source (or drain)electrode419 of theIGZO TFT410. In another embodiment, ex. an LED display, after the hybrid TFT structure are provided, where a pixel (or anode electrode) electrode and a common electrode (or cathode electrode) can be provided on or over the insulating layer470. A display medium layer, not shown on the figures, also be provide between the pixel electrode and the common electrode, and the display medium layer could be organic light emitting layer, an inorganic light emitting layer or and quantum dot light emitting layer. Similar structure as mentioned in the first embodiment is omitted there.

As discussed further with reference toFIGS. 5A-5D, the manufacturing method for the second embodiment of the hybrid TFT structure is described. For example, in a first step, as seen inFIG. 5A, a blanking material is deposited to form ablack matrix layer430 on asubstrate layer400, e.g., using a deposition and masking process, to form patterned layers in the IGZO TFT area and the LTPS TFT area. In a second step, as illustrated inFIG. 5B, a first buffer sublayer is provided over thesubstrate layer400 and theblack matrix layer430, where the first buffer sublayer can comprise a single layer of SiOx or multiple layers, e.g., a SiNx layer as a bottom layer and a SiOx layer as a top layer. As seen inFIG. 5C, the IGZOactive layer414 is deposited over the SiOx sublayer, e.g., through a deposition and masking process. Finally, a second buffer sublayer is deposited over the entire surface, which includes the surface of the buffer sublayer and the IGZO active layer. The second buffer sublayer comprises a SiOx layer which has a lower hydrogen concentration than other SiOx or SiNx layers of thehybrid TFT structure40, and in particular a lower hydrogen concentration than a gate insulator of the LTPS TFT. For example, the second buffer sublayer has a hydrogen concentration of less than or equal to 5 atomic percent, and, in another embodiment, less than or equal to 3 atomic percent, in comparison to other SiOx layer in thehybrid TFT structure40 having a hydrogen concentration of between about 5 and 10 atomic percent, and SiNx layers of thehybrid TFT structure40 having a hydrogen concentration between about 10 and 20 atomic percent. The remainder of thehybrid TFT structure40 is produced in a similar manner as in the first embodiment.

Third Embodiment

As seen inFIG. 6, a third embodiment of the disclosure is illustrated. In this embodiment, the IGZO active layer is disposed on or over the interlayer dielectric layer disposed over the LTPS TFT. For example, as shown inFIG. 6, thehybrid TFT structure60 includes asubstrate layer600 having anIGZO TFT610 and anLTPS TFT620, which are disposed on the substrate. In this embodiment, twoLTPS TFTs620 are provided to form a driver circuit, while the IGZO TFT is used in a pixel region of a display, but it's not limited here.

Thehybrid TFT structure60 also includes aninterlayer dielectric layer650 that has been formed or deposited over the gate electrodes of IGZO TFT and LTPS TFT and also over thebuffer layer640. Theinterlayer dielectric layer650 can be a single layer or a multilayer structure, where if theinterlayer dielectric layer650 has multiple layers, the top layer comprises SiOx and the bottom layer comprises SiNx.

In this embodiment, the IGZO TFT includes an IGZOactive layer614 that has been disposed on or over theinterlayer dielectric layer650. Thehybrid TFT structure60 then includes asecond buffer layer660 that has been deposited and/or formed on theinterlayer dielectric layer650 and the IGZOactive layer614, where thesecond buffer layer660 can be a single layer of SiOx or a multilayer structure comprising at least a bottom layer of SiOx and a top layer of SiNx. As in the above embodiments, the second buffer layer660 (or sublayer) directly adjacent to (e.g., over and around) the IGZO TFTactive layer614 is a SiOx layer that has a lower hydrogen concentration than other SiOx or SiNx layers of thehybrid TFT structure60, and in particular theactive layer614 has a lower hydrogen concentration than thegate insulator626 of theLTPS TFT620. TheIGZO TFT610 further includes thegate electrode617 that has been formed on thesecond buffer layer660 over theactive layer614, e.g., the IGZO semiconductor material. In so doing, thesecond buffer layer660 acts as a gate insulator for theIGZO TFT610. Thehybrid TFT structure60 can also include afirst passivation layer670 that has been formed on thesecond buffer layer660 and thegate electrode layer617.

Thehybrid TFT structure60 also includes the source and drain electrodes that have been formed on or disposed in (or through) theinterlayer dielectric layer650, thesecond buffer layer660, andfirst passivation layer670, e.g., through patterned contact holes, where source and drainelectrodes619 are provided for theIGZO TFT610 and source and drainelectrodes629 are provided for theLTPS TFTs620 which contact the source and drain areas of the active layers, e.g., the semiconductor materials. Then after thehybrid TFT structure60 is provided, an insulatinglayer675 is provided over thefirst passivation layer670 and source and drain

electrodes

619,629, where, e.g. LCD display,common electrode690 is provided on or over the insulatinglayer675. The insulatinglayer675 could be an organic layer or an inorganic layer. Lastly, asecond passivation layer680 is provided over the insulatinglayer675 and common electrode690 (or pixel electrode), where pixel electrode (or common electrode)695 is provide on or above thesecond passivation layer680 and connected to thesource electrode619 of theIGZO TFT610. The structure of the LED or OLED display is similar to the first embodiment and omitted here.

As seen inFIG. 7, an exemplary method for manufacturing the hybrid TFT structure for the third embodiment with top gate TFT structure is described. In afirst step700, a blanking material is deposited on a substrate to form a black matrix layer, for example, by patterning and forming the black matrix layer in an area of the substrate defined as an IGZO TFT area and at least one LTPS TFT area, e.g., using a depositing and masking process. In asecond step705, the first buffer layer is deposited over the substrate and the black matrix layer, where the first buffer layer can comprise a single layer or multiple layers comprising SiOx and SiNx layers. In the next step,step710, the LTPS TFT(s) is formed in the at least one LTPS TFT area by depositing the LTPS active layer and doping the LTPS active layer to form source and drain areas, where one of the LTPS TFTs is an n-channel TFT and the other LTPS TFT is a p-channel TFT depending on the doping impurity. Then, a gate insulator is deposited over the LTPS active layer, where the gate insulator can comprise SiOx and/or SiNx layers, and depositing a gate electrode over the gate insulator. In another embodiment, a TFT structure with bottom gate (not shown on the figures), depositing a gate electrode before depositing a gate insulator, and then depositing an active layer on the gate insulator. In a followingstep715, an interlayer dielectric layer is deposited over the first buffer layer and the LTPS TFT. For example, as seen inFIG. 8A, two LTPS TFTs are formed, where one LTPS TFT is an n-channel TFT and the other LTPS TFT is a p-channel TFT, e.g., via doping the LTPS active layer with phosphorus, boron, gallium, arsenic, e.g., group V-VI elements, group IV semiconductors, or the like.

The IGZO semiconductor material is then deposited on the interlayer dielectric layer over the IGZO TFT area instep720. For example, as seen inFIG. 8B, the IGZO active layer is patterned on the interlayer dielectric layer, e.g., via a photoresist and masking process, so that the IGZO active layer is only formed and deposited in the IGZO TFT area. Instep725, a second buffer layer is deposited over the interlayer dielectric layer and the IGZO active layer, where the second buffer layer comprises at least one oxide material layer that directly contacts the IGZO semiconductor material. The oxide material of the second buffer layer, which can be an SiOx material, has a lower hydrogen concentration that other SiOx or SiNx layer in the hybrid TFT structure, and in particular the second buffer layer has a lower hydrogen concentration than the first buffer layer. For example, the second buffer layer may have a hydrogen concentration of less than 5 atomic percent, in comparison to other SiOx or SiNx layers in thehybrid TFT structure60 which have a hydrogen concentration of greater than 5 atomic percent, such as 5-10 atomic percent in SiOx layers or 10-20 atomic percent in SiNx layers.

A gate electrode is then formed on the second buffer layer over the IGZO TFT area atstep730 and a first passivation layer is deposited over the gate electrode of the IGZO TFT and the second buffer layer instep735, for example, as seen inFIG. 8C. The remainder of thehybrid TFT structure60 is produced in a similar manner as the above embodiments, in steps740-755, however, instep740, the source and drain electrodes are formed in the interlayer dielectric layer, the second buffer layer, and passivation layer.

For example, as seen inFIG. 8D, the source and drain electrodes are formed for the IGZO TFT and the two LTPS TFTs, e.g., by forming channels during the deposition steps of the different layers. An insulating layer is then formed over the source and drain electrodes and the passivation layer, where a through hole is formed over the source/drain electrode of the IGZO TFT. Lastly, after the hybrid TFT structure is provided, an optional step is provided. The pixel electrodes (or anode) and common electrode are formed over the insulating layer and/or a second passivation layer, where the pixel electrode can be connected to the source electrode of the IGZO TFT through the through hole.

Fourth Embodiment

As seen inFIG. 9, a fourth embodiment of thehybrid TFT structure90 is illustrated, which is similar to the third embodiment. In this embodiment, however, a blanking layer provided for the IGZO TFT is not part of the black matrix layer disposed on the substrate, but is instead is a part of a LTPS-gate electrode layer that acts as the blanking layer for the IGZO TFT, e.g., to block light. In this embodiment, it means that the blanking layer for the IGZO TFT and the gate electrode of LTPS TFT are formed by the same process or have the same material.

That is, in this embodiment, the blanking material is disposed on the substrate layer900 to form ablack matrix layer930 only below theLTPS TFTs920. Specifically, thehybrid TFT structure90 includes afirst buffer layer940 disposed over theblack matrix layer930 and the substrate layer900, where thefirst buffer layer940 can comprise a single layer or multiple sublayers comprising SiOx and SiNx layers, in one embodiment, a first sublayer comprising a SiOx layer, a second sublayer comprising a SiNx layer, and third sublayer over the second sublayer comprising a SiOx layer. On thefirst buffer layer940, theLTPS TFT920 includes the LTPSactive layer924 that has been formed or deposited on thebuffer layer940 and doped to have a source area and adrain area928. TheLTPS TFT920 also includes thegate insulator926 and thegate electrode927 that have been formed or deposited over the LTPSactive layer924 in each LTPS TFT. In this embodiment, one of the LTPSactive layers924 is doped to form an n-channel TFT and the other LTPSactive layer924 is doped to form a p-channel TFT and form for driving the pixel of the display. Additionally, on thefirst buffer layer940, the materials for theLTPS gate insulator926 andgate electrode927 are also formed and/or deposited below theIGZO TFT910 and act as a blanking layer for theIGZO TFT910.

Thehybrid TFT structure90 also includes aninterlayer dielectric layer950 that has been formed or deposited over the entire structure, e.g., thebuffer layer940, theIGZO TFT910 and the LTPS TFT(s)920. Theinterlayer dielectric layer950 can be a single layer or a multilayer structure, where if theinterlayer dielectric layer950 has multiple layers, the top layer comprises SiOx and the bottom layer comprises SiNx.

The IGZO TFT includes an IGZOactive layer914 that has been disposed on or over theinterlayer dielectric layer950, where a second buffer layer960 has been disposed on theinterlayer dielectric layer950 and the IGZOactive layer914. The second buffer layer960 can be a single layer or multilayer structure comprising at least a SiOx layer and an additional SiOx and/or SiNx layer. As in the above embodiments, the second buffer layer960 (or sublayer) directly adjacent to (e.g., over) the IGZOactive layer914 is an oxide layer that has a lower hydrogen concentration than other SiOx or SiNx layers in thehybrid TFT structure90, and in particular the second buffer layer960 has a lower hydrogen concentration than thefirst buffer layer940. TheIGZO TFT910 further includes thegate electrode917 formed on the second buffer layer960 over the IGZOactive layer914, where the second buffer layer960 is (acts as) the gate insulator in this embodiment. Thehybrid TFT structure90 can also include thefirst passivation layer970 that has been formed on the second buffer layer960 and thegate electrode917.

The remainder of thehybrid TFT structure90 has similar features as in the third embodiment and will not be explained further in detail herein.

The method for manufacturing thehybrid TFT structure90 for the fourth embodiment has similar steps as in the third embodiment. However, in the third step of forming the LTPS TFT on the buffer layer, the LTPS gate insulator and gate electrode are also formed below the IGZO TFT to act as the blanking layer for the IGZO TFT. The LTPS gate insulator and gate electrode can be formed and/or deposited using similar processes as discussed above, for example, a photoresist and masking process along with a deposition process.

Fifth and Sixth Embodiments

As seen inFIGS. 10 and 11, fifth and sixth embodiments are illustrated, which are similar to the third embodiment of the disclosure. In these embodiments, however, the deposition and/or etching of the source and drain electrodes for the LTPS TFT(s) and the IGZO TFT are modified at least in part during the deposition of the gate electrode for the IGZO TFT.

For example, the fifth embodiment, illustrated inFIG. 10, illustrates a hybrid TFT structure having asimilar IGZO TFT1010 andLTPS TFT1020 as in the third embodiment, where the common components will not be discussed in detail. Rather, as seen inFIG. 10, theLTPS TFT1020 includes the source anddrain electrodes1029 having at least a first part and a second part, where the first part and the second part of the source and drain electrodes are formed of different materials. For example, the first part of the source and drain electrodes can be formed along with (and/or the same material as) thegate electrode1017 of theIGZO TFT1010 on thesecond buffer layer1060 during the same depositing and masking step. TheIGZO TFT1010 includes the source anddrain electrodes1019 which have been formed in the same manner as in the previous embodiments, as discussed above, through thepassivation layer1070, while the second part of the source anddrain electrodes1029 of theLTPS TFTs1020 are also formed during the deposition and masking step having the same material as the source anddrain electrodes1019 of theIGZO TFT1010. After the hybrid TFT structure is provided, an insulatinglayer1075 is formed over the passivation layer and source and drain electrodes of theIGZO TFT1010 and theLTPS TFTs1020. The insulatinglayer1075 could be an organic layer or an inorganic layer. It is appreciated that channels connecting the source and drain electrodes to the source and drain areas of the semiconductor material can be formed by masking and/or etching the different layers.

As seen inFIG. 11, in the sixth embodiment, the hybrid TFT structure has similar features as the third embodiment having theIGZO TFT1110 and the LTPS TFT(s)1120. In this embodiment, however, thegate electrodes1117 of theIGZO TFT1110 are made from the same material as the gate and

source electrodes

1119 and1129. In so doing, such features can simplify the manufacturing steps since thegate electrodes1117, which is formed and or deposited on thesecond buffer layer1160, can be deposited in the same deposition and masking step as the source and drain electrodes for theIGZO TFT1110 and the LTPS TFT(s)1120.

Seventh Embodiment

In the seventh embodiment of the disclosure, another embodiment of the hybrid TFT structure is provided, where the SiOx layer having the lower hydrogen concentration, e.g., less than or equal to 5 atomic percent, and preferably less than or equal to 3 atomic percent, is provided in at least the gate insulator in the IGZO TFT contacting the IGZO active layer, as seen inFIGS. 12A-12L. For example, as shown inFIG. 12A, thehybrid TFT structure1200 includes anIGZO TFT1210 and anLTPS TFT1220, where additional TFTs can be provided (not shown). While a blanking layer, such as a black matrix layer, is not shown in this embodiment, it is to be understood that the blanking layer to block light, as discussed in the above embodiments, can also be included.

In the embodiment shown inFIG. 12A, thehybrid TFT structure1200 includes thesubstrate layer1201 andbuffer layer1230, as discussed in previous embodiments, having at least one (preferably two) LTPS TFT and an IGZO TFT. As in the previous embodiments, the LTPS TFT includes the LTPSactive layer1224, that was deposited and formed on thebuffer layer1201, e.g., using a photoresist and masking process, and the source and drain electrodes that are connected to the source and drain areas, e.g., contact areas, on the LTPS active layer. The LTPS TFT also includes agate insulator1226, which can be deposited and formed over the LTPS active layer, and agate electrode1228. The IGZO TFT includes an IGZOactive layer1214, e.g., IGZO semiconductor material, source/drain electrodes connected to the contact (source and drain) areas on the IGZOactive layer1214, thegate insulator1216 that has been deposited and formed over theactive layer1214, and agate electrode1218. In this embodiment, each of thegate insulator1216 and thegate insulator1226 comprise at least one silicon oxide layer, where thegate insulator1216 of theIGZO TFT1210 has an oxide film having a lower hydrogen concentration, e.g., concentration of less than 5 atomic percent (preferably less than 3 atomic percent), than thegate insulator1226 in theLTPS TFT1220, e.g., having a hydrogen concentration greater than 5 atomic percent. Additionally, in some embodiments, thegate insulator1216 of theIGZO TFT1210 has a higher film density (i.e., etching rate is lower) than thegate insulator1226 of theLTPS TFT1220. As seen inFIG. 12A, thegate insulator1216 in the IGZO TFT does not overlap thegate insulator1226 in the LTPS TFT, which can be formed using different photoresist and masking processes, where thegate insulator1216 of theIGZO TFT1210 may not entirely etch off. While not limiting the manufacturing process, in one embodiment, thegate insulator1226 is formed in theLTPS TFT1220 before forming (and/or depositing) thegate insulator1216 in theIGZO TFT1210. In another embodiment with bottom gate TFT structure not shown on the figures, the gate electrode is formed before the gate insulator, and then the active layer is formed on the gate insulator.

Thehybrid TFT structure1200 also includes aninterlayer dielectric layer1250 that has been deposited and formed over theIGZO TFT1210 and theLTPS TFT1220. Theinterlayer dielectric layer1250 can be formed from a single layer of SiOx or a multilayer structure having a top layer of SiOx and bottom layer of SiNx.

In an alternative embodiment of this disclosure, as seen inFIG. 12B, while theIGZO TFT1210 has similar features as the IGZO TFT ofFIG. 12A, theLTPS TFT1220 in this embodiment has different features than the LTPS TFT ofFIG. 12A. For example, theLTPS TFT1220 has thegate insulator1226 formed over or on the LTPSactive layer1224, and thegate electrode1228 formed over or on thegate insulator1226, and additionally has a firstinterlayer dielectric layer1240 formed over theLTPS TFT1220, e.g., the firstinterlayer dielectric layer1240 is disposed out of the IGZO TFT or only disposed in the LTPS TFT. The firstinterlayer dielectric layer1240 can be formed from a single layer of SiNx or multiple layers of combinations of SiOx and SiNx layers. Thehybrid TFT structure1200 then includes theinterlayer dielectric layer1250 that is formed over the firstinterlayer dielectric layer1240 in theLTPS TFT1220 and theIGZO TFT1210. That is, in this embodiment, the gate insulator of the IGZO TFT does not overlap on the LTPS TFT and the interlayer dielectric SiNx layer is only included in the LTPS TFT.

In a variation of this embodiment, as seen inFIG. 12C, theLTPS TFT1220 comprises the LTPSactive layer1224, agate insulator1226 formed on or over the LTPSactive layer1224, and agate electrode1228 formed over thegate insulator1226. TheIGZO TFT1210 comprises the IGZOactive layer1214 formed over the buffer layer, thegate insulator1216 formed over (and/or around) the IGZOactive layer1214 and over the buffer layer in theIGZO TFT1210, but does not overlap theLTPS TFT1220, asecond gate insulator1217 formed over thegate insulator1216, which overlaps with thegate insulator1226 of theLTPS TFT1220, and thegate electrode1218 formed over thesecond gate insulator1217 and the IGZOactive layer1214. As in the previous embodiments, thegate insulator1216, which is adjacent to the IGZOactive layer1214 has an oxide layer that has a lower hydrogen concentration than other SiOx or SiNx layers of the hybrid TFT structure, and in particular thegate insulator1216 has a lower hydrogen concentration than thesecond gate insulator1217, the gate insulator of the LTPS TFT and/or the buffer layer, e.g., less than 5 atomic percent and preferably less than 3 atomic percent. Then, theinterlayer dielectric layer1250 is formed over theLTPS TFT1220 and theIGZO TFT1210.

In another variant of this embodiment, as seen inFIG. 12D, theLTPS TFT1220 and theIGZO TFT1210 are similar to the structures illustrated in the embodiment shown inFIG. 12A, except that thegate insulator1226 of theLTPS TFT1220 overlaps or covers theLTPS TFT1220 and is below or under theIGZO TFT1210. In so doing, thehybrid TFT structure1200 includes theIGZO TFT1210 that is formed and/or deposited on thegate insulator1226. That is thegate insulator1216 of the IGZO TFT does not overlap the LTPS TFT, but thegate insulator1226 of the LTPS TFT is beneath or below the IGZO TFT.

FIG. 12E shows another variant, which is similar to the embodiment illustrated inFIG. 12B, but thegate insulator1216 of theIGZO TFT1210 is formed only on (or above) the IGZOactive layer1214. While theLTPS TFT1220 has a firstinterlayer dielectric layer1240 comprising a SiNx layer formed over theLTPS TFT1220, a SiOxinterlayer dielectric layer1250 is formed over both theLTPS TFT1220 and theIGZO TFT1210. In this embodiment, thegate insulator1216 of theIGZO TFT1210 has a lower hydrogen concentration than theinterlayer dielectric layer1250 as well as the firstinterlayer dielectric layer1240 in theLTPS TFT1220. In other words, the SiNx interlayer dielectric layer is only included on the LTPS TFT, while the SiOx interlayer dielectric layer overlaps both the LTPS TFT and the IGZO TFT.

FIG. 12F shows yet another variant of this embodiment that includes the blanking layer as ablack matrix layer1235 formed on thesubstrate1201 below theLTPS TFT1220 and theIGZO TFT1210. In this embodiment, the hybrid TFT structure includes thebuffer layer1230 that is formed on the substrate and over theblack matrix layer1235, where the LTPS TFT and the IGZO TFT are formed on thebuffer layer1230. The hybrid TFT structure also includes aSiOx insulator layer1216 that is disposed over theentire buffer layer1230 and included in the LTPS TFT and the IGZO TFT. Then theLTPS TFT1220 also includes asecond gate insulator1227 comprising a SiNx layer that has been formed over the LTPSactive layer1224 in theLTPS TFT1220 and thegate electrode1228 that has been formed on thesecond gate insulator1227. In theIGZO TFT1210, the IGZO TFT includes thegate electrode1218 that has been formed on theSiOx insulator layer1216 over the IGZO active layer. The hybrid TFT structure then includes theinterlayer dielectric layer1250 comprising a SiOx layer that has been formed over theLTPS TFT1220 and theIGZO TFT1210. As in other embodiments, thebuffer layer1230 can comprise a single layer or multiple layers of SiNx and SiOx layers, where a SiOx layer is adjacent the IGZOactive layer1214. In other words, the SiNx gate insulator is only a part of the LTPS TFT, e.g., only on the LTPS area or region.

As seen inFIG. 12G, another embodiment of the hybrid TFT structure is illustrated where thegate insulator1226 of theLTPS TFT1220 overlaps onto and over theIGZO TFT1210. In this embodiment, theLTPS TFT1220 includes the LTPSactive layer1224 in the LTPS area and theIGZO TFT1210 includes the IGZOactive layer1214 in the IGZO area deposited on thebuffer layer1201. Then the IGZO TFT includes thegate insulator1216 that is disposed over (and around) the IGZOactive layer1214 and the LTPS TFT includes thegate insulator1226 that is deposited over the LTPSactive layer1224 in the LTPS TFT area and thegate insulator1216 in the IGZO TFT area (without patterning). The hybrid TFT structure further includes theinterlayer dielectric layer1250 that is disposed and/or deposited over thegate insulator1216, where theinterlayer dielectric layer1250 can comprise a top layer of SiOx and a bottom layer of SiNx.

FIG. 12H illustrates another embodiment of the disclosure, where the hybrid TFT structure has theLTPS TFT1220 including thegate insulator1226 that is formed in the LTPS TFT area before the formation of thegate insulator1216 for theIGZO TFT1210, where thegate insulator1226 does not overlap on theIGZO TFT1210. As seen inFIG. 12H, thegate insulator1216 of theIGZO TFT1210 at the source anddrain areas1219ahas a reduced (i.e., smaller) thickness, e.g., 500-1000 Angstroms, than the thickness of thegate insulator1216 above a part of the IGZOactive layer1214, e.g., thickness of 1000-5000 Angstroms. It is appreciated that such a thinning of the gate insulator at the source anddrain areas1219afavors the conductorization process for the formation of the source and drain areas of the IGZO active layer.

In another embodiment of the disclosure, as seen inFIG. 12I, theLTPS TFT1220 and theIGZO TFT1210 are formed on the buffer layer in the LTPS TFT area and the IGZO TFT area, respectively. The hybrid TFT structure includes a firstinterlayer dielectric layer1240, which comprises a SiNx layer, that is disposed over the LTPS TFT area or region and the IGZO TFT area or region, where thegate insulator1216 is disposed over the IGZOactive layer1214 including the source anddrain areas1219a. The hybrid TFT structure then includes theinterlayer dielectric layer1250, which comprises a SiOx layer, which is disposed over the firstinterlayer dielectric layer1240.

In a variant of the embodiment shown inFIG. 12C,FIG. 12J illustrates a hybrid TFT structure having anLTPS TFT1220 with similar features as theLTPS TFT1220 as illustrated inFIG. 12C. In this variant, however, theIGZO TFT1210 includes two gate insulators to further protect the IGZO active layer. Specifically, as seen inFIG. 12J, theIGZO TFT1210 includes, after the IGZOactive layer1214 has been disposed on the buffer layer in the IGZO TFT area or region, afirst gate insulator1216athat is disposed on or over the IGZOactive layer1214. Then asecond gate insulator1216bis disposed over at least a partial portion (or the entirety thereof) of thefirst gate insulator1216a, where thesecond gate insulator1216boverlaps with thegate insulator1226 of theLTPS TFT1220. The first and the

second gate insulators

1216a,1216bcan have a substantially uniform thickness over the entirety of the IGZOactive layer1214. The IGZO TFT also includes agate electrode1218 that is formed on thesecond gate insulator1216b, e.g., over a portion of the IGZO active layer. Finally, the hybrid TFT structure includes theinterlayer dielectric layer1250, which can comprise a top layer of SiOx and a bottom layer of SiNx, that is formed over the IGZO TFT area and LTPS TFT area.

Additionally, as seen inFIG. 12K, the IGZO TFT can have thesecond gate insulator1216bbe thinned to have a thicker region over a part of the IGZO active layer corresponding to the gate electrode of the IGZO TFT and thinner regions over the source anddrain areas1219aof the active layer. Such a second gate insulator can be formed through a thinning process, as known in the art, during the deposition step or after the second gate insulator has been deposited, e.g., chemical etching.FIG. 12L shows another embodiment, where thesecond gate insulator1216bhas been formed or deposited over thefirst gate insulator1216aover the IGZOactive layer1214. In this embodiment, thefirst gate insulator1216ahas a greater thickness over a part of the IGZOactive layer1214 corresponding to the gate electrode of the IGZO TFT and thinner regions over the source anddrain areas1219a. Thefirst gate insulator1216acan be formed from known methods for thinning the gate insulator, such as hard masking after the gate electrode has been formed over the first and second insulators. It is appreciated that such a hard masking process using the gate electrode as the mask can be used in any of the identified embodiments for forming the gate insulator and during the thinning processes.

One method for manufacturing the hybrid TFT structure ofFIG. 12A will now be discussed with reference toFIGS. 13A-13L. In a first step, as seen inFIG. 13A, abuffer layer1230 is deposited on asubstrate layer1201. In a subsequent step as seen inFIG. 13B, the LTPSactive layer1224 is deposited and patterned in the LTPS TFT area. In the step illustrated inFIG. 13C, the IGZOactive layer1214 is then deposited and patterned in the IGZO TFT area. Then thegate insulator1216 is deposited and patterned over the IGZOactive layer1214 in the IGZO TFT area, as seen inFIG. 13D. As seen inFIG. 13E, thegate insulator1226 is then deposited and patterned over the LTPSactive layer1224 in the LTPS TFT area. After disposing the gate insulators, the metal layer of the gate electrode is deposited and patterned using a photoresist over the respective active layers in the LTPS TFT area and the IGZO TFT area, as illustrated inFIG. 13F.FIG. 13G then illustrates the doping of the impurities in the LTPS active layer to form the source and drain areas, e.g., regions, for the LTPS TFTs, e.g., for forming an n-channel or p-channel TFT. For example, by doping the LTPS active layer with phosphorus, boron, gallium, arsenic, e.g., group V-VI elements, group IV semiconductors, or the like.

In a following step, as seen inFIG. 13H, thegate insulator1216 in the IGZO TFT area can be thinned using an etching process and conductorization, e.g., by H2 plasma, to define the source and drain areas for the IGZO TFT, where the region over a part of the IGZOactive layer1214 corresponding to the gate electrode is thicker than the thinned regions over the source and drain areas of the active layer. It is appreciated that the source and drain areas of the IGZO active layer can be formed by conductorization, plasma treatment, dry etching, or made from aluminum, titanium, molybdenum, copper, copper-manganese alloy, or a combination thereof.

Theinterlayer dielectric layer1250 is then deposited and patterned over the gate insulators and gate electrodes, as illustrated inFIG. 13I, where contact holes (or through holes) are formed during the deposition and patterning processes. As seen inFIG. 13J, the source and

drain electrodes

1219,1229 are deposited and patterned for the LTPS TFT and the IGZO TFT, where the source and drain electrodes connect to the source and drain areas in the respective TFT. After hybrid TFT structure is provided, a passivation layer1270 can then be deposited and patterned over the source and drain electrodes and the interlayer dielectric layer, where contact holes are formed in the passivation layer1270 to connect to the source and/or drain electrodes of the TFTs, as seen inFIG. 13K. Finally, as seen inFIG. 13L, thepixel electrodes1295 can then be deposited and patterned over and through the passivation layer to electrically connect to the source/drain electrode of the LTPS TFT and the source/drain electrode of the IGZO TFT.

A method is also disclosed for manufacturing the hybrid TFT structure ofFIG. 12C as discussed with reference toFIGS. 14A-14L. In a first step, as seen inFIG. 14A, abuffer layer1230 is deposited on asubstrate layer1201. In a subsequent step as seen inFIG. 14B, the LTPSactive layer1224 is deposited and patterned in the LTPS TFT area on the buffer layer. In the step illustrated inFIG. 14C, the IGZOactive layer1214 is then deposited and patterned in the IGZO TFT area on the buffer layer. Then thegate insulator1216 is deposited and patterned over the IGZO active layer in the IGZO TFT area, as seen inFIG. 14D. Then, as seen inFIG. 14E, thegate insulator1226 is deposited and patterned over the LTPS active layer in the LTPS TFT area as well as over the gate insulator in the IGZO TFT area. After which, the gate electrode is deposited and patterned over the respective active layer in the LTPS TFT area and the IGZO TFT area using a photoresist process, as illustrated inFIG. 14F.FIG. 14G then illustrates the doping of the impurities in the LTPS active layer to define the source and drain areas, e.g., regions, for the LTPS TFT(s), e.g., for forming an n-channel or p-channel TFT, along with the patterning and thinning of the gate insulator. As seen inFIG. 14G, thegate insulator1226 for the LTPS TFT and thegate insulator1217 for the IGZO TFT are etched and thefirst gate insulator1216 over the IGZO active layer is kept and may be thinned, e.g., using the gate electrode as a hard mask during a hard masking process, where the gate insulator over a part of the IGZO active layer corresponding to the gate electrode is thicker than the areas or regions over the source and drain areas. As seen inFIG. 14H, a conductorization process is used to form the source and drain areas of the IGZO active layer.

In a following step, as seen inFIG. 14I, theinterlayer dielectric layer1250 is then deposited and patterned over the gate insulators and gate electrodes, where contact holes are formed during the deposition and patterning processes. As seen inFIG. 14J, the source and

drain electrodes

1219,1229, respectively, are deposited and patterned for the LTPS TFT and the IGZO TFT, where the source and drain electrodes electrically connect to the source and drain areas in the respective TFT. A passivation layer1270 can then be deposited and patterned over the source anddrain electrodes1219/1229 and theinterlayer dielectric layer1250, where contact holes are formed in the passivation layer to connect to the source and/or drain electrodes of the TFTs, as seen inFIG. 14K. Finally, as seen inFIG. 14L, the pixel electrodes can then be deposited and patterned over and through the passivation layer to connect to the source/drain electrode of the LTPS TFT and the source/drain electrode of the IGZO TFT.

The method for manufacturing the hybrid TFT structure ofFIG. 12E will now be discussed with reference toFIGS. 15A-15M. In a first step, as seen inFIG. 15A, abuffer layer1230 is deposited on asubstrate layer1201. In a subsequent step as seen inFIG. 15B, the LTPS active layer is deposited and patterned in the LTPS TFT area, while the IGZO active layer is deposited and patterned in the IGZO TFT area, as seen inFIG. 15C. Then thegate insulator1216 is deposited and patterned over the IGZO active layer in the IGZO TFT area, as seen inFIG. 15D and thegate insulator1226 is deposited and patterned over the LTPS active layer in the LTPS TFT area, as illustrated inFIG. 15E. While the gate insulator for the LTPS TFT and the IGZO TFT can be formed from the same material, in this embodiment, the gate insulators are formed from different materials, e.g., the gate insulator for the IGZO TFT can comprise an oxide layer having a lower hydrogen concentration, e.g., SiOx, material layer, than the gate insulator for the LTPS TFT having a higher hydrogen concentration SiOx material layer or SiNx material layer, e.g., between 5 and 20 atomic percent.

After disposing the gate insulators, the

gate electrodes

1218,1228 are deposited and patterned over the respective active layer in the LTPS TFT area and the IGZO TFT area, as illustrated inFIG. 15F, using a photoresist process.FIG. 15G then illustrates the doping of the impurities in the LTPS active layer to define the source and drain areas, e.g., regions, for the LTPS TFTs. As seen inFIG. 15H, the gate insulator in the IGZO TFT area can be thinned using a dry etching process, where the gate insulator can remain over the IGZO active layer in the IGZO TFT area, where the gate insulator has a greater thickness over a part of the active layer and a smaller thickness over the source and drain areas. The firstinterlayer dielectric layer1240, which can comprise a SiNx layer, is then deposited and patterned over the gate insulators and gate electrodes, as illustrated inFIG. 15I.

In a following step, as seen inFIG. 15J, the firstinterlayer dielectric layer1240 comprising the SiNx layer is etched so that the interlayer dielectric layer is disposed out of the IGZO TFT area or is only disposed over the LTPS TFT area. And the gate insulator and gate electrode are still disposed above the IGZO active layer. The IGZO active layer is then plasma treated to form source and drain areas, e.g., to form an n-channel TFT. After which, as seen inFIG. 15K, the secondinterlayer dielectric layer1250, which comprises a SiOx layer, can be deposited and patterned over the first interlayer dielectric layer, the LTPS TFT area, and the IGZO TFT.

The source and drain electrodes are deposited and patterned for the LTPS TFT and the IGZO TFT, where the source and drain electrodes electrically connect to the source and drain areas through source/drain contact holes in the respective TFT, and the source/drain contact holes are formed in the secondinterlayer dielectric layer1250, as seen inFIG. 15L. A passivation layer1270 and apixel electrode1295 can then be deposited and patterned over the source and drain electrodes and the interlayer dielectric layer, where contact holes are formed in the passivation layer1270 to connect to the source and/or drain electrodes of the TFTs and the top electrodes, as seen inFIG. 15M.

While the present disclosure has been described in detail as different embodiments with reference to the drawings, it is understood that the present disclosure can be formed or manufactured having different steps and features without changing the principle of the disclosure. Therefore, the disclosure is not to be limited by the description of exemplary embodiments of the disclosure, but only by the scope of the appended claims. For example, the steps for manufacturing the hybrid TFT structure so that the IGZO active layer contacts a SiOx layer is not limited to particular sequential steps for forming the hybrid TFT structure, but can be performed in any specific order or include features described and illustrated in other embodiments of the disclosure.