US20190097001A1 - Electrode structure for field effect transistor - Google Patents

Abstract

A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

Description

TECHNICAL FIELD
• This disclosure relates generally to Field Effect Transistors (FETs) and more particularly to electrode structures for such FETs.
BACKGROUND
• As is known in the art, lateral field effect transistors (FETs) used for Radio Frequency (RF) or power electronics applications utilize field plates to lower the peak E-fields at the drain-edge of the gate electrode to enable higher breakdown capability and to mitigate against electric field-induced trapping thereby avoiding degraded high power performance. One such Group III-V (here AlGaN) FET having a field plate is described inFIG. 1A, see U.S. Pat. No. 7,893,500, Wu et al, issued Feb. 22, 2011. In I-V foundries with liftoff processing the field plate is deposited over a dielectric spacer layer deposited after gate top formation. Here, the source and drain are in Ohmic contact with the Group III-V AlGaN barrier layer and a gate electrode of the FET is in Schottky contact with the barrier layer and is used to control a flow of carriers through a channel between the source and drain. As described in the above-referenced U.S. Pat. No. 7,893,500, issued Feb. 22, 2011, Wu et al., a first insulating or dielectric passivation is deposited on the barrier layer and has a first portion extending between the source and the gate, while a second portion extends between the drain and the gate. A spacer layer is disposed over the passivation layer and over the gate. It is noted however, that the thickness of the spacer layer determines the distance of portions of the field plate from the top of the gate, and contributes, when combined with the thickness of the second portion of the passivation layer, to the distance between the field plate and the surface of the barrier layer in the region between the gate and the drain. Therefore, the field plate design and implementation is additionally constrained by the deposition/thickness of the spacer layers and by the overall three dimensional (3D) surface topology inherent in III-V foundry transistor gate processing which use lift-off processing to form the field plate after forming the second spacer layer. See also, U.S. Pat. No. 7,915,644, issued Mar. 29, 2011, Wu et al., where, as shown inFIG. 1B, a single spacer layer is used; however, here again, the field plate design is still constrained by the thickness of the deposited dielectric layer and the 3D structure of the gate. In addition to the field plate placement constraints posed by the approach of depositing spacer layers over 3D gate topology, it is noted that field plates processed by this method also may suffer from metal cracking and thinning where the field plate metal passes over the 3D gate topology.
• Referring toFIG. 1C, other example of a source connected field plate is shown, see U.S. Pat. No. 9,306,014, issued Apr. 5, 2016, Kudymov et al; here subtractive processing, such as used in silicon foundries is used to form the source connected field plate during Back End Of Line (BEOL) processing as one or more metal layers disposed horizontally as metal layers fabricated subsequently to the gate process with the thickness of the interlayer dielectric material disposed between the field plate and the carrier channel and the length of the field plate interacting with the gate to determine the field profile at the edge of the gate. This approach takes advantage of high yield planar silicon (Si)-like processes, but is inherently constrained in design of its tailoring of the electric field profile of the gate by the thickness of the each deposited planar dielectric layer beneath it. Additionally, this approach inherently has more limited ability to tailor the field for optimal breakdown and performance for small source to drain distances typically used for high frequency RF HEMTs and integrated circuits at GHz frequencies.
SUMMARY
• In accordance with the present disclosure, a transistor structure is provided having: a semiconductor, a first electrode structure; a second electrode structure; a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode structure passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor.
• In one embodiment, the fourth electrode structure is connected to the first electrode structure.
• In one embodiment, the fourth electrode structure is a field plate structure.
• In one embodiment, the first electrode structure and the field plate structure are at the same voltage potential.
• In one embodiment, the first electrode structure, the second electrode structure, third electrode and the fourth electrode structure are separate electrode structures.
• In one embodiment, the first electrode structure is a source electrode structure, the second electrode structure is a drain electrode structure and the fourth electrode structure is an electrode structure for controlling an electric field in a region of the semiconductor under the fourth electrode.
• In one embodiment, the first electrode structure, the second electrode structure, third electrode structure and the fourth electrode structure are electrically isolated one from the other.
• In one embodiment, the first electrode structure and the second electrode structure are in Ohmic contact with the semiconductor.
• In one embodiment, a Field Effect Transistor (FET) structure is provided having: a semiconductor, a source electrode structure and a drain in Ohmic contact with the semiconductor, a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode and the drain electrode, the gate electrode being in contact with the semiconductor, a dielectric structure disposed over the semiconductor and extending horizontally between gate electrode structure, the source electrode structure and the drain electrode structure; and a field plate electrically connected to the source electrode, the field plate passing vertically into the dielectric structure and terminating a predetermined, finite distance above the semiconductor.
• In one embodiment, a Field Effect Transistor (FET) structure is provided having: a semiconductor, a source electrode structure and a drain electrode structure each having: an upper, electrical interconnect portion; and a lower Ohmic contact portion in Ohmic contact with the semiconductor, the upper, electrical interconnect portion passing vertically from an upper surface of the structure to the lower Ohmic contact portion; a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode and the drain electrode, the gate electrode having: an upper, electrical interconnect portion; and a lower contact portion in contact with the semiconductor; the upper, electrical interconnect portion of the gate electrode passing vertically into the FET structure to the lower contact portion; a dielectric structure disposed over the semiconductor and extending horizontally between gate electrode structure and the drain electrode structure; and, a field plate electrically connected to the upper portion of the source electrode structure and passing vertically into the dielectric structure and terminating a predetermined, finite distance from the semiconductor.
• In one embodiment, a Field Effect Transistor (FET) structure is provided having: a semiconductor; a first dielectric structure disposed over the semiconductor, a second dielectric structure disposed on the first dielectric structure; a source electrode and a drain electrode each having: an upper, electrical interconnect portion; and a lower Ohmic contact portion in Ohmic contact with the semiconductor, the lower Ohmic contact portion passing vertically through the first dielectric structure to the semiconductor, the upper, electrical interconnect portion passing vertically into the second dielectric structure to the lower Ohmic contact portion; a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode and the drain electrode, the gate electrode having: an upper, electrical interconnect portion; and a lower portion in contact with the semiconductor; the upper, electrical interconnect portion passing vertically into the second dielectric structure to the lower portion; a portion of the first dielectric structure and a portion of the second dielectric structure extending horizontally between the gate electrode and the drain electrode; and a field plate parallel to: the upper, electrical interconnect portion of the source electrode and the drain electrode; and the upper, electrical interconnect portion of the gate electrode, the field plate being disposed between the upper, electrical interconnect portion of the drain electrode and the upper, electrical interconnect portion of the gate electrode, the field plate having: an upper, electrical interconnect portion electrically connected to the upper portion of the source electrode, the upper, electrical interconnect portion of the field plate passing vertically from the upper surface of the FET structure, into the second dielectric layer, and terminating at a lower portion of the field plate, the lower portion of the field plate being disposed a predetermined, finite distance from the semiconductor.
• In one embodiment, the first dielectric structure comprises an etch stop layer and the lower portion of the field plate terminates at the etch stop layer.
• In one embodiment, the first dielectric structure comprises an etch stop layer and the lower portion of the field plate terminates at the first dielectric structure.
• In one embodiment, the first dielectric structure comprises an etch stop layer the lower portion of the field plate terminates within the second dielectric layer.
• In one embodiment, the upper, electrical interconnect portion of the source electrode and the drain electrode and, the upper, electrical interconnect portion of the gate electrode are copper Damascene structures.
• In one embodiment, the upper, electrical interconnect portion of the field plate is electrically connected to the upper portion of the source electrode though an interconnection structure and wherein the interconnection portion is a copper Damascene structure.
• With such an arrangement, the field plate passing vertically into the dielectric structure and terminating a predetermined, finite, controllable distance above the semiconductor from the surface of the semiconductor of the FET and therefore its design is decoupled from the thickness of the deposited dielectric layer structures.
• The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
DESCRIPTION OF DRAWINGS
• FIGS. 1A, 1B and IC are diagrammatical cross-sectional views of FETs having field plate structures according to the PRIOR ART;
• FIG. 2A is a diagrammatical plan view sketch of a FET having a source connected field plate according to the disclosure;
• FIG. 2B is a diagrammatical cross-sectional view sketch of the FET ofFIG. 2A, such cross-section being taken alongline2B-2B inFIG. 2A according to the disclosure;
• FIG. 2C is a diagrammatical cross-sectional view sketch of the FET ofFIG. 2A, such cross-section being taken alongline2C-2C inFIG. 2A according to the disclosure;
• FIGS. 3A-3T are diagrammatical cross-sectional view sketches of the FET ofFIGS. 2A and 2B at various stages in the fabrication thereof according to the disclosure;
• FIG. 4A is a diagrammatical cross-sectional view sketch of an exemplary of a plurality of source and drain electrode structures used in the FET ofFIGS. 2A and 2B according to the disclosure;
• FIG. 4B is a diagrammatical cross-sectional view sketch of an exemplary of a plurality of source and drain electrode structures used in the FET ofFIGS. 2A and 2B according to another embodiment of the disclosure;
• FIG. 5A is a diagrammatical cross-sectional view sketch of an exemplary of a plurality of gate electrode structures used in the FET ofFIGS. 2A and 2B according to the disclosure;
• FIG. 5B is a diagrammatical cross-sectional view sketch of an exemplary of a plurality of gate electrode structures used in the FET ofFIGS. 2A and 2B according to another embodiment of the disclosure;
• FIGS. 6A-6G are diagrammatical cross-sectional view sketches of a FET at various stages in the fabrication thereof according to another embodiment of the disclosure;
• FIG. 7 is a diagrammatical cross-sectional view sketch of the FET according to another embodiment of the disclosure;
• FIG. 8 is a diagrammatical plan view sketch of the FET according to another embodiment of the disclosure;
• FIGS. 9A-9H are diagrammatical cross-sectional view sketches of a method of forming a Schottky gate metal layer for the FET ofFIGS. 2A and 2B at various stages in the fabrication thereof;
• FIGS. 10A and 10B are diagrams useful in understanding forming a Ohmic contact structure for FET ofFIGS. 2A and 2B at various stages in the fabrication thereof;
• FIGS. 11A-11G are diagrammatical cross-sectional view sketches of a FET at various stages in the fabrication thereof according to another embodiment of the disclosure;
• FIGS. 12A and 12A′ is a pair of diagrammatical cross sectional sketches useful in understanding a another low temperature anneal process used in forming the semiconductor structure according to the disclosure; and
• FIGS. 13A-13E′ are diagrammatical plan and cross sectional views of a FET according to another embodiment of the disclosure at various stages in the fabrication thereof;FIGS. 13A′-13D′,13D″,13D′″ andFIG. 13E′ being cross sectional diagrams of plan viewFIG. 13A-13E being taken alongline13A′-13D′,13D″,13D′″ and13E′ respectively, inFIGS. 13A-13E.
• Like reference symbols in the various drawings indicate like elements.
DETAILED DESCRIPTION
• Referring now toFIGS. 2A and 2B, asemiconductor structure10 is shown having formed therein a multi-gate Field Effect Transistor (FET)12, here a HEMT. TheFET12 includes a plurality of, here, for example two, gold-free, finger-likegate electrode structures14₁,14₂. Thesemiconductor structure10 includes adielectric substrate32, to be described in detail below, having, in this example, asemiconductor mesa11,such semiconductor mesa11 having asemiconductor layer36, to be described in detail below, on thesemiconductor mesa11. More particularly, thegate electrode structures14₁,14₂are disposed on thesemiconductor layer36 ofsemiconductor mesa11 and are electrically interconnected to a gold-free,gate pad16 disposed of thesemiconductor mesa11 and on thesubstrate32 through a gate-gate pad interconnect17 (FIG. 2C); a gold-free, finger-likedrain electrode structure20 disposed on, and in Ohmic contact with, thesemiconductor layer36 on thesemiconductor mesa11 and connected to adrain pad21 off of thesemiconductor mesa11 and on thesubstrate32 as shown, and a plurality of, here for example two, gold-free,source electrode structures22_k,22₂connected to a ground conductor plane conductor24 (FIG. 2B) which serves as asource pad25 for theFET12, on the back side of asubstrate32 through electricallyconductive vias26; and a pair offield plates23₁,23₂, here, for example, source-connected field plates, disposed between thegate electrode structure14₁and thedrain electrode structure20 and between thegate electrode structure14₂and thedrain electrode structure20, respectively, as shown. It is noted while thegate electrode structure14₁,14₂controls a flow of carriers between thesource electrode structures22_k,22₂anddrain electrode structure20 through thesemiconductor mesa11, thegate pad16,drain pad21 andsource pad25 are electrically isolated by thedielectric substrate32. It should be noted that the electrical isolation provided by the etched mesa structure inFIG. 1A could also be provided by ion implantation (instead of etching), here for example nitrogen, of the same masked layer. This would result in a planar structure.
• Thefield plates23₁,23₂extend vertically down (along the Z-axis) from the upper surface of the structure10 a predetermined depth into afirst dielectric structure49, havinglayers50,56, and58, to be described. Thefield plates23₁,23₂have: upper ends29U connected to the upper portion of thesource electrode structures22₁,22₂through field plate-interconnects27_k,27₂, respectively, andlower ends29L separated from thesemiconductor layer36 by a predetermined distance P; where P is the sum of: the predetermined distance (P₁) between the lower ends29L from the upper surface of adielectric structure31,such structure31 having: adielectric layer48, here Silicon nitride, SiNx, having a predetermined thickness (P₂); adielectric layer44, here SiNx, having a predetermined thickness (P₃); and, adielectric layer38, here SiNx, here having a predetermined thickness (P₄), as shown. Thus, P=P₁+P₂+P₃+P₄. Thefield plates23₁,23₂control an electric field in a region, R, in thesemiconductor layer36 under the bottom of thefield plates23₁,23₂Thedielectric structure49 has: anupper dielectric layer58, here for example, silicon dioxide (SiO₂); amiddle dielectric layer56, here for example, silicon nitride (SiNx); and a lowerdielectric layer50, here for example, silicon dioxide (SiO₂). Thefield plates23₁,23₂are laterally spaced along the X-axis in the X-Y plane, of theFET12structure10, as shown. It is noted that thesource electrode structures22₁,22₂, thedrain electrode structure20, thegate electrode structures14₁,14₂and thefield plates23₁,23₂, are mutually parallel with one another along the Y-axis and are elongated along the Z-axis, as shown. It should be understood that the number of gate electrodes, source electrodes and drain electrodes may be more or less that that shown; in any event, each one of thegate electrode structures14₁,14₂is disposed between a corresponding one of thedrain electrode structures20 and a corresponding one of thesource electrode structures22₁,22₂to control a flow of carriers in theFET12 between the corresponding one of thesource electrode structures22_k,22₂and thedrain electrode structure20. As will be described in more detail in connection withFIGS. 3A-3T, the front or top side of thestructure10 is processed in a silicon foundry to form themulti-gate FET12.
• More particularly, and continuing with reference toFIGS. 2A and 2B, thesemiconductor structure10 includes thesubstrate32 here for example, silicon (Si), silicon carbide (SiC), or silicon on insulator (SOI). A layer of a Group III-N layer34, here gallium nitride (GaN) on an upper portion of thesubstrate32 having a thickness of approximately ˜2-5 microns over the upper surface of thesubstrate32 and by a Group III-N semiconductor layer36, here aluminum gallium nitride (Al_(x)Ga_(1-x)N, where x is 0<x≤1) for example having thicknesses of approximately 50-300 angstroms, on the upper surface of the Group III-N layer34 (FIG. 2B). It should be understood that the layer34 (FIG. 2B) is here a GaN buffer structure, which also includes nucleation and strain relief layers, not shown. Conventional silicon (Si) foundry compatible (subtractive) lithographic-etching processing techniques are used to remove portions of the Group III-N semiconductor layer34 and Group III-N semiconductor layer36 to form thesemiconductor mesa11.
• Still more particularly, thesource electrode structure22₁,22₂anddrain electrode structure20, have lowerelectrical contact structures42₁,42₃, and42₂, respectively, in Ohmic contact with thelayer36 and anupper electrode structures54₁,54₃, and54₂respectively, here a copper Damascene structure having acopper layer54bdisposed within adiffusion barrier layer54a, to be described in more detail below and shown for an exemplary one of theupper electrode structures54₁,54₃, and54₂; here upper electrode structures54₁(FIG. 2B, 3D′). Thegate electrode structures14₁,14₂have a lowerSchottky contact structure14_GCin Schottky contact with thesemiconductor layer36 and anupper electrode structure54₄,54₅; here theupper electrode54₄,54₅being the same copper Damascene structure used for theupper electrode structures54₁,54₃,54₂, respectively, of thesource electrode structure22₁,drain electrode20 structure, and thesource electrode structure22₂. Thefield plates23₁,23₂each here the same copperDamascene electrode structures54_1L,54_3L,54_2L, and54₄,54₅used for thesource electrode structures22₁,drain electrode structure20,source electrode structures22₂, andgate electrode structures14₁,14₂. It is noted that theupper electrode structures54₁,54₂,54₃, and54₄,54₅of thesource electrodes22₁,22₂,drain electrode20, andgate electrodes14₁,14₂are electrically insulated one from another by thedielectric layers38,44,48,50,56, and58, to be described, as shown. It is further noted that the interconnectingmembers27₁,27₂are also the same copper Damascene electrode structures as used for thesource electrode structures22₁,22₂drain electrode structure20, andgate electrode structures14₁,14₂. It is also noted that each one of thefield plates23₁,23₂passes vertically (along the Z-axis as electrically conductive vias) throughdielectric layer58,56, and partially intolayer50, terminating the predetermined distance P₁from the upper surface of thedielectric layer48 to thereby terminate the predetermined distance P from the upper surface of the Group III-N semiconductor layer36, as described above; it being noted that the lower ends of thefield plates29L are: vertically separated from thesemiconductor layer36 by the thicknesses of thedielectric layers38,44 and48 plus the remaining un-etched portions of thedielectric layer50 located beneathopenings53 and abovelayer48, as noted above, and are laterally spaced, and dielectrically insulated from, thegate electrode structures14₁,14₂anddrain electrode structure20, as shown. The value of the predetermined distance P is typically is determined by a mixture of experimentation and testing and device level simulation to obtain optimum FET breakdown, dispersion, and gain characteristics.
• Referring now toFIG. 3A-3T, a process for forming thestructure10 will be described. Thus, referring first toFIG. 3A, the front or top side or surface (disposed in the X-Y plane (FIG. 2A) of thesubstrate32 shown inFIG. 3A is coated with thepassivation layer38, here for example, silicon nitride SiN_xas shown inFIG. 3B, here, for example, having the predetermined thickness (P₄) is a range of 0 nm to 150 nm.Layer38 is processed using conventional silicon (Si) foundry compatible (subtractive) lithographic-etching processing techniques to form windows or openings40₁-40₃through selected portions oflayer38 exposing underlying portions of theAlGaN semiconductor layer36, as shown inFIG. 3C, where electrical contact structures42₁-42₃, (FIG. 2B) are to be formed, as shown inFIG. 3D.
• More particularly, as shown inFIG. 3D, the electrical contact structures42₁-42₃(FIG. 2B) are identical in construction, an exemplary one thereof, hereelectrical contact structure42₁, is shown in more detail inFIG. 4A to include: (A) a gold-freeOhmic contact structure42_OChaving: abottom layer42aof titanium (Ti) or tantalum (Ta); alayer42bfor example, aluminum or Si doped aluminum (Al_1-xSi_x), where the Si doping, x, is typically ≤0.05) on thelayer42a; and alayer42c, for example tantalum (Ta) or a metal nitride, here for example titanium nitride (TiN); (B) a gold-free, electrically conductiveetch stop layer42_ES, here for example, nickel or molybdenum or platinum, disposed on theOhmic contact structure42_OC. It is noted that an etch stop layer etches at a rate at less than one half (≤½) the rate of a particular etchant than the rate such etchant etches through material being etched prior to reaching the etch stop layer. Thelayers42a,42b,42cand42_ESare disposed over the surface of the structure shown inFIG. 3D and through the openings40₁-40₃. After deposition thelayers42a,42b, and42cof theOhmic contact structures42_OCare formed using conventional silicon (Si) foundry compatible subtractive patterning (lithography and etching) techniques (specifically theOhmic contact structures42_OCare dry etched using a chlorine-based dry etch chemistry). Theelectrical contact structures42₁through42₃are then formed in Ohmic contact with the Group III-N semiconductor layer36, here the AlGaN layer during an anneal process to be described. Here, for example, theelectrical contact structures42₁through42₃, is greater than 60 nm thick.
• More particularly, each one of theOhmic contact structures42_OCis a tri-metal stack and includes: (a) thebottom layer42aof Ti or Ta (which may be recessed into the upper surface portions of the Group III-N semiconductor layer36 for structures42₁-42₃by chlorine plasma-based dry etching intolayer36 prior to depositinglayer42a; (b) the aluminum-basedlayer42b, here for example, aluminum or Si doped aluminum Al_1-xSi_xlayer42b(where x is less than 1; here, x is typically ≤0.05); and (c) thetop metal layer42c, for example tantalum or ametal nitride layer42c, here for example titanium nitride (TiN) on the aluminum-basedlayer42blayer. A typical thickness forlayer42aandlayer42cis 5-30 nm, while thelayer42bcan range from 50-350 nm depending on the metal layers chosen for the Ohmic contact three-layer structure42_OCstack.
• More particularly, in order to maintain optimum contact morphology and for contamination control, the anneal of theOhmic contact structure42_OCto form a semiconductor Ohmic contact is kept below the melting point of aluminum (≤660° C.). Such low temperature anneals typically take longer than five (5) minutes in a nitrogen ambient at a steady state temperature. More particularly, a first metal element of the metal to semiconductorOhmic contact structure42_OC, here for example Ti orTa layer42a, is deposited directly on or disposed in contact with the Group III-N surface here for example Al_xGa_1-xN layer36 and forms a metal nitride by reacting with the Group V element nitrogen in the Group III-Nmaterial interface layer36 during the temperature ramp from ambient temperature to a steady state anneal temperature during the Ohmic contact formation anneal (also herein referred to as Ohmic anneal) of theOhmic contact structure42_OC. It is noted that the temperature ramp is typically ≤15° C./sec when a linear temperature ramp is used, however stepped temperature ramp profiles, and mixed step and linear ramp profiles all may be used in order to optimizefirst metal layer42ainteraction with the Group III-N surface layer36 in the formation of the metal nitride. Next, a second lower resistance metal, here forexample aluminum layer42b, diffuses into the first metal (herelayer42a), the formed metal nitride, and into the surface of the Group III-N material (here layer36) during the steady state anneal process of ≤660° C. for ≥5 minutes to provide the lowest resistance Ohmic contact. Finally, in order to maximize the amount of interaction between the first and second metals, here layers42aand42bof the metal to semiconductorOhmic contact structure42_OCthat forms the Ohmic contact, and the Group III-N material layer36 at ≤660° C. temperatures, it is necessary to prevent intermixing with any third metal layer (a metal nitride or metal, herelayer42c) disposed above the two layers (here layers42aand42b) and in contact with the upper layer of the two (herelayer42b).
• The prevention of intermixing of the first two layers of the Ohmic contact structure42_OC(here layers42aand42b) with the third (herelayer42c) can be accomplished in several ways: It may be accomplished by depositing theOhmic contact structure42_OCand annealing theOhmic contact structure42_OCas a two-layer stack of the first and second metals (layers42aand42b) with a subsequent removal of any oxidized interface (by dry etching, wet etching, or in-situ dry sputter removal of the oxidized interface) prior to third metal deposition (herelayer42c); Alternately, when all threemetals layers42a,42band42cof theOhmic contact structure42_OCare deposited prior to Ohmic anneal of theOhmic contact structure42_OC, one of the following two methods may be used to form a low temperature (≤660° C.) Ohmic contact between theOhmic contact structure42_OCand the Group III-N semiconductor layer36: In the first method (as shown inFIGS. 10A and 10B respectively for the pre and post anneal Ohmic contact structures), a metal nitride layer (such as TiN, or TaN, herelayer42c) of theOhmic contact structure42_OCis disposed in contact with the second aluminum layer (42b) and resists intermixing withlayer42bduring the anneal at ≤660° C., andmetal layer42ais alloyed with Group III-N layer36 andmetal layer42bwith a metal nitride interlayer being formed betweenlayer42aand Group III-N layer36 (it is noted that there may be some Un-alloyed portions oflayer42aafter the anneal and that the metal nitride interlayer may be discontinuous) forming a post-annealOhmic contact structure42_OC; In the second method (not shown) a thin (˜1-10 nm thick) partially oxidized second metal (hereAluminum layer42b) or third metal (here Ta, TiN, orTaN layer42c) or combination thereof, an is formed by reaction with oxygen that is either present in the gases used in, or intentionally introduced into, the deposition and/or anneal apparatus during theOhmic contact structure42_OCdeposition process or Ohmic anneal of theOhmic contact structure42_OC. This partially oxidized metal interlayer is formed between the second metal layer (herealuminum layer42b) and the third metal or metal nitride layer (here Ta, TiN, orTaN layer42c) or in contact with the second aluminum layer (42b) which resists intermixing during the anneal at ≤660° C. forming post annealOhmic contact structure42_OC. To put it another way, in the second method, thethird metal layer42c(a metal nitride or metal) is prevented from intermixing withlayer42bduring annealing by the formation of an oxide interlayer during the metal deposition and/or the anneal process, and the oxide interlayer layer is formed betweenlayer42bandlayer42c, andmetal layer42ais alloyed with Group III-N Layer36 andmetal layer42b, and metal nitride interlayer is formed betweenlayer42aand Group 1-N layer36 (it is noted that there may be some un-alloyed portions oflayer42aafter the anneal). Thus, in one embodiment (FIGS. 12A and 12A′) the intermixing is prevented by forming a partially oxidized interlayer ILb between the second and third metals of theOhmic contact structure42_OCduring the electrical contact structure metal deposition and/or Ohmic anneal process. In the first method (FIGS. 10A and 10B), the intermixing is prevented by forming a metal or metal nitride layer aslayer42c.
• Further optimization of the metal to semiconductor Ohmic contact resistance may also be achieved by adding a small amount of Silicon dopant to the Ohmic contact structure as noted above. Silicon may be deposited by multiple methods such as electron beam deposition and sputtering. Silicon can be deposited as a separate layer within the Ohmic contact structure42_OC(by sputtering of a Silicon sputtering target or by electron beam deposition) or by mixing Silicon into another layer by co-sputtering pure targets (here for example silicon and aluminum) or by sputtering a Si doped target (here for example Si doped aluminum Al_1-xSi_xlayer42bwhere the Si doping, x, is typically ≤0.05).
• Thus, the Ohmic contact formation anneal at the low temperature may be summarized as follows: forming a metal nitride with a first metal of theOhmic contact structure42_OC, herelayer42a, during a temperature ramping phase of an anneal process from ambient temperature to a steady state temperature; wherein a second metal of the electrical contact structure herelayer42bdiffuses into the first metal and to an upper surface of the Group III-N semiconductor layer herelayer36 to reduce resistance of the Ohmic contact formed at the interface of Group III-N layer36 andOhmic contact structure42_OC; and wherein the first metal, in contact with the Group III-N semiconductor layer36, and the second metal of theOhmic contact layer42bare prevented from intermixing with a third metal (or metal nitride) of theOhmic contact layer42cduring the Ohmic anneal process; and wherein the first metal and the second metal and third metal (metal nitride or metal) are maintained below their melting points during the Ohmic contact formation anneal process. The prevention of intermixing of the first two metals (layers42aand42b) with the third metal (layer42c) indirectly enhances the interaction of the first two metals with the Group III-N interface at low temperatures, thereby facilitating lower contact resistance. After the anneal process described above, the electrically conductiveetch stop layer42_ES, here for example, nickel, molybdenum or platinum is disposed onlayer42c, as shown inFIG. 3B.
• Referring now toFIG. 3E, the surface of the structure shown inFIG. 3D is coated with thedielectric layer44, here also SiN_x, as shown, having the predetermined thickness (P₃), here, for example, a thickness in a range of 0 nm to 150 nm.
• Referring now toFIG. 3F, openings orwindows46 are formed inlayers44 and38, as shown using any conventional silicon (Si) foundry compatible (subtractive) lithography and etch processing techniques to expose portion of the Group III-N semiconductor layer36 where the finger-like, gamma-shaped,gate electrodes14₁,14₂are to be formed in Schottky contact with the Group III-N semiconductor layer36, here the AlGaN layer.
• Referring now toFIG. 3G, theSchottky contact structure14_GCportions of the finger-like gate electrode structures14₁-14₂(FIGS. 2A and 2B), are formed through the openings orwindows46 using silicon (Si) foundry compatible lithography and etch processes, as shown. More particularly, and each one of the gate electrode structures14₁-14₂is identical in construction, an exemplary one thereof, heregate electrode structures14₁, is shown in detail inFIG. 5A to include: (A) gateelectrical contact structure14_GChaving agate metal layer14a, here a single material or plurality of materials for example nickel (Ni), titanium nitride (TiN), nickel/tantalum nitride (Ni/TaN), nickel/tantalum (Ni/Ta), nickel/tantalum/tantalum nitride (Ni/Ta/TaN), nickel/molybdenum, (Ni/Mo), titanium nitride/tungsten (TiN/W), or doped silicide in Schottky contact with theAlGaN semiconductor layer36; and (B) gold-free electrode contact, here a copper Damascene electrode contact, to be described in connection withFIGS. 3J-3M. Thegate metal layer14a, formed using conventional silicon (Si) foundry compatible, subtractive patterning techniques, here is a Schottky contact metal that forms the Schottky contact with the Group III-N semiconductor layer36; it is noted that the gateelectrical contact structure14_GCmay have a thin (typically ˜2-10 nm)dielectric layer14b, for example aluminum oxide (Al₂O₃), disposed between thegate metal layer14aand the Group III-N semiconductor layer36, as indicated inFIG. 5A to form an metal insulated gate HEMT (MISHEMT). It should be noted that thegate metal layer14amay be T-shaped, as shown, or gamma-shaped (F-shaped), as shown inFIG. 5B to form a gate connected field plate structure having anoverhang portion15 pointing in the direction of the adjacent drain electrode structure.
• It is noted that the dry etches for the metals or metal nitrides comprising Schottkygate metal layer14awill typically be chlorine-based (to etch, for example, Ni and TiN) or fluorine-based (to etch, for example, Mo, TiN, W, Ta, and TaN) or a combination thereof (to etch for example for TiN, W, Ta, and TaN). However, when Ni is used in Schottkygate metal layer14ait can be quite difficult to dry etch due to lack of volatile etch byproducts. Therefore, nickel dry etches, here for example chlorine (Cl₂) and argon (Ar) gas mixtures, are primarily physical etches (sputtering) and not chemical-based etches. Since, predominately physical dry etches have poor etch selectivity to underlying layers, dry etching a Ni includingSchottky layer14amay result in unacceptable over etch intopassivation layer38 in some circumstances here for example when the thickness of the Ni in Schottkygate metal layer14aand the dielectric inpassivation layer38 are about the same. In such cases a sacrificial dielectric layer (not shown) here for example silicon dioxide (SiO₂) may need to be deposited betweenpassivation layer38 and theoverhang portion15 of the Schottkygate metal layer14a.
• An alternative method of etching a Schottkygate metal layer14acomprised of Ni is to employ a dry etch for a top metal (here for example TaN, Ta, Mo or a combination thereof), if present, and a wet etch (here for example HF, H₃PO₄, HNO₃, or H₂SO₄-based or a combination thereof) for the Ni layer. It is important to choose the Ni wet etchant ofSchottky metal layer14asuch that it is highly selective to the top metal layer (if used the t5 bottom Schottky metal layer becomes14a′ and the top Schottky layer becomes14a″ as in the description ofFIGS. 9A-9G below). Additionally, the unintended removal of the nickel underneath the masked Schottkygate metal layer14afeatures (herein also referred to as undercut) should be minimized so that the gate dimensions resulting from the process are repeatable and that the gate functions as intended. As a result, as the total width of the feature size masked bySchottky metal layer14ashrinks, the thickness of the nickel layer in Schottkygate metal layer14awill shrink as well to minimize undercut. For feature sizes less than one micron (≤1 μm) as defined bySchottky gate metal14athe thickness of the deposited Ni of Schottky contactgate metal layer14ais here for example likely to be ≤100 nm.
• The formation of thegate electrode structures14₁and14₂are shown in more detail in connection withFIGS. 9A-9H. Thus, after formingdielectric layer44, here also SiN_x, as shown inFIG. 9A and the openings orwindows46 inlayers44 and38, as shown inFIG. 9B, as described above in connection withFIGS. 3E and 3F, a first gate metal or Schottkycontact metal layer14′a, here for example Ni or TiN is deposited over thedielectric layer44 and through thewindow46 onto the exposed portion of theAlGaN layer36 as shown inFIG. 9C. Next, a secondgate metal layer14″ais deposited over the first gate metal or Schottky contact layer, here TaN, Ta, Mo, or W, for example, as shown inFIG. 9C.
• Next, either a photoresist orhard mask45 is formed over a portion of the surface of the secondgate contact metal14″ain registration with thewindow46, as shown inFIG. 9D. The portion of the secondgate contact metal14″aexposed by the mask is removed using a dry etch, as shown inFIG. 9E. Next, using thesame mask45, a dry or wet etch is used to remove the exposed portions of the first gate contact orSchottky contact metal14′a, as shown inFIG. 9G. Themask45 is then removed as shown inFIG. 9H.
• After forming theSchottky contact structure14_GCof the gate electrodes14₁-14₂thedielectric layer48, here SiNx, having the predetermined thickness (P₂), here, for example, a thickness in a range of 2 nm to 150 nm, is formed over the structure shown inFIG. 3H followed bydielectric layer50, here SiO₂as shown inFIG. 3L The upper surface oflayer50 is masked and processed to form openings51 (FIG. 3J) through thelayers50 and into the upper portion oflayer48 to expose the upper surface of theSchottky contact structure14_GC. Here the etchant is a fluorine based dry etch stops at or in the upper surface oflayer14a(FIG. 5A) of theSchottky contact structure14_GCdepending on metals and/or metal nitrides used for theSchottky contact structure14_GC.
• The upper surface oflayer50 is masked and processed again to form openings53 (FIG. 3K) through the upper portion oflayer50. More particularly, here the etchant is a fluorine based dry etch and is timed to stop at a predetermined distance P₁from the upper surface of thedielectric layer48 to thereby terminate the predetermined distance P from the upper surface of the Group III-N semiconductor layer36, as shown inFIG. 3K.
• The upper surface oflayer50 is masked and processed still again to form openings vias55 (FIG. 3L) through thelayer50. More particularly, here the etchant a fluorine based dry etch and stops at theetch stop layer42_ES, as shown inFIG. 3L.
• Next, lower copper Damascene electricalinterconnect structures section54_1L,54_2L,54_3L(FIGS. 2B, 3M) of Damascene electricalinterconnect structures section54₁,54₂, and54₃are formed along with thegate electrode structures14₁and14₂, and along with thelower sections29_Lof thefield plates23₁and23₂are formed simultaneously in thevias51,53 and55, as shown inFIG. 3M. Each one of the Damascene structures is identical in construction and includes anupper layer54bof copper having the bottom and sides lined with an adhesion and copperdiffusion barrier layer54a, here for example, tantalum or tantalum nitride or a combination thereof, as shown inFIG. 3M.
• The Damascene structures are formed by first sputtering a thin metal seed layer, not shown (typically Ta/Cu, Ta/TaN, or TaN/Cu and ≤1,000 Angstroms), following by using that layer to facilitate copper plating into trenches (vias51,53 and55) formed in the dielectric layer50 (FIG. 3L). It is noted that the seed layer also functions as a copper diffusion barrier and as an adhesion layer to thedielectric layer50. The excess copper overfill of the trenches is then removed with chemical mechanical polishing (CMP), which defines the metal interconnects by leaving only metal disposed in the trenches behind and forming a planarized surface as shown inFIG. 3M.
• Next, adielectric layer56, here SiNx, followed by adielectric layer58, here SiO₂, are formed over the planarized surface as shown inFIG. 3N.
• Next,openings60 are formed through selected portions of thedielectric layer58 disposed over the Damascene electricalinterconnect structures section54_1L,54_2L,54_3Land the Damascene,lower sections29_Lof thefield plates23₁and23₂using lithographic etch processing, here using a fluorine based dry etch. It is noted that the etching stops at thedielectric layer56 which serves as an etch stop layer, as shown inFIG. 3O.
• Next upper, selected portions, of thedielectric layer58 are removed using a lithographic, timed etching processing, here using a fluorine based dry etch to formrecesses62 in such selected portions of thedielectric layer58, as shown inFIG. 3P.
• Next, Damascene structures are formed in like manner to those formed as described in connection withFIG. 3M inopenings60 and recesses62, as shown inFIG. 3Q. One of these structures is the field plate-source interconnect27₁, (FIG. 2B) that electrically interconnects source electrode22₁(FIG. 2B) to thefield plates23₁; another one of these structures is the field plate-source interconnect27₂, (FIG. 2B) that electrically interconnects source electrode22₂(FIG. 2B) to thefield plate23₂; another one of these structures is the electricalinterconnect structure section54_3Lfor thedrain electrode structure20 shown inFIG. 2B; and still another one of the structures is the gate-gate pad interconnect17 (FIG. 2C).
• After the completion of front-side processing, and referring now toFIG. 3R, the back-side processing begins. More particularly the wafer is mounted face down on a temporary carrier, not shown, the wafer is then thinned, here for example to 50 or 100 microns. The exposed bottom surface of such structure is masked to expose portions of the bottom of thesubstrate32 under theelectrode contacts54₁and54₂. Next, viaholes70 are formed in the exposed portions by etching from the bottom of the SiC orSi substrate32 using a dry fluorine-based etch, here, for example sulfur hexafluoride (SF₆).
• Next vias70 are etched through the back surface of the thinnedsubstrate32 using lithographic-etching, here a fluorine based dry etch which etching stops at theGaN layer34;GaN layer34 serving as an etch stop layer, as shown inFIG. 3S.
• Next thevias70 are extended through the I—N layers34 and36, the Ohmic contact structure42_OC(42a,42b,42c) of theelectrical contact structures42₁and42₂(FIG. 4A) to theetch stop layer42_ESof theelectrical contact structures42₁and42₂(FIG. 4A) using lithographic-etch processing, where the etchant is a chlorine based dry etch, here for example a combination of boron tri-chloride (BCl₃) and chlorine (Cl₂), as shown inFIG. 3T.
• Next, referring toFIG. 2B, the bottom of the structure ofFIG. 3T has theground plane conductor26 and electricallyconductive vias26 bottom ofsubstrate32 and into viaholes70, here comprising copper as shown. Here, for example, thelayer28bis copper with an adhesion and copperdiffusion barrier layer28a, here for example, tantalum or tantalum nitride or a combination thereof (as shown inFIG. 2B). It should be understood that theconductive vias26 andground plane24 can have alternate metals here, for example a gold (Au)layer28b, and a titanium (Ti) or titanium/platinum (Ti/Pt)layer28a. In this case, the back-side processing would be performed in an area where gold would not present any contamination problems.
• Thus, here, in the embodiment described above in connection withFIGS. 3R through 3T andFIG. 2B, after front-side processing and back-side wafer thinning, a back-side viahole70 is formed using chemical dry etching with a two-step etch process that terminates on the electrically conductiveetch stop layer42_ES. In the first step of the via hole etch process, via holes are formed in exposed portions of the bottom of the SiC orSi substrate layer32 using a dry fluorine-based etch for example, sulfur hexafluoride (SF₆). This fluorine-based etch stops selectively on Group III-N layer34 such as gallium nitride (GaN) and aluminum nitride (AlN). In the second step, the bottom surface of the exposed Group III-N layer in the viahole70 is exposed to a dry chlorine-based etch, for example a combination of boron tri-chloride (BCl₃) and chlorine (Cl₂). As previously discussed, the chlorine based etch connects the vias70 to theelectrical contact structures42₁and42₂(FIG. 4A).
• Referring now toFIGS. 6A-6G, a process for forming another embodiment is shown. Here, after completing the structure shown inFIG. 3F, instead of forming only thegate contacts14acas inFIG. 4A, metal layers80 are also formed on portions of the surface ofdielectric layer44 simultaneously with the formation of thegate contacts14_GC, as shown inFIG. 6A. The metal layers80 are here the same material as used for thegate contacts14_GCand are formed at a position oflayer44 where thefield plates23₁and23₂are to be located.
• Next, the surface of the structure is cover with dielectric layer48 (FIG. 6B) followed bydielectric layer50, as described above in connection withFIG. 3F and shown inFIG. 6C.Layer50 is then planarized, as shown inFIG. 6C.
• Next,openings82 are formed throughplanarized layer50 over the over thegate contacts14_GCand over the metal layers80 using a lithographic-etching process, here the etchant is a fluorine based dry etch and thedielectric layer48, here for example SiNx, act as an etch stop layer.Dielectric layer48 is then subsequently removed in a fluorine based dry etch process thereby exposingmetal layers80 andgate contacts14_GCas shown inFIG. 6D. One or more layers ofmetal layers80 andgate contacts14_GCmay also serve as etch stop layers.
• Next,openings84 are formed throughplanarized layer50 over the over the lowerelectrical contact structures42₁,42₃, and42₂using a lithographic-etching process, here the etchant is a fluorine based dry etch anddielectric layer48, here for example SiNx, act as an etch stop layer.Dielectric layer48 is then subsequently removed in a fluorine based dry etch process thereby exposingelectrical contact structures42₁through42₃as shown inFIG. 6E. One or more metal layers ofelectrical contact structures42₁through42₃may also serve as etch stop layers.
• The process continues as described above in connection withFIGS. 3M through 3T followed by formation of theground plane conductor24 to form the structure shown inFIG. 6F. It is noted that here thefield plates23_k,23₂extend vertically down (along the Z-axis) from the upper surface of thestructure10 through thedielectric layer50 and havelower ends29L provided bymetal layers80 which are separated from thesemiconductor layer36 by a predetermined distance P′; where P′ is the sum of the thickness (P₃) of thedielectric layer44, here SiNx, and the thickness (P₄) of thedielectric layer38, here SiNx, as shown inFIG. 6G.
• Referring now toFIG. 7, another embodiment is shown. Here, instead of using a timed etch as described above in connection withFIG. 3K, here the etchant is allowed to go to theSiNx layer48 which acts as an etch stop layer. It is noted that here thefield plates23₁,23₂extend vertically down (along the Z-axis) from the upper surface of thestructure10 through thedielectric layer50 and have lower ends which are separated from thesemiconductor layer36 by a predetermined distance P″; where P″ is the sum of the thickness (P₂) of thedielectric layer48, here SiNx, and the thickness (P₃) of thedielectric layer44, here SiNx, as shown, and the thickness (P₄) of thedielectric layer38, here SiNx, as shown.
• Referring now toFIG. 8, here, the field plate-source interconnects27₁′ and27₂′ are off thesemiconductor mesa11 as shown which may be formed using either: the timed etch process as described above in connection withFIGS. 2A, 2B and 3A-3U, or the use of themetal layer80 as described inFIGS. 6A-6G; or the use of theSiNx layer48 inFIG. 7.
• More particularly,FIG. 8 is a diagrammatical plan view sketch of the FET according to another embodiment of the disclosure. Here the field plate interconnects27₁′ and27₂′ to thesource electrode structures22₁and22₂are formed off of thesemiconductor mesa11; the cross sectional view being the same as one shown inFIG. 3M, 6F, or11F.
• Referring now toFIG. 11A-11G, diagrammatical cross-sectional view sketches of a FET at various stages in the fabrication thereof according to another embodiment of the disclosure is shown. Here, as shown inFIG. 11G, the lower ends23L of thefield plates23₁,23₂are formed in asilicon dioxide layer58′ of adielectric structure49′, as shown. The position of the lower ends23L of thefield plates23₁,23₂is to place the depth of thefield plates23₁,23₂a predetermined distance P′″ from the Group III-N semiconductor layer36, as shown inFIG. 11G.
• Thus, after forming the structure shown inFIG. 3H, alayer50′ of silicon dioxide, here, for example, having thickness of 5 nm-700 nm is deposited over such structure, as shown inFIG. 11A. Next, an silicon nitride (SiNx)etch stop layer56′ is formed over the depositedlayer50′ here having a thickness in accordance with the selected predetermined distance P′″ (FIG. 11G), as shown inFIG. 11B.
• Next, alayer58′ of silicon dioxide is deposited overlayer56′, as shown inFIG. 11C.Next openings96 are formed through silicon dioxide layers58′, silicon nitrideetch stop layer56′,silicon dioxide layer50′ to expose thegate contact14_OG, as shown using lithographic-etch processing; here a fluorine based dry etch is used for etching through the silicon dioxide layers50′ and58′ and a fluorine based dry etch is used for etching through the SiNxetch stop layer56′ exposing thegate contacts14_GCas described above in connection withFIG. 3J, producing the structure shown inFIG. 11C.
• Next,openings98 are formed throughsilicon dioxide layer58′ to the SiNxetch stop layer56′ where thefield plates23₁,23₂are to be formed (more particularly here the using lithographic-etching techniques, here using a fluorine based dry etch, as shown inFIG. 11D.
• Next,openings100 are formed through thesilicon dioxide layer58′, SiNxetch stop layer56′, andsilicon dioxide layer50′ using lithographic-etching processing; here fluorine based dry etch is used for etching through the silicon dioxide layers50′ and58′ and a fluorine based dry etch is used for etching through the SiNxetch stop layer56′ exposing the source and drainelectrical contact structures42₁,42₂and42₃as described above in connection withFIG. 3M, as shown inFIG. 11E followed by the formation of the copper Damascene electrical interconnect structures54_1L-54_3L,54₄,54₅, and29_Las shown inFIG. 11F.
• Next, thesource electrode structures22₁and22₂,drain electrode structure20,field plates structures23₁,23₂, and field plate interconnects27₁,27₂are processed as described above in connection withFIGS. 3M to 3T to form the structure shown inFIG. 11G.
• Referring now toFIGS. 13A-13E andFIGS. 13A′-13E′, andFIG. 13D″ another embodiment of the disclosure is shown. Here thefield plate structures23₁,23₂are not connected to thesource electrode structures22₁,22₂but rather are connected to an independentfield plate pads27 through a field plate interconnect27_IC (FIG. 13 C), as shown. Thus, the pair offield plate structures23₁,23₂may be connected to a voltage source independent of a voltage applied to either thesource electrode structures22₁,22₂or thedrain electrode structure20 or thegate electrode structure14₁,14₂. Accordingly, for example, instead of thefield plate structures23₁,23₂being connected to the source they could be either floating (not electrically connected to another electrode) or electrically connected to voltage values other than the voltage applied to thegate structures14₁,14₂,drain electrode structure20, orsource electrode structures22₁,22₂₎.
• More particularly, here the field plate interconnect structure27_IC is formed at the same time as (concurrently with) thefield plate structures23₁and23₂andfield plate pad27 as copper Damascene structures of the type described above having a copper layer disposed within a diffusion barrier layer; albeit off of thesemiconductor mesa11. Thus, field plate interconnect structure27_IC is formed inlayer50 at the same predetermined depth, P, from thesemiconductor layer36 as the bottom of thefield plate structures23₁and23₂.
• After forming the structure shown inFIGS. 13A and 13A′ using the processes described above, a dielectric structure, here for example silicon dioxide (SiO2)layer58 on top of a silicon nitride (SiNx)etch stop layer56, is formed over theentire substrate32, as shown inFIGS. 13B and 13B′. It is noted that the dielectric structure (silicon dioxide (SiO2)layer58 on top of a silicon nitride (SiNx) etch stop layer56) is formed over thefield plate pads27, the field plate interconnect structure27_IC, thegate pad16, and entire thesemiconductor mesa11, as shown.
• Next, referring toFIGS. 13C and 13C′, openings are formed through the portions of dielectric structure (silicon dioxide (SiO₂)layer58 on top of a silicon nitride (SiNx) etch stop layer56) (vertically along the Z axis (FIG. 13C′)) over. (A) thedrain electrode structure20, to exposesuch drain electrode20; (B) thegate pad16 to expose thegate pad16 and, (C) thefield plate pads27 to expose thefield plate pads27. CopperDamascene structures92 are formed through the openings onto the exposed:drain electrode20;gate pad16; andfield plate pads27; theDamascene structure92 on thedrain electrode20 providing a bottom portion of a drain electrode crossover99 (FIGS. 13D, 13D′; and13D″), to be described. It is noted that not only does theDamascene structure92 on thedrain electrode20 provide a bottom portion of adrain electrode crossover99, theDamascene structure92 on thegate pad16 and on thefield plate pads27 builds up the heights of thefield plate pads27 and thegate pad16 to the same height as the bottom portion of thedrain crossover99 being formed.
• Next, referring toFIGS. 13D, 13D′,13D″ and13D′″, a second dielectric structure (silicon dioxide (SiO2)layer94 on top of a silicon nitride (SiNx) etch stop layer93), is formed over the entire structure and then openings are formed through portions of the second dielectric structure layers94 and93 to expose: (A) theDamascene structure92 on thedrain electrode20 and the bottom portion of thedrain crossover99; (B) theDamascene structure92 over thegate pad16; and (C) theDamascene structure92 over thefield plate pads27. ThenDamascene structures97a,97band97care formed through the openings onto, respectively: (A) theDamascene structure92 on thedrain electrode20 thereby completing the crossover99 (which crosses over the field plate interconnect27_IC but is electrically insulated from the field plate interconnect27_IC by thedielectric structure90, as shown inFIG. 13D″); (B)Damascene structure92 over thegate pad16 and (C) theDamascene structure92 over thefield plate pads27. A simplified, diagrammatical sketch of a portion of the structure ofFIG. 13D is shown inFIG. 13D″.
• After the completion of front-side processing, the back-side processing begins; for example as described above in connection withFIG. 3R and subsequent FIGS. The competed FET is shown inFIGS. 13E and 13E′.
• It is noted that, as described above, thegate electrode structure14₁,14₂controls a flow of carriers between thesource electrode structures22₁,22₂(which are electrically connected by theground plane conductor24 on the bottom of thesubstrate32, (theground plane conductor24 serving as asource pad25 as described above in connection withFIG. 2B) anddrain electrode structure20 through thesemiconductor layer34. It is also noted thatsubstrate32 provides electrical isolation between thesource pad25,gate pad16 anddrain pad21. It is also noted, as described above, a the secondDamascene structure97aof thedrain crossover99, which crosses over the field plate interconnect27_IC, is electrically insulated from the field plate interconnect27_IC by thedielectric structure58. Therefore, thegate pad16,drain pad20,source pad25, and field plate pad27 (and hence thefield plates23₁and23₂which are over the semiconductor layers34 and38 and control an electric field in a region in the semiconductor layers34 and38 beneath thefield plates23₁and23₂), may all be fed separate, independent voltages.
• It should be noted that the predetermined distance between the bottom of the field plate and the semiconductor, referred to above as P, P″ and P′″ are determined by, for example, simulation and adjusted to provide optimum device performance. Likewise, the voltage applied to thefield plate pad27 inFIGS. 13A and 13 B is determined by, for example, simulation and adjusted to provide optimum device performance.
• A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, theFET structure12 shown inFIGS. 2A and 2B may be fabricated such that the electrical contact structures42₁-42₃(FIG. 3D) are fabricated without the electrically conductiveetch stop layer42_ES, here for example, nickel or molybdenum or platinum, disposed on theOhmic contact structure42_OCthat is shown forelectrical contact structure42₁FIG. 4A′. An example of the electrical contact structures42₁-42₃(FIG. 2B) fabricated without an electrically conductiveetch stop layer42_ES, is shown inFIG. 4B. Additionally, the dielectric stop etch layers48 and56′, here for example SiNx, can be removed in a single etch step or during sequential etches (as shown in many of the figures) during the formation of electrical interconnect structures (54_1L-54_3L,14₁,14₂) and field plate structures (29_L) to electrode structures electrical contact structures (42₁,42₃, and42₂) andgate contacts14_GC. When etch stop layers48 and56′, here for example SiNx, are removed in a single etch step during the formation of electrical interconnect structures, the bottom of the field plate structures (29_L) will terminate inlayer50′ (instead of56′ as is shown inFIG. 11F). Accordingly, other embodiments are within the scope of the following claims.

Claims (25)

What is claimed is:

1. A transistor structure, comprising:

a semiconductor;

a first electrode structure;

a second electrode structure;

a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure;

a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and

a fourth electrode structure passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor.

2. The transistor structure recited inclaim 1 wherein the fourth electrode structure is a field plate structure.

3. The transistor structure recited inclaim 2 wherein the field plate structure is connected to the first electrode structure.

4. The transistor structure recited inclaim 1 wherein the fourth electrode structure is connected to the first electrode structure.

5. The transistor structure recited inclaim 1 wherein the first electrode structure and the fourth electrode structure are electrically isolated one from another.

6. The transistor structure recited inclaim 1 wherein the first electrode structure, the second electrode structure and the fourth electrode structure are electrically isolated one from another.

7. The transistor structure recited inclaim 1 wherein the first electrode structure and the second electrode structure are in Ohmic contact with the semiconductor.

8. The transistor structure recited inclaim 5 wherein the first electrode structure and the second electrode structure are in Ohmic contact with the semiconductor.

9. The transistor structure recited inclaim 6 wherein the first electrode structure and the second electrode structure are in Ohmic contact with the semiconductor.

10. A Field Effect Transistor (FET) structure, comprising:

a semiconductor;

a source electrode structure and a drain in Ohmic contact with the semiconductor,

a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode and the drain electrode, the gate electrode being in contact with the semiconductor;

a dielectric structure disposed over the semiconductor and extending horizontally between gate electrode structure, the source electrode structure and the drain electrode structure; and

a field plate electrically connected to the source electrode, the field plate passing vertically into the dielectric structure and terminating a predetermined, finite distance above the semiconductor.

11. A Field Effect Transistor (FET) structure, comprising:

a semiconductor,

a source electrode structure and a drain electrode structure in Ohmic contact with the semiconductor,

a gate electrode structure for controlling a flow of carriers in the semiconductor between the source electrode structure and the drain electrode structure, the gate electrode structure being in contact with the semiconductor,

a dielectric structure disposed over the semiconductor and extending horizontally between gate electrode structure and the drain electrode structure; and

a field plate electrically connected to the source electrode, the field plate passing vertically into the dielectric structure and terminating a predetermined, finite distance above the semiconductor.

12. A Field Effect Transistor (FET) structure, comprising:

a semiconductor;

a source electrode structure and a drain electrode structure each having: an upper, electrical interconnect portion; and a lower Ohmic contact portion in Ohmic contact with the semiconductor, the upper, electrical interconnect portion passing vertically from an upper surface of the FET structure to the lower Ohmic contact portion;

a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode structure and the drain electrode structure, the gate electrode structure having: an upper, electrical interconnect portion; and a lower contact portion in contact with the semiconductor, the upper, electrical interconnect portion of the gate electrode structure passing vertically into the upper surface of the FET structure to the lower contact portion;

a dielectric structure disposed over the semiconductor and extending horizontally between gate electrode structure and the drain electrode structure; and

a field plate electrically connected to the upper portion of the source electrode and passing vertically into the dielectric structure and terminating a predetermined, finite distance from the semiconductor.

13. A Field Effect Transistor (FET) structure, comprising:

a semiconductor;

a first dielectric structure disposed over the semiconductor,

a second dielectric structure disposed on the first dielectric structure;

a source electrode and a drain electrode each having: an upper, electrical interconnect portion; and a lower Ohmic contact portion in Ohmic contact with the semiconductor, the lower Ohmic contact portion passing vertically through the first dielectric structure to the semiconductor, the upper, electrical interconnect portion passing vertically into the second dielectric structure to the lower Ohmic contact portion;

a gate electrode for controlling a flow of carriers in the semiconductor between the source electrode and the drain electrode, the gate electrode having: an upper, electrical interconnect portion; and a lower portion in contact with the semiconductor; the lower portion; the upper, electrical interconnect portion passing vertically into the second dielectric structure to the lower portion

wherein a portion of the second dielectric structure extends horizontally between the gate electrode and the drain electrode; and

a field plate parallel to: the upper, electrical interconnect portion of the source electrode and the drain electrode; and the upper, electrical interconnect portion of the gate electrode, the field plate being disposed between the upper, electrical interconnect portion of the drain electrode and the upper, electrical interconnect portion of the gate electrode, the field plate having: an upper, electrical interconnect portion electrically connected to the upper portion of the source electrode, the upper, electrical interconnect portion of the field plate passing vertically from the upper surface of the FET structure, into the second dielectric layer, and terminating at a lower portion of the field plate, the lower portion of the field plate being disposed a predetermined, finite distance from the semiconductor.

14. The Field Effect Transistor (FT) recited inclaim 13 wherein: the first dielectric structure comprises an etch stop layer and wherein the lower portion of the field plate terminates at the etch stop layer.

15. The Field Effect Transistor (FET) recited inclaim 13 wherein: the first dielectric structure comprises an etch stop layer and wherein the lower portion of the field plate terminates at the upper surface of the first dielectric structure.

16. The Field Effect Transistor (FET) recited inclaim 13 wherein: the second dielectric structure comprises an etch stop layer and wherein the lower portion of the field plate terminates within the second dielectric layer.

17. The Field Effect Transistor (FET) recited inclaim 13 wherein the upper, electrical interconnect portion of the source electrode and the drain electrode; and the upper, electrical interconnect portion of the gate electrode are copper Damascene structures.

18. The Field Effect Transistor (FET) recited inclaim 13 wherein the field plate and upper, electrical interconnect portion of the source electrode and the drain electrode; and the upper, electrical interconnect portion of the gate electrode are copper Damascene structures.

19. The Field Effect Transistor (FET) recited inclaim 14 wherein the upper, electrical interconnect portion of the field plate is electrically connected to the upper portion of the source electrode through an interconnection structure and wherein the interconnection portion is a copper Damascene structure.

20. The Field Effect Transistor (FET) recited inclaim 13 wherein: the lower portion of the field plate terminates on a metal layer disposed above the first dielectric structure layer.

21. The Field Effect Transistor (FET) recited inclaim 20 wherein the upper, electrical interconnect portion of the field plate is electrically connected to the upper portion of the source electrode though an interconnection structure and wherein the interconnection portion is a copper Damascene structure.

22. The transistor structure recited inclaim 1 wherein the first electrode structure, the second electrode structure, the third electrode structure and the fourth electrode structure are electrically isolated one from another.

23. The transistor structure recited inclaim 22 wherein the first electrode structure is a source electrode structure, the second electrode structure is a drain electrode structure and the fourth electrode structure is an electrode structure for controlling an electric field in the semiconductor under the fourth electrode structure.

24. The transistor structure recited inclaim 1 wherein the first electrode structure, the second electrode structure, the third electrode structure are electrically isolated one from another and the fourth electrode structure is connected to the first electrode structure.

25. The transistor structure recited inclaim 24 wherein the fourth electrode structure is an electrode structure for controlling an electric field in the semiconductor under the fourth electrode structure.

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