US20190067848A1 - Memory mezzanine connectors - Google Patents

Abstract

Sleds for operation in racks of data centers are disclosed herein. A sled includes a circuit board substrate, one or more physical resources, and one or more memory devices. The circuit board substrate has a top side and a bottom side arranged opposite the top side. The one or more physical resources are coupled to the top side of the circuit board substrate. The one or more memory devices are coupled to the bottom side of the circuit board substrate. Additionally, the sled includes a connector to electrically couple the one or more physical resources to the one or more memory devices.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017, and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
BACKGROUND
• Typical enterprise-level data centers can include several to hundreds of racks or cabinets, with each rack/cabinet housing multiple servers. Each of the various servers of a data center may be communicatively connectable to each other via one or more local networking switches, routers, and/or other interconnecting devices, cables, and/or interfaces. The number of racks and servers of a particular data center, as well as the complexity of the design of the data center, may depend on the intended use of the data center, as well as the quality of service the data center is intended to provide.
• Traditional rack systems are self-contained physical support structures that include a number of pre-defined server spaces. A corresponding server may be mounted in each pre-defined server space. Each server may include physical resources and memory devices that interface with one another. Conventional interfaces between physical resources and memory devices may complicate service of the servers and be associated with undesirable maintenance and/or repair costs.
BRIEF DESCRIPTION OF THE DRAWINGS
• The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
• FIG. 1 is a diagram of a conceptual overview of a data center in which one or more techniques described herein may be implemented according to various embodiments;
• FIG. 2 is a diagram of an example embodiment of a logical configuration of a rack of the data center ofFIG. 1;
• FIG. 3 is a diagram of an example embodiment of another data center in which one or more techniques described herein may be implemented according to various embodiments;
• FIG. 4 is a diagram of another example embodiment of a data center in which one or more techniques described herein may be implemented according to various embodiments;
• FIG. 5 is a diagram of a connectivity scheme representative of link-layer connectivity that may be established among various sleds of the data centers ofFIGS. 1, 3, and 4;
• FIG. 6 is a diagram of a rack architecture that may be representative of an architecture of any particular one of the racks depicted inFIGS. 1-4 according to some embodiments;
• FIG. 7 is a diagram of an example embodiment of a sled that may be used with the rack architecture ofFIG. 6;
• FIG. 8 is a diagram of an example embodiment of a rack architecture to provide support for sleds featuring expansion capabilities;
• FIG. 9 is a diagram of an example embodiment of a rack implemented according to the rack architecture ofFIG. 8;
• FIG. 10 is a diagram of an example embodiment of a sled designed for use in conjunction with the rack ofFIG. 9;
• FIG. 11 is a diagram of an example embodiment of a data center in which one or more techniques described herein may be implemented according to various embodiments;
• FIG. 12A is an elevation view of a top side of a sled designed for use in conjunction with at least one of the racks depicted inFIGS. 1-4 and 9;
• FIG. 12B is an elevation view of a bottom side of the sled ofFIG. 12A;
• FIG. 13 is a diagrammatic view of one embodiment of the sled shown inFIG. 12 with passageways formed in a circuit board substrate of the sled that are sized to receive multiple connectors;
• FIG. 14 is a side elevation view of another embodiment of the sled shown inFIG. 12 with a cutout formed in a circuit board substrate of the sled that is sized to receive a casing that houses multiple connectors;
• FIG. 15 is a perspective view of a connector for use with at least one of the sleds shown inFIGS. 13 and 14;
• FIG. 16 is a sectional view of the sled shown inFIG. 12 taken about line16-16 with the casing received by the cutout formed in the circuit board substrate of the sled;
• FIG. 17 is a simplified flowchart of a method of mounting a plurality of physical resources to the circuit board substrate of the sled shown inFIG. 12;
• FIG. 18 is a diagrammatic view of another embodiment of the sled shown inFIG. 12 that includes a connector socket for use with another connector socket of a memory device;
• FIG. 19 is a side elevation view of the sled shown inFIG. 18 with the connector socket spaced from the connector socket of the memory device;
• FIG. 20 is a perspective view of connectors of the respective sockets shown inFIG. 18 spaced from one another;
• FIG. 21 is a detail view of one of the connectors ofFIG. 20;
• FIG. 22 is a side elevation view of the sled shown inFIG. 18 with the connector socket mated with the connector socket of the memory device;
• FIG. 23 is a perspective view of the connectors of the respective sockets shown inFIG. 18 mated with one another;
• FIG. 24 is a diagrammatic view of yet another embodiment of the sled shown inFIG. 12 that includes a pair of connector sockets;
• FIG. 25 is a side elevation view of the sled shown inFIG. 24 with a memory device partially received by one of the connector sockets;
• FIG. 26 is a sectional view of the sled shown inFIG. 24 taken about line26-26 with the memory device fully received by the one of the connector sockets; and
• FIG. 27 is a magnified perspective view of a portion of the connector socket shown inFIG. 26 that receives the memory device.
DETAILED DESCRIPTION OF THE DRAWINGS
• While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
• References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
• The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
• In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
• FIG. 1 illustrates a conceptual overview of adata center100 that may generally be representative of a data center or other type of computing network in/for which one or more techniques described herein may be implemented according to various embodiments. As shown inFIG. 1,data center100 may generally contain a plurality of racks, each of which may house computing equipment comprising a respective set of physical resources. In the particular non-limiting example depicted inFIG. 1,data center100 contains fourracks102A to102D, which house computing equipment comprising respective sets of physical resources (PCRs)105A to105D. According to this example, a collective set ofphysical resources106 ofdata center100 includes the various sets ofphysical resources105A to105D that are distributed amongracks102A to102D.Physical resources106 may include resources of multiple types, such as—for example—processors, co-processors, accelerators, field programmable gate arrays (FPGAs), memory, and storage. The embodiments are not limited to these examples.
• Theillustrative data center100 differs from typical data centers in many ways. For example, in the illustrative embodiment, the circuit boards (“sleds”) on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In particular, in the illustrative embodiment, the sleds are shallower than typical boards. In other words, the sleds are shorter from the front to the back, where cooling fans are located. This decreases the length of the path that air must to travel across the components on the board. Further, the components on the sled are spaced further apart than in typical circuit boards, and the components are arranged to reduce or eliminate shadowing (i.e., one component in the air flow path of another component). In the illustrative embodiment, processing components such as the processors are located on a top side of a sled while near memory, such as DIMMs, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in eachrack102A,102B,102C,102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.
• Furthermore, in the illustrative embodiment, thedata center100 utilizes a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds, in the illustrative embodiment, are coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, thedata center100 may, in use, pool resources, such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local. Theillustrative data center100 additionally receives utilization information for the various resources, predicts resource utilization for different types of workloads based on past resource utilization, and dynamically reallocates the resources based on this information.
• Theracks102A,102B,102C,102D of thedata center100 may include physical design features that facilitate the automation of a variety of types of maintenance tasks. For example,data center100 may be implemented using racks that are designed to be robotically-accessed, and to accept and house robotically-manipulatable resource sleds. Furthermore, in the illustrative embodiment, theracks102A,102B,102C,102D include integrated power sources that receive a greater voltage than is typical for power sources. The increased voltage enables the power sources to provide additional power to the components on each sled, enabling the components to operate at higher than typical frequencies.
• FIG. 2 illustrates an exemplary logical configuration of arack202 of thedata center100. As shown inFIG. 2,rack202 may generally house a plurality of sleds, each of which may comprise a respective set of physical resources. In the particular non-limiting example depicted inFIG. 2, rack202 houses sleds204-1 to204-4 comprising respective sets of physical resources205-1 to205-4, each of which constitutes a portion of the collective set ofphysical resources206 comprised inrack202. With respect toFIG. 1, ifrack202 is representative of—for example—rack102A, thenphysical resources206 may correspond to thephysical resources105A comprised inrack102A. In the context of this example,physical resources105A may thus be made up of the respective sets of physical resources, including physical storage resources205-1, physical accelerator resources205-2, physical memory resources205-3, and physical compute resources205-5 comprised in the sleds204-1 to204-4 ofrack202. The embodiments are not limited to this example. Each sled may contain a pool of each of the various types of physical resources (e.g., compute, memory, accelerator, storage). By having robotically accessible and robotically manipulatable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate.
• FIG. 3 illustrates an example of adata center300 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. In the particular non-limiting example depicted inFIG. 3,data center300 comprises racks302-1 to302-32. In various embodiments, the racks ofdata center300 may be arranged in such fashion as to define and/or accommodate various access pathways. For example, as shown inFIG. 3, the racks ofdata center300 may be arranged in such fashion as to define and/or accommodateaccess pathways311A,311B,311C, and311D. In some embodiments, the presence of such access pathways may generally enable automated maintenance equipment, such as robotic maintenance equipment, to physically access the computing equipment housed in the various racks ofdata center300 and perform automated maintenance tasks (e.g., replace a failed sled, upgrade a sled). In various embodiments, the dimensions ofaccess pathways311A,311B,311C, and311D, the dimensions of racks302-1 to302-32, and/or one or more other aspects of the physical layout ofdata center300 may be selected to facilitate such automated operations. The embodiments are not limited in this context.
• FIG. 4 illustrates an example of adata center400 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As shown inFIG. 4,data center400 may feature anoptical fabric412.Optical fabric412 may generally comprise a combination of optical signaling media (such as optical cabling) and optical switching infrastructure via which any particular sled indata center400 can send signals to (and receive signals from) each of the other sleds indata center400. The signaling connectivity thatoptical fabric412 provides to any given sled may include connectivity both to other sleds in a same rack and sleds in other racks. In the particular non-limiting example depicted inFIG. 4,data center400 includes fourracks402A to402D.Racks402A to402D house respective pairs ofsleds404A-1 and404A-2,404B-1 and404B-2,404C-1 and404C-2, and404D-1 and404D-2. Thus, in this example,data center400 comprises a total of eight sleds. Viaoptical fabric412, each such sled may possess signaling connectivity with each of the seven other sleds indata center400. For example, viaoptical fabric412,sled404A-1 inrack402A may possess signaling connectivity withsled404A-2 inrack402A, as well as the sixother sleds404B-1,404B-2,404C-1,404C-2,404D-1, and404D-2 that are distributed among theother racks402B,402C, and402D ofdata center400. The embodiments are not limited to this example.
• FIG. 5 illustrates an overview of aconnectivity scheme500 that may generally be representative of link-layer connectivity that may be established in some embodiments among the various sleds of a data center, such as any ofexample data centers100,300, and400 ofFIGS. 1, 3, and 4.Connectivity scheme500 may be implemented using an optical fabric that features a dual-modeoptical switching infrastructure514. Dual-modeoptical switching infrastructure514 may generally comprise a switching infrastructure that is capable of receiving communications according to multiple link-layer protocols via a same unified set of optical signaling media, and properly switching such communications. In various embodiments, dual-modeoptical switching infrastructure514 may be implemented using one or more dual-modeoptical switches515. In various embodiments, dual-modeoptical switches515 may generally comprise high-radix switches. In some embodiments, dual-modeoptical switches515 may comprise multi-ply switches, such as four-ply switches. In various embodiments, dual-modeoptical switches515 may feature integrated silicon photonics that enable them to switch communications with significantly reduced latency in comparison to conventional switching devices. In some embodiments, dual-modeoptical switches515 may constituteleaf switches530 in a leaf-spine architecture additionally including one or more dual-mode optical spine switches520.
• In various embodiments, dual-mode optical switches may be capable of receiving both Ethernet protocol communications carrying Internet Protocol (IP packets) and communications according to a second, high-performance computing (HPC) link-layer protocol (e.g., Intel's Omni-Path Architecture's, Infiniband) via optical signaling media of an optical fabric. As reflected inFIG. 5, with respect to any particular pair ofsleds504A and504B possessing optical signaling connectivity to the optical fabric,connectivity scheme500 may thus provide support for link-layer connectivity via both Ethernet links and HPC links. Thus, both Ethernet and HPC communications can be supported by a single high-bandwidth, low-latency switch fabric. The embodiments are not limited to this example.
• FIG. 6 illustrates a general overview of arack architecture600 that may be representative of an architecture of any particular one of the racks depicted inFIGS. 1 to 4 according to some embodiments. As reflected inFIG. 6,rack architecture600 may generally feature a plurality of sled spaces into which sleds may be inserted, each of which may be robotically-accessible via arack access region601. In the particular non-limiting example depicted inFIG. 6,rack architecture600 features five sled spaces603-1 to603-5. Sled spaces603-1 to603-5 feature respective multi-purpose connector modules (MPCMs)616-1 to616-5.
• FIG. 7 illustrates an example of asled704 that may be representative of a sled of such a type. As shown inFIG. 7,sled704 may comprise a set ofphysical resources705, as well as anMPCM716 designed to couple with a counterpart MPCM whensled704 is inserted into a sled space such as any of sled spaces603-1 to603-5 ofFIG. 6.Sled704 may also feature anexpansion connector717.Expansion connector717 may generally comprise a socket, slot, or other type of connection element that is capable of accepting one or more types of expansion modules, such as anexpansion sled718. By coupling with a counterpart connector onexpansion sled718,expansion connector717 may providephysical resources705 with access tosupplemental computing resources705B residing onexpansion sled718. The embodiments are not limited in this context.
• FIG. 8 illustrates an example of arack architecture800 that may be representative of a rack architecture that may be implemented in order to provide support for sleds featuring expansion capabilities, such assled704 ofFIG. 7. In the particular non-limiting example depicted inFIG. 8,rack architecture800 includes seven sled spaces803-1 to803-7, which feature respective MPCMs816-1 to816-7. Sled spaces803-1 to803-7 include respective primary regions803-1A to803-7A and respective expansion regions803-1B to803-7B. With respect to each such sled space, when the corresponding MPCM is coupled with a counterpart MPCM of an inserted sled, the primary region may generally constitute a region of the sled space that physically accommodates the inserted sled. The expansion region may generally constitute a region of the sled space that can physically accommodate an expansion module, such asexpansion sled718 ofFIG. 7, in the event that the inserted sled is configured with such a module.
• FIG. 9 illustrates an example of arack902 that may be representative of a rack implemented according torack architecture800 ofFIG. 8 according to some embodiments. In the particular non-limiting example depicted inFIG. 9, rack902 features seven sled spaces903-1 to903-7, which include respective primary regions903-1A to903-7A and respective expansion regions903-1B to903-7B. In various embodiments, temperature control inrack902 may be implemented using an air cooling system. For example, as reflected inFIG. 9,rack902 may feature a plurality offans919 that are generally arranged to provide air cooling within the various sled spaces903-1 to903-7. In some embodiments, the height of the sled space is greater than the conventional “1U” server height. In such embodiments,fans919 may generally comprise relatively slow, large diameter cooling fans as compared to fans used in conventional rack configurations. Running larger diameter cooling fans at lower speeds may increase fan lifetime relative to smaller diameter cooling fans running at higher speeds while still providing the same amount of cooling. The sleds are physically shallower than conventional rack dimensions. Further, components are arranged on each sled to reduce thermal shadowing (i.e., not arranged serially in the direction of air flow). As a result, the wider, shallower sleds allow for an increase in device performance because the devices can be operated at a higher thermal envelope (e.g., 250 W) due to improved cooling (i.e., no thermal shadowing, more space between devices, more room for larger heat sinks, etc.).
• MPCMs916-1 to916-7 may be configured to provide inserted sleds with access to power sourced by respective power modules920-1 to920-7, each of which may draw power from anexternal power source921. In various embodiments,external power source921 may deliver alternating current (AC) power to rack902, and power modules920-1 to920-7 may be configured to convert such AC power to direct current (DC) power to be sourced to inserted sleds. In some embodiments, for example, power modules920-1 to920-7 may be configured to convert 277-volt AC power into 12-volt DC power for provision to inserted sleds via respective MPCMs916-1 to916-7. The embodiments are not limited to this example.
• MPCMs916-1 to916-7 may also be arranged to provide inserted sleds with optical signaling connectivity to a dual-modeoptical switching infrastructure914, which may be the same as—or similar to—dual-modeoptical switching infrastructure514 ofFIG. 5. In various embodiments, optical connectors contained in MPCMs916-1 to916-7 may be designed to couple with counterpart optical connectors contained in MPCMs of inserted sleds to provide such sleds with optical signaling connectivity to dual-modeoptical switching infrastructure914 via respective lengths of optical cabling922-1 to922-7. In some embodiments, each such length of optical cabling may extend from its corresponding MPCM to an optical interconnect loom923 that is external to the sled spaces ofrack902. In various embodiments, optical interconnect loom923 may be arranged to pass through a support post or other type of load-bearing element ofrack902. The embodiments are not limited in this context. Because inserted sleds connect to an optical switching infrastructure via MPCMs, the resources typically spent in manually configuring the rack cabling to accommodate a newly inserted sled can be saved.
• FIG. 10 illustrates an example of asled1004 that may be representative of a sled designed for use in conjunction withrack902 ofFIG. 9 according to some embodiments.Sled1004 may feature anMPCM1016 that comprises anoptical connector1016A and a power connector1016B, and that is designed to couple with a counterpart MPCM of a sled space in conjunction with insertion ofMPCM1016 into that sled space.Coupling MPCM1016 with such a counterpart MPCM may causepower connector1016 to couple with a power connector comprised in the counterpart MPCM. This may generally enablephysical resources1005 ofsled1004 to source power from an external source, viapower connector1016 andpower transmission media1024 that conductively couplespower connector1016 tophysical resources1005.
• Sled1004 may also include dual-mode opticalnetwork interface circuitry1026. Dual-mode opticalnetwork interface circuitry1026 may generally comprise circuitry that is capable of communicating over optical signaling media according to each of multiple link-layer protocols supported by dual-modeoptical switching infrastructure914 ofFIG. 9. In some embodiments, dual-mode opticalnetwork interface circuitry1026 may be capable both of Ethernet protocol communications and of communications according to a second, high-performance protocol. In various embodiments, dual-mode opticalnetwork interface circuitry1026 may include one or moreoptical transceiver modules1027, each of which may be capable of transmitting and receiving optical signals over each of one or more optical channels. The embodiments are not limited in this context.
• Coupling MPCM1016 with a counterpart MPCM of a sled space in a given rack may causeoptical connector1016A to couple with an optical connector comprised in the counterpart MPCM. This may generally establish optical connectivity between optical cabling of the sled and dual-mode opticalnetwork interface circuitry1026, via each of a set ofoptical channels1025. Dual-mode opticalnetwork interface circuitry1026 may communicate with thephysical resources1005 ofsled1004 via electrical signaling media.1028. In addition to the dimensions of the sleds and arrangement of components on the sleds to provide improved cooling and enable operation at a relatively higher thermal envelope (e.g., 250 W), as described above with reference toFIG. 9, in sonic embodiments, a sled may include one or more additional features to facilitate air cooling, such as a heatpipe and/or heat sinks arranged to dissipate heat generated byphysical resources1005. It is worthy of note that although theexample sled1004 depicted inFIG. 10 does not feature an expansion connector, any given sled that features the design elements ofsled1004 may also feature an expansion connector according to some embodiments. The embodiments are not limited in this context.
• FIG. 11 illustrates an example of adata center1100 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As reflected inFIG. 11, a physicalinfrastructure management framework1150A may be implemented to facilitate management of aphysical infrastructure1100A ofdata center1100. In various embodiments, one function of physicalinfrastructure management framework1150A may be to manage automated maintenance functions withindata center1100, such as the use of robotic maintenance equipment to service computing equipment withinphysical infrastructure1100A. In some embodiments,physical infrastructure1100A may feature an advanced telemetry system that performs telemetry reporting that is sufficiently robust to support remote automated management ofphysical infrastructure1100A. In various embodiments, telemetry information provided by such an advanced telemetry system may support features such as failure prediction/prevention capabilities and capacity planning capabilities. In some embodiments, physicalinfrastructure management framework1150A may also be configured to manage authentication of physical infrastructure components using hardware attestation techniques. For example, robots may verify the authenticity of components before installation by analyzing information collected from a radio frequency identification (RFID) tag associated with each component to be installed. The embodiments are not limited in this context.
• As shown inFIG. 11, thephysical infrastructure1100A ofdata center1100 may comprise anoptical fabric1112, which may include a dual-mode optical switching infrastructure1114.Optical fabric1112 and dual-mode optical switching infrastructure1114 may be the same as—or similar to—optical fabric412 ofFIG. 4 and dual-modeoptical switching infrastructure514 ofFIG. 5, respectively, and may provide high-bandwidth, low-latency, multi-protocol connectivity among sleds ofdata center1100. As discussed above, with reference toFIG. 1, in various embodiments, the availability of such connectivity may make it feasible to disaggregate and dynamically pool resources such as accelerators, memory, and storage. In some embodiments, for example, one or more pooledaccelerator sleds1130 may be included among thephysical infrastructure1100A ofdata center1100, each of which may comprise a pool of accelerator resources—such as co-processors and/or FPGAs, for example—that is globally accessible to other sleds viaoptical fabric1112 and dual-mode optical switching infrastructure1114.
• In another example, in various embodiments, one or more pooledstorage sleds1132 may be included among thephysical infrastructure1100A ofdata center1100, each of which may comprise a pool of storage resources that is globally accessible to other sleds viaoptical fabric1112 and dual-mode optical switching infrastructure1114. In some embodiments, such pooledstorage sleds1132 may comprise pools of solid-state storage devices such as solid-state drives (SSDs). In various embodiments, one or more high-performance processing sleds1134 may be included among thephysical infrastructure1100A ofdata center1100. In some embodiments, high-performance processing sleds1134 may comprise pools of high-performance processors, as well as cooling features that enhance air cooling to yield a higher thermal envelope of up to 250 W or more. In various embodiments, any given high-performance processing sled1134 may feature an expansion connector1117 that can accept a far memory expansion sled, such that the far memory that is locally available to that high-performance processing sled1134 is disaggregated from the processors and near memory comprised on that sled. In some embodiments, such a high-performance processing sled1134 may be configured with far memory using an expansion sled that comprises low-latency SSD storage. The optical infrastructure allows for compute resources on one sled to utilize remote accelerator/FPGA, memory, and/or SSD resources that are disaggregated on a sled located on the same rack or any other rack in the data center. The remote resources can be located one switch jump away or two-switch jumps away in the spine-leaf network architecture described above with reference toFIG. 5. The embodiments are not limited in this context.
• In various embodiments, one or more layers of abstraction may be applied to the physical resources ofphysical infrastructure1100A in order to define a virtual infrastructure, such as a software-defined infrastructure1100B. In some embodiments, virtual computing resources1136 of software-defined infrastructure1100B may be allocated to support the provision ofcloud services1140. In various embodiments, particular sets of virtual computing resources1136 may be grouped for provision to cloudservices1140 in the form ofSDI services1138. Examples ofcloud services1140 may include—without limitation—software as a service (SaaS)services1142, platform as a service (PaaS)services1144, and infrastructure as a service (IaaS) services1146.
• In some embodiments, management of software-defined infrastructure1100B may be conducted using a virtualinfrastructure management framework1150B. In various embodiments, virtualinfrastructure management framework1150B may be designed to implement workload fingerprinting techniques and/or machine-learning techniques in conjunction with managing allocation of virtual computing resources1136 and/orSDI services1138 tocloud services1140. In some embodiments, virtualinfrastructure management framework1150B may use/consult telemetry data in conjunction with performing such resource allocation. In various embodiments, an application/service management framework1150C may be implemented in order to provide QoS management capabilities forcloud services1140. The embodiments are not limited in this context.
• Referring now toFIGS. 12A and 12B, each of thesleds204,404,504,704,1004 may be embodied as asled1200 in some embodiments. As discussed in more detail below, thesled1200 is configured to be mounted in acorresponding rack102,202,302,402,902 of thedata center100,300,400,1100. In some embodiments, thesled1200 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, in the illustrative embodiment, thesled1200 is embodied as a compute sled that includes various physical resources on a “top side” and a “bottom side” of thesled1200.
• Theillustrative sled1200 includes a chassis-lesscircuit board substrate1202, which supports various electrical components mounted thereon. It should be appreciated that thecircuit board substrate1202 is “chassis-less” in that thesled1200 does not include a housing or enclosure. Rather, thecircuit board substrate1202 is open to the local environment. Thecircuit board substrate1202 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, thecircuit board substrate1202 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form thecircuit board substrate1202 in other embodiments.
• Theillustrative sled1200 includes one or morephysical resources1220 mounted to a “top side”1250 of thecircuit board substrate1202. Although twophysical resources1220 are shown inFIG. 12A, it should be appreciated that thesled1200 may include one, two, or morephysical resources1220 in other embodiments. Thephysical resources1220 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of thesled1200 depending on, for example, the type or intended functionality of thesled1200. For example, as discussed in more detail below, thephysical resources1220 may be embodied as high-power processors in embodiments in which thesled1200 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which thesled1200 is embodied as an accelerator sled, and/or storage controllers in embodiments in which thesled1200 is embodied as a storage sled. Again, depending on the type or intended functionality of thesled1200, thesled1200 may include one or more additional components, such as, but not limited to, a communication circuit having a network interface controller, physical resources in addition to those discussed above, an input/output (I/O) subsystem, a power connector, and one or more data storage drives. In any case, it should be appreciated that each of thephysical resources1220 may include, or otherwise be embodied as, a packaged device that has features capable of interfacing with another device to facilitate interconnection between the devices.
• Referring now toFIG. 12B, in addition to thephysical resources1220 mounted on thetop side1250 of thecircuit board substrate1202, thesled1200 also includes one or morephysical resources1222. The one or morephysical resources1222 are illustratively embodied asmemory devices1222. Eachmemory device1222 illustratively includes a memory package1324 (seeFIG. 13) and a memory mezzanine PCB (i.e., a printed circuit board)1326 on which thememory package1324 is mounted. Thememory mezzanine PCB1326 faces a “bottom side”1252 of thecircuit board substrate1202. As such, thecircuit board substrate1202 is embodied as a double-sided circuit board.
• Because thememory devices1222 include thememory packages1324 mounted on thememory mezzanine PCB1326, thememory devices1222 may be said to include, or otherwise be embodied as, one or more memory mezzanine devices, or simply memory mezzanines. Thememory devices1222 may be embodied as any type of memory device capable of storing data for thephysical resources1220 during operation of thesled1200. For example, in the illustrative embodiments, thememory devices1222 are embodied as dual in-line memory modules (DIMMs), which may support DDR, DDR2, DDR3, DDR4, or DDR5 random access memory (RAM). Of course, in other embodiments, thememory devices1222 may utilize other memory technologies, including volatile and/or non-volatile memory. For example, types of volatile memory may include, but are not limited to, data rate synchronous dynamic RAM (DDR SDRAM), static random-access memory (SRAM), thyristor RAM (T-RAM) or zero-capacitor RAM (Z-RAM). Types of non-volatile memory may include byte or block addressable types of non-volatile memory. The byte or block addressable types of non-volatile memory may include, but are not limited to, 3-dimensional (3-D) cross-point memory, memory that uses chalcogenide phase change material (e.g., chalcogenide glass), multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM), or a combination of any of the above, or other non-volatile memory types. In any case, similar to thephysical resources1220, it should be appreciated that each of thephysical resources1222 may include, or otherwise be embodied as, a packaged device that has features capable of interfacing with another device to facilitate interconnection between the devices.
• As discussed in more detail below, the physical resources1220 (e.g., processors) mounted on thetop side1250 are electrically coupled to thememory packages1324 mounted on thememory mezzanine PCB1326. To do so, in some embodiments, one or more of theconnectors1340,1740,2240 may extend through thecircuit board substrate1202 and interface directly with the one or morephysical resources1220 and thememory mezzanine PCB1326 to facilitate electrical connection between the one or morephysical resources1220 and the one ormore memory devices1222, as discussed below. In other embodiments, as further discussed below, one or more of theconnectors1340,1740,2240 may interface directly with the one ormore memory devices1222 without interfacing directly with the one or morephysical resources1220.
• Referring now toFIG. 13, in some embodiments as discussed above, thesled1200 includes one ormore connectors1340 to facilitate electrical coupling of thephysical resources1220 facing thetop side1250 with thememory devices1222 facing thebottom side1252. In the illustrative embodiment ofFIG. 13, thecircuit board substrate1202 includesmultiple passageways1330 extending therethrough. Eachpassageway1330 includes anopening1332 located on thetop side1250 of thecircuit board substrate1202 and anopening1334 located on thebottom side1252 of thecircuit board substrate1202. Aconnector1340 is inserted into eachpassageway1330 such that anupper contact1442 of the connector1340 (seeFIG. 14) is accessible from thetop side1250 and alower contact1444 of the connector1340 (seeFIG. 14) is accessible from thebottom side1252. In the illustrative embodiment ofFIG. 13, theconnector1340 is configured to interface directly with each of thephysical resources1220 coupled to thetop side1250 and thememory mezzanine PCB1326 of thememory devices1222 coupled to thebottom side1252. That is, theupper contact1442 of eachconnector1340 is configured to mate with a corresponding feature or contact1320 of the physical resource1220 (e.g., a processor), and thelower contact1444 of eachconnector1340 is configured to mate with a corresponding feature or contact1322 of the memory device1222 (i.e., thefeature1322 may be embedded in, included in, or coupled to the memory mezzanine PCB1326). In some embodiments, portions of theconnector1340 may extend outwardly from theopenings1332,1334. Additionally, in the illustrative embodiment ofFIG. 13, theconnector1340 is configured to interface directly with each of thephysical resources1220 and thememory devices1222 coupled to the respective top andbottom sides1250,1252.
• Referring now toFIG. 15, in the illustrative embodiment, theconnector1340 includes, or is otherwise embodied as, a low insertion force (LIF) connector. Theillustrative connector1340 includes amain body1540 having a pair ofcontact sides1542,1544 located at opposite ends of themain body1540. As shown inFIG. 15, theside1542 includes theelectrical contact1442 that is configured to interface or mate with the corresponding feature or contact1320 of thephysical resource1220. Similarly, theside1544 includes theelectrical contact1444 that is configured to interface or mate with the corresponding feature or contact1322 of thememory device1222.
• Although theillustrative connector1340 is embodied as a LIF connector, theconnector1340 may be embodied as another suitable connector in other embodiments, such as a zero insertion force (ZIF) connector, for example. Furthermore, in some embodiments, theelectrical contacts1442,1444 of therespective contact sides1542,1544 of theillustrative connector1340 may be arranged in a pin grid array (PGA) package. In such embodiments, the correspondingfeatures1320 of the one or morephysical resources1220 and the correspondingfeatures1322 of the one ormore memory devices1222 may each be arranged in a PGA package. In other embodiments, theelectrical contacts1442,1444 may be arranged in another suitable package.
• Referring now toFIG. 14, in some embodiments, thesled1200 may include a housing orcasing1436 that housesmultiple connectors1340. Thecasing1436 may include, or otherwise be embodied as, any structure capable of housing and/or protecting theconnectors1340. Thecasing1436 is illustratively formed from one or more polymeric materials. In other embodiments, however, thecasing1436 may have another suitable construction.
• Thecasing1436 is illustratively received by thecircuit board substrate1202 to secure theconnector1340 to thecircuit board substrate1202 between the one or morephysical resources1220 and thememory mezzanine PCB1326 of the one ormore memory devices1222, as shown inFIG. 14. As such, in the illustrative embodiment, thecircuit board substrate1202 includes acutout1446 that is sized to receive thecasing1436. When thecasing1436 is received by thecutout1446, theconnector1340 is embedded in, or otherwise inserted into, thecircuit board substrate1202. In some embodiments, a tool (not shown) may be used to insert thecasing1436 into thecutout1446 to attach theconnector1340 to thecircuit board substrate1202.
• In the illustrative embodiment, thecasing1436 is removable from thecutout1446 to electrically decouple the one or morephysical resources1220 from the one ormore memory devices1222. As such, theconnector1340 includes, or is otherwise embodied as, a separable or removable interconnect between thephysical resources1220 and thememory devices1222. During service of thesled1200, thecasing1436 and theconnector1340 may be removed to facilitate access to thephysical resources1220 and/or thememory devices1222 for repair and/or replacement. In some instances, such as when components (e.g., one or more of the memory devices1222) of thesled1200 are damaged, those components may be repaired and/or replaced with little or no impact to theconnector1340, which may be removed beforehand. Theillustrative connector1340 may therefore mitigate service and/or reliability costs associated with thesled1200 to a greater degree than other configurations.
• Thecasing1436 illustratively includesmultiple passageways1438 with eachpassageway1438 having an opening oraperture1439 located on, or otherwise accessible from, thetop side1250 of thecircuit board substrate1202 and an opening oraperture1440 located on, or otherwise accessible from, thebottom side1252 of thecircuit board substrate1202. Aconnector1340 is inserted into eachpassageway1438 such that theupper contact1442 of theconnector1340 is accessible from thetop side1250 and thelower contact1444 is accessible from thebottom side1252 when thecasing1436 is received by thecutout1446 of thecircuit board substrate1202. That is, when thecasing1436 is received by thecutout1446, theelectrical contacts1442 of thecontact side1542 of eachconnector1340 extend through, or are otherwise accessible through, theopenings1439 from thetop side1250 of thecircuit board substrate1202. In addition, when thecasing1436 is received by thecutout1446, theelectrical contacts1444 of thecontact side1544 of eachconnector1340 extend through, or are otherwise accessible through, theapertures1440 from thebottom side1252 of thecircuit board substrate1202.
• Referring now toFIG. 16, a cross-sectional view of theillustrative sled1200 is shown with thebottom side1252 facing upward and thecasing1436 received by thecutout1446 such that eachconnector1340 is secured between aphysical resource1220 and amemory mezzanine PCB1326 of amemory device1222. In the illustrative embodiment, when thecasing1436 is received by thecutout1446, thephysical resource1220 is electrically coupled to thememory device1222 by theconnectors1340 of thecasing1436. In this way, thecasing1436 forms a connector socket for the physical resource(s)1220 and the memory device(s)1222. In some embodiments, thecasing1436 and associatedconnectors1340 provide the electrical coupling between thephysical resources1220 and thememory devices1222 without provision of heat sink to dissipate heat associated with operation of theconnector1340. Because a heat sink need not be provided to dissipate heat associated with operation of theconnectors1340 in some embodiments, thesled1200 may include fewer components in the illustrative configuration than in other configurations.
• Referring now toFIG. 17, anillustrative method1700 of mounting thephysical resources1220,1222 to thecircuit board substrate1202 is shown. Themethod1700 may be performed by a robot or installer to mount aphysical resource1220 and aphysical resource1222 to thecircuit board substrate1202. Of course, it should be appreciated that themethod1700 may be performed to mount multiplephysical resources1220 and multiplephysical resources1222 to thecircuit board substrate1202. Additionally, it should be appreciated that themethod1700 may be performed in a number of sequences other than the sequence described below.
• Themethod1700 begins withblock1702, in which theconnector1340 is embedded in thecircuit board substrate1202. In some embodiments (e.g., as described above with reference toFIG. 13),block1702 may be performed by inserting theconnector1340 into one of thepassageways1330 formed in thecircuit board substrate1202, as indicated by sub-block1708. In such embodiments, theconnector1340 may be inserted into thepassageway1330 such that theupper contact1442 of theconnector1340 is accessible from thetop side1250 of thecircuit board substrate1202 and thelower contact1444 of theconnector1340 is accessible from thebottom side1252 of thecircuit board substrate1202. In other embodiments (e.g., as described above with reference toFIG. 14),block1702 may be performed by inserting thecasing1436 into thecutout1446 formed in thecircuit board substrate1202, as indicated by sub-block1710. In those embodiments, thecasing1436 may be inserted into thecutout1446 such that theupper contacts1442 of theconnectors1340 housed by thecasing1436 are accessible from thetop side1250 of thecircuit board substrate1202 and thelower contacts1444 of theconnectors1340 housed by thecasing1436 are accessible from thebottom side1252 of thecircuit board substrate1202.
• It should be appreciated that subsequent to embedding theconnector1340 in thecircuit board substrate1202, theconnector1340 may be removed by a robot or installer for servicing, repair, and/or replacement. That is, theconnector1340 may be removed from thepassageway1330 in some embodiments, and thecasing1436 that housesmultiple connectors1340 may be removed from thecutout1446 in other embodiments, for example.
• From theblock1702, themethod1700 subsequently proceeds to theblock1704. In theblock1704, thephysical resource1220 is mounted to thetop side1250 of thecircuit board substrate1202. To do so, thephysical resource1220 may be mounted to thetop side1250 such that acontact1320 of thephysical resource1220 mates with theupper contact1442 of theconnector1340, as indicated by sub-block1712.
• It should be appreciated that subsequent to mounting thephysical resource1220 to thetop side1250 of thecircuit board substrate1202, thephysical resource1220 may be removed by a robot or installer for servicing, repair, and/or replacement. That is, thephysical resource1220 may be removed from thetop side1250 such that thecontact1320 of thephysical resource1220 is de-coupled from thecontact1442 of theconnector1340.
• From theblock1704, themethod1700 subsequently proceeds to theblock1706. In theblock1706, thephysical resource1222 is mounted to thebottom side1252 of thecircuit board substrate1202. To do so, thememory mezzanine PCB1326 of thememory device1222 may be mounted to thebottom side1252 such that acontact1322 of thephysical resource1222 mates with thelower contact1444 of theconnector1340, as indicated by sub-block1714.
• It should be appreciated that subsequent to mounting thephysical resource1222 to thebottom side1252 of thecircuit board substrate1202, thephysical resource1222 may be removed by a robot or installer for servicing, repair, and/or replacement. That is, thephysical resource1222 may be removed from thebottom side1252 such that thecontact1322 of thephysical resource1222 is de-coupled from thecontact1444 of theconnector1340.
• Referring now toFIG. 18, in some embodiments as discussed above, thesled1200 includes one ormore connectors1840 to facilitate electrical coupling of aphysical resource1220 coupled to thetop side1250 with amemory device1222 coupled to thebottom side1252. Of course, in some embodiments, the one ormore connectors1840 may facilitate electrical coupling of one or morephysical resources1220 with one ormore memory devices1222. In the illustrative embodiment ofFIG. 18, theconnectors1840 are grouped together or housed in aconnector socket1842, which is electrically coupled to thebottom side1252 of thecircuit board substrate1202 and coupled to thememory mezzanine PCB1326 of thememory device1222.
• Each of theillustrative connectors1840 may include, or otherwise be embodied as, any device capable of interfacing with thephysical resource1220 and thememory mezzanine PCB1326 of thememory device1222 to electrically couple thephysical resource1220 to thememory device1222. In the illustrative embodiment, theconnector socket1842 does not extend through, and is not embedded in, thecircuit board substrate1202. Rather, as will be apparent from the discussion below, theconnector socket1842 is arranged beneath thebottom side1252 of thecircuit board substrate1202 and electrically coupled (e.g., soldered) thereto.
• In the illustrative embodiment, thecircuit board substrate1202 is arranged between thephysical resource1220 and theconnector socket1842. Moreover, theconnector socket1842 is illustratively arranged between thebottom side1252 of thecircuit board substrate1202 and thememory mezzanine PCB1326 of thememory device1222.
• It should be appreciated that, as shown inFIG. 18, thephysical resource1220 does not directly interface with, and is not affixed or attached to, theconnector socket1842. Rather, thephysical resource1220 interfaces withvias1844 included in thecircuit board substrate1202 along thetop side1250 of thecircuit board substrate1202. Thevias1844 extend from thetop side1250 to thebottom side1252 of thecircuit board substrate1202 to electrically couple thetop side1250 to thebottom side1252. As such, in the illustrative embodiment, thevias1844 include, or are otherwise embodied as, through-hole vias. In other embodiments, however, thevias1844, or a portion thereof, may include, or otherwise be embodied as, other suitable vias, such as blind vias or buried vias, for example.
• Each of thevias1844 is electrically coupled to a corresponding electrical contact1320 (shown in phantom) of thephysical resource1220, such as a processor pin or a contact of another connector socket located on thetop side1250 of thecircuit board substrate1202. Specifically, each of thevias1844 is electrically coupled to a correspondingelectrical contact1320 of the physical resource1220 (or of another connector socket) by asoldering ball1843. Thesoldering balls1843 are illustratively arranged between thephysical resource1220 and thetop side1250 of thecircuit board substrate1202 to affix and electrically connect thephysical resource1220 to thetop side1250.Soldering balls1845 are also illustratively arranged between thebottom side1252 of thecircuit board substrate1202 and theconnector socket1842 to affix and electrically connect theconnector socket1842 to thebottom side1252.
• In the illustrative embodiment ofFIG. 18, thememory device1222 includes acorresponding connector socket1822 that includesconnectors1824. Theconnector socket1822 and theconnectors1824 may be mounted to, embedded in, or otherwise inserted into thememory mezzanine PCB1326. Theconnector socket1822 to configured to interface or mate with theconnector socket1842 to electrically couple thephysical resource1220 to thememory device1222, as further discussed below.
• Referring now toFIG. 20, each of theconnectors1840 of theconnector socket1842 illustratively includes, or is otherwise embodied as, a low insertion force (LIF) connector. In other embodiments, however, each of theconnectors1840 of theconnector socket1842 may include, or otherwise be embodied as, another suitable connector, such as a zero insertion force (ZIF) connector, pins, or the like.
• Theconnectors1824 are illustratively grouped together or housed in theconnector socket1822 of thememory device1222, as shown inFIG. 20. Each of theconnectors1824 of theconnector socket1822 illustratively includes, or is otherwise embodied as, a low insertion force (LIF) connector. In other embodiments, however, each of theconnectors1824 of theconnector socket1822 may include, or otherwise be embodied as, another suitable connector, such as a zero insertion force (ZIF) connector, for example.
• Each of theillustrative connectors1840 of theconnector socket1842 includes acontact side2044 and acontact side2046 arranged opposite thecontact side2044. Thecontact side2044 includes an electrical contact1944 (seeFIG. 19) that is electrically coupled to a corresponding via1844 of thecircuit board substrate1202 through acorresponding soldering ball1845. In some embodiments, eachelectrical contact1944 may be electrically coupled to a corresponding via1844 through acorresponding solder ball1845 and a connector socket substrate1942S. Thecontact side2046 includes an electrical contact1946 (seeFIG. 19) that extends away from thebottom side1252 of thecircuit board substrate1202 and is configured to mate with anelectrical contact1926 of acorresponding connector1824 of theconnector socket1822.
• Each of theillustrative connectors1824 of theconnector socket1822 includes acontact side2026 and acontact side2028 arranged opposite thecontact side2026, as best seen inFIG. 21. Thecontact side2026 includes theelectrical contact1926 and thecontact side2028 includes anelectrical contact1928. Asolder ball1847 may be coupled to thecontact side2028 of each of theconnectors1824.
• Theconnectors1840 of theconnector socket1842 are illustratively supported by aconnector carrier2042 that may be housed by, or otherwise included in, a housing (not shown). The contact sides2044 of theconnectors1840 extend outwardly from atop face2042F of thecontact carrier2042 such that theelectrical contacts1944 are arranged outwardly of thetop face2042F. Thesoldering balls1845 are coupled to theelectrical contacts1944 and arranged outwardly of thetop face2042F.
• Theconnectors1824 of theconnector socket1822 are illustratively supported by aconnector carrier2022 that may be housed by, or otherwise included in, a housing. The contact sides2028 of theconnectors1824 extend outwardly from abottom face2022F of thecontact carrier2022 such that theelectrical contacts1928 are arranged outwardly of thebottom face2022F. Thesoldering balls1847 are coupled to theelectrical contacts1928 and arranged outwardly of thebottom face2022F.
• Referring now toFIG. 19, each of theelectrical contacts1944 of theconnectors1840 of theconnector socket1842 is electrically coupled to a correspondingelectrical contact1320 of thephysical resource1220. In an illustrativede-coupled state1950 of thesled1200, theelectrical contacts1946 of theconnectors1840 of theconnector socket1842 are spaced from theelectrical contacts1926 of theconnectors1824 of theconnector socket1822 in a vertical direction V. Theconnector sockets1842,1822 are therefore electrically de-coupled from one another in thestate1950, as shown inFIGS. 19 and 20. As such, thephysical resource1220 is electrically de-coupled from thememory device1222 in thede-coupled state1950.
• Astandoff1952 is illustratively affixed to thebottom side1252 of thecircuit board substrate1202. In some embodiments, thestandoff1952 may constrain movement of theconnector socket1842 in the vertical direction V relative to theconnector socket1822, or vice versa. In such embodiments, thestandoff1952 may facilitate mating of theelectrical contacts1946 with theelectrical contacts1926. In other embodiments, thestandoff1952 may elevate thecircuit board substrate1202 above a support surface (not shown) to facilitate mounting of one or more components to thecircuit board substrate1202, among other things.
• Referring now toFIGS. 22 and 23, in an illustrative coupledstate2252 of thesled1200, theelectrical contacts1946 of theconnectors1840 of theconnector socket1842 are mated with theelectrical contacts1926 of theconnectors1824 of theconnector socket1822. Accordingly, thephysical resource1220 is electrically coupled to thememory device1222 in the coupledstate2252. Thestandoff1952 contacts thememory device1222 in the coupledstate2252. Contact between thestandoff1952 and thememory device1222 may secure the position of theelectrical contacts1946 in the vertical direction V relative to theelectrical contacts1926 or vice versa, to facilitate mating between theconnector sockets1842,1822. Additionally, when thesled1200 is in the coupledstate2252, theconnector carrier2042 contacts theconnector carrier2022.
• In some embodiments, theelectrical contacts1944,1946 of theconnectors1840 of theconnector socket1842 may be arranged in a pin grid array (PGA) package. Similarly, in some embodiments, theelectrical contacts1926,1928 of theconnectors1824 of theconnector socket1822 may be arranged in a pin grid array (PGA) package. In other embodiments, however, theelectrical contacts1944,1946, as well as theelectrical contacts1926,1928, may be arranged in another suitable package.
• In the illustrative embodiment, thephysical resource1220 may be electrically coupled to thememory device1222 by theconnector socket1842 without provision of heat sink to dissipate heat associated with operation of theconnector socket1842. Because a heat sink need not be provided to dissipate heat associated with operation of theconnector1842, thesled1200 may include fewer components in the illustrative configuration than in other configurations.
• Referring now toFIG. 24,connector sockets2452,2462 may be included in thesled1200 in yet another embodiment thereof. Theconnector sockets2452,2462 may includerespective connectors2454,2464 that may include, or otherwise be embodied as, any devices capable of cooperatively interfacing with thephysical resource1220 and thememory mezzanine PCB1326 of thememory device1222 to electrically couple thephysical resource1220 to thememory device1222. Of course, in some embodiments, theconnectors2454,2464 may cooperatively electrically couple one or morephysical resources1220 to one ormore memory devices1222. In the illustrative embodiment, theconnector sockets2452,2462 do not extend through, and are not embedded in, thecircuit board substrate1202. Rather, as will be apparent from the discussion below, theconnector sockets2452,2462 are arranged beneath thebottom side1252 of thecircuit board substrate1202.
• In the illustrative embodiment, thecircuit board substrate1202 is arranged between thephysical resource1220 and theconnector sockets2452,2462. Moreover, theconnector sockets2452,2462 illustratively extend between thebottom side1252 of thecircuit board substrate1202 and thememory mezzanine PCB1326 of thememory device1222.
• Thephysical resource1220 does not directly interface with, and is not affixed or attached to, theconnector sockets2452,2462, as shown inFIG. 24. Rather, thephysical resource1220 interfaces withvias2444 included in thecircuit board substrate1202 along thetop side1250 of thecircuit board substrate1202. Thevias2444 extend from thetop side1250 to thebottom side1252 of thecircuit board substrate1202 to electrically couple thetop side1250 to thebottom side1252. As such, in the illustrative embodiment, thevias2444 include, or are otherwise embodied as, through hole vias. In other embodiments, however, thevias2444 may include, or otherwise be embodied as, other suitable vias, such as blind vias or buried vias, for example.
• Each of thevias2444 is electrically coupled to a corresponding electrical contact1320 (shown in phantom) of thephysical resource1220. Specifically, each of thevias2444 is electrically coupled to a correspondingelectrical contact1320 of thephysical resource1220 by asoldering ball2443. Thesoldering balls2443 are illustratively arranged between thephysical resource1220 and thetop side1250 of thecircuit board substrate1202 to affix thephysical resource1220 to thetop side1250.Soldering balls2445 are also illustratively arranged between thebottom side1252 of thecircuit board substrate1202 and theconnector sockets2452,2462 to affix theconnector sockets2452,2462 to thebottom side1252. Theconnector sockets2452,2462 are affixed to thebottom side1252 of thecircuit board substrate1202 adjacent to one another.
• Theillustrative connector socket2452 may include, or otherwise be embodied as, any device or physical interface capable of interfacing with thephysical resource1220 and theconnector socket2462 to electrically couple thephysical resource1220 to theconnector socket2462. Theillustrative connector socket2462 may include, or otherwise be embodied as, any device or physical interface capable of interfacing with theconnector socket2452 and thememory mezzanine PCB1326 of thememory device1222 to electrically couple theconnector socket2452 to thememory device1222.
• Referring now toFIG. 25, eachconnector2454 of theillustrative connector socket2452 includes an electrical contact2556 (shown in phantom) and an electrical contact2558 (shown in phantom) arranged opposite theelectrical contact2556. In some embodiments, eachelectrical contact2556 may be a pin or solder pad electrically coupled to acorresponding soldering ball2445 and via2444. Eachelectrical contact2558 may extend away from eachelectrical contact2556 and thebottom side1252 of thecircuit board substrate1202. When thememory device1222 is received by theconnector socket2462, eachelectrical contact2558 may be configured to mate or interface with a corresponding contact2622 (seeFIG. 26) of thememory device1222 that may be mounted to thememory mezzanine PCB1326.
• In the illustrative embodiment, theelectrical contacts2556,2558 of theconnectors2454 of theconnector socket2452 are arranged in a land grid array (LGA) package. As such, theillustrative connector socket2452 may include, or otherwise be embodied as, an LGA connector socket. In other embodiments, theelectrical contacts2556,2558 may be arranged in another suitable package, and theconnector socket2452 may include, or otherwise be embodied as, another suitable connector socket.
• In the illustrative embodiment, theconnector socket2462 is sized to receive thememory mezzanine PCB1326 of thememory device1222, as shown inFIG. 25. Eachconnector2464 of theconnector socket2462 includes an electrical contact2566 (shown in phantom) that is electrically coupled to a corresponding via2444 andsoldering ball2445.
• In the illustrative embodiment, theconnector socket2462 defines agap2702G (seeFIG. 27) that is sized to receive thememory mezzanine PCB1326 of thememory device1222. Theconnector socket2462 includes a pair ofcylindrical pivot posts2562P, only one of which is shown inFIG. 25. The illustrative memory device1222 (e.g., the memory mezzanine PCB1326) includes a pair offlanges2522F each having anotch2522N formed therein (only one of theflanges2522F is shown) that is sized to receive one of thepivot posts2562P. When thenotches2522N receive thepivot posts2562P, the memory device1222 (e.g., the memory mezzanine PCB1326) may be pivoted on the pivot posts2562P about an axis2562A that extends into the page toward thebottom side1252 of thecircuit board substrate1202, as indicated byarrow2524.
• Referring now toFIGS. 26 and 27, thememory device1222 is pivoted on the pivot posts2562P about the axis2562A toward thebottom side1252 of thecircuit board substrate1202 until thememory mezzanine PCB1326 of thememory device1222 is fully received by thegap2702G. In the illustrative embodiment, thegap2702G is defined betweenelectrical contacts2668,2670 of theconnector socket2462 that are vertically spaced from one another, as best seen inFIG. 27. Theelectrical contacts2668 and2670 provide theillustrative features2624 of thememory interface2624. One of theelectrical contacts2566,2668,2670 of theconnector socket2462 may be configured to mate or interface with theelectrical contact2558 of theconnector socket2452.
• When thememory device1222 is fully received by thegap2702G, thememory mezzanine PCB1326 of thememory device1222 contacts each of theelectrical contacts2668,2670 of theconnector socket2462, as shown inFIG. 26. Specifically, thememory mezzanine PCB1326 contacts respective cantileveredcontact arms2668A,2670A of theelectrical contacts2668,2670. Thecontact arms2668A,2670A may cooperate to hold thememory device1222 in place when thememory mezzanine PCB1326 is fully received by thegap2702G.
• In the illustrative embodiment, theconnector socket2462 includes, or is otherwise embodied as, a small outline dual in-line memory module (SODIMM) connector. In other embodiments, however, theconnector socket2462 may include, or otherwise be embodied as, another suitable connector.
EXAMPLES
• Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
• Example 1 includes a sled for operation in a rack of a data center, the sled comprising a circuit board substrate having a top side and a bottom side opposite the top side; a physical resource coupled to the top side of the circuit board substrate; a memory device coupled to the bottom side of the circuit board substrate; and a connector to electrically couple the physical resource to the memory device, wherein the connector extends through the circuit board substrate to the top and bottom sides thereof, and wherein the connector comprises (i) a first contact accessible from the top side of the circuit board substrate and electrically mated with a corresponding contact of the physical resource and (ii) a second contact, opposite the first contact, accessible from the bottom side of the circuit board substrate and electrically mated with a corresponding contact of the memory device.
• Example 2 includes the subject matter of Example 1, and wherein the connector comprises a low insertion force connector.
• Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the circuit board substrate comprises a passageway extending through the circuit board substrate and having a first opening located on the top side and a second opening, opposite the first opening, located on the bottom side, wherein the connector is inserted into the passageway of the circuit board substrate.
• Example 4 includes the subject matter of any of Examples 1-3, and wherein the first contact of the connector extends outwardly from the first opening and the second contact of the connector extends outwardly from the second opening.
• Example 5 includes the subject matter of any of Examples 1-4, and wherein the connector is coupled directly to the circuit board substrate.
• Example 6 includes the subject matter of any of Examples 1-5, and further including a casing that houses a plurality of connectors that includes the connector.
• Example 7 includes the subject matter of any of Examples 1-6, and wherein the casing is formed from a polymeric material.
• Example 8 includes the subject matter of any of Examples 1-7, and wherein the circuit board substrate includes a cutout sized to receive the casing to secure the casing and connector to the circuit board substrate between the physical resource and the memory device.
• Example 9 includes the subject matter of any of Examples 1-8, and wherein the casing is secured to the circuit board substrate to electrically couple the one or more physical resources to the one or more memory devices by the connector without provision of a heat sink to dissipate heat associated with operation of the connector.
• Example 10 includes the subject matter of any of Examples 1-9, and wherein the casing is removable from the cutout to electrically decouple the one or more physical resources from the one or more memory devices.
• Example 11 includes the subject matter of any of Examples 1-10, and wherein the casing comprises a plurality of passageways and each of the plurality of connectors is inserted into a corresponding passageway.
• Example 12 includes the subject matter of any of Examples 1-11, and wherein each passageway includes a first opening located on the top side of the circuit board substrate and a second opening, opposite the first opening, located on the bottom side of the circuit board substrate, and wherein each first contact of each connector extends from the first opening of the corresponding passageway and each second contact of each connector extends from the second opening of the corresponding passageway.
• Example 13 includes the subject matter of any of Examples 1-12, and wherein the physical resource comprises a processor.
• Example 14 includes a sled for operation in a rack of a data center, the sled comprising a circuit board substrate having a top side and a bottom side opposite the top side, wherein the circuit board substrate comprises a plurality of vias extending therethrough; a physical resource coupled to the top side of the circuit board substrate and comprising a plurality of contacts, wherein each contact of the plurality of contacts of the physical resource is electrically coupled to a corresponding via of the circuit board substrate; a memory mezzanine comprising a plurality of contacts; and a connector socket coupled to the bottom side of the circuit board substrate, wherein the connector socket comprises a plurality of connectors and each connector comprises (i) a first contact electrically coupled to a corresponding via of the circuit board substrate and (ii) a second contact, opposite the first contact, extending away from the bottom side of the circuit board substrate, wherein each second contact is to mate with a corresponding contact of the memory mezzanine.
• Example 15 includes the subject matter of Example 14, and wherein the connector socket is arranged between the bottom side of the circuit board substrate and the memory mezzanine.
• Example 16 includes the subject matter of any of Examples 14 and 15, and wherein the physical resource is electrically coupled to the memory mezzanine by the connector socket without provision of a heat sink to dissipate heat associated with operation of the connector socket.
• Example 17 includes the subject matter of any of Examples 14-16, and wherein each connector of the connector socket comprises a low insertion force connector.
• Example 18 includes the subject matter of any of Examples 14-17, and wherein the memory mezzanine comprises connector socket having a plurality of connectors, wherein each connector of the connector socket of the memory mezzanine comprises a corresponding contact of the plurality of contacts of the memory mezzanine, wherein the connector socket of the memory mezzanine is to mate with the connector socket coupled to the bottom side of the circuit board substrate.
• Example 19 includes the subject matter of any of Examples 14-18, and wherein each of the connectors of the connector socket of the memory mezzanine comprises a low insertion force connector.
• Example 20 includes the subject matter of any of Examples 14-19, and wherein the connector socket comprises a land grid array socket.
• Example 21 includes the subject matter of any of Examples 14-20, and wherein the connector socket comprises a first connector socket and wherein the sled further comprises a second connector socket coupled to the bottom side of the circuit board substrate adjacent to the first connector socket, wherein the second connector socket is to receive a circuit board substrate of the memory mezzanine and comprises a plurality of connectors and each connector of the second connector socket includes a first contact electrically coupled to a corresponding via of the circuit board substrate.
• Example 22 includes the subject matter of any of Examples 14-21, and wherein the second connector socket comprises second electrical contacts and third electrical contacts vertically spaced from the second electrical contacts to define a gap therebetween.
• Example 23 includes the subject matter of any of Examples 14-22, and wherein each of the second electrical contacts and the third electrical contacts comprise a cantilevered contact arm.
• Example 24 includes the subject matter of any of Examples 14-23, and wherein the second connector socket comprises a small outline dual in-line memory module connector.
• Example 25 includes the subject matter of any of Examples 14-24, and wherein the physical resource comprises a processor.
• Example 26 includes a sled for operation in a rack of a data center, the sled comprising a circuit board substrate having a top side and a bottom side opposite the top side; and a connector to electrically couple a first physical resource located on the top side of the circuit board substrate with a second physical resource located on the bottom side of the circuit board substrate, wherein the connector comprises (i) a first contact accessible from the top side of the circuit board substrate to electrically mate with a corresponding contact of the first physical resource and (ii) a second contact, opposite the first contact, accessible from the bottom side of the circuit board substrate to electrically mate with a corresponding contact of the second physical resource.
• Example 27 includes the subject matter of Example 26, and wherein the connector comprises a low insertion force connector.
• Example 28 includes the subject matter of any of Examples 26 and 27, and wherein the circuit board substrate comprises a passageway extending through the circuit board substrate and having a first opening located on the top side and a second opening, opposite the first opening, located on the bottom side, wherein the connector is inserted into the passageway of the circuit board substrate.
• Example 29 includes the subject matter of any of Examples 26-28, and further including a casing that houses a plurality of connectors that includes the connector.
• Example 30 includes the subject matter of any of Examples 26-29, and wherein the circuit board substrate includes a cutout sized to receive the casing to secure the casing and connector to the circuit board substrate between the first physical resource and the second physical resource.
• Example 31 includes the subject matter of any of Examples 26-30, and wherein the casing is removable from the cutout to electrically decouple the first physical resource from the second physical resource.
• Example 32 includes the subject matter of any of Examples 26-31, and wherein the casing comprises a plurality of passageways and each of the plurality of connectors is inserted into a corresponding passageway.
• Example 33 includes the subject matter of any of Examples 26-32, and wherein the first physical resource comprises a processor and the second physical resource comprises a memory device.
• Example 34 includes a sled for operation in a rack of a data center, the sled comprising a circuit board substrate having a top side and a bottom side opposite the top side, wherein the circuit board substrate comprises a plurality of vias extending therethrough, wherein each via is to electrically couple a first physical resource positioned on the top side of the circuit board substrate to one or more other physical resources positioned on the bottom side of the circuit board substrate; a connector socket coupled to the bottom side of the circuit board substrate, wherein the connector socket comprises a plurality of connectors and each connector comprises (i) a first contact electrically coupled to a corresponding via of the circuit board substrate and (ii) a second contact, opposite the first contact, extending away from the bottom side of the circuit board substrate, wherein each second contact is to mate with a corresponding contact of a second physical resource to electrically couple the second physical resource to the first physical resource.
• Example 35 includes the subject matter of Example 34, and wherein the connector socket is arranged between the bottom side of the circuit board substrate and the second physical resource.
• Example 36 includes the subject matter of any of Examples 34 and 35, and wherein each connector of the connector socket comprises a low insertion force connector.
• Example 37 includes the subject matter of any of Examples 34-36, and wherein the connector socket is to mate with a corresponding connector socket of the second physical resource.
• Example 38 includes the subject matter of any of Examples 34-37, and wherein the connector socket comprises a land grid array socket.
• Example 39 includes the subject matter of any of Examples 34-38, and wherein the connector socket comprises a first connector socket and wherein the sled further comprises a second connector socket coupled to the bottom side of the circuit board substrate adjacent to the first connector socket, wherein the second connector socket is to receive a circuit board substrate of the second physical resource and comprises a plurality of connectors and each connector of the second connector socket includes a first contact electrically coupled to a corresponding via of the circuit board substrate.
• Example 40 includes the subject matter of any of Examples 34-39, and wherein the second connector socket comprises second electrical contacts and third electrical contacts vertically spaced from the second electrical contacts to define a gap therebetween.
• Example 41 includes the subject matter of any of Examples 34-40, and wherein each of the second electrical contacts and the third electrical contacts comprise a cantilevered contact arm.
• Example 42 includes the subject matter of any of Examples 34-41, and wherein the second connector socket comprises a small outline dual in-line memory module connector.
• Example 43 includes the subject matter of any of Examples 34-42, and wherein the first physical resource comprises a processor and the second physical resource comprises a memory device.
• Example 44 includes a method of mounting a plurality of physical resources to a circuit board substrate, the method comprising embedding a connector in the circuit board substrate, mounting a first physical resource of the plurality of physical resources to a top side of the circuit board substrate, and mounting a second physical resource of the plurality of physical resources to a bottom side of the circuit board substrate opposite the top side of the circuit board substrate.
• Example 45 includes the subject matter of Example 44, wherein embedding the connector in the circuit board substrate comprises inserting the connector into a passageway of the circuit board substrate.
• Example 46 includes the subject matter of any of Examples 44 and 45, wherein inserting the connector into the passageway comprises inserting the connector into the passageway such that a first contact of the connector is accessible from the top side of the circuit board substrate and a second contact of the connector, spaced from the first contact, is accessible from the bottom side of the circuit board substrate.
• Example 47 includes the subject matter of any of Examples 44-46, wherein embedding the connector in the circuit board substrate comprises inserting a casing that houses multiple connectors, including the connector, into a cutout of the circuit board substrate.
• Example 48 includes the subject matter of any of Examples 44-47, wherein inserting the casing into the cutout comprises inserting the casing into the cutout such that a first contact of the connector is accessible from the top side of the circuit board substrate and a second contact of the connector, spaced from the first contact, is accessible from the bottom side of the circuit board substrate.
• Example 49 includes the subject matter of any of Examples 44-48, wherein mounting the first physical resource to the top side comprises mounting the first physical resource to the top side such that an electrical contact of the first physical resource mates with a corresponding feature of the connector.
• Example 50 includes the subject matter of any of Examples 44-49, wherein the first physical resource is a processor.
• Example 51 includes the subject matter of any of Examples 44-50, wherein mounting the second physical resource to the bottom side comprises mounting a memory mezzanine printed circuit board of the second physical resource to the bottom side such that an electrical contact of the second physical resource mates with a corresponding feature of the connector.
• Example 52 includes the subject matter of any of Examples 44-51, wherein the second physical resource is a memory device.
• Example 53 includes a physical resource comprising a processor and a connector socket, wherein the connector socket includes a first connector, and wherein the first connector includes a first electrical contact mated with the processor and a second electrical contact, spaced from the first electrical contact, to mate with a corresponding feature of a second connector separate from the first connector.
• Example 54 includes the subject matter of Example 53, wherein the connector socket includes a plurality of first connectors.
• Example 55 includes the subject matter of any of Examples 53 and 54, further comprising a casing that houses the processor and the connector socket.
• Example 56 includes the subject matter of any of Examples 53-55, wherein the physical resource is mountable to a circuit board substrate.
• Example 57 includes a physical resource comprising a memory package and a memory mezzanine printed circuit board, wherein the memory mezzanine printed circuit board includes a connector socket having a first connector, and wherein the first connector includes a first electrical contact mated with the memory package and a second electrical contact, spaced from the first electrical contact, to mate with a corresponding feature of a second connector separate from the first connector.
• Example 58 includes the subject matter of Example 57, wherein the connector socket includes a plurality of first connectors.
• Example 59 includes the subject matter of any of Examples 57 and 58, further comprising a casing that houses the memory package and the memory mezzanine printed circuit board.
• Example 60 includes the subject matter of any of Examples 57-59, wherein the physical resource is mountable to a circuit board substrate.

Claims (30)

1. A sled comprising:

a circuit board substrate having a top side and a bottom side opposite the top side;

a physical resource coupled to the top side of the circuit board substrate;

a memory device coupled to the bottom side of the circuit board substrate; and

a connector to electrically couple the physical resource to the memory device, wherein the connector extends through the circuit board substrate to the top and bottom sides thereof, and wherein the connector comprises (i) a first contact accessible from the top side of the circuit board substrate and mated with a corresponding contact of the physical resource and (ii) a second contact, opposite the first contact, accessible from the bottom side of the circuit board substrate and electrically mated with a corresponding contact of the memory device.

2. The sled ofclaim 1, wherein the circuit board substrate comprises a passageway extending through the circuit board substrate and having a first opening located on the top side and a second opening, opposite the first opening, located on the bottom side,

wherein the connector is located in the passageway of the circuit board substrate, the first contact of the connector extends outwardly from the first opening, and the second contact of the connector extends outwardly from the second opening.

3. The sled ofclaim 1, wherein the connector is coupled directly to the circuit board substrate, wherein the connector comprises a low insertion force connector.

4. The sled ofclaim 1, further comprising a casing that houses a plurality of connectors that includes the connector.

5. The sled ofclaim 4, wherein the circuit board substrate includes a cutout sized to receive the casing to secure the casing and connector to the circuit board substrate between the physical resource and the memory device,

wherein the casing is removable from the cutout to electrically decouple the one or more physical resources from the one or more memory devices.

6. The sled ofclaim 5, wherein the casing is secured to the circuit board substrate to electrically couple the one or more physical resources to the one or more memory devices by the connector without provision of a heat sink to dissipate heat associated with operation of the connector.

7. The sled ofclaim 4, wherein the casing comprises a plurality of passageways and each of the plurality of connectors is located in a corresponding passageway.

8. The sled ofclaim 7, wherein each passageway includes a first opening located on the top side of the circuit board substrate and a second opening, opposite the first opening, located on the bottom side of the circuit board substrate, and

wherein each first contact of each connector extends from the first opening of the corresponding passageway and each second contact of each connector extends from the second opening of the corresponding passageway.

9. A sled comprising:

a circuit board substrate having a top side and a bottom side opposite the top side, wherein the circuit board substrate comprises a plurality of vias extending therethrough;

a physical resource coupled to the top side of the circuit board substrate and comprising a plurality of contacts, wherein each contact of the plurality of contacts of the physical resource is electrically coupled to a corresponding via of the circuit board substrate;

a memory mezzanine comprising a plurality of contacts; and

a connector socket coupled to the bottom side of the circuit board substrate, wherein the connector socket comprises a plurality of connectors and each connector comprises (i) a first contact electrically coupled to a corresponding via of the circuit board substrate and (ii) a second contact, opposite the first contact, extending away from the bottom side of the circuit board substrate, wherein each second contact is to mate with a corresponding contact of the memory mezzanine.

10. The sled ofclaim 9, wherein the connector socket is arranged between the bottom side of the circuit board substrate and the memory mezzanine.

11. The sled ofclaim 9, wherein the memory mezzanine comprises connector socket having a plurality of connectors, wherein each connector of the connector socket of the memory mezzanine comprises a corresponding contact of the plurality of contacts of the memory mezzanine, wherein the connector socket of the memory mezzanine is to mate with the connector socket coupled to the bottom side of the circuit board substrate, wherein each of the connectors of the connector socket of the memory mezzanine comprises a low insertion force connector, wherein the connector socket comprises a land grid array socket.

12. The sled ofclaim 9, wherein the connector socket comprises a first connector socket and wherein the sled further comprises a second connector socket coupled to the bottom side of the circuit board substrate adjacent to the first connector socket, wherein the second connector socket is to receive a circuit board substrate of the memory mezzanine and comprises a plurality of connectors and each connector of the second connector socket includes a first contact electrically coupled to a corresponding via of the circuit board substrate.

13. The sled ofclaim 12, wherein the second connector socket comprises second electrical contacts and third electrical contacts vertically spaced from the second electrical contacts to define a gap therebetween, wherein each of the second electrical contacts and the third electrical contacts comprise a cantilevered contact arm.

14. The sled ofclaim 12, wherein the second connector socket comprises a small outline dual in-line memory module connector.

15. A sled comprising:

a circuit board substrate having a top side and a bottom side opposite the top side; and

a connector to electrically couple a first physical resource located on the top side of the circuit board substrate with a second physical resource located on the bottom side of the circuit board substrate, wherein the connector comprises (i) a first contact accessible from the top side of the circuit board substrate to electrically mate with a corresponding contact of the first physical resource and (ii) a second contact, opposite the first contact, accessible from the bottom side of the circuit board substrate to electrically mate with a corresponding contact of the second physical resource.

16. The sled ofclaim 15, wherein the circuit board substrate comprises a passageway extending through the circuit board substrate and having a first opening located on the top side and a second opening, opposite the first opening, located on the bottom side,

wherein the connector is located in the passageway of the circuit board substrate.

17. The sled ofclaim 15, further comprising a casing that houses a plurality of connectors that includes the connector.

18. The sled ofclaim 17, wherein the circuit board substrate includes a cutout sized to receive the casing to secure the casing and connector to the circuit board substrate between the first physical resource and the second physical resource,

wherein the casing is removable from the cutout to electrically decouple the first physical resource from the second physical resource.

19. The sled ofclaim 17, wherein the casing comprises a plurality of passageways and each of the plurality of connectors is located in a corresponding passageway.

20. The sled ofclaim 15, wherein the first physical resource comprises a processor and the second physical resource comprises a memory device.

21. A sled comprising:

a circuit board substrate having a top side and a bottom side opposite the top side, wherein the circuit board substrate comprises a plurality of vias extending therethrough, wherein each via is to electrically couple a first physical resource positioned on the top side of the circuit board substrate to one or more other physical resources positioned on the bottom side of the circuit board substrate;

a connector socket coupled to the bottom side of the circuit board substrate, wherein the connector socket comprises a plurality of connectors and each connector comprises (i) a first contact electrically coupled to a corresponding via of the circuit board substrate and (ii) a second contact, opposite the first contact, extending away from the bottom side of the circuit board substrate, wherein each second contact is to mate with a corresponding contact of a second physical resource to electrically couple the second physical resource to the first physical resource.

22. The sled ofclaim 21, wherein the connector socket is arranged between the bottom side of the circuit board substrate and the second physical resource.

23. The sled ofclaim 21, wherein the connector socket is to mate with a corresponding connector socket of the second physical resource, wherein the connector socket comprises a land grid array socket.

24. The sled ofclaim 21, wherein the connector socket comprises a first connector socket and wherein the sled further comprises a second connector socket coupled to the bottom side of the circuit board substrate adjacent to the first connector socket, wherein the second connector socket is to receive a circuit board substrate of the second physical resource and comprises a plurality of connectors and each connector of the second connector socket includes a first contact electrically coupled to a corresponding via of the circuit board substrate, wherein the second connector socket comprises a small outline dual in-line memory module connector.

25. The sled ofclaim 24, wherein the second connector socket comprises second electrical contacts and third electrical contacts vertically spaced from the second electrical contacts to define a gap therebetween,

wherein each of the second electrical contacts and the third electrical contacts comprise a cantilevered contact arm.

26. A method of mounting a plurality of physical resources to a circuit board substrate, the method comprising:

embedding a connector in the circuit board substrate;

mounting a first physical resource of the plurality of physical resources to a top side of the circuit board substrate; and

mounting a second physical resource of the plurality of physical resources to a bottom side of the circuit board substrate opposite the top side of the circuit board substrate.

27. The method ofclaim 26, wherein embedding the connector in the circuit board substrate comprises inserting the connector into the passageway such that a first contact of the connector is accessible from the top side of the circuit board substrate and a second contact of the connector, spaced from the first contact, is accessible from the bottom side of the circuit board substrate.

28. The method ofclaim 26, wherein embedding the connector in the circuit board substrate comprises inserting a casing that houses multiple connectors, including the connector, into a cutout of the circuit board substrate.

29. The method ofclaim 28, wherein inserting the casing into the cutout comprises inserting the casing into the cutout such that a first contact of the connector is accessible from the top side of the circuit board substrate and a second contact of the connector, spaced from the first contact, is accessible from the bottom side of the circuit board substrate.

30. The method ofclaim 26, wherein mounting the second physical resource to the bottom side comprises mounting a memory mezzanine printed circuit board of the second physical resource to the bottom side such that an electrical contact of the second physical resource mates with a corresponding feature of the connector.

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