US20180182458A1 - Semiconductor Device Having Electrically Floating Body Transistor, Semiconductor Device Having Both Volatile and Non-Volatile Functionality and Method of Operating - Google Patents

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Description

CROSS-REFERENCE
• This application is a continuation application of co-pending U.S. application Ser. No. 15/436,641, filed on Feb. 17, 2017, now U.S. Pat. No. 9,747,983, which is a continuation of U.S. application Ser. No. 15/237,441, filed on Aug. 15, 2016, now U.S. Pat. No. 9,614,080, which is a continuation application of U.S. application Ser. No. 14/834,695, filed on Aug. 25, 2015, now U.S. Pat. No. 9,455,262, which is a divisional application of U.S. application Ser. No. 13/577,282, having a filing or 371(c) date of Oct. 5, 2012, now U.S. Pat. No. 9,153,309, which claims the benefit under 35 USC 371(c) of PCT Application No. PCT/US2011/023947, which claims the benefit of U.S. Provisional Application No. 61/302,129, filed Feb. 7, 2010, and U.S. Provisional Application No. 61/425,820, filed Dec. 22, 2010, which applications and patents are each hereby incorporated herein, in their entireties, by reference thereto and to which applications we claim priority under 35 U.S.C. Sections 120, 371 and 119, respectively.
• This application also hereby incorporates, in its entirety by reference thereto, application Ser. No. 12/797,320, filed on Jun. 9, 2010, titled “Semiconductor Memory Having Electrically Floating Body Transistor”, application Ser. No. 12/797,334 filed on Jun. 9, 2010, titled “Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor”, application Ser. No. 12/897,528, titled “Compact Semiconductor Device Having Reduced Number of Contacts, Methods of Operating and Method of Making”, application Ser. No. 12/897,516, titled “Semiconductor Memory Device Having An Electrically Floating Body Transistor”, application Ser. No. 12/897,538, titled “Semiconductor Memory Device Having An Electrically Floating Body Transistor”.
FIELD OF THE INVENTION
• The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device having an electrically floating body transistor and a semiconductor memory device having both volatile and non-volatile functionality.
BACKGROUND OF THE INVENTION
• Semiconductor memory devices are used extensively to store data. Static and Dynamic Random Access Memory (SRAM and DRAM, respectively) are widely used in many applications. SRAM typically consists of six transistors and hence has a large cell size. However, unlike DRAM, it does not require periodic refresh operations to maintain its memory state. Conventional DRAM cells consist of a one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell feature is being scaled, difficulties arise due to the necessity of maintaining the capacitance value.
• DRAM based on the electrically floating body effect has been proposed (see for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. However, unlike SRAM, such DRAM memory cell still requires refresh operation, since the stored charge leaks over time.
• A conventional 1T/1C DRAM refresh operation involves first reading the state of the memory cell, followed by re-writing the memory cell with the same data. Thus this read-then-write refresh requires two operations: read and write. The memory cell cannot be accessed while being refreshed. An “automatic refresh” method”, which does not require first reading the memory cell state, has been described in Fazan et al., U.S. Pat. No. 7,170,807. However, such operation still interrupts access to the memory cells being refreshed.
• In addition, the charge in a floating body DRAM memory cell decreases over repeated read operations. This reduction in floating body charge is due to charge pumping, where the floating body charge is attracted to the surface and trapped at the interface (see for example “Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs”, S. Okhonin, et al., pp. 279-281, IEEE Electron Device Letters, vol. 23, no. 5, May 2002).
• Thus there is a continuing need for semiconductor memory devices and methods of operating such devices such that the states of the memory cells of the semiconductor memory device are maintained without interrupting the memory cell access.
• There is also a need for semiconductor memory devices and methods of operating the same such that the states of the memory cells are maintained upon repeated read operations.
• Non-volatile memory devices, such as flash erasable programmable read only memory (Flash EPROM) devices, retain stored data even in the absence of power supplied thereto. Unfortunately, non-volatile memory devices typically operate more slowly than volatile memory devices.
• Flash memory device typically employs a floating gate polysilicon as the non-volatile data storage. This introduces additional process steps from the standard complementary metal-oxide-semiconductor (CMOS) process. US 2010/0172184 “Asymmetric Single Poly NMOS Non-volatile Memory Cell” to Roizin et al. (“Roizin”), describes a method of forming a single poly non-volatile memory device. Similar to many non-volatile memory devices, it operates more slowly than volatile memory devices. In addition, non-volatile memory devices can only perform limited number of cycles, often referred to as endurance cycle limitation.
• Accordingly, it would be desirable to provide a universal type memory device that includes the advantages of both volatile and non-volatile memory devices, i.e., fast operation on par with volatile memories, while having the ability to retain stored data when power is discontinued to the memory device. It would further be desirable to provide such a universal type memory device having a size that is not prohibitively larger than comparable volatile or non-volatile devices and which has comparable storage capacity to the same.
• The present invention meets the above needs and more as described in detail below.
SUMMARY OF THE INVENTION
• In one aspect of the present invention, a method of maintaining a state of a memory cell without interrupting access to the memory cell is provided, including: applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
• In at least one embodiment, the applying comprises applying the back bias to a terminal of the cell that is not used for address selection of the cell.
• In at least one embodiment, the back bias is applied as a constant positive voltage bias.
• In at least one embodiment, the back bias is applied as a periodic pulse of positive voltage.
• In at least one embodiment, a maximum potential that can be stored in the floating body is increased by the application of back bias to the cell, resulting in a relatively larger memory window.
• In at least one embodiment, the application of back bias performs a holding operation on the cell, and the method further comprises simultaneously performing a read operation on the cell at the same time that the holding operation is being performed.
• In at least one embodiment, the cell is a multi-level cell, wherein the floating body is configured to indicate more than one state by storing multi-bits, and the method further includes monitoring cell current of the cell to determine a state of the cell.
• In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; the method including: performing a holding operation on at least all of the cells not aligned in a row or column of a selected cell; and accessing the selected cell and performing a read or write operation on the selected cell while performing the hold operation on the at least all of the cells not aligned in a row or column of the selected cell.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells and the performing a read or write operation comprises performing a read operation on the selected cell.
• In at least one embodiment, the holding operation is performed by applying back bias to a terminal not used for memory address selection.
• In at least one embodiment, the terminal is segmented to allow independent control of the applied back bias to a selected portion of the memory array.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell, and the performing a read or write operation comprises performing a write “0” operation on the selected cell, wherein a write “0” operation is also performed on all of the cells sharing a common source line terminal with the selected cell during the performing a write“0” operation.
• In at least one embodiment, an individual bit write “0” operation is performed, wherein the performing a holding operation comprises performing the holding operation on all of the cells except for the selected cell, while the performing a read or write operation comprises performing a write “0” operation on the selected cell.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a write “1” operation on the selected cell.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, using an alternating write and verify algorithm.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, wherein the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current through the selected cell; and removing the ramped voltage applied once the change in cell current reaches a predetermined value.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, wherein the multi-level write operation includes: ramping a current applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in voltage across a bit line and a source line of the selected cell; and removing the ramped current applied once the change in cell voltage reaches a predetermined value.
• In at least one embodiment, the multi-level write operation permits bit-level selection of a bit portion of memory of the selected cell.
• In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a single-level or multi-level write operation on the selected cell, wherein the single-level and each level of the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current toward an addressable terminal of the selected cell; and verifying a state of the write operation using a reference memory cell.
• In at least one embodiment, the method further includes configuring a state of the reference memory cell using a write-then-verify operation, prior to performing the write operation.
• In at least one embodiment, configuring a state of the reference memory cell comprises configuring the state upon power up of the memory array.
• In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; and wherein the method includes: refreshing a state of at least one of the memory cells; and accessing at least one other of the memory cells, wherein access of the at least one other of the memory cells in not interrupted by the refreshing, and wherein the refreshing is performed without alternating read and write operations.
• In at least one embodiment, at least one of the memory cells is a multi-level memory cell.
• In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; and wherein the method includes: accessing a selected memory cell from the memory cells; and performing a simultaneous write and verify operation on the selected memory cell without performing an alternating write and read operation.
• In at least one embodiment, the selected memory cell is a multi-level memory cell.
• In at least one embodiment, a verification portion of the write and verify operation is performed by sensing a current change in the column direction of the array in a column that the selected cell is connected to.
• In at least one embodiment, a verification portion of the write and verify operation is performed by sensing a current change in the row direction of the array in a row that the selected cell is connected to.
• In at least one embodiment, a write portion of the write and verify operation employs use of a drain or gate voltage ramp.
• In at least one embodiment, a write portion of the write and verify operation employs use of a drain current ramp.
• In one aspect of the present invention, an integrated circuit is provided that includes a link or string of semiconductor memory cells, wherein each memory cell comprises a floating body region for storing data; and the link or string comprises at least one contact configured to electrically connect the memory cells to at least one control line, wherein the number of contacts is the same as or less than the number of the memory cells.
• In at least one embodiment, the number of contacts is less than the number of memory cells.
• In at least one embodiment, the semiconductor memory cells are connected in series and form the string.
• In at least one embodiment, the semiconductor memory cells are connected in parallel and form the link.
• In at least one embodiment, the integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.
• In at least one embodiment, the integrated circuit is fabricated on a bulk silicon substrate.
• In at least one embodiment, the number of contacts is two, and the number of semiconductor memory cells is greater than two.
• In at least one embodiment, the memory cells further comprise first and second conductive regions interfacing with the floating body region.
• In at least one embodiment, the first and second conductive regions are shared by adjacent ones of the memory cells for each the memory cell having the adjacent memory cells.
• In at least one embodiment, each memory cell further comprises first, second, and third conductive regions interfacing with the floating body region.
• In at least one embodiment, each memory cell further comprises a gate insulated from the floating body region.
• In at least one embodiment, at least one of the memory cells is a contactless memory cell.
• In at least one embodiment, a majority of the memory cells are contactless memory cells.
• In at least one embodiment, the memory cells store multi-bit data.
• In another aspect of the present invention, an integrated circuit is provided that includes a plurality of contactless semiconductor memory cells, each semiconductor memory cell including: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate from the floating body region.
• In at least one embodiment, the contactless memory cells are connected in series.
• In at least one embodiment, the contactless memory cells are connected in parallel.
• In at least one embodiment, the integrated circuit comprises at least one semiconductor memory cell having at least one contact, a total number of the contacts being less than a total number of memory cells that includes a total number of the memory cells having at least one contact and a total number of the contactless memory cells.
• In another aspect of the present invention, an integrated circuit is provided that includes: a plurality of semiconductor memory cells connected in series, each semiconductor memory cell comprising: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate and the floating body region.
• In at least one embodiment, at least one of the semiconductor memory cells is a contactless semiconductor memory cell.
• In at least one embodiment, the at least one contactless semiconductor memory cell comprises a third conductive region interfacing with the floating body region.
• In another aspect of the present invention, an integrated circuit is provided that includes a plurality of semiconductor memory cells connected in parallel, each semiconductor memory cell comprising: a floating body region for storing data; a conductive region interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate from the floating substrate region; wherein at least one of the semiconductor memory cells is a contactless semiconductor memory cell.
• In at least one embodiment, a majority of the semiconductor memory cells are contactless semiconductor memory cells.
• In at least one embodiment, the integrated circuit comprises a number of contacts, the number being less than or equal to a number of the memory cells.
• In at least one embodiment, the memory cells each further comprise a second conductive region interfacing with the floating body region.
• In at least one embodiment, the memory cells each further comprise second and third conductive regions interfacing with the floating body region.
• In another aspect of the present invention, an integrated circuit is provided that includes a plurality of contactless semiconductor memory cells connected in parallel, each semiconductor memory cell comprising: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating region; and an insulating region insulating the gate and the floating body region.
• In another aspect of the present invention, an integrated circuit is provided that includes: a memory string or link comprising a set of contactless semiconductor memory cells; and a first contact contacting a first additional semiconductor memory cell; wherein the contactless semiconductor memory cells are accessible via the first contact.
• In at least one embodiment, the integrated circuit further includes a second contact contacting a second additional semiconductor memory cell; wherein the contactless semiconductor memory cells are accessible via the second contact.
• In at least one embodiment, the contactless semiconductor memory cells and the additional semiconductor memory cell are connected in series.
• In at least one embodiment, the memory string or link comprises a first memory string or link and the set comprises a first set, the integrated circuit further comprising: a second memory string or link comprising a second set of contactless semiconductor memory cells; and a second contact contacting a second additional semiconductor memory cell; wherein the second set of contactless semiconductor memory cells are accessible via the second contact.
• In at least one embodiment, the memory string or link comprises a first memory string and the set comprises a first set, the integrated circuit further comprising: a second memory string comprising a second set of contactless semiconductor memory cells; a third contact contacting a third additional semiconductor memory cell; and a fourth contact contacting a fourth additional semiconductor memory cell; wherein the second set of contactless semiconductor memory cells are accessible via the third and fourth contacts; wherein the first set of contactless semiconductor memory cells, the first additional semiconductor memory cell and the second additional semiconductor memory cell are connected in series, and wherein the second set of contactless semiconductor memory cells, the third additional semiconductor memory cell and the fourth additional semiconductor memory cell are connected in series in the second string.
• In at least one embodiment, the integrated circuit further includes a first terminal connected to the first contact and the third contact; a second terminal connected to the second contact; and a third terminal connected to the fourth contact.
• In at least one embodiment, the semiconductor memory cells comprise substantially planar semiconductor memory cells.
• In at least one embodiment, the semiconductor memory cells comprise fin-type, three-dimensional semiconductor memory cells.
• In at least one embodiment, the first set of contactless semiconductor memory cells are aligned side-by side of the second set of contactless semiconductor memory cells; the first string comprises a first set of insulation portions that insulate adjacent memory cells in the first string, and a second set of insulation portions that insulate the memory cells in the first string from adjacent memory cells in the second string; and the second string comprises a third set of insulation portions that insulate adjacent memory cells in the second string, and a fourth set of insulation portions that insulate the memory cells in the second string from adjacent memory cells in the first string.
• In at least one embodiment, the first and second contacts are located at first and second ends of the memory string.
• In at least one embodiment, each semiconductor memory cell comprises: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating region; an insulating region insulating the gate from the floating body region; and a word line terminal electrically connected to the gate.
• In another aspect of the present invention an integrated circuit includes a plurality of floating body memory cells which are linked either in series or in parallel. The connections between the memory cells are made to reduce the number of contacts for the overall circuit. Because several memory cells are connected either in series or in parallel, a compact memory array is provided.
• These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the integrated circuits, strings, links memory cells and methods as more fully described below.
• In one aspect of the present invention, a semiconductor memory cell includes: a substrate having a first conductivity type; a substrate terminal connected to the substrate; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; one of a bit line terminal and a source line terminal connected to the first region; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; the other of the bit line terminal and the source line terminal connected to the second region; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, wherein the first and second storage locations are each configured to receive transfer of data stored by the volatile memory; and a control gate positioned above the trapping layer.
• In at least one embodiment, the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type; and a buried well terminal connected to the buried layer.
• In at least one embodiment, the floating body is completely bounded by the top surface, the first and second regions and the buried layer.
• In at least one embodiment, the first conductivity type is “p” type and the second conductivity type is “n” type.
• In at least one embodiment, the semiconductor memory cell further comprises insulating layers bounding the side surfaces of the substrate.
• In at least one embodiment, the cell functions as a multi-level cell.
• In at least one embodiment, at least one of the first and second storage locations is configured so that more than one bit of data can be stored in the at least one of the first and second storage locations, respectively.
• In at least one embodiment, the floating body is configured so that more than one bit of data can be stored therein.
• In another aspect of the present invention, a method of operating a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, and a trapping layer having first and second storage locations for storing data as non-volatile memory is provided, including: operating the memory cell as a volatile memory cell when power is supplied to the memory cell; upon discontinuation of power to the memory cell, resetting non-volatile memory of the memory cell to a predetermined state; and performing a shadowing operation wherein content of the volatile memory cell is loaded into the non-volatile memory.
• In at least one embodiment, the method further includes shutting down the memory cell device, wherein the memory cell device, upon the shutting down, operates as a flash, erasable, programmable read-only memory.
• In at least one embodiment, the method further includes restoring power to the memory cell, wherein upon the restoring power, carrying out a restore process wherein content of the non-volatile memory is loaded into the volatile memory.
• In another aspect of the present invention, a method of operating a memory cell device includes: providing a memory cell device having a plurality of memory cells, each the memory cell having a floating body for storing data as volatile memory and a trapping layer for storing data as non-volatile memory; and operating at least one of the memory cells as a volatile memory cell, independently of the non-volatile memory of the respective memory cell.
• In at least one embodiment, the operating comprises applying a voltage to a region at a surface of the cell adjacent to a non-volatile storage location of the non-volatile memory.
• In at least one embodiment, the applying a voltage comprises applying a positive voltage and the floating body of the cell has a p-type conductivity type.
• In at least one embodiment, the operating comprises operating the volatile memory to perform at least one of a reading operation, a writing operation, and or a holding operation.
• In at least one embodiment, the method further includes performing a reset operation to initialize a state of the non-volatile memory.
• In at least one embodiment, the method further includes performing a shadowing operation to load a content of the volatile memory into the non-volatile memory.
• In another aspect of the present invention, a semiconductor memory cell is provided that includes a floating body region for storing data as volatile memory; and a trapping layer for storing data as non-volatile memory; wherein the data stored as volatile memory and the data stored as non-volatile memory are independent of one another, as the floating body region can be operated independently of the trapping layer and the trapping layer can be operated independently of the floating body region.
• In at least one embodiment, the floating body region has a first conductivity type and is bounded by a buried layer have a second conductivity type different from the first conductivity type.
• In at least one embodiment, the first conductivity type is “p” type and the second conductivity type is “n” type.
• In at least one embodiment, the floating body region is bounded by a buried insulator.
• In at least one embodiment, the floating body region is formed in a substrate, the cell further comprises insulating layers bounding side surfaces of the substrate.
• In at least one embodiment, the cell functions as a multi-level cell.
• In at least one embodiment, the trapping layer comprises first and second storage locations, the first and second storage locations each being configured to store data independently of the other, as non-volatile memory.
• In one aspect of the present invention, a single polysilicon floating gate semiconductor memory cell is provided that includes: a substrate; a floating body region exposed at a surface of the substrate and configured to store volatile memory; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating the floating body region from the single polysilicon floating gate; and first and second regions exposed at the surface at locations other than where the floating body region is exposed; wherein the floating gate is configured to receive transfer of data stored by the volatile memory.
• In at least one embodiment, the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
• In at least one embodiment, one of the first and second regions at the surface has a higher coupling to the floating gate relative to coupling of the other of the first and second regions to the floating gate.
• In at least one embodiment, the cell includes a buried layer at a bottom portion of the substrate, the buried layer having a conductivity type that is different from a conductivity type of the floating body region.
• In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried layer.
• In at least one embodiment, insulating layers bound side surfaces of the substrate.
• In at least one embodiment, a buried insulator layer is buried in a bottom portion of the substrate
• In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried insulator layer.
• In at least one embodiment, the floating gate overlies an area of the floating body exposed at the surface, and a gap is located between the area overlaid and one of the first and second regions.
• In at least one embodiment, a select gate is positioned adjacent to the single polysilicon floating gate.
• In at least one embodiment, the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
• In at least one embodiment, the select gate overlaps the floating gate.
• In another aspect of the present invention, a semiconductor memory cell is provided that includes: a substrate; a floating body region configured to store volatile memory; a stacked gate nonvolatile memory comprising a floating gate adjacent the substrate and a control gate adjacent the floating gate such that the floating gate is positioned between the control gate and the substrate; and a select gate positioned adjacent the substrate and the floating gate.
• In at least one embodiment, the floating body is exposed at a surface of the substrate, and the cell further includes: first and second regions each exposed at the surface at locations other than where the floating body region is exposed; wherein the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
• In at least one embodiment, one of the first and second regions at the surface has a higher coupling to the floating gate relative to coupling of the other of the first and second regions to the floating gate.
• In at least one embodiment, a buried layer is buried in a bottom portion of the substrate, the buried layer having a conductivity type different from a conductivity type of the floating body region.
• In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried layer.
• In at least one embodiment, insulating layers bound side surfaces of the substrate.
• In at least one embodiment, a buried insulator layer is buried in a bottom portion of the substrate.
• In at least one embodiment, the floating body is bounded by the surface, the first and second regions and the buried insulator layer.
• In another aspect of the present invention, a single polysilicon floating gate semiconductor memory cell is provided that includes: a substrate; a floating body region for storing data as volatile memory, and a single polysilicon floating gate for storing data as non-volatile memory; wherein the floating body region stores the data stored as volatile memory independently of the data stored as non-volatile memory, and the single polysilicon floating gate stores the data stored as volatile memory independently of the data stored as volatile memory.
• In at least one embodiment, the floating body region has a first conductivity type and is bounded by a buried layer having a second conductivity type different from the first conductivity type.
• In at least one embodiment, the floating body region is bounded a buried insulator.
• In at least one embodiment, the first conductivity type is “p” type and the second conductivity type is “n” type.
• In at least one embodiment, insulating layers bound side surfaces of the substrate.
• In another aspect of the present invention, a method of operating a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, and a floating gate for storing data as non-volatile memory is provided, including: operating the memory cell as a volatile memory cell when power is supplied to the memory cell; upon discontinuation of power to the memory cell, resetting non-volatile memory of the memory cell to a predetermined state; and performing a shadowing operation wherein content of the volatile memory cell is loaded into the non-volatile memory.
• In at least one embodiment, the method further includes shutting down the memory cell device, wherein the memory cell device, upon the shutting down, operates as a flash, erasable, programmable read-only memory.
• In at least one embodiment, the method further includes restoring power to the memory cell, wherein upon the restoring power, carrying out a restore process wherein content of the non-volatile memory is loaded into the volatile memory.
• In another aspect of the present invention, a method of operating a memory cell device includes: providing a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, a floating gate for storing data as non-volatile memory, and a control gate; and operating the memory cell as a volatile memory cell independent of the non-volatile memory data.
• In at least one embodiment, the method further includes applying a voltage to the control gate to invert a channel region underneath the floating gate, regardless of charge stored in the floating gate.
• In at least one embodiment, the method further includes applying a positive voltage to a region of the substrate coupled to the floating gate, and wherein the floating body has a “p” type conductivity type.
• In at least one embodiment, the operation the memory cell as a volatile memory comprises performing at least one of reading, writing, and holding operations.
• In at least one embodiment, the method further includes performing a reset operation to initialize a state of the non-volatile memory.
• In at least one embodiment, the method further includes performing a shadowing operation to load content of the volatile memory into the non-volatile memory.
• These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the methods, devices and arrays as more fully described below.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic illustration of a memory cell according to an embodiment of the present invention.
• FIG. 2 schematically illustrates multiple cells joined in an array to make a memory device according to an embodiment of the present invention.
• FIG. 3 schematically illustrates n-p-n bipolar devices that are inherently formed in a memory cell according to an embodiment of the present invention.
• FIG. 4A illustrates segmenting of substrate terminals in an array according to an embodiment of the present invention.
• FIG. 4B schematically illustrates multiplexers used to determine the biases applied to segmented substrate terminals according to an embodiment of the present invention.
• FIG. 4C schematically illustrates use of a voltage generator circuitries to input positive bias to the multiplexers according to an embodiment of the present invention.
• FIG. 5 graphically illustrates that the maximum charge stored in a floating body of a memory cell can be increased by applying a positive bias to the substrate terminal according to an embodiment of the present invention.
• FIG. 6A graphs floating body potential as a function of floating body current and substrate potential according to an embodiment of the present invention.
• FIG. 6B graphs floating body potential as a function of floating body current and buried well potential according to an embodiment of the present invention.
• FIG. 7 shows bias conditions for a selected memory cell and unselected memory cells in a memory array according to an embodiment of the present invention.
• FIG. 8A illustrates an unselected memory cell sharing the same row as a selected memory cell during a read operation of the selected memory cell according to an embodiment of the present invention.
• FIG. 8B illustrates the states of the n-p-n bipolar devices of the unselected memory cell ofFIG. 8A during the read operation of the selected memory cell according to the embodiment ofFIG. 8A.
• FIG. 8C illustrates an unselected memory cell sharing the same column as a selected memory cell during a read operation of the selected memory cell according to the embodiment ofFIG. 8A.
• FIG. 8D illustrates the states of the n-p-n bipolar devices of the unselected memory cell ofFIG. 8C during the read operation of the selected memory cell according to the embodiment ofFIG. 8A.
• FIG. 8E illustrates an unselected memory cell that shares neither the same row nor the same column as a selected memory cell during a read operation of the selected memory cell according to the embodiment ofFIG. 8A.
• FIG. 8F illustrates the states of the n-p-n bipolar devices of the unselected memory cell ofFIG. 8E during the read operation of the selected memory cell according to the embodiment ofFIG. 8A.
• FIG. 9 is a schematic illustration of a write “0” operation to a memory cell according to an embodiment of the present invention.
• FIG. 10 shows an example of bias conditions for a selected memory cell and unselected memory cells during a write “0” operation in a memory array according to an embodiment of the present invention.
• FIG. 11A illustrates an example of bias conditions on unselected memory cells during a write “0” operation according to an embodiment of the present invention.
• FIG. 11B shows an equivalent circuit diagram for the cell ofFIG. 11A illustrating the intrinsic n-p-n bipolar devices.
• FIG. 12 shows bias conditions for selected and unselected memory cells of a memory array during a write “0” operation according to an embodiment of the present invention.
• FIG. 13A illustrates an example of bias conditions on a selected memory cell during a write “0” operation according to an embodiment of the present invention.
• FIG. 13B shows an equivalent circuit diagram for the cell ofFIG. 13A illustrating the intrinsic n-p-n bipolar devices.
• FIG. 13C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment ofFIG. 13A.
• FIG. 13D shows an equivalent circuit diagram for the cell ofFIG. 13C illustrating the intrinsic n-p-n bipolar devices.
• FIG. 13E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment ofFIG. 13A.
• FIG. 13F shows an equivalent circuit diagram for the cell ofFIG. 13E illustrating the intrinsic n-p-n bipolar devices.
• FIG. 13G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment ofFIG. 13A.
• FIG. 13H shows an equivalent circuit diagram for the cell ofFIG. 13G illustrating the intrinsic n-p-n bipolar devices.
• FIG. 14 illustrates an example of bias conditions of a selected memory cell and unselected memory cells in an array under a band-to-band tunneling write “1” operation of the selected cell according to an embodiment of the present invention.
• FIG. 15A illustrates an example of bias conditions on the selected memory cell ofFIG. 14.
• FIG. 15B shows an equivalent circuit diagram for the cell ofFIG. 15A illustrating the intrinsic n-p-n bipolar devices.
• FIG. 15C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write “1” operation of the selected memory cell, according to the embodiment ofFIG. 15A.
• FIG. 15D shows an equivalent circuit diagram for the cell ofFIG. 15C illustrating the intrinsic n-p-n bipolar devices.
• FIG. 15E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write “1” operation of the selected memory cell, according to the embodiment ofFIG. 15A.
• FIG. 15F shows an equivalent circuit diagram for the cell ofFIG. 15E illustrating the intrinsic n-p-n bipolar devices.
• FIG. 15G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write “1” operation of the selected memory cell, according to the embodiment ofFIG. 15A.
• FIG. 15H shows an equivalent circuit diagram for the cell ofFIG. 15G illustrating the intrinsic n-p-n bipolar devices.
• FIG. 16A shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to an embodiment of the present invention.
• FIG. 16B shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to another embodiment of the present invention.
• FIG. 16C shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to another embodiment of the present invention.
• FIG. 17 graphically illustrates that the potential of the floating body of a memory cell will increase over time as bias conditions are applied that will result in hole injection to the floating body, according to an embodiment of the present invention.
• FIG. 18A schematically illustrates reference generator circuitry and read circuitry connected to a memory array according to an embodiment of the present invention.
• FIG. 18B shows a schematic of a voltage sensing circuitry configured to measure the voltage across the source line and the bit line terminals of a memory cell according to an embodiment of the present invention.
• FIG. 19 illustrates bias conditions on a selected cell and unselected cells of an array during a read operation on the selected cell according to an embodiment of the present invention.
• FIG. 20 illustrates bias conditions on a selected cell and unselected cells of an array during a write “0” operation on the selected cell according to an embodiment of the present invention.
• FIG. 21 illustrates bias conditions on a selected cell and unselected cells of an array during a write “0” operation on the selected cell according to another embodiment of the present invention.
• FIG. 22 illustrates bias conditions on a selected cell and unselected cells of an array during a band-to-band tunneling write “1” operation on the selected cell according to another embodiment of the present invention.
• FIG. 23A is a schematic illustration of a memory cell according to another embodiment of the present invention.
• FIG. 23B is a schematic illustration of a memory cell according to another embodiment of the present invention showing contacts to the buried well and substrate regions.
• FIG. 24 schematically illustrates an array of memory cells of the type illustrated inFIGS. 23A-23B.
• FIG. 25 schematically illustrates n-p-n bipolar devices inherent in the cell ofFIGS. 23A-23B.
• FIG. 26 illustrates an example of bias conditions on an array during performance of a read operation on a selected cell according to an embodiment of the present invention.
• FIG. 27 illustrates bias conditions on a selected cell and unselected cells of an array during a write “0” operation on the selected cell according to an embodiment of the present invention.
• FIG. 28A illustrates an example of bias conditions on the selected memory cell ofFIG. 27.
• FIG. 28B shows an equivalent circuit diagram for the cell ofFIG. 28A illustrating the intrinsic n-p-n bipolar devices.
• FIG. 28C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment ofFIG. 27.
• FIG. 28D shows an equivalent circuit diagram for the cell ofFIG. 28C illustrating the intrinsic n-p-n bipolar devices.
• FIG. 28E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment ofFIG. 27.
• FIG. 28F shows an equivalent circuit diagram for the cell ofFIG. 28E illustrating the intrinsic n-p-n bipolar devices.
• FIG. 28G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write “0” operation of the selected memory cell, according to the embodiment ofFIG. 27.
• FIG. 28H shows an equivalent circuit diagram for the cell ofFIG. 28G illustrating the intrinsic n-p-n bipolar devices.
• FIG. 29 illustrates an example of bias conditions applied to a selected memory cell under a band-to-band tunneling write “1” operation according to an embodiment of the present invention.
• FIG. 30 is a schematic illustration of a memory cell according to another embodiment of the present invention.
• FIG. 31 is a schematic illustration of a memory cell according to another embodiment of the present invention.
• FIG. 32 is a schematic illustration of a memory cell according to another embodiment of the present invention.
• FIG. 33 is a schematic illustration of a memory cell according to another embodiment of the present invention.
• FIG. 34 is a top view, schematic illustration of a memory cell ofFIGS. 30 and 32.
• FIGS. 35A through 35E illustrate an array and details of a first exemplary memory cell according to the present invention.
• FIGS. 36A through 36U illustrate a method of manufacturing a memory cell according to the present invention.
• FIGS. 37A through 37C illustrate a method of maintaining the state of a memory cell according to the present invention.
• FIGS. 38A through 38D illustrate methods of maintaining the state of the data stored in an array of memory cells according to the present invention.
• FIG. 39 is a graph of the floating body voltage in a memory cell according to the present invention.
• FIG. 40 is a graph of current-voltage curves of a memory cell according to the present invention.
• FIG. 41 illustrates a read operation performed on an array of memory cells according to the present invention.
• FIGS. 42A through 42H illustrate the operation of four representative memory cells of the array ofFIG. 41.
• FIGS. 43A and 43B illustrates the operation of selected memory cells according to the present invention during a first type of write logic-0 operation.
• FIG. 44 illustrates an array of memory cells according to the present invention during the first type of write logic-0 operation ofFIG. 43.
• FIGS. 45A-45B illustrate the operation of unselected memory cells according to the present invention of the array ofFIG. 46 during a second type of write logic-0 operation.
• FIG. 46 illustrates an array of memory cells according to the present invention during a second type of write logic-0 operation.
• FIG. 47 illustrates an array of memory cells according to the present invention during a third type of write logic-0 operation.
• FIGS. 48A through 48H illustrate the operation of four representative memory cells of the array ofFIG. 47 during the third type of logic operation.
• FIG. 49 illustrates an array of memory cells according to the present invention during a first type of write logic-1 operation.
• FIGS. 50A through 50H illustrate the operation of four representative memory cells of the array ofFIG. 15 during the first type of write logic-1 operation.
• FIG. 51 illustrates an array of memory cells according to the present invention during a second type of write logic-1 operation.
• FIGS. 52A through 52H illustrate the operation of four representative memory cells of the array ofFIG. 51 during the second type of write logic-1 operation.
• FIGS. 53A through 53E illustrate a second exemplary memory cell according to the present invention.
• FIGS. 54A through 54H illustrate performing operations on an array of the memory cell ofFIGS. 53A through 53E.
• FIGS. 55A through 55F illustrate multilevel operations on a memory cell according to the present invention.
• FIG. 56 illustrates an alternate memory cell according to the present invention.
• FIG. 57 illustrates a top view of the memory cell ofFIG. 56.
• FIG. 58A illustrates another alternate memory cell according to the present invention.
• FIG. 58B illustrates an array of the memory cell ofFIG. 58A.
• FIGS. 59A through 59F illustrate a third exemplary memory cell according to the present invention.
• FIGS. 60A through 60F illustrate an alternate physical embodiment of the memory cell ofFIGS. 59A through 59F.
• FIG. 61A illustrates an array of the memory cell of the embodiments ofFIGS. 59A through 59F andFIGS. 60A through 60F.
• FIG. 61B illustrates a circuit schematic of an individual cell of the embodiments ofFIGS. 59A through 59F andFIGS. 60A through 60F.
• FIG. 62 illustrates a hold operation performed on the array ofFIG. 61A.
• FIG. 63 illustrates a read operation performed on the array ofFIG. 61A.
• FIGS. 64A through 64P illustrate the operation of eight representative memory cells of the array ofFIG. 63.
• FIG. 65 illustrates a two row write logic-0 operation on the memory array ofFIG. 61A.
• FIGS. 66A and 66B illustrate the operation of unselected memory cells inFIG. 65.
• FIG. 67 illustrates a single column write logic-0 operation on the memory array ofFIG. 61A.
• FIG. 68 illustrates a single memory cell write logic-0 operation on the memory array ofFIG. 61A.
• FIGS. 69A through 69P illustrate the operation of eight representative memory cells of the array ofFIG. 68.
• FIG. 70 illustrates a single memory cell write logic-1 operation on the memory array ofFIG. 61A.
• FIGS. 71A through 71P illustrate the operation of eight representative memory cells of the array ofFIG. 70.
• FIG. 72 illustrates an alternate single memory cell write logic-1 operation on the memory array ofFIG. 61A.
• FIGS. 73A through 73B illustrates a possible write disturb condition resulting from the single memory cell write logic-1 operation ofFIG. 72.
• FIG. 74 illustrates another alternate single memory cell write logic-1 operation on the memory array ofFIG. 61A.
• FIGS. 75A and 75B illustrates additional alternate methods of manufacturing a memory cell according to the present invention.
• FIGS. 76A through 76AA illustrate a method of manufacturing the memory cell ofFIG. 75B.
• FIGS. 77A through 77F illustrate a fourth exemplary memory cell according to the present invention.
• FIGS. 78A and 78B illustrate different holding operations on a memory array of the memory cells ofFIGS. 77A through 77F.
• FIGS. 79 and 80A through 80H illustrate a read operation on a memory array of the memory cells ofFIGS. 77A through 77F.
• FIG. 81 illustrates a single memory cell write logic-0 operation on the memory array ofFIG. 77F.
• FIGS. 82A through 82B illustrate the operation of the unselected memory cells of the array ofFIG. 81.
• FIG. 83 illustrates a single memory cell write logic-0 operation on the memory array ofFIG. 77F.
• FIGS. 84A through 84H illustrate the operation of four representative memory cells of the array ofFIG. 83.
• FIGS. 85A through 85F illustrate a fifth exemplary memory cell according to the present invention.
• FIG. 86 illustrates the hold operation when using memory cells of the present invention in SCR mode.
• FIG. 87 illustrates the single cell read operation when using memory cells of the present invention in SCR mode.
• FIG. 88 illustrates the single cell write logic-1 operation when using memory cells of the present invention in SCR mode.
• FIG. 89 illustrates the single cell write logic-0 operation when using memory cells of the present invention in SCR mode.
• FIGS. 90A through 90C illustrate standard MOSFET transistors of the prior art.
• FIG. 91 schematically illustrates a memory cell in accordance with an embodiment of the present invention.
• FIG. 92A schematically illustrates a memory array having a plurality of memory cells according to an embodiment of the present invention.
• FIG. 92B schematically illustrates a memory array having a plurality of memory cells, with read circuitry connected thereto that can be used to determine data states, according to an embodiment of the present invention
• FIG. 93 shows exemplary bias conditions for reading a selected memory cell, as wells as bias conditions of unselected memory cells in a memory array according to an embodiment of the present invention.
• FIG. 94A shows exemplary bias conditions for reading a selected memory cell according to an embodiment of the present invention.
• FIGS. 94B-94D illustrate bias conditions on unselected memory cells during the exemplary read operation described with regard toFIG. 93, according to an embodiment of the present invention.
• FIG. 95 schematically illustrates and example of a write “0” operation of a cell according to an embodiment of the present invention.
• FIGS. 96A-96B show an example of bias conditions of selected and unselected memory cells during a write “0” operation according to an embodiment of the present invention.
• FIG. 97 illustrates bias conditions for cells in an array during a write “0” operation in which all memory cells sharing the same BL terminal are written into state “0” according to an embodiment of the present invention.
• FIG. 98 illustrates bias conditions for selected and unselected memory cells of a memory array for a write “0” operation according to an alternative embodiment of the present invention.
• FIG. 99A illustrates bias conditions of the selected memory cell under the write “0” operation described with regard to the example ofFIG. 98.
• FIGS. 99B-99D illustrate examples of bias conditions on the unselected memory cells during write “0” operations described with regard to the example shown inFIG. 98.
• FIGS. 100 and 101A illustrate an example of the bias conditions of a selected memory cell under a write “1” operation using band-to-band tunneling according to an embodiment of the present invention.
• FIGS. 101B-101D show examples of bias conditions of the unselected memory cells during write “1” operations of the type described with regard toFIG. 100.
• FIG. 102 schematically illustrates bias conditions on memory cells during a write “1” operation using impact ionization according to and embodiment of the present invention.
• FIGS. 103A-103D and 104 illustrate an example of the bias conditions of the selectedmemory cell750 under a write “1” operation using an impact ionization write “1” operation according to an embodiment of the present invention.
• FIG. 105 illustrates a prior art arrangement in which adjacent memory cells share common contacts.
• FIG. 106A shows a cross-sectional schematic illustration of a memory string according to an embodiment of the present invention.
• FIG. 106B shows a top view schematic illustration of a memory cell array including two strings of memory cells between the SL terminal and BL terminal according to an embodiment of the present invention.
• FIG. 107 shows an equivalent circuit representation of the memory array ofFIG. 106B.
• FIGS. 108 and 109A-109B illustrate bias conditions during a read operation according to an embodiment of the present invention.
• FIGS. 110-111 illustrate bias conditions during a write “0” operation according to an embodiment of the present invention.
• FIGS. 112A-112B illustrate bias conditions during a write “0” operation that allows for individual bit writing according to an embodiment of the present invention.
• FIGS. 113A-113B illustrate bias conditions during a band-to-band tunneling write “1” operation according to an embodiment of the present invention.
• FIGS. 114A-114B illustrate bias conditions during an impact ionization write “1” operation according to an embodiment of the present invention.
• FIG. 115A schematically illustrates a fin-type, three-dimensional memory cell according to an embodiment of the present invention.
• FIG. 115B schematically illustrates a fin-type, three-dimensional memory cell according to another embodiment of the present invention.
• FIG. 116A shows an energy band diagram of the intrinsic n-p-n bipolar device of the cell ofFIG. 23 when the floating body region is positively charged and a positive bias voltage is applied to the buried well region according to an embodiment of the present invention.
• FIG. 116B shows an energy band diagram of the intrinsic n-p-n bipolar device of the cell ofFIG. 23 when the floatingbody region24 is neutrally charged and a bias voltage is applied to the buried well region according to an embodiment of the present invention.
• FIG. 117 schematically illustrates bias conditions on memory cells during a read operation of a selected memory cell according to an embodiment of the present invention.
• FIG. 118 schematically illustrates bias conditions on memory cells during a write “0” operation according to an embodiment of the present invention.
• FIG. 119 schematically illustrates bias conditions on memory cells during a write “0” operation according to another embodiment of the present invention.
• FIG. 120A schematically illustrates an example of bias conditions of a selected memory cell under a band-to-band tunneling write “1” operation according to an embodiment of the present invention.
• FIG. 120B shows bias conditions of selected andunselected memory cells150 during an impact ionization write “1” operation according to an embodiment of the present invention.
• FIG. 121A shows a cross-sectional schematic illustration of a memory string according to an embodiment of the present invention.
• FIG. 121B shows a top view schematic illustration of a memory cell array including two strings of memory cells between the SL terminal and BL terminal according to an embodiment of the present invention.
• FIG. 121C shows an equivalent circuit representation of a memory array that includes strings shown inFIG. 121B as well as additional strings, in accordance with an embodiment of the present invention.
• FIG. 122 shows bias conditions on a memory string during a read operation according to an embodiment of the present invention.
• FIG. 123A illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a read operation according to an embodiment of the present invention.
• FIG. 123B illustrates the array ofFIG. 123A with read circuitry attached to measure or sense the current flow from the BL terminal to the SL terminal in regard to the selected cell, according to an embodiment of the present invention.
• FIG. 124 shows bias conditions on a memory string during a write “0” operation according to an embodiment of the present invention.
• FIG. 125 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a write “0” operation according to an embodiment of the present invention.
• FIG. 126 shows bias conditions on a memory string during a write “0” operation that allows for individual bit writing according to an embodiment of the present invention.
• FIG. 127 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a write “0” operation that allows for individual bit writing according to an embodiment of the present invention.
• FIG. 128 shows bias conditions on a memory string during a band-to-band tunneling write “1” operation according to an embodiment of the present invention.
• FIG. 129 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a band-to-band tunneling write “1” operation according to an embodiment of the present invention.
• FIG. 130A shows bias conditions on a memory string during an impact ionization write “1” operation according to an embodiment of the present invention.
• FIG. 130B illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during an impact ionization write “1” operation according to an embodiment of the present invention.
• FIG. 131A schematically illustrates a top view of two strings of memory cells in a memory array according to an embodiment of the present invention.
• FIG. 131B is a cross-sectional view of a string from the array illustrated inFIG. 131A.
• FIGS. 132A-132U illustrates various stages during manufacture of a memory array according to an embodiment of the present invention.
• FIG. 133 schematically illustrates a link of memory cells connected in parallel according to an embodiment of the present invention.
• FIG. 134A schematically illustrates a top view of a memory cell of the link ofFIG. 133.
• FIG. 134B is a sectional view of the memory cell ofFIG. 48A taken along line I-I′ ofFIG. 134A.
• FIG. 134C is a sectional view of the memory cell ofFIG. 48A taken along line II-II′ ofFIG. 134A.
• FIG. 135 shows an equivalent circuit representation of a memory array that includes the link ofFIG. 133, according to an embodiment of the present invention.
• FIG. 136 is a schematic illustration of an equivalent circuit of a memory array of links in which a read operation is being performed on a selected memory cell of one of the links according to an embodiment of the present invention.
• FIG. 137 schematically illustrates the selected memory cell of the array represented inFIG. 135 and bias conditions thereon during the read operation.
• FIG. 138 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed on a selected link of the array according to an embodiment of the present invention.
• FIG. 139 schematically illustrates a memory cell of the link represented inFIG. 138 that is having a write “0” operation performed thereon according to an embodiment of the present invention.
• FIG. 140 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed according to an alternative embodiment of the present invention.
• FIG. 141 schematically illustrates a memory cell of the array represented inFIG. 140 that is having a write “0” operation performed thereon according to the alternative embodiment described with regard toFIG. 140.
• FIG. 142 is a schematic illustration of an equivalent circuit of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.
• FIG. 143 schematically illustrates a selected memory cell of the array ofFIG. 142 on which the write “1” operation is being performed, and the bias conditions thereon.
• FIG. 144 schematically illustrates a link according to another embodiment of the present invention.
• FIG. 145A schematically illustrates a top view of a memory cell of the memory array ofFIG. 144.
• FIG. 145B is a sectional view of the memory cell ofFIG. 145A taken along line I-I′ ofFIG. 145A.
• FIG. 145C is a sectional view of the memory cell ofFIG. 145A taken along line II-II′ ofFIG. 145A.
• FIG. 146 shows an equivalent circuit representation of a memory array of links, including the link ofFIG. 144.
• FIG. 147 is a schematic illustration of an equivalent circuit of a memory array in which a read operation is being performed on a selected memory cell according to an embodiment of the present invention.
• FIG. 148 schematically illustrates the selected memory cell of the array represented inFIG. 147 and bias conditions thereon during the read operation.
• FIG. 149 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed according to an embodiment of the present invention.
• FIG. 150 schematically illustrates a memory cell of the array represented inFIG. 149 that is having a write “0” operation performed thereon according to an embodiment of the present invention.
• FIG. 151 is a schematic illustration of an equivalent circuit of a memory array in which a write “0” operation is being performed according to an alternative embodiment of the present invention that allows for individual bit writing.
• FIG. 152 schematically illustrates a selected memory cell of the array represented inFIG. 151 that is being written to by the write “0” operation according to the alternative embodiment described with regard toFIG. 151.
• FIG. 153 is a schematic illustration of an equivalent circuit of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.
• FIG. 154 schematically illustrates a selected memory cell of the array ofFIG. 153 on which the write “1” operation is being performed, and the bias conditions thereon.
• FIG. 155 is a schematic illustration of an equivalent circuit of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.
• FIG. 156 schematically illustrates a selected memory cell of the array ofFIG. 155 on which the write “1” operation is being performed, and the bias conditions thereon.
• FIG. 157 shows a memory array where adjacent regions are connected a common BL terminal through a conductive region according to an alternative embodiment of the present invention.
• FIG. 158A shows a memory array according to another embodiment of the present invention.
• FIG. 158B shows, in isolation, a memory cell from the memory array ofFIG. 158A.
• FIGS. 158C and 158D show sectional views of the memory cell ofFIG. 158B taken along lines I-I′ and II-II′ ofFIG. 158B, respectively.
• FIG. 159 is an equivalent circuit representation of a memory array of the type shown inFIG. 158A according to an embodiment of the present invention.
• FIG. 160A shows an equivalent circuit representation of the memory cell ofFIGS. 158B-158D according to an embodiment of the present invention.
• FIG. 160B shows an energy band diagram of the intrinsic n-p-n bipolar device ofFIG. 160A when the floating body region is positively charged and a positive bias voltage is applied to the buried well region, according to an embodiment of the present invention.
• FIG. 160C shows an energy band diagram of the intrinsic n-p-nbipolar device30 ofFIG. 160A when the floating body region is neutrally charged and a bias voltage is applied to the buried well region, according to an embodiment of the present invention.
• FIG. 161 is a schematic illustration of a memory array in which a read operation is being performed on a selected memory cell according to an embodiment of the present invention.
• FIG. 162 is a schematic illustration of the selected memory cell inFIG. 161 that is being read, and bias conditions thereon during the read operation.
• FIG. 163 is a schematic illustration of a memory array in which a write “0” operation is being performed according to an embodiment of the present invention.
• FIG. 164 schematically illustrates a memory cell of the array represented inFIG. 163 that is having a write “0” operation performed thereon according to an embodiment of the present invention.
• FIG. 165 is a schematic illustration of a memory array in which a write “0” operation is being performed according to an alternative embodiment of the present invention.
• FIG. 166 schematically illustrates a memory cell of the array represented inFIG. 165 that is having a write “0” operation performed thereon according to the alternative embodiment described with regard toFIG. 165.
• FIG. 167 is a schematic illustration of a memory array in which a write “1” operation is being performed by band-to-band tunneling according to an embodiment of the present invention.
• FIG. 168 schematically illustrates a selected memory cell of the array ofFIG. 167 on which the write “1” operation is being performed, and the bias conditions thereon.
• FIG. 169 is a schematic illustration of a memory array in which a write “1” operation is being performed by impact ionization according to an embodiment of the present invention.
• FIG. 170 schematically illustrates a selected memory cell of the array ofFIG. 169 on which the write “1” operation is being performed, and the bias conditions thereon.
• FIG. 171 is a flow chart illustrating the operation of a memory cell according to an embodiment of the present invention.
• FIG. 172 is a flow chart illustrating operation of a memory cell according to another embodiment of the present invention.
• FIG. 173A is a cross-section, schematic illustration of a memory cell according to an embodiment of the present invention.
• FIG. 173B shows an exemplary array of memory cells arranged in rows and columns according to an embodiment of the present invention.
• FIG. 173C shows an array architecture of a memory cell device according to another embodiment of the present invention.
• FIG. 174 illustrates an operating condition for a write state “1” operation that can be carried out on a memory cell according to an embodiment of the present invention.
• FIG. 175 illustrates an operating condition for a write state “0” operation that can be carried out on a memory cell according to an embodiment of the present invention.
• FIG. 176 illustrates a read operation that can be carried out on a memory cell according to an embodiment of the present invention
• FIG. 177 illustrates a holding or refresh operation that can be carried out on a memory cell according to an embodiment of the present invention
• FIGS. 178A-178B illustrate shadowing operations that can be carried out according to an embodiment of the present invention.
• FIGS. 179A-179B illustrate restore operations that can be carried out according to an embodiment of the present invention.
• FIG. 180 illustrates resetting the trapping layer(s) of a memory cell to a predetermined state, according to an embodiment of the present invention.
• FIG. 181A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 181B shows an array architecture of a memory cell device according to an embodiment of the present invention.
• FIGS. 182-183 illustrate cross-sectional schematic illustrations of fin-type semiconductor memory cell devices according to embodiments of the present invention
• FIG. 184 illustrates a top view of a fin-type semiconductor memory cell device according to the embodiment shown inFIG. 182.
• FIG. 185A illustrates states of a bi-level memory cell.
• FIG. 185B illustrates states of a multi-level memory cell.
• FIGS. 186A through 186E illustrate an array and details of a first exemplary memory cell according to the present invention.
• FIG. 187 is a flowchart illustrating operation of a memory device according to the present invention.
• FIG. 188 illustrates a holding operation performed on an array of memory cells according to the present invention.
• FIGS. 189A and 189B illustrate the energy band diagram of a memory device according to the present invention during holding operation.
• FIGS. 190A and 190B illustrate read operations performed on an array of memory cells according to the present invention.
• FIGS. 191A and 191B illustrate write logic-0 operations performed on an array of memory cells according to the present invention.
• FIGS. 192A and 192B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.
• FIGS. 193A through 193C illustrate a shadowing operation performed on an array of memory cells according to the present invention.
• FIGS. 194A through 194C illustrate a restore operation performed on an array of memory cells according to the present invention.
• FIG. 195 illustrates a reset operation performed on an array of memory cells according to the present invention.
• FIGS. 196A through 196R illustrate a method of manufacturing a memory cell according to the present invention.
• FIGS. 197A through 197R illustrate an alternative method of manufacturing a memory cell according to the present invention.
• FIG. 198 illustrates a cross-sectional view of an alternative memory device according to the present invention.
• FIGS. 199A and 199B illustrate a shadowing operation performed on an array of memory cells according to the present invention.
• FIGS. 200A through 200C illustrate a restore operation performed on an array of memory cells according to the present invention.
• FIG. 201 illustrates a reset operation performed on an array of memory cells according to the present invention.
• FIGS. 202A and 202B illustrate cross-sectional views of alternative memory devices according to the present invention.
• FIG. 203 illustrates an equivalent circuit representation of memory devices shown inFIGS. 202A and 202B.
• FIG. 204 illustrates an exemplary array of memory devices according to the present invention.
• FIG. 205 illustrates a holding operation performed on an array of memory cells according to the present invention.
• FIG. 206 illustrates a read operation performed on an array of memory cells according to the present invention.
• FIGS. 207A through 207C illustrate write logic-0 operations performed on an array of memory cells according to the present invention.
• FIGS. 208A and 208B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.
• FIGS. 209, 210A through 210B illustrate a shadowing operation performed on an array of memory cells according to the present invention.
• FIGS. 211, 212A through 212B illustrate a restore operation performed on an array of memory cells according to the present invention.
• FIGS. 213A and 213B illustrate reset operations performed on an array of memory cells according to the present invention.
• FIGS. 214 and 215A-215B illustrate cross-sectional views of alternative memory devices according to the present invention.
• FIG. 216 illustrates an equivalent circuit representation of memory devices shown inFIGS. 215A-215B.
• FIG. 217 illustrates an exemplary array of memory devices according to the present invention.
• FIG. 218 illustrates a holding operation performed on an array of memory cells according to the present invention.
• FIG. 219 illustrates a read operation performed on an array of memory cells according to the present invention.
• FIGS. 220A, 220B, and 221 illustrate write logic-0 operations performed on an array of memory cells according to the present invention.
• FIGS. 222A and 222B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.
• FIGS. 223A and 223B illustrate a shadowing operation performed on an array of memory cells according to the present invention.
• FIG. 224 illustrates a restore operation performed on an array of memory cells according to the present invention.
• FIGS. 225A and 225B illustrate reset operations performed on an array of memory cells according to the present invention.
• FIG. 226 is a flowchart illustrating an alternative operation of a memory device according to the present invention.
• FIG. 227 illustrates a read operation performed on an array of memory cells according to the present invention.
• FIG. 228 illustrates a write logic-1 operation performed on an array of memory cells according to the present invention.
• FIGS. 229A through 229C illustrate cross sectional views of alternative memory devices according to the present invention, fabricated on silicon-on-insulator (SOI) substrate.
• FIGS. 230A through 230E illustrate cross-sectional views and top view of alternative memory devices according to the present invention, comprising of fin structures.
DETAILED DESCRIPTION OF THE INVENTION
• Before the present systems, devices and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.
• Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.
• Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.
• It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the terminal” includes reference to one or more terminals and equivalents thereof known to those skilled in the art, and so forth.
• The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.
Definitions
• A “holding operation”, “standby operation” or “holding/standby operation”, as used herein, refers to a process of sustaining a state of a memory cell by maintaining the stored charge. Maintenance of the stored charge may be facilitated by applying a back bias to the cell in a manner described herein.
• A “a multi-level write operation” refers to a process that includes an ability to write more than more than two different states into a memory cell to store more than one bit per cell.
• A “write-then-verify” “write and verify” or “alternating write and verify” algorithm or operation refers to a process where alternating write and read operations to a memory cell are employed to verify whether a desired memory state of the memory cell has been achieved during the write operation.
• A “read verify operation” refers to a process where a read operation is performed to verify whether a desired memory state of a memory cell has been achieved.
• A “read while programming” operation refers to a process where simultaneous write and read operations can be performed to write a memory cell state.
• A “back bias terminal” refers to a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor. A back bias terminal is also commonly referred to as a “back gate terminal”. Herein, the back bias terminal refers to the substrate terminal or the buried well terminal, depending upon the embodiment being described.
• The term “back bias” refers to a voltage applied to a back bias terminal.
• A “memory cell” as used herein, refers to a semiconductor memory cell comprising an electrically floating body as the data storage element.
• A “contactless memory cell” as used herein, refers to a memory cell which does not have a contact (or contacts) forming a direct connection(s) to a control line (or control lines). Contactless memory cells are typically connected in series when formed in a string or in parallel when formed in a link.
• A “memory string” or “string” as used herein, refers to a set of interconnected memory cells connected in series, where conductive regions at the surfaces of adjacent memory cells are shared or electrically connected. In a series connection, the same current flows through each of the memory cells.
• A “link” as used herein, refers to a set of interconnected memory cells connected in parallel, where conductive regions at the surfaces of adjacent memory cells are electrically connected. In a parallel connection, the voltage drop across each of the memory cells is the same.
• A “memory array” or “memory cell array” as used herein, refers to a plurality of memory cells typically arranged in rows and columns. The plurality of memory cells may further be connected in strings or links within the memory array.
• The terms “shadowing” “shadowing operation” and “shadowing process” refer to a process of copying the contents of volatile memory to non-volatile memory.
• “Restore”, “restore operation”, or “restore process”, as used herein, refers to a process of copying the contents of non-volatile memory to volatile memory.
• “Reset”, “reset operation”, or “reset process”, as used herein, refers to a process of setting non-volatile memory to a predetermined state.
• “Permanent data” as used herein, is referred to data that typically will not be changed during the operation of a system employing a memory cell device as described herein, and thus can be stored indefinitely in non-volatile memory. Examples of such “permanent data” include, but are not limited to program files, application files, music files, video files, operating systems, etc.
• The term “single polysilicon” flash memory refers to a non-volatile memory cell that has only one polysilicon gate, for example where the polysilicon is a floating gate used to store non-volatile data. As a result, single polysilicon flash memory is compatible with typical complementary metal oxide semiconductor (CMOS) processes. The polysilicon materials can be deposited and formed in conjunction with the gates of logic transistors.
• The term “stacked gate” flash memory refers to a non-volatile memory cell that has multiple polysilicon layers/gates, for example where a second polysilicon gate (e.g., a control gate) is stacked above a polysilicon floating gate used to store the non-volatile data (see for example FIG. 4.6 on p. 197 in “Nonvolatile Semiconductor Memory Technology”, W. D. Brown and J. E. Brewer “Brown”), which is hereby incorporated herein, in its entirety, by reference thereto. Such stacked gate memory cells typically require dual (or more) polysilicon layer processing, where the first polysilicon layer (e.g. floating gate) is deposited and formed, followed by the formation of a second polysilicon (e.g. control gate) layer.
DETAILED DESCRIPTION
• Referring now toFIG. 1, amemory cell50 according to an embodiment of the present invention is shown. Thecell50 includes asubstrate12 of a first conductivity type, such as n-type conductivity type, for example.Substrate12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. Thesubstrate12 has asurface14. Afirst region16 having a first conductivity type, such as n-type, for example, is provided insubstrate12 and which is exposed atsurface14. Asecond region18 having the first conductivity type is also provided insubstrate12, which is exposed atsurface14 and which is spaced apart from thefirst region16. First andsecond regions16 and18 are formed by an implantation process formed on the material making upsubstrate12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first andsecond regions16 and18.
• A floatingbody region24 having a second conductivity type different from the first conductivity type, such as p-type conductivity type when the first conductivity type is n-type conductivity type, is bounded bysurface14, first andsecond regions16,18, insulatinglayers26, andsubstrate12. The floatingbody region24 can be formed by an implantation process formed on the material making upsubstrate12, or can be grown epitaxially. Insulating layers26 (e.g. shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 insulatecell50 from neighboringcells50 whenmultiple cells50 are joined in anarray80 to make a memory device as illustrated inFIG. 2. Agate60 is positioned in between theregions16 and18, and above thesurface14. Thegate60 is insulated fromsurface14 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell50 further includes word line (WL) terminal70 electrically connected togate60, source line (SL) terminal72 electrically connected to one ofregions16 and18 (connected to16 as shown, but could, alternatively, be connected to18), bit line (BL) terminal74 electrically connected to the other ofregions16 and18 (connected to18 as shown, but could, alternatively, be connected to16 when72 is connected to18), andsubstrate terminal78 electrically connected tosubstrate12. Alternatively, contact tosubstrate region12 could be made through a region having a first conductivity type, which is electrically connected to substrate region12 (not shown).
• In another embodiment, thememory cell50 has a p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type, as noted above.
• The operation of amemory cell50 has been described for example in “Scaled 1T-Bulk Devices Built withCMOS 90 nm Technology for Low-cost eDRAM Applications”, R. Ranica, et al., pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005, which is hereby incorporated herein, in its entirety, by reference thereto. The memory cell states are represented by the charge in the floatingbody24. Ifcell50 has holes stored in the floatingbody region24, then thememory cell50 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to whencell50 does not store holes in floatingbody region24.
• The positive charge stored in the floatingbody region24 will decrease over time due to the p-n diode leakage formed by floatingbody24 andregions16,18, andsubstrate12 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to allmemory cells50 of thearray80. The holding operation can be performed by applying a positive back bias to thesubstrate terminal78 while groundingterminal72 and/orterminal74. The positive back bias applied to the substrate terminal will maintain the state of thememory cells50 that it is connected to. The holding operation is relatively independent of the voltage applied toterminal70. As shown inFIG. 3, inherent in thememory cell50 are n-p-nbipolar devices30aand30bformed bysubstrate region12, floatingbody24, and SL andBL regions16,18. If floatingbody24 is positively charged (i.e. in a state “1”), thebipolar transistor30aformed bySL region16, floatingbody24, andsubstrate region12 andbipolar transistor30bformed byBL region18, floatingbody24, andsubstrate region12 will be turned on.
• A fraction of the bipolar transistor current will then flow into floating region24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed bysubstrate12, floatingregion24, andregions16,18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofsubstrate terminal78 to the base current flowing into the floatingregion24.
• For memory cells in state “0” data, thebipolar devices30a,30bwill not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in state “0” will remain in state “0”.
• As can be seen, the holding operation can be performed in mass, parallel manner as the substrate terminal78 (e.g.,78a,78b,78n) is typically shared by all thecells50 in thememory array80. Thesubstrate terminal78 can also be segmented to allow independent control of the applied bias on the selected portion of the memory array as shown inFIG. 4A, wheresubstrate terminal78a,78bis shown segmented fromsubstrate terminal78m,78n, for example. Also, becausesubstrate terminal78 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.
• In another embodiment, a periodic pulse of positive voltage can be applied tosubstrate terminal78, as opposed to applying a constant positive bias, in order to reduce the power consumption of thememory cell50. The state of thememory cell50 can be maintained by refreshing the charge stored in floatingbody24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal78).FIG. 4B further showsmultiplexers40 that determine the bias applied tosubstrate terminal78 where the control signal could be theclock signal42 or as will be described later, determined by different operating modes. The positive input signals could be the power supply voltage Vcc (FIG. 4B) or a different positive bias could be generated by voltage generator circuitry44 (seeFIG. 4C).
• The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floatingbody24. Without the holding/standby operation, the maximum potential that can be stored in the floatingbody24 is limited to the flat band voltage V_FBas the junction leakage current toregions16 and18 increases exponentially at floating body potential greater than V_FB. However, by applying a positive voltage tosubstrate terminal78, the bipolar action results in a hole current flowing into the floatingbody24, compensating for the junction leakage current between floatingbody24 andregions16 and18. As a result, the maximum charge V_MCstored in floatingbody24 can be increased by applying a positive bias to thesubstrate terminal78 as shown inFIG. 5. The increase in the maximum charge stored in the floatingbody24 results in a larger memory window.
• The holding/standby operation can also be used for multi-bit operations inmemory cell50. To increase the memory density without increasing the area occupied by thememory cell50, a multi-level operation is typically used. This is done by dividing the overall memory window into different levels. In floating body memory, the different memory states are represented by different charges in the floatingbody24, as described for example in “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 and U.S. Pat. No. 7,542,345 “Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same”, each of which is hereby incorporated herein, in its entirety, by reference thereto. However, since the state with zero charge in the floatingbody24 is the most stable state, the floatingbody24 will, over time, lose its charge until it reaches the most stable state. In multi-level operations, the difference of charge representing different states is smaller than that for a single-level operation. As a result, a multi-level memory cell is more sensitive to charge loss, as less charge loss is required to change states.
• FIG. 6 shows the floatingbody24 relative net current for different floatingbody24 potentials as a function of the voltage applied tosubstrate terminal78 with BL, SL, andWL terminals72,74, and70, grounded. When zero voltage is applied tosubstrate terminal78, no bipolar current is flowing into the floatingbody24 and as a result, the stored charge will leak over time. When a positive voltage is applied tosubstrate terminal78, hole current will flow into floatingbody24 and balance the junction leakage current toregions16 and18. The junction leakage current is determined by the potential difference between the floatingbody24 andregions16 and18, while the bipolar current flowing into floatingbody24 is determined by both thesubstrate terminal78 potential and the floatingbody24 potential. As indicated inFIG. 6, for different floating body potentials, at acertain substrate terminal78 potential V_HOLD, the current flowing into floatingbody24 is balanced by the junction leakage between floatingbody24 andregions16 and18. The different floatingbody24 potentials represent different charges used to represent different states ofmemory cell50. This shows that different memory states can be maintained by using the holding/standby operation described here.
• An example of the bias condition for the holding operation is hereby provided: zero voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, and a positive voltage is applied to thesubstrate terminal78. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, and about +1.2 volts is applied toterminal78. However, these voltage levels may vary.
• The charge stored in the floatingbody24 can be sensed by monitoring the cell current of thememory cell50. Ifcell50 is in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current, compared to ifcell50 is in a state “0” having no holes in floatingbody region24. A sensing circuit/read circuitry90 typically connected toBL terminal74 of memory array80 (e.g., see readcircuitry90 inFIG. 18A) can then be used to determine the data state of the memory cell. Examples of the read operation is described in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, and Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003 and U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor”, both of which are hereby incorporated herein, in their entireties, by reference thereto. An example of a sensing circuit is described in “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, Ohsawa et al., pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
• The read operation can be performed by applying the following bias condition: a positive voltage is applied to thesubstrate terminal78, zero voltage is applied toSL terminal72, a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70. The unselected BL terminals will remain at zero voltage and the unselected WL terminals will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about +0.4 volts is applied to the selectedterminal74, about +1.2 volts is applied to the selectedterminal70, and about +1.2 volts is applied toterminal78. Theunselected terminals74 remain at 0.0 volts and theunselected terminals70 remain at 0.0 volts.FIG. 7 shows the bias conditions for the selectedmemory cell50aandunselected memory cells50b,50c, and50dinmemory array80. However, these voltage levels may vary.
• Theunselected memory cells50 during read operations are shown inFIGS. 8A, 8C and 8E, with illustration of the states of the n-p-nbipolar devices30a,30binherent in thecells50 ofFIGS. 8A, 8C and 8E inFIGS. 8B, 8D and 8F, respectively. The bias conditions formemory cells50 sharing the same row (e.g. memory cell50b) and those sharing the same column (e.g. memory cell50c) as the selectedmemory cell50aare shown inFIGS. 8A-8B andFIGS. 8C-8D, respectively, while the bias condition formemory cells50 not sharing the same row or the same column as the selected memory cell50 (e.g. memory cell50d) is shown inFIGS. 8E-8F.
• Formemory cells50 sharing the same row as the selected memory cell, both theSL terminal72 andBL terminal74 are at about 0.0 volts (FIGS. 8A-8B). As can be seen, these cells will be at holding mode, with memory cells in state “1” and will maintain the charge in floatingbody24 because the intrinsic n-p-nbipolar devices30a,30bwill generate hole current to replenish the charge in floatingbody24; whilememory cells50 in state “0” will remain in the neutral state.
• Formemory cells50 sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal74 (FIGS. 8C-8D). However, the n-p-nbipolar device30aformed bysubstrate12, floatingbody24, andregion16 will still maintain the state of the floatingbody24 as theSL terminal72 connected toregion16 is grounded.
• Formemory cells50 not sharing the same row or the same column as the selected memory cell, both theSL terminal72 andBL terminal74 are at about 0.0 volts (FIGS. 8E-8F). As can be seen, these cells will be at holding mode, where memory cells in state “1” will maintain the charge in floatingbody24 because the intrinsic n-p-nbipolar devices30a,30bwill generate holes current to replenish the charge in floatingbody24; while memory cells in state “0” will remain in the neutral state.
• From the above description, it can be seen that the holding operation does not interrupt the read operation of thememory cells50. At the same time, theunselected memory cells50 during a read operation will remain in a holding operation.
• Write operations ofmemory cell50 are now described. A write “0” operation of thecell50 is described with reference toFIG. 9. To write “0” tocell50, a negative bias is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, and zero or positive voltage is applied tosubstrate terminal78. TheSL terminal72 for the unselected cells will remain grounded. Under these conditions, the p-n junction between24 and16 is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −2.0 volts is applied toterminal72, about 0.0 volts is applied toterminal70, and about +1.2 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• FIG. 10 shows an example of bias conditions for the selected andunselected memory cells50 during a write “0” operation inmemory array80. For the selected memory cells, the negative bias applied toSL terminal72 causes large potential difference between floatingbody24 andregion16. Even for memory cells having a positively charged floatingbody24, the hole current generated by the intrinsic n-p-nbipolar devices30a,30bwill not be sufficient to compensate for the forward bias current of p-n diode formed by floatingbody24 andjunction16.
• An example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-nbipolar devices30a,30bofunselected memory cells50 during write “0” operations are illustrated inFIGS. 11A-11B. Since the write “0” operation only involves applying a negative voltage to theSL terminal72, the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with both BL and SL terminals at about 0.0 volts. The positive back bias applied to thesubstrate terminal78 employed for the holding operation does not interrupt the write “0” operation of the selected memory cells. Furthermore, the unselected memory cells remain in the holding operation.
• The write “0” operation referred to above has a drawback in that allmemory cells50 sharing the same SL terminal will be written to simultaneously and as a result, this does not allow individual bit writing, i.e., writing to asingle cell50 memory bit. To write multiple data todifferent memory cells50, write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.
• An alternative write “0” operation that allows for individual bit writing can be performed by applying a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, and zero or positive voltage tosubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between24 and18 is forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells50 in thememory array80, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to as V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. A positive voltage can be applied toSL terminal72 to further reduce the undesired write “0” disturb onother memory cells50 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied toWL terminal70 and zero voltage applied toBL terminal74.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell50a: a potential of about 0.0 volts is applied toterminal72, a potential of about −0.2 volts is applied toterminal74, a potential of about +0.5 volts is applied toterminal70, and about +1.2 volts is applied toterminal78; while about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, and about +1.2 volts is applied toterminal78 of the unselected memory cells.FIG. 12 shows the bias conditions for the selected and unselected memory cells inmemory array80. However, these voltage levels may vary.
• The bias conditions of the selectedmemory cell50aunder write “0” operation are further elaborated and are shown inFIGS. 13A-13B. As discussed, the potential difference between floatingbody24 and junction18 (connected to BL terminal74) is now increased, resulting in a higher forward bias current than the base hole current generated by the n-p-nbipolar devices30a,30bformed bysubstrate12, floatingbody24, andregions16 and18. The net result is that holes will be evacuated from floatingbody24.
• Theunselected memory cells50 during write “0” operations are shown inFIGS. 13C-13H. The bias conditions for memory cells sharing the same row (e.g. memory cell50b) are illustrated inFIGS. 13C-13D, and the bias conditions for memory cells sharing the same column (e.g. memory cell50c) as the selectedmemory cell50aare shown inFIGS. 13E-13F, while the bias conditions for memory cells not sharing the same row or the same column (e.g. memory cell50d) as the selectedmemory cell50 are shown inFIGS. 13G-13H.
• For memory cells sharing the same row as the selected memory cell, both theSL terminal72 andBL terminal74 are at about 0.0 volts (FIGS. 13C and 13D). The floatingbody24 potential of these cells will also increase due to capacitive coupling from theWL terminal70. For memory cells in state “1”, the increase in the floatingbody24 potential is not sustainable as the forward bias current of the p-n diodes formed by floatingbody24 andjunctions16 and18 is greater than the base hole current generated by the n-p-nbipolar device30 formed bysubstrate12, floatingbody24, andjunctions16 and18. As a result, the floatingbody24 potential will return to the initial state “1” equilibrium potential. For memory cells in state “0”, if the increase in floatingbody24 potential is sufficiently high (i.e., at least V_FB/3, see below), then both n-p-nbipolar devices30aand30bare turned on, and as a result the floatingbody24 reaches a new equilibrium potential, between that of state “0” and state “1”. Therefore, the WL potential needs to be optimized so that the n-p-nbipolar devices30a,30bwill not be turned on or that the base hole current is low enough that it does not result in an increase of the floatingbody24 potential over the time during which the write operation is carried out (write operation time). It has been determined by the present inventor that a floatingbody24 potential increase of V_FB/3 is low enough to suppress the floatingbody24 potential increase.
• Accordingly, with careful design concerning the voltage applied toWL terminal70, the states of the unselected memory cells sharing the same WL terminal (i.e. the same row) as the selected memory cells will be maintained.
• For memory cells sharing the same column as the selected memory cell, a negative voltage is applied to the BL terminal74 (seeFIGS. 13E and 13F), resulting in an increase in the potential difference between floatingbody24 andregion18 connected toBL terminal74. As a result a higher forward bias current between floatingbody24 andjunction18 occurs. For memory cells in state “0”, the potential difference between floatingbody24 andjunction18 is still sufficiently low that the p-n diode formed by floatingbody24 andjunction18 is still not forward biased. Thus those memory cells will remain in state “0”. For memory cells in state “1”, junction leakage caused by forward bias current will increase. However, the hole current of the n-p-nbipolar device30bformed bysubstrate12, floatingbody24, andregion18 will also increase as a result of the increase in potential difference between thesubstrate12 and region18 (the collector and emitter terminals, respectively). Hence, the floatingbody24 of memory cells in state “1” will also remain positively charged (i.e., in state “1”).
• As to memory cells not sharing the same row or the same column as the selected memory cell, both theSL terminal72 andBL terminal74 are at about 0.0 volts (seeFIGS. 13G and 13H). These cells will thus be in a holding mode and continue a holding operation, with memory cells in state “1” maintaining the charge in floatingbody24 because the intrinsic n-p-nbipolar device30 will generate hole current to replenish the charge in floatingbody24; while memory cells in state “0” will remain in the neutral state.
• Accordingly, the present invention provides for a write “0” operation that allows for bit selection. The positive bias applied to thesubstrate terminal78 of thememory cells50 is necessary to maintain the states of theunselected cells50, especially those sharing the same row and column as the selectedcells50, as the bias conditions can potentially alter the states of thememory cells50 without the intrinsicbipolar devices30a,30b(formed bysubstrate12, floatingbody24, andregions16,18, respectively) re-establishing the equilibrium condition. Also, the positive bias applied to thesubstrate terminal78 employed for the holding operation does not interrupt the write “0” operation of the selected memory cell(s).
• A write “1” operation can be performed onmemory cell50 through impact ionization or band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
• An example of the bias condition of the selectedmemory cell50 under band-to-band tunneling write “1” operation is illustrated inFIG. 14 andFIGS. 15A-15B. The negative bias applied to theWL terminal70 and the positive bias applied to theBL terminal74 results in hole injection to the floatingbody24 of the selectedmemory cell50. The positive bias applied to thesubstrate terminal78 maintains the resulting positive charge on the floatingbody24 as discussed above. Theunselected cells50 remain at the holding mode, with zero or negative voltage applied to theunselected WL terminal70 and zero voltage is applied to theunselected BL terminal74 to maintain the holding operation (holding mode).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell50a: a potential of about 0.0 volts is applied toterminal72, a potential of about +1.2 volts is applied toterminal74, a potential of about −1.2 volts is applied toterminal70, and about +1.2 volts is applied toterminal78; and the following bias conditions are applied to the unselected memory cells50: about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, and about +1.2 volts is applied toterminal78.FIG. 14 shows the bias conditions for the selected and unselected memory cells inmemory array80. However, these voltage levels may vary.
• The unselected memory cells during write “1” operations are shown inFIGS. 15C-15H. The bias conditions for memory cells sharing the same row (e.g. memory cell50b) are shown inFIGS. 15C-15D and the bias conditions for memory cells sharing the same column as the selectedmemory cell50a(e.g. memory cell50c) are shown inFIGS. 15E-15F. The bias conditions formemory cells50 not sharing the same row or the same column as the selectedmemory cell50a(e.g. memory cell50d) are shown inFIGS. 15G-15H.
• For memory cells sharing the same row as the selected memory cell, both theSL terminal72 andBL terminal74 are at about 0.0 volts, with theWL terminal70 at zero or negative voltage (FIGS. 15C-15D). Comparing with the holding operation bias condition, it can be seen that cells sharing the same row (i.e. the same WL terminal70) are in holding mode. As a result, the states of these memory cells will remain unchanged.
• For memory cells sharing the same column as the selected memory cell, a positive voltage is applied to theBL terminal74. As a result, thebipolar device30bformed bysubstrate12, floatingbody24, andregion18 connected toBL terminal74 will be turned off because of the small voltage difference between thesubstrate terminal78 and BL terminal74 (the collector and emitter terminals, respectively). However, thebipolar device30aformed bysubstrate12, floatingbody24, andregion16 connected toSL terminal72 will still generate base hole current for memory cells in state “1” having positive charge in floatingbody24. Memory cells in state “0” will remain in state “0” as thisbipolar device30a(formed bysubstrate12, floatingbody24, and region16) is off.
• For memory cells not sharing the same row or the same column as the selected memory cell, both theSL terminal72 andBL terminal74 are at about 0.0 volts (seeFIGS. 15G-15H). As can be seen, these cells will be in a holding operation (holding mode), where memory cells in state “1” will maintain the charge in floatingbody24 because the intrinsic n-p-nbipolar devices30a,30bwill generate hole current to replenish the charge in floatingbody24; while memory cells in state “0” will remain in the neutral state.
• Thus the positive bias applied to thesubstrate terminal78 employed for the holding operation does not interrupt the write “1” operation of the selected memory cell(s). At the same time, the unselected memory cells during write “1” operation will remain in holding operation.
• A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to thememory cell50, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to thememory cell50, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
• For example, using band-to-band tunneling hot hole injection, a positive voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, a negative voltage is applied toWL terminal70, and a positive voltage is applied to thesubstrate terminal78. Positive voltages of different amplitude are applied toBL terminal74 to write different states to floatingbody24. This results in different floatingbody potentials24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied toBL terminal74. By applying positive voltage tosubstrate terminal78, the resulting floatingbody24 potential is maintained through base hole current flowing into floatingbody24. In one particular non-limiting embodiment, the write operation is performed by applying the following bias condition: a potential of about 0.0 volts is applied toterminal72, a potential of about −1.2 volts is applied toterminal70, and about +1.2 volts is applied toterminal78, while the potential applied toBL terminal74 is incrementally raised. For example, in onenon-limiting embodiment 25 millivolts is initially applied toBL terminal74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e., cell current corresponding to whichever of 00, 01, 10 or 11 is desired is achieved), then the multi write operation is commenced. If the desired state is not achieved, then the voltage applied toBL terminal74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.
• The write-then-verify algorithm is inherently slow since it requires multiple write and read operations. The present invention provides a multi-level write operation that can be performed without alternate write and read operations. This is accomplished by ramping the voltage applied toBL terminal74, while applying zero voltage toSL terminal72, a positive voltage toWL terminal70, and a positive voltage tosubstrate terminal78 of the selected memory cells. The unselected memory cells will remain in holding mode, with zero or negative voltage applied toWL terminal70 and zero voltage applied toBL terminal74. These bias conditions will result in a hole injection to the floatingbody24 through impact ionization mechanism. The state of thememory cell50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry90 (FIGS. 16A-16C) coupled to thesource line72. The cell current measured in the source line direction is a cumulative cell current of allmemory cells50 which share the same source line72 (seeFIGS. 16A-16C). As a result, only onememory cell50 sharing thesame source line72 can be written. This ensures that the change in the cumulative cell current is a result of the write operation on the selectedmemory cell50.
• As shown inFIG. 17, the potential of the floatingbody24 increases over time as these bias conditions result in hole injection to floatingbody24 through an impact ionization mechanism. Once the change in cell current reaches the desired level associated with a state of thememory cell50, the voltage applied toBL terminal74 can be removed. By applying a positive voltage (back bias) tosubstrate terminal78, the resulting floatingbody24 potential is maintained through base hole current flowing into floatingbody24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
• FIGS. 16A-16C also show areference generator circuit92, which serves to generate the initial cumulative cell current of thememory cells50 sharing thesame source line72 being written. For example, the cumulative charge of the initial state for allmemory cells50 sharing thesame source line72 can be stored in a capacitor94 (seeFIG. 16B).Transistor96 is turned on when charge is to be written into or read fromcapacitor94. Alternatively, areference cell50R (FIG. 16C) similar to amemory cell50 can also be used to store the initial state. Using a similar principle, a write operation is performed on thereference cell50R using the cumulative cell current from thesource line72.Transistor96 is turned on when a write operation is to be performed on thereference cell50R. A positive bias is also applied to the substrate of the reference cell to maintain its state. The size of thereference cell50R needs to be configured such that it is able to store the maximum cumulative charge of all thememory cells50, i.e. when all of thememory cells50 sharing thesame source line72 are positively charged.
• In a similar manner, a multi-level write operation using an impact ionization mechanism can be performed by ramping the write current applied toBL terminal74 instead of ramping theBL terminal74 voltage.
• In yet another embodiment, a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage applied toBL terminal74, while applying zero voltage toSL terminal72, a negative voltage toWL terminal70, and zero or positive voltage tosubstrate terminal78 of the selectedmemory cells50. Theunselected memory cells50 will remain in holding mode, with zero or negative voltage applied toWL terminal70 and zero voltage applied toBL terminal74. Optionally,multiple BL terminals74 can be simultaneously selected to write multiple cells in parallel. The potential of the floatingbody24 of the selected memory cell(s)50 will increase as a result of the band-to-band tunneling mechanism. The state of the selected memory cell(s)50 can be simultaneously read for example by monitoring the change in the cell current through aread circuitry90 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied toBL terminal74 can be removed. If positive voltage is applied tosubstrate terminal78, the resulting floatingbody24 potential is maintained through base hole current flowing into floatingbody24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
• Similarly, the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied toBL terminal74 instead of ramping the voltage applied toBL terminal74.
• In another embodiment, a read while programming operation can be performed by monitoring the change in cell current in the bit line direction through a readingcircuitry90 coupled to thebit line74 as shown inFIG. 18A.Reference cells50R representing different memory states are used to verify the state of the write operation Thereference cells50R can be configured through a write-then-verify operation for example when the memory device is first powered up.
• In the voltage ramp operation, the resulting cell current of thememory cell50 being written is compared to thereference cell50R current by means of the readcircuitry90. During this read while programming operation, thereference cell50R is also being biased at the same bias conditions applied to the selectedmemory cell50 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of thereference cell50R. For the current ramp operation, the voltage at thebit line74 can be sensed instead of the cell current. The bit line voltage can be sensed for example using a voltage sensing circuitry (seeFIG. 18B) as described in “VLSI Design of Non-Volatile Memories”, Campardo G. et al., 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
• An example of a multi-level write operation without alternate read and write operations, using a read while programming operation/scheme in the bit line direction is given, where two bits are stored permemory cell50, requiring four states to be storable in eachmemory cell50. With increasing charge in the floatingbody24, the four states are referred to as states “00”, “01”, “10”, and “11”. To program amemory cell50 to a state “01”, thereference cell50R corresponding to state “01” is activated. Subsequently, the bias conditions described above are applied both to the selectedmemory cell50 and to the “01”reference cell50R: zero voltage is applied to thesource line terminal72, a positive voltage is applied to thesubstrate terminal78, a positive voltage is applied to the WL terminal70 (for the impact ionization mechanism), while theBL terminal74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of thereference cell50R does not change.
• The voltage applied to theBL terminal74 is then increased. Consequently, holes are injected into the floatingbody24 of the selectedcell50 and subsequently the cell current of the selectedcell50 increases. Once the cell current of the selectedcell50 reaches that of the “01” reference cell, the write operation is stopped by removing the positive voltage applied to theBL terminal74 andWL terminal70.
• As was noted above, a periodic pulse of positive voltage can be applied tosubstrate terminal78, as opposed to applying a constant positive bias, to reduce the power consumption of thememory cell50. Thememory cell50 operations during the period where thesubstrate terminal78 is being grounded are now briefly described. During the period when thesubstrate terminal78 is grounded, thememory cells50 connected to aground substrate terminal78 are no longer in holding mode. Therefore the period during which the substrate terminal is grounded must be shorter than the charge retention time period of the floating body, to prevent the state of the floating body from changing when the substrate terminal is grounded. The charge lifetime (i.e., charge retention time period) of the floatingbody24 without use of a holding mode has been shown to be on the order of milliseconds, for example, see “A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond”, Ban et al., pp. 92-92, Symposium on VLSI Technology, 2008, which is hereby incorporated herein, in its entirety, by reference thereto. The state of thememory cell50 can be maintained by refreshing the charge stored in floatingbody24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal78).
• A read operation can be performed by applying the following bias conditions: zero voltage is applied to thesubstrate terminal78, zero voltage is applied toSL terminal72, a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70. Theunselected BL terminals74 will remain at zero voltage and theunselected WL terminals70 will remain at zero or negative voltage. If thesubstrate terminals78 are segmented (as for example shown inFIGS. 4A-4C), a positive voltage can be applied to theunselected substrate terminals78. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about +0.4 volts is applied to the selectedterminal74, about +1.2 volts is applied to the selectedterminal70, and about 0.0 volts is applied toterminal78. Theunselected terminals74 remain at 0.0 volts and theunselected terminals70 remain at 0.0 volts. The unselected terminals78 (in the case where thesubstrate terminals78 are segmented as inFIGS. 4A and 4B) can remain at +1.2 volts (seeFIG. 19). Because the read operation is carried out over a time period on the order of nanoseconds, it is of a much shorter duration than the charge lifetime (charge retention time period) of the floatingbody24 unassisted by a holding operation. Accordingly, the performance of a read operation does not affect the states of the memory cells connected to the terminal78 as it is momentarily (on the order of nanoseconds) grounded.
• A write “0” operation of thecell50 can be performed by applying the following bias conditions: a negative bias is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, and zero voltage is applied tosubstrate terminal78. TheSL terminal72 for the unselected cells will remain grounded. If thesubstrate terminals78 are segmented (as for example shown inFIGS. 4A-4C), a positive voltage can be applied to theunselected substrate terminals78. Under these conditions, the p-n junction between24 and16 is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −2.0 volts is applied toterminal72, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminal78. The unselected terminals78 (in the case where thesubstrate terminals78 are segmented as inFIGS. 4A and 4B) can remain at +1.2 volts. With thesubstrate terminal78 being grounded, there is no bipolar hole current flowing to the floatingbody24. As a result, the write “0” operation will also require less time. Because the write “0” operation is brief, occurring over a time period on the order of nanoseconds, it is of much shorter duration than the charge retention time period of the floatingbody24, unassisted by a holding operation. Accordingly, the write “0” operation does not affect the states of theunselected memory cells50 connected to the terminal78 being momentarily grounded to perform the write “0” operation. The bias conditions applied to thememory array80 are shown inFIG. 20. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• An example of the bias conditions for an alternative write “0” operation which allows for individual bit write is shown inFIG. 21. The following conditions are applied to selected memory cell50: a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, and zero voltage tosubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between24 and18 is forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb to other memory cells in the memory array sharing the same row or column as the selected memory cell, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to as V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. A positive voltage can be applied toSL terminal72 to further reduce the undesired write “0” disturb onother memory cells50 in the memory array that do not share the samecommon SL terminal72 as the selected memory cell. The unselected cells will remain at holding state, i.e. zero or negative voltage applied toWL terminal70, zero voltage applied toBL terminal74, and positive voltage applied to substrate terminal78 (in the case thesubstrate terminals78 are segmented as for example shown inFIGS. 4A-4C). Because the write “0” operation is brief, occurring over a time period on the order of nanoseconds, it is of much shorter duration than the charge retention time period of the floatingbody24, unassisted by a holding operation. Accordingly, the write “0” operation does not affect the states of theunselected memory cells50 connected to the terminal78 being momentarily grounded to perform the write “0” operation.
• Still referring toFIG. 21, in one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell50a: a potential of about 0.0 volts is applied to terminal72a, a potential of about −0.2 volts is applied to terminal74a, a potential of about +0.5 volts is applied to terminal70a, and about 0.0 volts is applied to terminal78a; while about 0.0 volts is applied to terminal72nand the other SL terminals not connected to the selectedcell50a, about 0.0 volts is applied to terminal74nand the other BL terminals not connected to the selectedcell50a, about 0.0 volts is applied to terminal70nand the other WL terminals not connected to the selectedcell50a, and about +1.2 volts is applied to terminal78nand the other substrate terminals not connected to the selectedcell50a. However, these voltage levels may vary.
• An example of the bias conditions applied to thememory array80 under a band-to-band tunneling write “1” operation tocell50ais shown inFIG. 22, where a negative bias is applied toWL terminal70a, a positive bias is applied toBL terminal74a, zero voltage is applied toSL terminal72a, and zero voltage is applied tosubstrate terminal78a. The negative bias applied to theWL terminal70aand the positive bias applied to theBL terminal74awill result in hole injection to the floatingbody24 of the selectedmemory cell50a. Theunselected cells50 will remain at the holding mode, with zero or negative voltage applied to the unselected WL terminals70 (in this case, terminal70nand anyother WL terminal70 not connected to selectedcell50a) and zero voltage is applied to the unselected BL terminals74 (in this case,terminals74b,74nand anyother BL terminal74 not connected to selectedcell50a) and positive voltage applied to unselected substrate terminals78 (in the case thesubstrate terminals78 are segmented as for example shown inFIGS. 4A and 4B; and, inFIG. 22, toterminals78nand anyother substrate terminals78 not connected to selectedcell50a).
• Still referring toFIG. 22, in one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell50a: a potential of about 0.0 volts is applied to terminal72a, a potential of about +1.2 volts is applied to terminal74a, a potential of about −1.2 volts is applied to terminal70a, and about 0.0 volts is applied to terminal78a; while about 0.0 volts is applied to the unselected terminals72 (defined in the preceding paragraph), about 0.0 volts is applied to unselected terminals74 (defined in the preceding paragraph), about 0.0 volts is applied to unselected terminals70 (defined in the preceding paragraph), and about +1.2 volts is applied to unselected substrate terminals78 (defined in the preceding paragraph) of the unselected memory cells. However, these voltage levels may vary.
• FIG. 23A shows another embodiment of amemory cell150 according to the present invention. Thecell150 includes asubstrate12 of a first conductivity type, such as a p-type conductivity type, for example.Substrate12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. Thesubstrate12 has asurface14. Afirst region16 having a second conductivity type, such as n-type, for example, is provided insubstrate12 and is exposed atsurface14. Asecond region18 having the second conductivity type is also provided insubstrate12, and is also exposed atsurface14.Second region18 is spaced apart from thefirst region16, as shown. First andsecond regions16 and18 may be formed by an implantation process on the material making upsubstrate12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process may be used to form first andsecond regions16 and18.
• A buriedlayer22 of the second conductivity type is also provided in thesubstrate12, buried in thesubstrate12, as shown.Buried layer22 may also be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can be grown epitaxially. A floatingbody region24 of thesubstrate12 having a first conductivity type, such as a p-type conductivity type, is bounded by surface, first andsecond regions16,18, insulatinglayers26 and buriedlayer22. Insulating layers26 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 insulatecell150 from neighboringcells150 whenmultiple cells150 are joined in anarray180 to make a memory device as illustrated inFIG. 24. Agate60 is positioned in between theregions16 and18, and above thesurface14. Thegate60 is insulated fromsurface14 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell150 further includes word line (WL) terminal70 electrically connected togate60, source line (SL) terminal72 electrically connected to one ofregions16 and18 (connected to16 as shown, but could, alternatively, be connected to18), bit line (BL) terminal74 electrically connected to the other ofregions16 and18, buried well (BW) terminal76 electrically connected to buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12 at a location beneath buriedlayer22. Contact to buriedwell region22 could be made throughregion20 having a second conductivity type, which is electrically connected to buriedwell region22, while contact tosubstrate region12 could be made throughregion28 having a first conductivity type, which is electrically connected tosubstrate region12, as shown inFIG. 23B
• In another embodiment, thememory cell150 may be provided with p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type.
• As shown inFIG. 25, inherent in this embodiment of thememory cell150 are n-p-nbipolar devices130a,130bformed by buriedwell region22, floatingbody24, and SL andBL regions16,18. The memory cell operations will be described as follows. As will be seen, the operation principles of this embodiment of thememory cell150 will follow the descriptions above, where the bias applied on the n-type substrate terminal78 for the above describedmemory cell50 is now applied to the n-type buried well terminal76 ofcell150. The p-type substrate12 of the current embodiment of thememory cell150 will be grounded, reverse biasing the p-n junction betweensubstrate12 and buried welllayer22, thereby preventing any leakage current betweensubstrate12 and buried welllayer22.
• A holding operation can be performed by applying a positive back bias to theBW terminal76 while groundingterminal72 and/orterminal74. If floatingbody24 is positively charged (i.e. in a state “1”), the bipolar transistor formed bySL region16, floatingbody24, and buried wellregion22 and bipolar transistor formed byBL region18, floatingbody24, and buried wellregion22 will be turned on.
• A fraction of the bipolar transistor current will then flow into floating region24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing thebipolar devices130a,130bformed by buriedwell layer22, floatingregion24, andregions16/18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofBW terminal76 to the base current flowing into the floatingregion24.
• For memory cells in state “0” data, thebipolar devices130a,130bwill not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in state “0” will remain in state “0”.
• The holding operation can be performed in mass, parallel manner as the BW terminal76 (functioning as back bias terminal) is typically shared by all thecells150 in thememory array180, or at least bymultiple cells150 in a segment of thearray180. TheBW terminal76 can also be segmented to allow independent control of the applied bias on a selected portion of thememory array180. Also, becauseBW terminal76 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.
• An example of the bias conditions applied tocell150 to carry out a holding operation includes: zero voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, a positive voltage is applied to theBW terminal76, and zero voltage is applied tosubstrate terminal78. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary.
• A read operation can be performed oncell150 by applying the following bias conditions: a positive voltage is applied to theBW terminal76, zero voltage is applied toSL terminal72, a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70, while zero voltage is applied tosubstrate terminal78. Whencell150 is in anarray180 ofcells150, the unselected BL terminals74 (e.g.,74b,74n) will remain at zero voltage and the unselected WL terminals70 (e.g.,70nand anyother WL terminals70 not connected to selectedcell150a) will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about +0.4 volts is applied to the selected terminal74a, about +1.2 volts is applied to the selected terminal70a, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78, as illustrated inFIG. 26. Theunselected terminals74 remain at 0.0 volts and the unselected terminal70 remain at 0.0 volts as illustrated inFIG. 26. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above. As a result of the bias conditions applied as described, the unselected memory cells (150b,150cand150d) will be at holding mode, maintaining the states of the respective floatingbodies24 thereof. Furthermore, the holding operation does not interrupt the read operation of the selectedmemory cell150a.
• To write “0” tocell150, a negative bias is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, zero or positive voltage is applied toBW terminal76, and zero voltage is applied tosubstrate terminal78. TheSL terminal72 for theunselected cells150 that are not commonly connected to the selectedcell150awill remain grounded. Under these conditions, the p-n junctions (junction between24 and16 and between24 and18) are forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −2.0 volts is applied toterminal72, about −1.2 volts is applied toterminal70, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• The bias conditions for all the unselected cells are the same since the write “0” operation only involves applying a negative voltage to the SL terminal72 (thus to the entire row). As can be seen, the unselected memory cells will be in holding operation, with both BL and SL terminals at about 0.0 volts.
• Thus, the holding operation does not interrupt the write “0” operation of the memory cells. Furthermore, the unselected memory cells will remain in holding operation during a write “0” operation.
• An alternative write “0” operation, which, unlike the previous write “0” operation described above, allows for individual bit write, can be performed by applying a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, zero or positive voltage toBW terminal76, and zero voltage tosubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction (junction between24 and16) is forward-biased, evacuating any holes from the floatingbody24. The applied bias to selectedWL terminal70 and selectedBL terminal74 can potentially affect the states of theunselected memory cells150 sharing the same WL or BL terminal as the selectedmemory cell150. To reduce undesired write “0” disturb toother memory cells150 in thememory array180, the applied potential can be optimized as follows: If the floatingbody24 potential of state “1” is referred to as V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. This will minimize the floatingbody24 potential change in theunselected cells150 in state “1” sharing the same BL terminal as the selectedcell150 from V_FB1to V_FB1/2. Formemory cells150 in state “0” sharing the same WL terminal as the selectedcell150, if the increase in floatingbody24 potential is sufficiently high (i.e., at least V_FB/3, see below), then both n-p-nbipolar devices130aand130bwill not be turned on or so that the base hold current is low enough that it does not result in an increase of the floatingbody24 potential over the time during which the write operation is carried out (write operation time). It has been determined according to the present invention that a floatingbody24 potential increase of V_FB/3 is low enough to suppress the floatingbody24 potential increase. A positive voltage can be applied toSL terminal72 to further reduce the undesired write “0” disturb onother memory cells150 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied toWL terminal70 and zero voltage applied toBL terminal74. Theunselected cells150 not sharing the same WL or BL terminal as the selectedcell150 will remain at holding state, i.e., with zero or negative voltage applied to unselected WL terminal and zero voltage applied tounselected BL terminal74.
• In one particular non-limiting embodiment, for the selectedcell150 a potential of about 0.0 volts is applied toterminal72, a potential of about −0.2 volts is applied toterminal74, a potential of about +0.5 volts is applied toterminal70, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. For the unselected cells not sharing the same WL terminal or BL terminal with the selectedmemory cell50, about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78.FIG. 27 shows the bias conditions for the selected andunselected memory cells150 inmemory array180. However, these voltage levels may vary.
• An example of the bias conditions applied to a selectedmemory cell150 during a write “0” operation is illustrated inFIGS. 28A-28B. An example of the bias conditions applied to theunselected memory cells150 during write “0” operations are shown inFIGS. 28C-28H. The bias conditions forunselected memory cells150 sharing the same row as selectedmemory cell150a(e.g. memory cell150binFIG. 27) are shown inFIGS. 28C-28D. The bias conditions forunselected memory cells150 sharing the same column as selectedmemory cell150a(e.g. memory cell150cinFIG. 27) are shown inFIGS. 28E-28H. The bias conditions forunselected memory cells150 not sharing the same row or the same column as the selectedmemory cell150a(e.g. memory cell150dinFIG. 27) are shown inFIGS. 28G-28H.
• During the write “0” operation (individual bit write “0” operation described above) inmemory cell150, the positive back bias applied to theBW terminal76 of thememory cells150 is necessary to maintain the states of theunselected cells150, especially those sharing the same row or column as the selectedcell150a, as the bias condition can potentially alter the states of thememory cells150 without the intrinsic bipolar device130 (formed by buriedwell region22, floatingbody24, andregions16,18) re-establishing the equilibrium condition. Furthermore, the holding operation does not interrupt the write “0” operation of thememory cells150.
• A write “1” operation can be performed onmemory cell150 through an impact ionization mechanism or a band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
• An example of bias conditions applied to selectedmemory cell150aunder a band-to-band tunneling write “1” operation is further elaborated and is shown inFIG. 29. The negative bias applied to theWL terminal70aand the positive bias applied to theBL terminal74awill result in hole injection to the floatingbody24. The positive bias applied to theBW terminal76awill maintain the resulting positive charge on the floatingbody24 as discussed above. Theunselected cells150 will remain at the holding mode, with zero or negative voltage applied to the unselected WL terminal70 (inFIG. 27, 70nand allother WL terminals70 not connected tocell150a) and zero voltage is applied to theunselected BL terminal74b,74nand all otherBL terminals74 not connected tocell150a). The positive bias applied to theBW terminal76 employed for the holding operations does not interrupt the write “1” operation of the selected memory cell(s). At the same time, theunselected memory cells150 will remain in a holding operation during a write “1” operation on a selectedmemory cell150.
• A multi-level operation can also be performed onmemory cell150. A holding operation to maintain the multi-level states ofmemory cell50 is described with reference toFIG. 6. The relationship between the floatingbody24 current for different floatingbody24 potentials as a function of theBW terminal76 potential (FIG. 6B) is similar to that of floatingbody24 current as a function of thesubstrate terminal78 potential (FIG. 6A). As indicated inFIG. 6B, for different floating body potentials, at acertain BW terminal76 potential V_HOLD, the current flowing into floatingbody24 is balanced by the junction leakage between floatingbody24 andregions16 and18. The different floatingbody24 potentials represent different charges used to represent different states ofmemory cell150. This shows that different memory states can be maintained by using the holding/standby operation described here.
• A multi-level write operation without alternate write and read operations onmemory cell150 is now described. To perform this operation, zero voltage is applied toSL terminal72, a positive voltage is applied toWL terminal70, a positive voltage (back bias) is applied toBW terminal76, and zero voltage is applied tosubstrate terminal78, while the voltage ofBL terminal74 is ramped up. These bias conditions will result in a hole injection to the floatingbody24 through an impact ionization mechanism. The state of thememory cell150 can be simultaneously read for example by monitoring the change in the cell current through aread circuitry90 coupled to thesource line72. The cell current measured in the source line direction (where source line current equals bit line current plus BW current and the currents are measured in the directions from buried well to source line and from bit line to source line) is a cumulative cell current of allmemory cells150 which share the same source line72 (e.g. seeFIGS. 16A-16C for examples of monitoring cell current in the source line direction. The same monitoring scheme can be applied tomemory array80 as well as memory array180). As a result, only onememory cell150 sharing thesame source line72 can be written. This ensures that the change in the cumulative cell current is a result of the write operation on the selectedmemory cell150.
• The applied bias conditions will result in hole injection to floatingbody24 through an impact ionization mechanism.FIG. 17 shows the resulting increase of the floatingbody potential24 over time. Once the change in cell current reaches the desired level associated with a state of the memory cell150 (levels are schematically represented inFIG. 17), the voltage applied toBL terminal74 can be removed. By applying a positive voltage toBW terminal76, the resulting floatingbody24 potential is maintained through base hole current flowing into floatingbody24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
• In a similar manner, the multi-level write operation using impact ionization mechanism can also be performed by ramping the write current applied toBL terminal74 instead of ramping theBL terminal74 voltage.
• In yet another embodiment, a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage applied toBL terminal74, while applying zero voltage toSL terminal72, a negative voltage toWL terminal70, a positive voltage toBW terminal76, and zero voltage tosubstrate terminal78. The potential of the floatingbody24 will increase as a result of the band-to-band tunneling mechanism. The state of thememory cell50 can be simultaneously read for example by monitoring the change in the cell current through aread circuitry90 coupled to thesource line72. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied toBL terminal74 can be removed. If positive voltage is applied tosubstrate terminal78, the resulting floatingbody24 potential is maintained through base hole current flowing into floatingbody24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
• Similarly, the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied toBL terminal74 instead of ramping the voltage applied toBL terminal74.
• Similarly, a read while programming operation can be performed by monitoring the change in cell current in thebit line74 direction (where bit line current equals SL current plus BW current) through a readingcircuitry90 coupled to thebit line74, for example as shown inFIG. 18A. For the current ramp operation, the voltage at thebit line74 can be sensed, rather than sensing the cell current. The bit line voltage can be sensed, for example, using a voltage sensing circuitry, seeFIG. 18B.
• Another embodiment ofmemory cell150 operations, which utilizes the silicon controlled rectifier (SCR) principle has been disclosed in U.S. patent application Ser. No. 12/533,661, filed Jul. 31, 2009, which was incorporated by reference, in its entirety, above.
• FIGS. 30 and 31 show another embodiment of thememory cell50 described in this invention. In this embodiment,cell50 has afin structure52 fabricated onsubstrate12 having a first conductivity type (such as n-type conductivity type) so as to extend from the surface of the substrate to form a three-dimensional structure, withfin52 extending substantially perpendicularly to, and above the top surface of thesubstrate12.Fin structure52 includes first andsecond regions16,18 having the first conductivity type. The floatingbody region24 is bounded by the top surface of thefin52, the first andsecond regions16,18 and insulating layers26 (insulatinglayers26 can be seen in the top view ofFIG. 34). Insulatinglayers26 insulatecell50 from neighboringcells50 whenmultiple cells50 are joined to make a memory device (array80). The floatingbody region24 is conductive having a second conductivity type (such as p-type conductivity type) and may be formed through an ion implantation process or may be grown epitaxially.Fin52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
• Memory cell device50 further includesgates60 on two opposite sides of the floatingsubstrate region24 as shown inFIG. 30. Alternatively,gates60 can enclose three sides of the floatingsubstrate region24 as shown inFIG. 31.Gates60 are insulated from floatingbody24 by insulatinglayers62.Gates60 are positioned between the first andsecond regions16,18, adjacent to the floatingbody24.
• Device50 includes several terminals: word line (WL) terminal70, source line (SL) terminal72, bit line (BL)terminal74, andsubstrate terminal78.Terminal70 is connected to thegate60.Terminal72 is connected tofirst region16 andterminal74 is connected tosecond region18. Alternatively, terminal72 can be connected tosecond region18 and terminal74 can be connected tofirst region16.Terminal78 is connected tosubstrate12.
• FIGS. 32 and 33 show another embodiment ofmemory cell150 described in this invention. In this embodiment,cell150 has afin structure52 fabricated onsubstrate12, so as to extend from the surface of the substrate to form a three-dimensional structure, withfin52 extending substantially perpendicularly to, and above the top surface of thesubstrate12.Fin structure52 is conductive and is built on buried welllayer22.Region22 may be formed by an ion implantation process on the material ofsubstrate12 or grown epitaxially. Buried well layer22 insulates the floatingsubstrate region24, which has a first conductivity type (such as p-type conductivity type), from thebulk substrate12.Fin structure52 includes first andsecond regions16,18 having a second conductivity type (such as n-type conductivity type). Thus, the floatingbody region24 is bounded by the top surface of thefin52, the first andsecond regions16,18 the buried welllayer22, and insulating layers26 (seeFIG. 34). Insulatinglayers26 insulatecell150 from neighboringcells150 whenmultiple cells150 are joined to make a memory device.Fin52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
• Memory cell device150 further includesgates60 on two opposite sides of the floatingsubstrate region24 as shown inFIG. 32. Alternatively,gates60 can enclose three sides of the floatingsubstrate region24 as shown inFIG. 33.Gates60 are insulated from floatingbody24 by insulatinglayers62.Gates60 are positioned between the first andsecond regions16,18, adjacent to the floatingbody24.
• Device150 includes several terminals: word line (WL) terminal70, source line (SL) terminal72, bit line (BL)terminal74, buried well (BW)terminal76 andsubstrate terminal78.Terminal70 is connected to thegate60.Terminal72 is connected tofirst region16 andterminal74 is connected tosecond region18. Alternatively, terminal72 can be connected tosecond region18 and terminal74 can be connected tofirst region16.Terminal76 is connected to buriedlayer22 andterminal78 is connected tosubstrate12.
• FIG. 34 illustrates the top view of thememory cells50/150 shown inFIGS. 30 and 32.
• From the foregoing it can be seen that with the present invention, a semiconductor memory with electrically floating body is achieved. The present invention also provides the capability of maintaining memory states or parallel non-algorithmic periodic refresh operations. As a result, memory operations can be performed in an uninterrupted manner. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.
• In a floating body memory, the different memory states are represented by different levels of charge in the floating body. In “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 (“Okhonin-1”) and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002) (“Ohsawa-1”), a single bit (two voltage levels) in a standard MOSFET is contemplated. Others have described using more than two voltage levels stored in the floating body of a standard MOSFET allowing for more than a single binary bit of storage in a memory cell like, for example, “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”) which is incorporated by reference herein in its entirely, and U.S. Pat. No. 7,542,345 “Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same” to Okhonin, et al (“Okhonin-2”). Tack describes obtaining more than two states in the floating body of a standard MOSFET built in SOI by manipulating the “back gate”—a conductive layer below the bottom oxide (BOX) of the silicon tub the MOSFET occupies. Okhonin-2 discloses attaining more than two voltage states in the floating body utilizing the intrinsic bipolar junction transistor (BJT) formed between the two source/drain regions of the standard MOSFET to generate read and write currents.
• In memory design in general, sensing and amplifying the state of a memory cell is an important aspect of the design. This is true as well of floating body DRAM memories. Different aspects and approaches to performing a read operation are known in the art like, for example, the ones disclosed in “A Design of a Capacitor-less 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003 (“Yoshida”) which is incorporated by reference herein in its entirely; in U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor” (“Okhonin-3”) which is incorporated by reference herein in its entirely; and in “An 18.5 ns 128 Mb SOI DRAM with a Floating Body Cell”, Ohsawa et al., pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005 (“Ohsawa-2”) which is incorporated by reference herein in its entirely. Both Yoshida and Okhonin-3 disclose a method of generating a read current from a standard MOSFET floating body memory cell manufactured in SOI-CMOS processes. Okhonin-3 describes using the intrinsic BJT transistor inherent in the standard MOSFET structure to generate the read current. Ohsawa-2 discloses a detailed sensing scheme for use with standard MOSFET floating body memory cells implemented in both SOI and standard bulk silicon.
• Writing a logic-0 to a floating body DRAM cell known in the art is straight forward. Either the source line or the bit line is pulled low enough to forward bias the junction with the floating body removing the hole charge, if any. Writing a logic-1 typically may be accomplished using either a band-to-band tunneling method (also known as Gate Induced Drain Leakage or GIDL) or an impact ionization method
• In floating body DRAM cells, writing a logic-0 is straightforward (simply forward biasing either the source or drain junction of the standard MOSFET will evacuate all of the majority carriers in the floating body writing a logic-0) while different techniques have been explored for writing a logic-1. A method of writing a logic-1 through a gate induced band-to-band tunneling mechanism, as described for example in Yoshida. The general approach in Yoshida is to apply an appropriately negative voltage to the word line (gate) terminal of the memory cell while applying an appropriately positive voltage to the bit line terminal (drain) and grounding the source line terminal (source) of the selected memory cell. The negative voltage on WL terminal and the positive voltage on BL terminal creates a strong electric field between the drain region of the MOSFET transistor and the floating body region in the proximity of the gate (hence the “gate induced” portion of GIDL) in the selected memory cell. This bends the energy bands sharply upward near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current (hence the “drain leakage” portion of GIDL), while the holes are injected into floatingbody region24 and become the hole charge that creates the logic-1 state. This process is well known in the art and is illustrated in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4).
• A method of writing a logic-1 through impact ionization is described, for example, in “A New 1T DRAM Cell with Enhanced Floating Body Effect”, Lin and Chang, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, (“Lin”) which is incorporated in its entirety by reference herein. The general approach in Lin is to bias both the gate and bit line (drain) terminals of the memory cell to be written at a positive voltage while grounding the source line (source). Raising the gate to a positive voltage has the effect of raising the voltage potential of the floating body region due to capacitive coupling across the gate insulating layer. This in conjunction with the positive voltage on the drain terminal causes the intrinsic n-p-n bipolar transistor (drain (n=collector) to floating body (p=base) to source (n=emitter)) to turn on regardless of whether or not a logic-1 or logic-0 is stored in the memory cell. In particular, the voltage across the reversed biased p-n junction between the floating body (base) and the drain (collector) will cause a small current to flow across the junction. Some of the current will be in the form of hot carriers accelerated by the electric field across the junction. These hot carriers will collide with atoms in the semiconductor lattice which will generate hole-electron pairs in the vicinity of the junction. The electrons will be swept into the drain (collector) by the electric field and become bit line (collector) current, while the holes will be swept into the floating body region, becoming the hole charge that creates the logic-1 state.
• Much of the work to date has been done on SOL which is generally more expensive than a bulk silicon process. Some effort has been made to reduce costs of manufacturing floating body DRAMs by starting with bulk silicon. An example of a process to selectively form buried isolation region is described in “Silicon on Replacement Insulator (SRI) Floating Body Cell (FBC) Memory”, S. Kim et al., pp. 165-166, Tech Digest, Symposium on VLSI Technology, 2010, (“S_Kim”) which is incorporated in its entirety by reference herein. In S_Kim bulk silicon transistors are formed. Then the floating bodies are isolated by creating a silicon-on-replacement-insulator (SRI) structure. The layer of material under the floating body cells is selectively etched away and replaced with insulator creating an SOI type of effect. An alternate processing approach to selectively creating a gap and then filling it with an insulator is described in “A 4-bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation”, Oh et al., pp. 58-59, Tech Digest, Symposium on VLSI Technology, 2006 (“Oh”) which is incorporated in its entirety by reference herein.
• Most work to date has involved standard lateral MOSFETs in which the source and drain are disposed at the surface of the semiconductor where they are coupled to the metal system above the semiconductor surface. A floating body DRAM cell using a vertical MOSFET has been described in “Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application”, J. Kim et al., pp. 163-164, Symposium of VLSI Technology, 2010, (“J_Kim”) which is incorporated in its entirety by reference herein. In J_Kim, the floating body is bounded by a gate on two sides with a source region above and a buried drain region below. The drain is connected to a tap region, which allows a connection between a conductive plug at the surface to the buried drain region.
• An alternate method of using a standard lateral MOSFET in a floating body DRAM cell is described in co-pending and commonly owned U.S. Patent Application Publication 2010/0034041 to Widjaja (“Widjaja”), which is incorporated in its entirety by reference herein. Widjaja describes a standard lateral MOSFET floating body DRAM cell realized in bulk silicon with a buried well and a substrate which forms a vertical silicon controlled rectifier (SCR) with a P1-N2-P3-N4 formed by the substrate, the buried well, the floating body, and the source (or drain) region of the MOSFET respectively. This structure behaves like two bipolar junction transistor (BJT) devices coupled together—one an n-p-n (N2-P3-N4) and one a p-n-p (P3-N2-P1)—which can be manipulated to control the charge on the floating body region (P3).
• The construction and operation of standard MOSFET devices is well known in the art. An exemplary standard metal-oxide-semiconductor field effect transistor (MOSFET)device100 is shown inFIG. 90A.MOSFET device100 consists of a substrate region of a first conductivity type82 (shown as p-type in the figure), and first andsecond regions84 and86 of a second conductivity type (shown as n-type) on thesurface88, along with agate90, separated from the semiconductor surface region by an insulatinglayer92.Gate90 is positioned in between theregions84 and86. Insulatinglayers96 can be used to separate one transistor device from other devices on thesilicon substrate82.
• As shown inFIG. 90B, astandard MOSFET device100A may also consist of awell region94A of a first conductivity type (shown as p-type in the figure) in asubstrate region82A of a second conductivity type (shown as n-type in the figure), with first andsecond regions84A and86A of a second conductivity type on thesurface88A. In addition, agate90A, separated from thesurface region88A by an insulatinglayer92A, is also present in between the first andsecond regions84A and86A. Insulatinglayers96A can be used to separate one transistor device from other devices in thewell region94A.MOSFET devices100 and100A are both constructed in bulk silicon CMOS technology.
• As shown inFIG. 90C, astandard MOSFET device100B is shown constructed out of silicon-on-insulator technology.MOSFET device100B consists of a tub region of afirst conductivity type82B (shown as p-type in the figure), and first andsecond regions84B and86B of a second conductivity type (shown as n-type) on thesurface88B, along with a gate90B, separated from the semiconductor surface region by an insulating layer92B. Gate90B is positioned in between theregions84B and86B. Thetub region82B is isolated from other devices on the sides by insulatinglayers96B and on the bottom by insulatinglayer83B. Optionally, there may be a conductive layer affixed to the bottom of insulatinglayer83B (not shown) which may be used as a “back gate” by coupling through the insulatinglayer83B to thetub region82B.
• Thetransistors100,100A, and100B are all called n-channel transistors because when turned on by applying an appropriate voltage to thegates90,90A and90B respectively, the p-material under the gates is inverted to behave like n-type conductivity type for as long as the gate voltage is applied. This allows conduction between the two n-type regions84 and86 inMOSFET100,84A and86A inMOSFET100A and84B and86B inMOSFET100B. As is well known in the art, the conductivity types of all the regions may be reversed (i.e., the first conductivity type regions become n-type and the second conductivity type regions become p-type) to produce p-channel transistors. In general, n-channel transistors are be preferred for use in memory cells (of all types and technologies) because of the greater mobility of the majority carrier electrons (as opposed to the majority carrier holes in p-channel transistors) allowing more read current for the same sized transistor, but p-channel transistors may be used as a matter of design choice.
• The invention below describes a semiconductor memory device having an electrically floating body that utilizes a back bias region to further reduce the memory device size. One or more bits of binary information may be stored in a single memory cell. Methods of construction and of operation of the semiconductor device are also provided.
• This disclosure uses the standard convention that p-type and n-type semiconductor “diffusion” layers or regions (regardless of how formed during manufacture) such as transistor source, drain or source/drain regions, floating bodies, buried layers, wells, and the semiconductor substrate as well as related insulating regions between the diffusion regions (like, for example, silicon dioxide whether disposed in shallow trenches or otherwise) are typically considered to be “beneath” or “below” the semiconductor surface—and the drawing figures are generally consistent with this convention by placing the diffusion regions at the bottom of the drawing figures. The convention also has various “interconnect” layers such as transistor gates (whether constructed of metal, p-type or n-type polysilicon or some other material), metal conductors in one or more layers, contacts between diffusion regions at the semiconductor surface and a metal layer, contacts between the transistor gates and a metal layer, vias between two metal layers, and the various insulators between them (including gate insulating layers between the gates and a diffusion at the semiconductor surface) are considered to be “above” the semiconductor surface—and the drawing figures are generally consistent with this convention placing these features, when present, near the top of the figures. One exception worth noting is that gates may in some embodiments be constructed in whole or in part beneath the semiconductor surface. Another exception is that some insulators may be partially disposed both above and below the surface. Other exceptions are possible. Persons of ordinary skill in the art will appreciate that the convention is used for ease of discussion with regards to the standard way of drawing and discussing semiconductor structures in the literature, and that a physical semiconductor in use in an application may be deployed at any angle or orientation without affecting its physical or electrical properties thereby.
• The exemplary embodiments disclosed herein have at most one surface contact from the semiconductor region below the semiconductor surface to the interconnect region above the semiconductor surface within the boundary of the memory cell itself. This is in contrast to one-transistor (1T) floating body cell (FBC) DRAMs of the prior art which have two contacts—one for the source region and one for the drain region of the transistor. While some 1T FBC DRAM cells of the prior art can share the two contacts with adjacent cells resulting in an average of one contact per cell, some embodiments of the present invention can also share its contact with an adjacent cell averaging half a contact per cell.
• The advantage of the present invention is in the elimination of one of the source/drain regions at the surface of the semiconductor region thereby eliminating the need to contact it at the surface. Compare, for example,FIG. 90B illustrating a prior art MOSFET withFIG. 35C illustrating an analogous cross section of one embodiment of the present invention. In any processing technology, the structure ofFIG. 35C is inherently smaller than the structure ofFIG. 90B. In some embodiments of the present invention, the gate terminal is removed as well further reducing the size of the memory cell. Compare, for example, the analogous cross sections of the structures inFIGS. 77C and 85C to the prior art MOSFET ofFIG. 90B. This new class of memory cell is referred to as a “Half Transistor Memory Cell” as a convenient shorthand for identical, similar or analogous structures. A structure identical, similar or analogous to the structure ofFIG. 35C is referred to as a “Gated Half Transistor Memory Cell.” A structure identical, similar or analogous to the structures ofFIGS. 77C and 85C is referred to as a “Gateless Half Transistor Memory Cell.” The vertical arrangement of the diffusion regions beneath the semiconductor surface common to all half transistor memory cells—specifically a bit line region at the surface of the semiconductor (allowing coupling to a bit line disposed above the semiconductor surface), a floating body region (for storing majority charge carriers, the quantity of majority carriers determining the logical state of the data stored in memory cell), and a source line region (completely beneath the semiconductor surface within the boundary of the memory cell allowing coupling to a source line running beneath the semiconductor surface, typically running beneath and coupling to a plurality of memory cells), wherein the bit line region, the floating body, and the source line region form a vertical bipolar junction transistor that is used operatively and constructed deliberately by design for use in a floating body DRAM memory cell application—is referred to as a “Half Transistor.”
• Persons of ordinary skill in the art will appreciate that the following embodiments and methods are exemplary only for the purpose of illustrating the inventive principles of the invention. Many other embodiments are possible and such alternate embodiments and methods will readily suggest themselves to such skilled persons after reading this disclosure and examining the accompanying drawing. Thus the disclosed embodiments are exemplary only and the present invention is not to be limited in any way except by the appended claims.
• Drawing figures in this specification, particularly diagrams illustrating semiconductor structures, are drawn to facilitate understanding through clarity of presentation and are not drawn to scale. In the semiconductor structures illustrated, there are two different conductivity types: p-type where the majority charge carriers are positively charged holes that typically migrate along the semiconductor valence band in the presence of an electric field, and n-type where the majority charge carriers are negatively charged electrons that typically migrate along the conduction band in the presence of an electric field. Dopants are typically introduced into an intrinsic semiconductor (where the quantity of holes and electrons are equal and the ability to conduct electric current is low: much better than in an insulator, but far worse than in a region doped to be conductive—hence the “semi-” in “semiconductor”) to create one of the conductivity types.
• When dopant atoms capable of accepting another electron (known and “acceptors”) are introduced into the semiconductor lattice, the “hole” where an electron can be accepted becomes a positive charge carrier. When many such atoms are introduced, the conductivity type becomes p-type and the holes resulting from the electrons being “accepted” are the majority charge carriers. Similarly, when dopant atoms capable of donating another electron (known and “donors”) are introduced into the semiconductor lattice, the donated electron becomes a negative charge carrier. When many such atoms are introduced, the conductivity type becomes n-type and the “donated” electrons are the majority charge carriers.
• As is well known in the art, the quantities of dopant atoms used can vary widely over orders of magnitude of final concentration as a matter of design choice. However it is the nature of the majority carries and not their quantity that determines if the material is p-type or n-type. Sometimes in the art, heavily, medium, and lightly doped p-type material is designated p+, p and p− respectively while heavily, medium, and lightly doped n-type material is designated n+, n and n− respectively. Unfortunately, there are no precise definitions of when a “+” or a “−” is an appropriate qualifier, so to avoid overcomplicating the disclosure the simple designations p-type and n-type abbreviated “p” or “n” respectively are used without qualifiers throughout this disclosure. Persons of ordinary skill in the art will appreciate that there are many considerations that contribute to the choice of doping levels in any particular embodiment as a matter of design choice.
• Numerous different exemplary embodiments are presented. In many of them there are common characteristics, features, modes of operation, etc. When like reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.
• FIGS. 35A through 35E illustrate an embodiment of a gated half transistor FBC DRAM memory cell according to the present invention.FIG. 35A shows a top view of an embodiment of a partial memory array including memory cell250 (shown by a dotted line) andFIG. 35B showsmemory cell250 in isolation.FIGS. 35C and 35D show thememory cell250 cross sections along the I-I′ line and II-II′ cut lines, respectively, whileFIG. 35E shows a method for electrically contacting the buried well and substrate layers beneath the cell.
• Referring toFIGS. 35C and 35D together, thecell250 includes asubstrate12 of a first conductivity type such as a p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention,substrate12 can be the bulk material of the semiconductor wafer. In other embodiments,substrate12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, thesubstrate12 will usually be drawn as the semiconductor bulk material as it is inFIGS. 35C and 35D.
• A buriedlayer22 of a second conductivity type such as n-type, for example, is provided in thesubstrate12.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can also be grown epitaxially on top ofsubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top bybit line region16 and insulatinglayer62, on the sides by insulatinglayers26 and28, and on the bottom by buriedlayer22. Floatingbody24 may be the portion of theoriginal substrate12 above buriedlayer22 if buriedlayer22 is implanted. Alternatively, floatingbody24 may be epitaxially grown. Depending on how buriedlayer22 and floatingbody24 are formed, floatingbody24 may have the same doping assubstrate12 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.
• Insulatinglayers26 and28 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulatinglayers26 and28 insulatecell250 from neighboringcells250 whenmultiple cells250 are joined in anarray280 to make a memory device as illustrated inFIGS. 38A-38C. Insulatinglayer26 insulates bothbody region24 and buriedregion22 of adjacent cells (seeFIG. 35C), while insulatinglayer28 insulates neighboringbody region24, but not the buriedlayer22, allowing the buriedlayer22 to be continuous (i.e. electrically conductive) in one direction (along the II-II′ direction as shown inFIG. 35D). This connecting of adjacent memory cells together through buriedlayer22 forming a source line beneathadjacent memory cells250 allows the elimination of a contacted source/drain region or an adjacent contacted plug inside the memory cell required in memory cells of the prior art. As can be seen inFIGS. 35A and 35B, there is no contact to the buriedlayer22 at the semiconductor surface inside the boundary ofmemory cell250.
• Abit line region16 having a second conductivity type, such as n-type, for example, is provided in floatingbody region24 and is exposed atsurface14.Bit line region16 is formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region16.
• Agate60 is positioned in between thebit line region16 and insulatinglayer26 and above the floatingbody region24. Thegate60 is insulated from floatingbody region24 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell250 further includes word line (WL) terminal70 electrically connected togate60, bit line (BL) terminal74 electrically connected to bitline region16, source line (SL) terminal72 electrically connected to buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12.
• As shown inFIG. 35E, contact betweenSL terminal72 and buriedlayer22 can be made throughregion20 having a second conductivity type, and which is electrically connected to buriedwell region22, while contact betweensubstrate terminal78 andsubstrate region12 can be made throughregion21 having a first conductivity type, and which is electrically connected tosubstrate region12.
• TheSL terminal72 connected to the buriedlayer region22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor coupled to the body or bulk of the device corresponding toregion82 intransistor100 ofFIG. 90A orregion94A intransistor100A inFIG. 90B. In a floating body DRAM cell, a conductive coupling to the floating body would be counterproductive since it would cease to be a floating body with such a connection. In some embodiments, the p-n junction between the floatingbody24 and the buried well22 coupled to thesource line terminal72 is forward biased to be conductive by applying a negative voltage to thesource line terminal72. In some embodiments, the SL terminal is biased to a positive voltage potential to maintain the charge in the floatingbody region24. In some embodiments, thesource line terminal72 is used in a manner similar to the source line in floating body DRAM cells of the prior art. Thus in variousembodiments SL terminal72 may be used in a manner similar to a back bias terminal, or it may be used like a source line, or it may be used for another purpose entirely. In some embodiments it may be used in two or more of these ways in different operations. Thus both the terms “source line terminal” and “back bias terminal” are used interchangeably in this specification and should be deemed equivalent.
• Comparing the structure of thememory device250, for example, as shown inFIG. 35C to the structure oftransistor devices100,100A and100B inFIGS. 90A through 90C, it can be seen that the memory device of present invention constitutes a smaller structure relative to theMOSFET devices100,100A and100B, where only one region of a second conductivity type is present at the surface of the silicon substrate. Thus,memory cell250 of the present invention provides an advantage that it consists of only one region of second conductivity at the surface (i.e.bit line region16 as opposed toregions84 and86 orregions84A and86A) and hence requires only one contact per memory cell250 (i.e. to create a connection betweenbit line region16 and terminal74).
• Persons of ordinary skill in the art will appreciate that inFIGS. 35A through 35E and that the first and second conductivity types can be reversed inmemory cell250 as a matter of design choice and that the labeling of regions of the first conductivity type as p-type and the second conductivity type as p-type is illustrative only and not limiting in any way. Thus the first and second conductivity types can be p-type and n-type respectively in some embodiments ofmemory cell50 and be n-type and p-type respectively in other embodiments. Further, such skilled persons will realize that the relative doping levels of the various regions of either conductivity type will also vary as a matter of design choice, and that there is no significance to the absence of notation signifying higher or lower doping levels such as p+ or p− or n+ or n− in any of the diagrams.
• A method ofmanufacturing memory cell250 will be described with reference toFIGS. 36A through 36U. These 21 figures are arranged in groups of three related views, with the first figure of each group being a top view, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a horizontal cross section of the top view in the first figure of the group designated II-II′. ThusFIGS. 36A, 36D, 36G, 36J, 36M, 36P and 36S are a series of top views of thememory cell50 at various stages in the manufacturing process,FIGS. 36B, 36E, 36H, 36K, 36N, 36Q and 36T are their respective vertical cross sections labeled I-I′, andFIGS. 36C, 36F, 36I, 36L, 36O, 36R and 36U are their respective horizontal cross sections labeled II-II′. Identical reference numbers fromFIGS. 35A through 35E appearing inFIGS. 36A through 36U represent similar, identical or analogous structures as previously described in conjunction with the earlier drawing figures. Here “vertical” means running up and down the page in the top view diagram and “horizontal” means running left and right on the page in the top view diagram. In a physical embodiment ofmemory cell50, both cross sections are vertical with respect to the surface of the semiconductor device.
• Turning now toFIGS. 36A through 36C, the first steps of the process are seen. In an exemplary 130 nanometer (nm) process a thinsilicon oxide layer102 with a thickness of about 100 A may be grown on the surface ofsubstrate12. This may be followed by a deposition of about 200 A ofpolysilicon layer104. This in turn may be followed by deposition of about 1200 Asilicon nitride layer106. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other numbers of, thicknesses of, and combinations ofprotective layers102,104 and106 may be used as a matter of design choice.
• As shown inFIGS. 36D through 36F, a pattern opening the areas to becometrench108 may be formed using a lithography process. Then thesilicon oxide102,polysilicon104,silicon nitride106 layers may be subsequently patterned using the lithography process and then may be etched, followed by a silicon etch process, creatingtrench108.
• As shown inFIGS. 36G through 36I, a pattern opening the areas to becometrenches112 may be formed using a lithography process, which may be followed by etching of thesilicon oxide102,polysilicon104, silicon nitride layers106, and a silicon trench etch process, creatingtrench112. Thetrench112 is etched such that the trench depth is deeper than that oftrench108. In an exemplary 130 nm process, thetrench108 depth may be about 1000 A and thetrench112 depth may be about 2000 A. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other trench depths may be used as a matter of design choice.
• As shown inFIGS. 36J through 36L, this may be followed by a silicon oxidation step, which will grow silicon oxide films intrench108 andtrench112 which will become insulatinglayers26 and28. In an exemplary 130 nm process, about 4000 A silicon oxide nay be grown. A chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface. A silicon dry etching step can then be performed so that the remaining silicon oxide layer height of insulatinglayers26 and28 may be about 300 A from the silicon surface. In other embodiments the top of insulatinglayers26 and28 may be flush with the silicon surface. Thesilicon nitride layer106 and thepolysilicon layer104 may then be removed which may then be followed by a wet etch process to remove silicon oxide layer102 (and a portion of the silicon oxide films formed in the area offormer trench108 and former trench112). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other insulating layer materials, heights, and thicknesses as well as alternate sequences of processing steps may be used as a matter of design choice.
• As shown inFIGS. 36M through 36O, an ion implantation step may then be performed to form the buriedlayer region22 of a second conductivity (e.g. n-type conductivity). The ion implantation energy is optimized such that the buriedlayer region22 is formed shallower than the bottom of the insulatinglayer26 and deeper than the bottom of insulatinglayer28. As a result, the insulatinglayer26 isolates buriedlayer region22 between adjacent cells while insulatinglayer28 does not isolate buriedlayer region22 between cells. This allows buriedlayer region22 to be continuous in the direction of the II-II′ cross section.Buried layer22 isolates the eventual floatingbody region24 of the first conductivity type (e.g., p-type) from thesubstrate12.
• As shown inFIGS. 36P through 36R, a silicon oxide or high-dielectric materialgate insulation layer62 may then be formed on the silicon surface (e.g. about 100 A in an exemplary 130 nm process), which may then be followed by a polysilicon ormetal gate60 deposition (e.g. about 500 A in an exemplary 130 nm process). A lithography step may then be performed to pattern thelayers62 and60, which may then be followed by etching of the polysilicon and silicon oxide layers. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other gate and gate insulation materials with different thicknesses may be used a matter of design choice.
• As shown inFIGS. 36S through 36U, another ion implantation step may then be performed to form thebit line region16 of a second conductivity type (e.g. n-type conductivity). This may then be followed by backend process to form contact and metal layers (not shown inFIGS. 36A through 36U). Thegate60 and the insulatinglayers26 and28 serve as masking layer for the implantation process such that regions of second conductivity are not formed outsidebit line region16. In this and many subsequent figures,gate layer60 andgate insulating layer62 are shown flush with the edge of insulatinglayer26. In some embodiments,gate layer60 andgate insulating layer62 may overlap insulatinglayer16 to prevent any of the implant dopant forbit line region16 from inadvertently implanting betweengate layer60 andgate insulating layer62 and the adjacent insulatinglayer26.
• The states ofmemory cell250 are represented by the charge in the floatingbody24. Ifcell250 is positively charged due to holes stored in the floatingbody region24, then the memory cell will have a lower threshold voltage (the gate voltage where an ordinary MOSFET transistor is turned on—or in this case, the voltage at which an inversion layer is formed under gate insulating layer62) compared to ifcell250 does not store holes inbody region24.
• The positive charge stored in the floatingbody region24 will decrease over time due to the diode leakage current of the p-n junctions formed between the floatingbody24 andbit line region16 and between the floatingbody24 and the buriedlayer22 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells of the array.
• As shown inFIG. 37A, the holding operation can be performed by applying a positive back bias to buriedlayer22 through theSL terminal72 while simultaneously grounding thebit line region16 through theBL terminal74 and grounding thesubstrate12 throughsubstrate terminal78. The positive back bias applied to the buried layer region connected to the SL terminal will maintain the state of thememory cell250 that it is connected to. The holding operation is relatively independent of the voltage applied togate60 throughword line terminal70. In some embodiments of the invention, the word line terminal may be grounded. Inherent in thememory cell250 is n-p-nbipolar device30 formed by buried well region22 (the collector region), floating body24 (the base region), and bit line region16 (the emitter region).
• If floatingbody24 is positively charged, a state corresponding to logic-1, thebipolar transistor30 formed bybit line region16, floatingbody24, and buried wellregion22 will be turned on due to an impact ionization mechanism like that described with reference to Lin cited above. In particular, the voltage across the reversed biased p-n junction between the floatingbody24 and the buriedwell region22 will cause a small current to flow across the junction. Some of the current will be in the form of hot carriers accelerated by the electric field across the junction. These hot carriers will collide with atoms in the semiconductor lattice which will generate hole-electron pairs in the vicinity of the junction. The electrons will be swept into the buriedlayer region22 by the electric field, while the holes will be swept into the floatingbody region24.
• The hole current flowing into the floating region24 (usually referred to as the base current) will maintain the logic-1 state data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by buriedwell region22, floatingregion24, and bitline region16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofSL terminal72 to the base current flowing into the floatingregion24.
• FIG. 37B shows the energy band diagram of the intrinsic n-p-nbipolar device30 when the floatingbody region24 is positively charged and a positive bias voltage is applied to the buriedwell region22. The dashed lines indicate the Fermi levels in the various regions of then-p-n transistor30. The Fermi level is located in the band gap between thesolid line17 indicating the top of the valance band (the bottom of the band gap) and thesolid line19 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. The positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floatingbody region24, the electrons will be swept into the buried well region22 (connected to SL terminal72) due to the positive bias applied to the buriedwell region22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theSL terminal72 while the resulting hot holes will subsequently flow into the floatingbody region24. This process restores the charge on floatingbody24 and will maintain the charge stored in the floatingbody region24 which will keep the n-p-nbipolar transistor30 on for as long as a positive bias is applied to the buriedwell region22 throughSL terminal72.
• If floatingbody24 is neutrally charged (the voltage on floatingbody24 being equal to the voltage on grounded bit line region16), a state corresponding to logic-0, no current will flow through then-p-n transistor30. Thebipolar device30 will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
• FIG. 37C shows the energy band diagram of the intrinsic n-p-nbipolar device30 when the floatingbody region24 is neutrally charged and a bias voltage is applied to the buriedwell region22. In this state the energy level of the band gap bounded bysolid lines17A and19A is different in the various regions of n-p-nbipolar device30. Because the potential of the floatingbody region24 and thebit line region16 is equal, the Fermi levels are constant, resulting in an energy barrier between thebit line region16 and the floatingbody region24.Solid line23 indicates, for reference purposes, the energy barrier between thebit line region16 and the floatingbody region24. The energy barrier prevents electron flow from the bit line region16 (connected to BL terminal74) to the floatingbody region24. Thus the n-p-nbipolar device30 will remain off.
• The difference between an impact ionization write logic-1 operation as described with reference to Lin cited above and a holding operation is that during a holding operation thegate60 is not biased at a higher voltage than normal during a holding operation. During a write logic-1 operation, the capacitive coupling from thegate60 to the floatingbody region24 forces the n-p-nbipolar device30 on regardless of the data stored in the cell. By contrast, without the gate boost a holding operation only generates carriers through impact ionization when a memory cell stores a logic-1 and does not generate carries through impact ionization when a memory cell stores a logic-0.
• In the embodiment discussed inFIGS. 37A through 37C,bipolar device30 has been an n-p-n transistor. Persons of ordinary skill in the art will readily appreciate that by reversing the first and second connectivity types and inverting the relative values of the appliedvoltages memory cell50 could comprise abipolar device30 which is a p-n-p transistor. Thus the choice of an n-p-n transistor is an illustrative example for simplicity of explanation inFIGS. 37A through 37C is not limiting in any way.
• FIG. 38A shows anexemplary array280 of memory cells250 (four exemplary instances ofmemory cell250 being labeled as250a,250b,250cand250d) arranged in rows and columns. In many, but not all, of the figures whereexemplary array280 appears,representative memory cell250awill be representative of a “selected”memory cell250 when the operation being described has one (or more in some embodiments) selectedmemory cells250. In such figures,representative memory cell250bwill be representative of anunselected memory cell250 sharing the same row as selectedrepresentative memory cell250a,representative memory cell250cwill be representative of anunselected memory cell250 sharing the same column as selectedrepresentative memory cell250a, andrepresentative memory cell250dwill be representative of amemory cell250 sharing neither a row or a column with selectedrepresentative memory cell250a.
• Present inFIG. 38A areword lines70athrough70n, source lines72athrough72n,bit lines74athrough74p, andsubstrate terminal78. Each of the word lines70athrough70nis associated with a single row ofmemory cells250 and is coupled to thegate60 of eachmemory cell250 in that row. Similarly, each of the source lines72athrough72nis associated with a single row ofmemory cells50 and is coupled to the buriedwell region22 of eachmemory cell50 in that row. Each of the bit lines74athrough74pis associated with a single column ofmemory cells50 and is coupled to thebit line region16 of eachmemory cell50 in that column. In the holding operation described inFIGS. 37A through 37C, there is no individually selected memory cell. Rather cells are selected in rows by the source lines72athrough72nand may be selected as individual rows, as multiple rows, or as all of therows comprising array280.
• Substrate12 is present at all locations underarray280. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals78 will be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that whileexemplary array280 is shown as a single continuous array inFIG. 38A, that many other organizations and layouts are possible like, for example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray280 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed aroundexemplary array280 or inserted between sub-arrays ofarray280. Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.
• Turning now toFIG. 38B,array280 previously discussed is shown along withmultiplexers40athrough40nandvoltage waveforms42athrough42n. A periodic pulse of positive voltage can be applied to the back bias terminals ofmemory cells250 throughSL terminal72 as opposed to applying a constant positive bias to reduce the power consumption of thememory cell250.FIG. 38B further showsmultiplexers40athrough40neach coupled to one of the source lines72athrough72nthat determine the bias voltages applied toSL terminals72athrough72n, which will be determined by different operating modes. The pulsing of the voltage on the SL terminals may be controlled, for example, by applying pulses of logic signals likewaveforms42athrough42nto the select input ofmultiplexers40athrough40nthereby selecting, for example, ground (0.0 volts) or a power supply voltage such as V_cc. Many other techniques may be used to pulse the voltage applied toSL terminals72athrough72nlike, for example, applying thewaveforms42athrough42nat different times, or applying them simultaneously, or coupling the select inputs ofmultiplexers42athrough42ntogether and applying a single pulsed waveform to all of themultiplexers42athrough42nsimultaneously (not shown in the figure). Many other options will readily suggest themselves to persons of ordinary skill in the art. Thus the described exemplary embodiments are not limiting in any way.
• FIG. 38C shows another method to provide voltage pulses toSL terminals72athrough72nofexemplary array280 ofmemory cells250. The positive input signals to multiplexers40athrough40nmay be generated byvoltage generator circuits44athrough44ncoupled to one input of each of themultiplexers40athrough40n. Alternatively, a single voltage generator circuit may be coupled to each of themultiplexers40athrough40nreducing the amount of overhead circuitry required to refresh thememory cells250 ofarray280. Other embodiments are possible including, for example, applying thewaveforms42athrough42nat different times, or applying them simultaneously, or coupling the select inputs ofmultiplexers42athrough42ntogether and applying a single pulsed waveform to all of themultiplexers42athrough42nsimultaneously (not shown in the figure).
• FIG. 38D shows a reference generator circuit suitable for use asreference generator circuits44athrough44ninFIG. 38C. The reference generator includes reference cell53, which consists of a modified version of Gated halftransistor memory cell250 described above withregion25 of the first conductivity type (p-type conductivity). The p-type25 region allows for a direct sensing of the floatingbody region24 potential.Region25 is drawn separately even though it has the same conductivity type as floatingbody region24 because it may be doped differently to facilitate contacting it. The reference cell53 for example can be configured to be in state logic-1 where the potential of the floatingbody region24 is positive, for example at +0.5V. The potential sensed through the p-type region is then compared with a reference value V_REF, e.g. +0.5V, byoperational amplifier27. If the potential of the floatingbody region24 is less than the reference value, the voltage applied to the back bias terminal72 (which is connected to buriedregion22 of the reference cell53 and can also be connected to buriedregion22 of the Gated half transistor memory cell250) is increased byoperational amplifier27 until the potential of the floatingbody region24 reaches the desired reference voltage. If the potential of the floatingbody24 region is higher than that of the reference value, the voltage applied to backbias terminal72 can be reduced byoperational amplifier27 until the potential of the floatingbody region24 reaches the desired reference voltage. Reference voltage V_REFmay be generated in many different ways like, for example, using a band gap reference, a resistor string, a digital-to-analog converter, etc. Similarly alternate voltage generators of types known in the art may be used
• As shown inFIG. 39, the holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floatingbody24. Without the holding/standby operation, the maximum potential that can be stored in the floatingbody24 is limited to the flat band voltage V_FBas the junction leakage current from floatingbody24 tobit line region16 increases exponentially at floating body potential greater than V_FB. However, by applying a positive voltage toSL terminal72, the bipolar action results in a hole current flowing into the floatingbody24, compensating for the junction leakage current between floatingbody24 andbit line region16. As a result, the maximum charge V_MCstored in floatingbody24 can be increased by applying a positive bias to theSL terminal72 as shown in the graph inFIG. 39. The increase in the maximum charge stored in the floatingbody24 results in a larger memory window.
• The holding/standby operation can also be used for multi-bit operation inmemory cell250. To increase the memory density without increasing the area occupied by the memory cell, a multi-level operation is typically used. This is done by dividing the overall memory window into more than two different levels. In one embodiment four levels representing two binary bits of data are used, though many other schemes like, for example, using eight levels to represent three binary bits of data are possible. In a floating body memory, the different memory states are represented by different charge in the floatingbody24, as described, for example, in Tack and Oknonin-2 cited above. However, since the state with zero charge in the floatingbody24 is the most stable state, the floatingbody24 will over time lose its charge until it reaches the most stable state. In multi-level operation, the difference of charge representing different states is smaller than a single-level operation. As a result, a multi-level memory cell is more sensitive to charge loss.
• FIG. 40 shows the floatingbody24 net current for different floatingbody24 potential as a function of the voltage applied toSL terminal72 with BL, WL andsubstrate terminals74,70, and78, grounded. When zero voltage is applied toSL terminal72, no bipolar current is flowing into the floatingbody24 and as a result, the stored charge will leak over time. When a positive voltage is applied toSL terminal72, hole current will flow into floatingbody24 and balance the junction leakage current to bitline region16. The junction leakage current is determined by the potential difference between the floatingbody24 andbit line region16, while the bipolar current flowing into floatingbody24 is determined by both theSL terminal72 potential and the floatingbody24 potential. As indicated inFIG. 40, for different floating body potentials, at acertain SL terminal72 potential V_HOLD, the current flowing into floatingbody24 is balanced by the junction leakage between floatingbody24 andbit line region16. The different floatingbody24 potentials represent different charges used to represent different states ofmemory cell50. This shows that different memory states can be maintained by using the holding/standby operation described here.
• In one embodiment the bias condition for the holding operation formemory cell250 is: 0 volts is applied toBL terminal74, a positive voltage like, for example, +1.2 volts is applied toSL terminal72, 0 volts is applied toWL terminal70, and 0 volts is applied to thesubstrate terminal78. In another embodiment, a negative voltage may be applied toWL terminal70. In other embodiments, different voltages may be applied to the various terminals ofmemory cell250 as a matter of design choice and the exemplary voltages described are not limiting in any way.
• The read operation of thememory cell250 andarray280 of memory cells will described in conjunction withFIGS. 41 and 42A through 42H. Any sensing scheme known in the art can be used withmemory cell250. Examples include, for example, the sensing schemes disclosed in Ohsawa-1 and Ohsawa-2 cited above.
• The amount of charge stored in the floatingbody24 can be sensed by monitoring the cell current of thememory cell250. Ifmemory cell250 is in a logic-1 state having holes in thebody region24, then the memory cell will have a higher cell current (e.g. current flowing from theBL terminal74 to SL terminal72), compared to ifcell250 is in a logic-0 state having no holes in floatingbody region24. A sensing circuit typically connected toBL terminal74 can then be used to determine the data state of the memory cell.
• A read operation may be performed by applying the following bias condition to memory cell250: a positive voltage is applied to the selectedBL terminal74, and an even more positive voltage is applied to the selectedWL terminal70, zero voltage is applied to the selectedSL terminal72, and zero voltage is applied to thesubstrate terminal78. This has the effect of operatingbipolar device30 as a backward n-p-n transistor in a manner analogous to that described for operatingbipolar device30 for a hold operation as described in conjunction withFIGS. 37A through 37C. The positive voltage applied to theWL terminal70 boosts the voltage on the floatingbody region24 by means of capacitive coupling from thegate60 to the floatingbody region24 throughgate insulating layer62. This has the effect of increasing the current inbipolar device30 when it is on significantly more than it increases the current when it is off, thus making it easier to sense the data stored in thememory cell250. The optimal bias voltage to apply toWL terminal70 will vary from embodiment to embodiment and process to process. The actual voltage applied in any given embodiment is a matter of design choice.
• FIG. 41 showsarray280 ofmemory cells250 during a read operation in one exemplary embodiment of the present invention. Reading amemory cell250 inarray280 is more complicated than reading a single cell as described above, since cells are coupled together along rows byword lines70athrough70nandsource lines72athrough72nand coupled together along columns bybit lines74athrough74p. In one exemplary embodiment, about 0.0 volts is applied to the selected SL terminal72a, about +0.4 volts is applied to the selectedbit line terminal74a, about +1.2 volts is applied to the selectedword line terminal70a, and about 0.0 volts is applied tosubstrate terminal78. All the unselectedbit line terminals74b(not shown) through74phave 0.0 volts applied, the unselectedword line terminals70b(not shown) through70nhave 0.0 volts applied, and theunselected SL terminals72b(not shown) have +1.2 volts applied.FIG. 41 shows the bias conditions for the selectedrepresentative memory cell250aand three unselectedrepresentative memory cells250b,250c, and250dinmemory array280, each of which has a unique bias condition. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
• FIG. 42A also shows the bias condition of the selectedrepresentative memory cell250ain cross section whileFIG. 42B shows the equivalent circuit diagram illustrating the intrinsic n-p-nbipolar device30 under the read bias conditions described above.
• The three cases forunselected memory cells250 during read operations are shown inFIGS. 42C, 42E, and 42G, while illustrations of the equivalent circuit diagrams are shown inFIGS. 42D, 42F, and 42H respectively. The bias conditions formemory cells250 sharing the same row (e.g.representative memory cell250b) and those sharing the same column (e.g.,representative memory cell250c) as the selectedrepresentative memory cell250aare shown inFIGS. 42C-42D andFIGS. 42E-42F, respectively, while the bias condition formemory cells250 not sharing the same row nor the same column as the selectedrepresentative memory cell250a(e.g.,representative memory cell250d) is shown inFIG. 42G-42H.
• As shown inFIGS. 42C and 42D, forrepresentative memory cell250bsharing the same row as the selectedrepresentative memory cell250a, theSL terminal72ais now grounded and consequently these cells will not be at the holding mode. However, because a read operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the hole charge in the floating body24 (on the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 42E and 42F,representative memory cell250csharing the same column as the selectedmemory cell250a, a positive voltage is applied to theBL terminal74a. Less base current will flow into the floatingbody24 due to the smaller potential difference between SL terminal72nand BL terminal74a(i.e. the emitter and collector terminals of the n-p-n bipolar device30). However, because read operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (on the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 42G and 42H,representative memory cell250dsharing neither the same row nor the same column as the selectedrepresentative memory cell250a, theSL terminal72nwill remain positively charged and theBL terminal74pwill remain grounded. As can be seen, these cells will be in the holding mode, where memory cells in the logic-1 state will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24 and memory cells in the logic-0 state will remain in neutral state.
• The read operation of thememory cell250 andarray280 of memory cells have been described in conjunction withFIGS. 41 through 42H. Persons of ordinary skill in the art will realize that the drawing figures are not drawn to scale, that the various voltages described are illustrative only and will vary from embodiment to embodiment, that embodiments discussed have been illustrative only, and that many more embodiments employing the inventive principles of the invention are possible. For example, the two conductivity types may be reversed and the relative voltages of the various signals may be inverted, thememory array280 may be built as a single array or broken into sub-arrays, the accompanying control circuits may be implemented in different ways, different relative or absolute voltage values may be applied tomemory cell250 orarray280, etc. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• A first type of write logic-0 operation of anindividual memory cell250 is now described with reference toFIGS. 43A and 43B. InFIG. 43A, a negative voltage bias is applied to the back bias terminal (i.e. SL terminal72), a zero voltage bias is applied toWL terminal70, a zero voltage bias is applied toBL terminal72 andsubstrate terminal78. Under these conditions, the p-n junction between floatingbody24 and buried well22 of the selectedcell250 is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −0.5 volts is applied to sourceline terminal72, about 0.0 volts is applied toword line terminal70, and about 0.0 volts is applied tobit line terminal74 andsubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• InFIG. 43B, an alternative embodiment ofmemory cell250 is shown wheresubstrate12 is replaced byregion12A of the first conductivity type (p-type in the figure) which is a well insidesubstrate29 of the second conductivity type (n-type in the figure). This arrangement overcomes an undesirable side effect of the embodiment ofFIG. 43A where lowering the buriedwell region22 voltage on buried well terminal72 to approximately −0.5V to forward bias the p-n junction between buried well22 and floatingbody24 also forward biases the p-n junction between buried well22 andsubstrate12 resulting in unwanted substrate current. The embodiment ofFIG. 43B allows thewell12A to be lowered by applying the same voltage to well terminal78 as buriedlayer terminal72 thus preventing the p-n diode between those regions to forward bias. Thesubstrate29 is preferably biased to 0.0V throughsubstrate terminal31 as shown inFIG. 43B. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice, Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 44 shows an example of bias conditions for the selected andunselected memory cells250 during the first type of write logic-0 operation (as described inFIG. 43A) inmemory array280. For the selectedrepresentative memory cells250aand250b, the negative bias applied toSL terminal72acauses large potential difference between floatingbody24 and buried wellregion22. Because the buried well22 is shared amongmultiple memory cells250, logic-0 will be written into allmemory cells250 includingmemory cells250aand250bsharing thesame SL terminal72asimultaneously.
• FIGS. 45A through 45B illustrate an example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-nbipolar devices30 ofunselected memory cells250 likerepresentative memory cells250cand250dinarray280 during the first type of logic-0 write operations. In particularrepresentative memory cell250dwill be discussed for clarity of presentation though the principles apply to allunselected memory cells250. Since the logic-0 write operation only involves a negative voltage to the selected SL terminal72a, thememory cells250 coupled to theunselected SL terminals72b(not shown inFIG. 44) through72nare placed in a holding operation by placing a positive bias condition onSL terminals72bthrough72n. As can be seen inFIGS. 45A and 45B, the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero voltage, and the unselected SL terminal positively biased.
• As shown inFIG. 46, a second type of write logic-0 operation can also be performed by applying a negative bias to theBL terminal74 as opposed to theSL terminal72. InFIG. 46, the selectedmemory cells250 includerepresentative memory cells250aand250cand all thememory cells250 that share the selectedbit line74a. TheSL terminal72 will be positively biased, while zero voltage is applied to thesubstrate terminal78, and zero voltage is applied to theWL terminal70. Under these conditions, all memory cells sharing thesame BL terminal74 will be written to the logic-0 state.
• The first and second types of write logic-0 operations referred to above each has a drawback that allmemory cells250 sharing either the same SL terminal72 (the first type—row write logic-0) or thesame BL terminal74 will (the second type—column write logic-0) be written to simultaneously and as a result, does not allow writing logic-0 toindividual memory cells250. To write arbitrary binary data todifferent memory cells250, a write logic-0 operation is first performed on all the memory cells to be written followed by one or more write logic-1 operations on the bits that must be written to logic-1.
• A third type of write logic-0 operation that allows for individual bit writing can be performed onmemory cell250 by applying a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, and zero voltage tosubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between24 andbit line region16 is forward-biased, evacuating any holes from the floatingbody24.
• To reduce undesired write logic-0 disturb toother memory cells250 in thememory array280, the applied potential can be optimized as follows: if the floatingbody24 potential of state logic-1 is referred to as V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. Additionally, either ground or a slightly positive voltage may also be applied to theBL terminals74 ofunselected memory cells250 that do not share thesame BL terminal74 as the selectedmemory cell250, while a negative voltage may also be applied to theWL terminals70 ofunselected memory cells250 that do not share thesame WL terminal70 as the selectedmemory cell250.
• As illustrated inFIG. 47, the following bias conditions are applied to the selectedrepresentative memory cell250ainexemplary memory array280 to perform an individual write logic-0 operation exclusively inrepresentative memory cell250a: a potential of about 0.0 volts toSL terminal72a, a potential of about −0.2 volts toBL terminal74a, a potential of about +0.5 volts is applied toword line terminal70a, and about 0.0 volts is applied tosubstrate terminal78. In the rest ofarray280 about +1.2 volts is applied to unselected SL terminals72 (includingSL terminal72n), about 0.0 volts (or possibly a slightly positive voltage) is applied to unselected BL terminals74 (includingBL terminal74p), and about 0.0 volts is applied to unselected WL terminal70 (includingWL terminal70n). Persons of ordinary skill in the art will appreciate that the voltage levels inFIG. 47 are illustrative only and that different embodiments will have different voltage levels as a matter of design choice.
• The bias conditions shown inFIG. 47 of the selectedrepresentative memory cell250ainmemory array280 to perform the individual bit write logic-0 operation are further illustrated inFIGS. 48A and 48B. As discussed above, the potential difference between floatingbody24 andbit line region16 connected toBL terminal74ais now increased due to the capacitive coupling from raising WL terminal70afrom ground to +0.5V, resulting in a higher forward bias current than the base hole current generated by the n-p-nbipolar device30 formed by buriedwell region22 connected toSL terminal72a, floatingbody24, and bitline region16. The result is that holes will be evacuated from floatingbody24.
• Theunselected memory cells250 inmemory array280 under the bias conditions ofFIG. 47 during the individual bit write logic-0 operation are shown inFIGS. 48C through 48H. The bias conditions for memory cells sharing the same row (e.g.representative memory cell250b) as the selectedrepresentative memory cell250aare illustrated inFIGS. 48C and 48D, and the bias conditions for memory cells sharing the same column (e.g.representative memory cell250c) as the selectedrepresentative memory cell250aare shown inFIGS. 48E and 48F, and the bias conditions for memory cells sharing neither the same row nor the same column (e.g.representative memory cell250d) as the selectedrepresentative memory cell250aare shown inFIGS. 48G and 48H.
• As shown inFIGS. 48C and 48D, the floatingbody24 potential ofmemory cell250bsharing the same row as the selectedrepresentative memory cell250awill increase due to capacitive coupling fromWL terminal70 by ΔV_FB. For memory cells in state logic-0, the increase in the floatingbody24 potential is not sustainable as the forward bias current of the p-n diodes formed by floatingbody24 andjunction16 will evacuate holes from floatingbody24. As a result, the floatingbody24 potential will return to the initial state logic-0 equilibrium potential. For memory cells in state logic-1, the floatingbody24 potential will initially also increase by ΔV_FB, which will result in holes being evacuated from floatingbody24. After the positive bias on theWL terminal70 is removed, the floatingbody24 potential will decrease by ΔV_FB. If the initial floatingbody24 potential of state logic-1 is referred to as V_FB1, the floatingbody24 potential after the write logic-0 operation will become V_FB1−ΔV_FB. Therefore, the WL potential needs to be optimized such that the decrease in floating body potential ofmemory cells50 in state logic-1 is not too large during the time when the positive voltage is applied to (and subsequently removed from)WL terminal70a. For example, the maximum floating body potential increase due to the coupling from the WL potential cannot exceed V_FB1/2. Thus in some embodiments it may be advantageous to have a slightly positive voltage onunselected BL terminal74p. This means thatbipolar device30 can only evacuate holes in reverse operation (e.g., only the p-n junction between the floatingbody24 and buried well22 will be on enough to evacuate holes from the floating body region24) which may minimize the reduction of holes in floatingbody region24 in the logic-1 state.
• As shown inFIGS. 48E and 48F, forrepresentative memory cell250csharing the same column as the selectedrepresentative memory cell250a, a negative voltage is applied to theBL terminal74a, resulting in an increase in the potential difference between floatingbody24 andbit line region16 connected to theBL terminal74a. As a result, the p-n diode formed between floatingbody24 andbit line region16 will be forward biased. For memory cells in the logic-0 state, the increase in the floatingbody24 potential will not change the initial state from logic-0 as there is initially no hole stored in the floatingbody24. For memory cells in the logic-1 state, the net effect is that the floatingbody24 potential after write logic-0 operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential ofmemory cells250 in state logic-1 is not too large during the time when the negative voltage is applied toBL terminal74a. For example, the −V_FB1/2 is applied to theBL terminal74a.
• As shown inFIGS. 48G and 48H,memory cell250dsharing neither the same row nor the same column as the selectedrepresentative memory cell250a, these cells will be in a holding mode as positive voltage is applied to theSL terminal72n, zero voltage is applied to theBL terminal74p, and zero or negative voltage is applied toWL terminal70n, and zero voltage is applied tosubstrate terminal78.
• Three different methods for performing a write logic-0 operation onmemory cell250 have been disclosed. Many other embodiments and component organizations are possible like, for example, reversing the first and second conductivity types while inverting the relative voltage biases applied. Anexemplary array280 has been used for illustrative purposes, but many other possibilities are possible like, for example, applying different bias voltages to the various array line terminals, employing multiple arrays, performing multiple single bit write logic-0 operations to multiple selected bits in one or more arrays or by use of decoding circuits, interdigitating bits so as to conveniently write logic-0s to a data word followed by writing logic-1s to selected ones of those bits, etc. Such embodiments will readily suggest themselves to persons of ordinary skill in the art familiar with the teachings and illustrations herein. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• A write logic-1 operation may be performed onmemory cell250 through impact ionization as described, for example, with reference to Lin cited above, or through a band-to-band tunneling mechanism (also known as Gate Induced Drain Leakage or GIDL), as described, for example with reference to Yoshida cited above. An example of a write logic-1 operation using the GIDL method is described in conjunction withFIGS. 49 and 50A through 50H while an example of a write logic-1 operation using the impact ionization method is described in conjunction withFIGS. 51 and 52A through 52H.
• InFIG. 49 an example of the bias conditions of thearray280 including selectedrepresentative memory cell250aduring a band-to-band tunneling write logic-1 operation is shown. The negative bias applied to theWL terminal70aand the positive bias applied to theBL terminal74aresults in hole injection to the floatingbody24 of the selectedrepresentative memory cell250a. TheSL terminal72aand thesubstrate terminal78 are grounded during the write logic-1 operation.
• The negative voltage onWL terminal70 couples the voltage potential of the floatingbody region24 inrepresentative memory cell250adownward. This combined with the positive voltage onBL terminal74acreates a strong electric field between thebit line region16 and the floatingbody region24 in the proximity of gate60 (hence the “gate induced” portion of GIDL) in selectedrepresentative memory cell250a. This bends the energy bands sharply upward near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current (hence the “drain leakage” portion of GIDL), while the holes are injected into floatingbody region24 and become the hole charge that creates the logic-1 state. This process is well known in the art and is illustrated in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above.
• As shown inFIGS. 50A through 50B, the following bias conditions may be applied to the selectedrepresentative memory cell250a: a potential of about 0.0 volts is applied toSL terminal72a, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about −1.2 volts is applied toWL terminal70a, and about 0.0 volts is applied tosubstrate terminal78.
• Elsewhere inarray280 the following bias conditions are applied to the terminals forunselected memory cells250 includingrepresentative memory cells250b,250cand250d: about +1.2 volts is applied toSL terminal72n, about 0.0 volts is applied toBL terminal74p, a potential of about 0.0 volts is applied toWL terminal70n, and about 0.0 volts is applied tosubstrate terminal78.FIG. 49 shows the bias condition for the selected and unselected memory cells inmemory array280. However, these voltage levels may vary from embodiment to embodiment of the present invention and are exemplary only and are in no way limiting.
• The unselected memory cells during write logic-1 operations are shown inFIGS. 50C through 50H. The bias conditions for memory cells sharing the same row (e.g.representative memory cell250b) are shown inFIGS. 50C and 50D. The bias conditions for memory cells sharing the same column as the selectedrepresentative memory cell250a(e.g.representative memory cell250c) are shown inFIGS. 50E and 50F. The bias conditions formemory cells250 not sharing the same row nor the same column as the selectedrepresentative memory cell250a(e.g.representative memory cell250d) are shown inFIGS. 50G and 50H.
• As illustrated inFIGS. 50C and 50D,representative memory cell250b, sharing the same row as the selectedrepresentative memory cell250a, has bothterminals72aand74pgrounded, while about −1.2 volts is applied toWL terminal70a. BecauseSL terminal70ais grounded,memory cell250bwill not be at the holding mode since there is no voltage across between the emitter and collector terminals of the n-p-nbipolar device30 turning it off. However, because the write logic-1 operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As illustrated inFIGS. 50E and 50F, forrepresentative memory cell250csharing the same column as the selected memory cell, a positive voltage is applied to theBL terminal74n. No base current will flow into the floatingbody24 because there is no potential difference between SL terminal72nand BL terminal74a(i.e. there is no voltage between the emitter and collector terminals of the n-p-nbipolar device30 turning it off). However, because a write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As illustrated inFIGS. 50G and 50H, formemory cell250dsharing neither the same row nor the same column as the selected memory cell, theSL terminal72nwill remain positively charged while thegate terminal70nand theBL terminal74premain grounded. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30awill generate holes current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• FIG. 51 shows a write logic-1 operation using the impact ionization method. In this case, both thegate60 and bitline16 of thememory cell250 to be written are biased at a positive voltage. This is similar to the holding operation described earlier in conjunction withFIGS. 37A through 38D which also uses impact ionization to supply hole current to the floatingbody24. However in the holding operation, the n-p-nbipolar device30 stays off when a logic-0 is stored inmemory cell250 and impact ionization current only flows when a logic-1 is stored in the cell restoring the charge level in the floatingbody24 to a full logic-1 level. By contrast, in the case of a write logic-1 operation using impact ionization, the voltage on the gate terminal is positive rather than zero. The action of raising thegate60 to a positive voltage has the effect of raising the voltage potential of the floatingbody region24 due to capacitive coupling across thegate insulating layer62 which causes the n-p-nbipolar transistor30 to turn on regardless of whether or not a logic-1 or logic-0 is stored inmemory cell250. This causes impact ionization current to flow charging the floatingbody24 to the logic-1 state regardless of the data originally stored in the cell.
• In the exemplary embodiment shown inFIG. 51, the selectedword line terminal70ais biased at about +1.2V while the unselectedword line terminals70b(not shown) through70nare biased at about 0.0V, the selectedbit line terminal74ais also biased at about +1.2V while the unselectedbit line terminals74bthrough74pare biased at about 0.0V, the selectedsource line72ais biased at about 0.0V, while the unselectedsource line terminals72b(not shown) through72nare biased at about +1.2V, and thesubstrate terminal78 is biased at about 0.0V. These voltage bias levels are exemplary only and will vary from embodiment to embodiment and are thus in no way limiting.
• As shown inFIGS. 52A through 52B, selectedrepresentative memory cell50ais shown withgate60 coupled to WL terminal70A biased at +1.2V,bit line region16 coupled toBL terminal74abiased at +1.2V, and buriedlayer22 coupled to sourceline terminal72abiased at 0.0V. In this state, impact ionization current flows into the cell from BL terminal74ainjecting holes into the floatingbody region24 writing a logic-1 state intorepresentative memory cell250a.
• As shown inFIGS. 52C through 52D, unselectedrepresentative memory cell250b, sharing a row but not a column with selectedrepresentative memory cell250a, is shown withgate60 coupled toWL terminal70abiased at +1.2V,bit line region16 coupled toBL terminal74pbiased at 0.0V, and buriedlayer22 coupled to sourceline terminal72abiased at 0.0V. In this state, the collector-to-emitter voltage of n-p-nbipolar device30 is 0.0V causing the device to be off protecting the contents ofrepresentative memory cell250b.
• As shown inFIGS. 52E through 52F, unselectedrepresentative memory cell250c, sharing a column but not a row with selectedrepresentative memory cell250a, is shown withgate60 coupled toWL terminal70nbiased at 0.0V,bit line region16 coupled toBL terminal74abiased at +1.2V, and buriedlayer22 coupled to sourceline terminal72nbiased at +1.2V. In this state, the n-p-nbipolar device30 will be off since there is no voltage difference between the collector and emitter terminals of n-p-nbipolar device30.
• As shown inFIGS. 52G through 52H, unselectedrepresentative memory cell250d, sharing neither a row nor a column with selectedrepresentative memory cell250a, is shown withgate60 coupled toWL terminal70nbiased at 0.0V,bit line region16 coupled toBL terminal74pbiased at 0.0V, and buriedlayer22 coupled to sourceline terminal72nbiased at +1.2V. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30awill generate holes current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• FIG. 53A shows a top view of an embodiment of a partial memory array including Gated halftransistor memory cell350 according to the present invention andFIG. 53B showsmemory cell350 in isolation.FIGS. 53C and 53D show thememory cell350 cross sections along the I-I′ line and II-II′ cut lines, respectively, whileFIG. 53E shows a method of contacting the buried well and substrate layers beneath the cells.FIGS. 54A through 54Hshow memory array380 comprised of rows and columns ofmemory cell350. The primary difference betweenmemory cell250 andmemory cell350 is that while insulatinglayers26 isolate the buriedlayer22 between memory cells in adjacent rows inmemory cell250, inmemory cell350 the regions occupied by insulatinglayer26 are replaced by insulatinglayer28. Thusmemory cell350 is surrounded by insulatinglayer28 on all four sides and the buriedlayer22 is continuously connected as a single “source line” amongst all of thememory cells350 inmemory array380. This makes for a memory array that is very similar tomemory array280, however some operations will be different as described below in conjunction withFIGS. 54A through 54F. As was the case withmemory cell250 inmemory cell280, there is no contact to the buriedlayer22 within the boundary ofmemory cell350.
• Referring toFIGS. 53C and 53D together, thecell350 includes asubstrate12 of a first conductivity type such as a p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention,substrate12 can be the bulk material of the semiconductor wafer. In other embodiments,substrate12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, thesubstrate12 will is drawn as the semiconductor bulk material as it is inFIGS. 53C and 53D though it may also be a well in a substrate of material of the second type of conductivity.
• A buriedlayer22 of a second conductivity type such as n-type, for example, is provided in thesubstrate12.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can also be grown epitaxially on top ofsubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top bybit line region16 an insulatinglayer62, on the sides by insulatinglayer28, and on the bottom by buriedlayer22. Floatingbody24 may be the portion of theoriginal substrate12 above buriedlayer22 if buriedlayer22 is implanted. Alternatively, floatingbody24 may be epitaxially grown. Depending on how buriedlayer22 and floatingbody24 are formed, floatingbody24 may have the same doping assubstrate12 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.
• Insulating layers28 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulatinglayers28 insulatecell350 from neighboringcells350 whenmultiple cells350 are joined in anarray380 to make a memory device as illustrated inFIGS. 54A-54F. Insulatinglayer28 insulates neighboringbody regions24, but not the buriedlayer22, allowing the buriedlayer22 to be continuous (i.e. electrically conductive) under theentire array380.
• Abit line region16 having a second conductivity type, such as n-type, for example, is provided in floatingbody region24 and is exposed atsurface14.Bit line region16 is formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region16.
• Agate60 is positioned in between thebit line region16 and insulatinglayer28 and above the floatingbody region24. Thegate60 is insulated from floatingbody region24 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Memory cell350 further includes word line (WL) terminal70 electrically connected togate60, bit line (BL) terminal74 electrically connected to bitline region16, source line (SL) terminal72 electrically connected to buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12.
• As shown inFIG. 53E, contact betweenSL terminal72 and buriedlayer22 can be made throughregion20 having a second conductivity type, and which is electrically connected to buriedwell region22, while contact betweensubstrate terminal78 andsubstrate region12 can be made throughregion21 having a first conductivity type, and which is electrically connected tosubstrate region12.
• TheSL terminal72 connected to the buriedlayer region22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor.
• Comparing the structure of thememory device350, for example, as shown inFIG. 53C to the structure oftransistor devices100,100A and100B inFIGS. 90A through 90C, it can be seen that the memory device of present invention constitutes a smaller structure relative to theMOSFET devices100,100A and100B, where only one region of a second conductivity type is present at the surface of the silicon substrate. Thus,memory cell350 of the present invention provides an advantage that it consists of only one region of second conductivity at the surface (i.e.bit line region16 as opposed toregions84 and86 orregions84A and86A) and hence requires only one contact per memory cell350 (i.e. to create a connection betweenbit line region16 and terminal74).
• Persons of ordinary skill in the art will appreciate that inFIGS. 53A through 53E and that the first and second conductivity types can be reversed inmemory cell350 as a matter of design choice and that the labeling of regions of the first conductivity type as p-type and the second conductivity type as p-type is illustrative only and not limiting in any way. Thus the first and second conductivity types can be p-type and n-type respectively in some embodiments ofmemory cell350 and be n-type and p-type respectively in other embodiments. Further, such skilled persons will realize that the relative doping levels of the various regions of either conductivity type will also vary as a matter of design choice and that there is no significance to the absence of notation signifying higher or lower doping levels such as p+ or p− or n+ or n− in any of the diagrams.
• FIG. 54A shows anexemplary memory array380 of memory cells350 (four exemplary instances ofmemory cell350 being labeled as350a,350b,350cand350d) arranged in rows and columns. In many, but not all, of the figures whereexemplary memory array380 appears,representative memory cell350awill be representative of a “selected”memory cell350 when the operation being described has one (or more in some embodiments) selectedmemory cells350. In such figures,representative memory cell350bwill be representative of anunselected memory cell350 sharing the same row as selectedrepresentative memory cell350a,representative memory cell350cwill be representative of anunselected memory cell350 sharing the same column as selectedrepresentative memory cell350a, andrepresentative memory cell350dwill be representative of amemory cell350 sharing neither a row or a column with selectedrepresentative memory cell350a.
• Present inFIG. 54A areword lines70athrough70n, source line terminal72X,bit lines74athrough74p, andsubstrate terminal78. Each of the word lines70athrough70nis associated with a single row ofmemory cells350 and is coupled to thegate60 of eachmemory cell350 in that row. Each of the bit lines74athrough74pis associated with a single column ofmemory cells350 and is coupled to thebit line region16 of eachmemory cell350 in that column. It is noteworthy that while the source line terminal72X is really no longer a control line terminal associated with thesource line72 of a row ofmemory cells350 but a control terminal associated with all of thememory cells350 inexemplary memory array380, it will still be referred to as “source line” terminal72X to minimize confusion since it still serves that function for eachindividual memory cell350.
• Substrate12 and buriedlayer22 are both present at all locations underarray380. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals78 and one or more buriedwell terminals72 will be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that whileexemplary array380 is shown as a single continuous array inFIG. 54A, that many other organizations and layouts are possible like, for example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray380 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed aroundexemplary array380 or inserted between sub-arrays ofarray380. Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.
• FIG. 54B illustrates an array hold operation onexemplary memory array380. For allmemory cells350 in thearray380, the hold operation is performed simultaneously by applying about +1.2V to thesource line terminal72 while applying about 0.0V to theword line terminals70athrough70n, thebit line terminals74athrough74p, and thesubstrate terminal78. This bias condition causes each of thememory cells350 in thearray380 storing a logic-1 to have its intrinsicbipolar transistor30 turned on to restore the hole charge on its floatingbody24 as discussed above. Simultaneously, this bias condition causes each of thememory cells350 in thearray380 storing a logic-0 to have its intrinsicbipolar transistor30 turned off to retain charge neutrality in its floatingbody24 as previously discussed. The voltages applied are exemplary only, may vary from embodiment to embodiment and are in no way limiting.
• FIG. 54C illustrates a single cell read operation of selectedrepresentative memory cell350ainexemplary memory array350. To accomplish this, the selectedword line terminal70ais biased to approximately +1.2V while the unselectedword line terminals70b(not shown) through70nare biased to about 0.0V, the selectedbit line terminal74ais biased to approximately +0.4V while the unselectedbit line terminals74bthrough74pare biased to about 0.0V, thesource line terminal72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
• This has the effect of operatingbipolar device30 as a backward n-p-n transistor in a manner analogous to that described for operatingbipolar device30 for a hold operation as described in conjunction withFIGS. 37A through 37C.
• The capacitive coupling between theword line terminal70aand the floatingbody24 of selectedmemory cell350aincrease the differentiation in the read current between the logic-1 and logic-0 states as previously described. The optimal bias voltage to apply toWL terminal70 will vary from embodiment to embodiment and process to process. The actual voltage applied in any given embodiment is a matter of design choice.
• Unselectedrepresentative memory cell350b, which shares a row with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
• Unselectedrepresentative memory cell350c, which shares a column with selectedrepresentative memory cell350a, will either be off or be in a weak version of the holding operation depending on the device characteristics of the process of any particular embodiment. It also retains its logic state during the short duration of the read operation.
• Unselectedrepresentative memory cell350d, which shares neither a row nor a column with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
• FIG. 54D illustrates an array write logic-0 operation of all thememory cells350 inexemplary memory array350. To accomplish this, all theword line terminals70athrough70nare biased to approximately 0.0V, all thebit line terminals74athrough74pare biased to approximately −1.2V, thesource line terminal72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
• This bias condition forward biases the p-n junction between the floatingbody24 and thebit line region16 turning on the intrinsicbipolar device30 in each of thememory cells350 as previously described. This evacuates all of the holes in the floatingbody regions24 writing a logic-0 to all of thememory cells350 inarray380.
• FIG. 54E illustrates a column write logic-0 operation of one column of thememory cells350 inexemplary memory array350. To accomplish this, all theword line terminals70athrough70nare biased to approximately 0.0V, selected thebit line terminal74ais biased to approximately −1.2V while the unselectedbit line terminals74bthrough74pare biased to about 0.0V, thesource line terminal72 is biased to about +1.2V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
• This bias condition forward biases the p-n junction between the floatingbody24 and thebit line region16 turning on the intrinsicbipolar device30 in each of thememory cells350 coupled tobit line74a, includingrepresentative memory cells350aand350c, as previously described. This evacuates all of the holes in the floatingbody regions24 writing a logic-0 to all of thememory cells350 in the selected column.
• The remainingmemory cells350 inarray380, includingrepresentative memory cells350band350d, are in a holding operation and will retain their logic state during the write logic-0 operation.
• FIG. 54F illustrates a single cell write logic-0 operation of selectedrepresentative memory cell350ainexemplary memory array350. To accomplish this, the selectedword line terminal70ais biased to approximately +0.5V while the unselectedword line terminals70b(not shown) through70nare biased to about −1.2V, the selectedbit line terminal74ais biased to approximately −0.2V while the unselectedbit line terminals74bthrough74pare biased to about 0.0V, thesource line terminal72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
• This bias condition forward biases the p-n junction between the floatingbody24 and thebit line region16 turning on the intrinsicbipolar device30 in selectedrepresentative memory cell350a. The capacitive coupling between theword line terminal70aand the floatingbody24 of selectedmemory cell350acausesbipolar device30 to turn on evacuating the holes in floatingbody region24 as previously described.
• Unselectedrepresentative memory cell350b, which shares a row with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
• Unselectedrepresentative memory cell350c, which shares a column with selectedrepresentative memory cell350a, has the voltage potential of its floating body temporarily lowered because the negative capacitive coupling between its floatingbody24 its gate60 (coupled toword line terminal70n) preventing itsbipolar device30 from turning on. It also retains its logic state during the short duration of the read operation, and the voltage potential of its floatingbody24 is restored to its previous level by the positive coupling between its floatingbody24 its gate60 (coupled toword line terminal70n) when the word line terminal is returned to its nominal value of about 0.0V after the operation is complete.
• Unselectedrepresentative memory cell350d, which shares neither a row nor a column with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
• FIG. 54G illustrates a single cell write logic-1 operation using a GIDL mechanism in selectedrepresentative memory cell350ainexemplary memory array350. To accomplish this, the selectedword line terminal70ais biased to approximately −1.2V while the unselectedword line terminals70b(not shown) through70nare biased to about 0.0V, the selectedbit line terminal74ais biased to approximately +1.2V while the unselectedbit line terminals74bthrough74pare biased to about 0.0V, thesource line terminal72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
• This bias condition causes selectedrepresentative memory cell350ato conduct current due to the GIDL mechanism discussed with reference to Yoshida cited above. The combination of −1.2V on word line terminal and +1.2V onbit line terminal74acreates the strong electric field necessary to produce GIDL current frombit line74aintorepresentative memory cell350agenerating sufficient hole charge in its floatingbody24 to place it in the logic-1 state.
• Unselectedrepresentative memory cell350b, which shares a row with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
• Unselectedrepresentative memory cell350c, which shares a column with selectedrepresentative memory cell350a, is in the holding state. It also retains its logic state during the short duration of the write logic-1 operation.
• Unselectedrepresentative memory cell350d, which shares neither a row nor a column with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
• FIG. 54H illustrates a single cell write logic-1 operation using an impact ionization mechanism in selectedrepresentative memory cell350ainexemplary memory array350. To accomplish this, the selectedword line terminal70ais biased to approximately +1.2V while the unselectedword line terminals70b(not shown) through70nare biased to about 0.0V, the selectedbit line terminal74ais biased to approximately +1.2V while the unselectedbit line terminals74bthrough74pare biased to about 0.0V, thesource line terminal72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V. The voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
• This bias condition causes selectedrepresentative memory cell350ato conduct current due to the impact ionization mechanism discussed with reference to Lin cited above. The combination of +1.2V on word line terminal and +1.2V onbit line terminal74aturns on thebipolar device30 inrepresentative memory cell350aregardless of its prior logic state and generating sufficient hole charge in its floatingbody24 to place it in the logic-1 state.
• Unselectedrepresentative memory cell350b, which shares a row with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
• Unselectedrepresentative memory cell350c, which shares a column with selectedrepresentative memory cell350a, is in the holding state. It also retains its logic state during the short duration of the write logic-1 operation.
• Unselectedrepresentative memory cell350d, which shares neither a row nor a column with selectedrepresentative memory cell350a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
• In the previous embodiments, a single binary bit has been written to, read from, and maintained in asingle memory cell250 or350. While this approach makes for the simplest support circuitry, the simplest operating methods, and the largest noise margins, greater memory density may be achieved by storing two or more bits permemory cell250 or350 at the cost of increasing the complexity of the support circuitry and operating methods. Additionally, the noise margin is also reduced because the voltage window insidememory cell250 or350 is shared by more than two logic levels.
• Preferably the information stored inmemory cell250 or350 corresponds to an integer number of binary bits, meaning that the number of voltage levels stored inmemory cell50 or350 will be equal to a power of two (e.g., 2, 4, 8, 16, etc.), though other schemes are possible within the scope of the invention. Due to the lower noise margins, it may be desirable to encode the data inmemory array80 or380 using any error correction code (ECC) known in the art. In order to make the ECC more robust, the voltage levels inside may be encoded in a non-binary order like, for example, using a gray code to assign binary values to the voltage levels. In the case of gray coding, only one bit changes in the binary code for a single level increase or decrease in the voltage level. Thus for an example a two bit gray encoding, the lowest voltage level corresponding to the floatingbody region24 voltage being neutral might be encoded as logic-00, the next higher voltage level being encoded as logic-01, the next higher voltage level after that being encoded as logic-11, and the highest voltage level corresponding to the maximum voltage level on floatingbody region24 being encoded as logic-10. In an exemplary three bit gray encoding, the logic levels from lowest to highest might be ordered logic-000, logic-001, logic-011, logic-010, logic-110, logic-111, logic-101, and logic-100. Since the most likely reading error is to mistake one voltage level for one of the two immediately adjacent voltage levels, this sort of encoding ensures that a single level reading error will produce at most a single bit correction per error minimizing the number of bits needing correction for any single error in a single cell. Other encodings may be used, and this example is in no way limiting.
• A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to thememory cell250 or350, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to thememory cell250 or350, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
• For example, using band-to-band hot hole injection to writememory cell250 or350, initially zero voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, a negative voltage is applied toWL terminal70, and zero voltage is applied to thesubstrate terminal78. Then positive voltages of different amplitudes are applied toBL terminal74 to write different states to floatingbody24. This results in different floatingbody potentials24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied toBL terminal74. Note thatmemory cell250 or350 must be written to the lowest voltage state on floatingbody region24 prior to executing this algorithm.
• In one particular non-limiting embodiment, the write operation is performed by applying the following bias condition: a potential of about 0.0 volts is applied toSL terminal72, a potential of about −1.2 volts is applied toWL terminal70, and about 0.0 volts is applied tosubstrate terminal78, while the potential applied toBL terminal74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied toBL terminal74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever binary value of 00, 01, 11 or 10 is desired is achieved), then the multi-level write operation is successfully concluded. If the desired state is not achieved, then the voltage applied toBL terminal74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary from embodiment to embodiment and the above voltage levels are exemplary only and in no way limiting. To write four levels to the memory cells, at least three different positive voltage pulses (which may comprise of different amplitudes) to theBL terminal74 are required. The first pulse corresponds to writing the memory cell to the level associated with the binary value of 01, the second pulse corresponds to writing the memory cell to the level associated with the binary value of 11, and the third pulse corresponds to writing the memory cell to the level associated with the binary value of 10.
• The write-then-verify algorithm is inherently slow since it requires multiple write and read operations. The present invention provides a multi-level write operation that can be performed without alternate write and read operations as described inFIGS. 55A through 55F with respect toexemplary memory array280. Persons of ordinary skill in the art will appreciate that the principles described will apply to all of the Half Transistor memory cells within the scope of the present invention.
• As shown inFIG. 55A, the potential of the floatingbody24 increases over time as a result of hole injection to floatingbody24, for example through an impact ionization mechanism. Once the change in cell current reaches the level associated with the desired state of the selectedrepresentative memory cell250, the voltage applied toBL terminal74 can be removed. In this manner, the multi-level write operation can be performed without alternate write and read operations by applying a voltage ramp of the correct duration. After the end of the pulse time, the applied voltage returns to the starting value like, for example, ground. Thus as shown inFIG. 55A, a voltage ramp of pulse width T1 applied to thebit line terminal74 ofmemory cell250 in the lowest (logic-00 state) potential state will increase the potential of the floatingbody24 from the logic-00 level to the logic-01 level. Similarly, a voltage ramp of pulse width T2 applied to thebit line terminal74 ofmemory cell250 in the lowest (logic-00 state) potential state will increase the potential of the floatingbody24 from the logic-00 level to the logic-11 level, and a voltage ramp of pulse width T3 applied to thebit line terminal74 ofmemory cell250 in the lowest (logic-00 state) potential state will increase the potential of the floatingbody24 from the logic-00 level to the logic-10 level.
• InFIG. 55B this is accomplished in selectedrepresentative memory cell250aby ramping the voltage applied toBL terminal74a, while applying zero voltage toSL terminal72a, a positive voltage toWL terminal70, and zero voltage tosubstrate terminal78 of the selected memory cells. These bias conditions will result in a hole injection to the floatingbody24 through an impact ionization mechanism. The state of thememory cell250acan be simultaneously read for example by monitoring the change in the cell current through readcircuitry91acoupled to thesource line72a.
• In the rest ofarray280, zero voltage is applied to theunselected WL terminals70b(not shown) through70n, zero voltage is applied to theunselected SL terminals72b(not shown) through72n, and zero voltage is applied to theunselected BL terminals74bthrough74p. The cell current measured in the source line direction is the total cell current of allmemory cells250 which share thesame source line72a, but all of the unselected cells likerepresentative memory cell50bare biased with zero voltage across them from theirbit line region16 to theirsource line region22 and do not conduct current as long as thesource line terminal72ais correctly biased to maintain zero volts. As a result, only one selectedmemory cell50asharing thesame source line72 can be written at a time.
• InFIG. 55B, the unselectedrepresentative memory cell250bhas zero volts between theBL terminal74pand theSL terminal72aso no current flows and the state of the data stored in them will not change. Unselectedrepresentative memory cell250csharingBL terminal74awith selectedrepresentative memory cell250ahas its WL terminal grounded. Thus its floatingbody region24 does not get the voltage coupling boost that the floatingbody region24 in selectedrepresentative memory cell250agets. A positive bias is also applied to theunselected SL terminal72n. This condition substantially reduces the current inrepresentative memory cell250cwhich reduces the degree of hole charge its floatingbody region24 receives as the voltage applied toBL terminal74ais ramped up. Unselectedrepresentative memory cell250d, sharing neither a row nor a column with selectedrepresentative memory cell250a, is shown withgate60 coupled toWL terminal70nbiased at 0.0V,bit line region16 coupled toBL terminal74pbiased at 0.0V, and buriedlayer22 coupled to sourceline terminal72nbiased at +1.2V. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30awill generate holes current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• FIG. 55B also showsreference generator circuits93athrough93ncoupled respectively to sourceline terminals72athrough72nand readcircuits91athrough91ncoupled respectively to sourceline terminals72athrough72nand coupled respectively toreference generator circuit93athrough93n.Reference generator circuit93aserves to store the initial total cell current of selectedrepresentative memory cell250aand provide this value to readcircuit91aduring the write operation in real time so that the change in current can be monitored and feedback (not shown inFIG. 55B) can be used to shut off the voltage ramp at the appropriate time. This function can be implemented in a variety of ways.
• InFIG. 55C, for example, the cumulative charge of the initial state for selectedmemory cell250asharing thesame source line72acan be stored in acapacitor97a.Transistor95ais turned on when charge is to be written into or read fromcapacitor94.
• Alternatively, as shown inFIG. 55D, reference cells250Ra through250Rn similar to amemory cell250 replacecapacitors97athrough97ninreference generator circuits93athrough93n. The reference cells250Ra through250Rn can also be used to store the initial state of selectedrepresentative memory cell250a.
• In a similar manner, a multi-level write operation using an impact ionization mechanism can be performed by ramping the write current applied toBL terminal74 instead of ramping theBL terminal74 voltage.
• In another embodiment, a multi-level write operation can be performed onmemory cell250 through a band-to-band tunneling mechanism by ramping the voltage applied toBL terminal74, while applying zero voltage toSL terminal72, a negative voltage toWL terminal70, and zero voltage tosubstrate terminal78 of the selectedmemory cells250. Theunselected memory cells250 will remain in holding mode, with zero or negative voltage applied toWL terminal70, zero voltage applied toBL terminal74, and a positive voltage applied toSL terminal72. Optionally,multiple BL terminals74 can be simultaneously selected to write multiple cells in parallel. The potential of the floatingbody24 of the selected memory cell(s)250 will increase as a result of the band-to-band tunneling mechanism. The state of the selected memory cell(s)250 can be simultaneously read for example by monitoring the change in the cell current through a read circuit91 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied toBL terminal74 can be removed. In this manner, the multi-level write operation can be performed without alternate write and read operations.
• Similarly, the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied toBL terminal74 instead of ramping the voltage applied toBL terminal74.
• In another embodiment, as shown inFIG. 55E, a read while writing operation can be performed by monitoring the change in cell current in the bit line direction through areading circuit99acoupled to thebit line74a. In some embodiments a reading circuit99bthrough99p(not shown inFIG. 55E) may be coupled to each bit of theother bit lines74bthrough74p, while in otherembodiments reading circuit99amay be shared between multiple columns using a decoding scheme (not shown).
• Reference cells250R representing different memory states are used to verify the state of the write operation. Thereference cells250R can be configured through a write-then-verify operation, for example, when the memory device is first powered up or during subsequent refresh periods. Thus while selectedrepresentative memory cell250ais being written, selectedreference cell250R containing the desired voltage state (or a similar voltage) to be written is read and the value is used to provide feedback to read circuit so that the write operation may be terminated when the desired voltage level in selectedrepresentative memory cell250ais reached. In some embodiments, multiple columns of reference cells containing different reference values corresponding to the different multilevel cell write values may be present (not shown inFIG. 55E).
• In the voltage ramp operation, the resulting cell current of therepresentative memory cell250abeing written is compared to thereference cell250R current by means of the readcircuitry99a. During this read while writing operation, thereference cell250R is also being biased at the same bias conditions applied to the selectedmemory cell250 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of thereference cell250R.
• As shown inFIG. 55F, for the current ramp operation, the voltage at thebit line74acan be sensed instead of the cell current. In the current ramp operation, a positive bias is applied to thesource line terminal72aand current is forced through theBL terminal74a. The voltage of theBL terminal74awill reflect the state of thememory cell250a. Initially, whenmemory cell250ais in logic-0 state, a large voltage drop is observed across thememory cell250aand the voltage of theBL terminal74awill be low. As the current flow through thememory cell250aincreases, hole injection will increase, resultingmemory cell250ato be in logic-1 state. At the conclusion of the logic-1 state write operation, the voltage drop across thememory cell250awill decrease and an increase in the potential of BL terminal74awill be observed.
• An example of a multi-level write operation without alternate read and write operations, using a read while programming operation/scheme in the bit line direction is given, where two bits are stored permemory cell250, requiring four states to be storable in eachmemory cell250.
• With increasing charge in the floatingbody24, the four states are referred to as states “00”, “01”, “10”, and “11”. To program amemory cell250ato a state “01”, thereference cell250R corresponding to state “01” is activated. Subsequently, the bias conditions described above are applied both to the selectedmemory cell250 and to the “01”reference cell250R: zero voltage is applied to thesource line terminal72, zero voltage is applied to thesubstrate terminal78, a positive voltage is applied to the WL terminal70 (for the impact ionization mechanism), while theBL terminal74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of thereference cell250R does not change.
• The voltage applied to theBL terminal74ais then increased. Consequently, holes are injected into the floatingbody24 of the selectedcell50 and subsequently the cell current of the selectedcell250 increases. Once the cell current of the selectedcell250 reaches that of the “01” reference cell, the write operation is stopped by removing the positive voltage applied to theBL terminal74 andWL terminal70.
• Unselectedrepresentative memory cell250b, which shares a row with selectedrepresentative memory cell250a, has itsbipolar device30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the multi-level write operation.
• Unselectedrepresentative memory cell250c, which shares a column with selectedrepresentative memory cell250a, is in the holding state. Less base current will flow into the floatingbody24 due to the smaller potential difference between SL terminal72nand BL terminal74a(i.e. the emitter and collector terminals of the n-p-n bipolar device30). It also retains its logic state during the short duration of the multi-level write operation.
• Unselectedrepresentative memory cell250d, which shares neither a row nor a column with selectedrepresentative memory cell250a, is in the holding state. It too retains its logic state during the short duration of the multi-level write operation.
• It is noteworthy that the holding operation formemory cell250 in multistate mode is self-selecting. In other words, the quantity of holes injected into the floatingbody24 is proportional to the quantity of holes (i.e., the charge) already present on the floatingbody24. Thus each memory cell selects its own correct degree of holding current.
• FIGS. 56 and 57 show gated halftransistor memory cell250V withFIG. 57 showing the top view of thememory cell250V shown inFIG. 56. Referring now to bothFIGS. 56 and 57, reference numbers previously referred to in earlier drawing figures have the same, similar, or analogous functions as in the earlier described embodiments.Memory cell250V has afin structure52 fabricated onsubstrate12, so as to extend from the surface of the substrate to form a three-dimensional structure, withfin52 extending substantially perpendicular to and above the top surface of thesubstrate12.Fin structure52 is conductive and is built on buried well layer22 which is itself built on top ofsubstrate12. Alternatively, buried well22 could be a diffusion insidesubstrate12 with the rest of thefin52 constructed above it, or buried well22 could be a conductive layer on top ofsubstrate12 connected to all theother fin52 structures in a manner similar tomemory cell350 described above.Fin52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
• Buried well layer22 may be formed by an ion implantation process on the material ofsubstrate12 which may be followed by an etch so that buried well22 is above the portion ofsubstrate12 remaining after the etch. Alternatively, buried well layer22 may be grown epitaxially abovesubstrate22 and the unwanted portions may then be etched away. Buried well layer22, which has a second conductivity type (such as n-type conductivity type), insulates the floatingbody region24, which has a first conductivity type (such as p-type conductivity type), from thebulk substrate12 also of the first conductivity type.Fin structure52 includesbit line region16 having a second conductivity type (such as n-type conductivity type).Memory cell250V further includesgates60 on two opposite sides of the floatingsubstrate region24 insulated from floatingbody24 by insulatinglayers62.Gates60 are insulated from floatingbody24 by insulatinglayers62.Gates60 are positioned between thebit line region16 and the insulatinglayer28, adjacent to the floatingbody24.
• Thus, the floatingbody region24 is bounded by the top surface of thefin52, the facing side and bottom ofbit line region16, top of the buried welllayer22, and insulatinglayers26,28 and62. Insulatinglayers26 and28 insulatecell250V from neighboringcells250V whenmultiple cells250V are joined to make a memory array. Insulatinglayer26 insulates adjacent buriedlayer wells22, while insulatinglayer28 does not. Thus the buriedlayer22 is therefore continuous (i.e. electrically conductive) in one direction. In this embodiment, thesurface14 of the semiconductor is at the level of the top of the fin structure. As in other embodiments, there is no contact to the buriedlayer22 at thesemiconductor surface14 inside the boundary ofmemory cell250V.
• As shown inFIG. 58A, analternate fin structure52A can be constructed. In this embodiment,gates60 and insulatinglayers62 can enclose three sides of the floatingsubstrate region24. The presence of thegate60 on three sides allows better control of the charge in floatingbody region24.
• Memory cell250V can be used to replacememory cell250 in an array similar toarray280 having similar connectivity between the cells and the array control signal terminals. In such a case, the hold, read and write operations are similar to those in the lateral device embodiments described earlier formemory cell250 inarray280. As with the other embodiments, the first and second conductivity types can be reversed as a matter of design choice. As with the other embodiments, many other variations and combinations of elements are possible, and the examples described in no way limit the present invention.
• FIG. 58B shows anarray280V ofmemory cells250V. Due the nature offin structure52A, the most compact layout will typically be with the word lines70 running perpendicular to the source lines72, instead of in parallel as inmemory array280 discussed above. This leads to the structure ofarray580 where thecell250V is constructed usingfin structure52A and the source lines72athrough72prun parallel to the bit lines74athrough74pand orthogonal to the word lines70athrough70m. The operation ofmemory array280V is described in commonly assigned U.S. patent application entitled “COMPACT SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED NUMBER OF CONTACTS, METHODS OF OPERATING AND METHODS OF MAKING,” Attorney Docket No. Zeno-014, Ser. No. 12/897,528, filed on Oct. 4, 2010 and incorporated by reference above.
• FIG. 59A shows another embodiment of a gated half transistor memory cell450 (denoted by a dotted line) according to the present invention.FIG. 59B shows a smaller portion ofFIG. 59A comprising asingle memory cell450 with two cross section lines I-I′ and II-II′.FIG. 23C shows the cross section designated I-I′ inFIG. 59B.FIG. 59D shows the cross section designated II-II′ inFIG. 59B. Present inFIGS. 59A through 59F aresubstrate12,semiconductor surface14,bit line region16, buried welllayer22, floatingbody region24, insulatinglayers26 and28,gate60,gate insulator62,word line terminal70, buried well terminal72,bit line terminal74 andsubstrate terminal78, all of which perform similar functions in the exemplary embodiments ofmemory cell450 as they did in the exemplary embodiments ofmemory cell250 described above.
• Referring now toFIGS. 59A, 59B, 59C and 59D, thecell450 includes asubstrate12 of a first conductivity type, such as a p-type conductivity type, for example.Substrate12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. A buriedlayer22 of the second conductivity type is provided in thesubstrate12.Buried layer22 is also formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can also be grown epitaxially.
• Abit line region16 having a second conductivity type, such as n-type, for example, is provided in floatingbody24 and is exposed atsurface14.Bit line region16 is formed by an implantation process formed on the material making up floatingbody24, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region16.
• A floatingbody region24 of thesubstrate12 is bounded bysurface14,bit line region16, insulatinglayers26 and28 and buriedlayer22. Insulatinglayers26 and28 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 and28 insulatecell450 from neighboringcells450 whenmultiple cells450 are joined in anarray180 to make a memory device as illustrated inFIG. 61A. Insulatinglayer26 insulates both neighboringbody regions24 and buriedregions22 of adjacentcells memory cells450A,450, and450B, while insulatinglayer28 insulates neighboringbody regions24, but not neighboring buriedlayer regions22, allowing the buriedlayer22 to be continuous (i.e. electrically conductive) in one direction in parallel with the II-II′ cut line as shown inFIGS. 59B and 59D. As in other embodiments, there is no contact to the buriedlayer22 at thesemiconductor surface14 inside the boundary ofmemory cell450.
• Agate60 is positioned in betweenbit line regions16 of neighboringcells450 and450A and above thesurface14, the floatingbody regions24, and one of the adjacent insulatinglayers26 as shown inFIG. 59C. In this arrangement, thegate terminal70 is coupled to thegates60 of bothmemory cells450 and450A. Thegate60 is insulated fromsurface14 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. InFIGS. 59A, 59B and 59C, thegate60 is shown above the insulatinglayer26 isolating neighboringcells450 and450A.
• Cell450 further includes word line (WL) terminal70 electrically connected togate60, bit line (BL) terminal74 electrically connected to bitline region16, source line (SL) terminal72 electrically connected to the buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12.
• As shown inFIG. 59E, contact to buriedwell region22 can be made throughregion20 having a second conductivity type, and which is electrically connected to buriedwell region22 and buried well terminal72, while contact tosubstrate region12 can be made throughregion28 having a first conductivity type, and which is electrically connected tosubstrate region12 andsubstrate terminal78. TheSL terminal72 serves as the back bias terminal for thememory cell450.
• As shown inFIG. 59F, the buried well22 (and subsequently SL terminal72) may also be shared between twoadjacent memory cells450 and450B not sharing thesame WL terminal70. In this embodiment, insulatinglayer26A is built to a similar depth as insulatinglayer28 allowing this connection to be made using buried well22. Thus when a plurality ofmemory cells450 are arranged in an array thesource line terminals72 are shared between pairs of adjacent rows ofcells450 and theword line terminals70 are shared between pairs of adjacent rows that are offset by one row from the pairs of rows sharingsource line terminal72. Thus eachmemory cell450 shares a source line terminal with one adjacent cell (e.g.,450B) and aword line terminal70 with another adjacent cell (e.g.,450A). It is worth noting that this connectivity is possible because whenmemory cells450 are mirrored in alternate rows when arrayed, whilememory cell50 is not mirrored when arrayed.
• FIGS. 60A through 60E shown an alternate embodiment ofmemory cell450 where a part of thegate60 can also be formed inside a trench adjacent to the floatingbody regions24 of twoadjacent memory cells450. The primary difference between this embodiment and the one described inFIGS. 59A through 59E is that the insulatinglayers26 in alternate rows adjacent to the floatingbody regions24 and under thegates60 are replaced with a trench labeled26T inFIG. 60C. This trench can be filled withgate insulator62 andgate material60 to form a “T” shaped structure. This allowsgate60 to be adjacent to floatingbody region24 on two sides allowing better control of the charge in floatingbody region24 in response to electrical signals applied togate60 throughword line terminal70. In particular, operations where word line terminal is driven to a positive voltage potential to provide a boost to the voltage potential of the floatingbody24 by means of capacitive coupling will benefit from this arrangement since the capacitance between thegate60 and the floatingbody24 will be substantially increased.
• FIG. 60A shows a top view of one such embodiment of a memory cell450 (denoted by a dotted line) according to the present invention.FIG. 60B shows a smaller portion ofFIG. 60A with two cross section lines I-I′ and II-II′.FIG. 60C shows the cross section designated I-I′ inFIG. 60B.FIG. 60D shows the cross section designated II-II′ inFIG. 60B. Present inFIGS. 60A through 60F aresubstrate12,semiconductor surface14,region16, buried welllayer22, floatingbody region24, insulatinglayers26 and28,gate60,gate insulator62,word line terminal70, buried well terminal72,bit line terminal74 andsubstrate terminal78, all of which perform similar functions in this exemplary embodiment as they did in the earlier exemplary embodiments ofmemory cell450 described above.
• Referring now toFIGS. 60A, 60B, 60C and 60D, thecell450 includes asubstrate12 of a first conductivity type, such as a p-type conductivity type, for example.Substrate12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. A buriedlayer22 of the second conductivity type is provided in thesubstrate12.Buried layer22 is also formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can also be grown epitaxially.
• Aregion16 having a second conductivity type, such as n-type, for example, is provided in floatingbody24 and is exposed atsurface14.Region16 is formed by an implantation process formed on the material making up floatingbody24, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process could be used to formregion16.
• A floatingbody region24 of thesubstrate12 is bounded bysurface14,region16, insulatinglayers26, and28, buriedlayer22, andtrench26T. Insulatinglayers26 and28 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 and28 combined withtrench26T insulatecell450 from neighboringcells450 whenmultiple cells450 are joined in anarray480 to make a memory device as illustrated inFIG. 61A. Insulatinglayer26 andtrench26T together insulate both neighboringbody regions24 and buriedregions22 of adjacentcells memory cells450A,450, and450B, while insulatinglayer28 insulates neighboringbody regions24, but not neighboring buriedlayer regions22, allowing the buriedlayer22 to be continuous (i.e. electrically conductive) in one direction in parallel with the II-II′ cut line as shown inFIGS. 60B and 60D.
• Agate60 is positioned intrench26T in betweenbit line regions16 of neighboringcells450 and450A and above thesurface14 over the floatingbody regions24 forming a “T” shaped structure as shown inFIG. 60C. In this arrangement, thegate terminal70 is coupled to thegates60 of bothmemory cells450 and450A. Thegate60 is insulated from floatingbody regions24 by an insulatinglayer62 both onsurface14 and along the walls and bottom oftrench26T. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. Thetrench26T could be formed through silicon etching process similar to the STI formation after theSTI26 and28 have been formed. Instead of filling thetrench26T with thick oxide,gate oxide62 could be grown after the trench etch, followed bygate60 formation.
• Cell450 further includes word line (WL) terminal70 electrically connected togate60, bit line (BL) terminal74 electrically connected toregion16, source line (SL) terminal72 electrically connected to the buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12.
• As shown inFIG. 60E, contact to buriedwell region22 can be made throughregion20 having a second conductivity type, and which is electrically connected to buriedwell region22 and buried well terminal72, while contact tosubstrate region12 can be made throughregion28 having a first conductivity type, and which is electrically connected tosubstrate region12 andsubstrate terminal78. TheSL terminal72 serves as the back bias terminal for thememory cell450.
• As shown inFIG. 60F, the buried well22 (and subsequently SL terminal72) may also be shared between twoadjacent memory cells450 and450B not sharing thesame WL terminal70. In this embodiment, insulatinglayer26A is built to a similar depth as insulatinglayer28 allowing this connection to be made using buried well22. Thus when a plurality ofmemory cells450 are arranged in an array thesource line terminals72 are shared between pairs of adjacent rows ofcells450 and theword line terminals70 are shared between pairs of adjacent rows that are offset by one row from the pairs of rows sharingsource line terminal72. Thus eachmemory cell450 shares a source line terminal with one adjacent cell (e.g.,450B) and aword line terminal70 with another adjacent cell (e.g.,450A). It is worth noting that this connectivity is possible because whenmemory cells450 are mirrored in alternate rows when arrayed, whilememory cell50 is not mirrored when arrayed.
• Persons of ordinary skill in the art will appreciate that many other embodiments of thememory cell450 other than the exemplary embodiments described in conjunction withFIGS. 59A through 60F are possible. For example, the first and second conductivity types may be reversed as a matter of design choice. Other physical geometries may be used like, for example,substrate12 may be replaced by a well placed in a substrate of the second conductivity type (not shown) as a matter of design choice. Thus the embodiments shown are in no way limiting of the present invention.
• FIG. 61A shows anexemplary memory array480 ofmemory cells450. In theexemplary array480 an embodiment ofmemory cell450 is chosen where word lines70athrough70nare shared between adjacent rows ofmemory cells450 andsource lines72athrough72n+1 are shared between adjacent rows ofmemory cells450 offset by one row. Thus there is onemore source line72 than there arerow lines70 because the top and bottom rows do not have an adjacent row ofmemory cells450 to share source lines72 with. Because theWL terminals70athrough70nandsource line terminals72athrough72n+1 can be shared between neighboring memory cells, asmaller memory array480 may be realized since the effective size ofmemory cell450 is reduced due the shared features. Alternatively, thememory array480 ofmemory cells450 can be arranged with onemore word line70 than there aresource lines72 with the top and bottom rows each not sharingword line70 with adjacent rows.
• As shown inFIG. 61B, the circuit schematic for anindividual memory cell450 is identical to that formemory cell250 as shown inFIG. 37A, the main differences betweenmemory cells250 and450 being the physical construction, relative orientation, and the sharing of control lines. Thus the operating principles ofmemory cell450 will follow the principles of the previously describedmemory cell250. The memory cell operations will be described, realizing that the WL and SL terminals are now shared between neighboring memory cells. Persons of ordinary skill in the art will realize the operation of the embodiments ofmemory cell450 which share word lines70 but haveseparate source lines72 can be handled identically by manipulating the non-shared source lines72 identically or by manipulating them in an analogous manner to other rows in the memory array as a matter of design choice.
• As illustrated inFIG. 62, the holding operation formemory cell450 can be performed in a similar manner to that formemory cell250 by applying a positive bias to the back bias terminal (i.e.SL terminal72 coupled to buried well region22) while groundingbit line terminal74 coupled tobit line region16 andsubstrate terminal78 coupled tosubstrate12. As previously described, the holding operation is relatively independent of the voltage applied to terminal70 which is preferably grounded in some embodiments. Inherent in thememory cell450 is n-p-nbipolar device30 formed by buriedwell region22, floatingbody24, and bitline region16.
• If floatingbody24 is positively charged (i.e. in a logic-1 state), thebipolar transistor30 formed bybit line region16, floatingbody24, and buried wellregion22 will be turned on as discussed above in conjunction withFIGS. 37A through 37C above. A fraction of the bipolar transistor current will then flow into floating body region24 (usually referred to as the base current) and maintain the logic-1 data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by buriedwell region22, floatingregion24, and bitline region16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofSL terminal72 to the base current flowing into the floatingregion24.
• For memory cells in the logic-0 state, the bipolar device will not be turned on, and consequently no base hole current will flow into floatingbody region24 as discussed above in conjunction withFIGS. 37A through 37C above. Therefore, memory cells in state logic-0 will remain in state logic-0.
• A periodic pulse of positive voltage can be applied to theSL terminal72 as opposed to applying a constant positive bias to reduce the power consumption of thememory cell450 in a manner analogous to that described in conjunction withFIGS. 38A through 38D above.
• As illustrated inFIG. 62, an example of the bias condition for a two row holding operation is applied toexemplary memory array480. In one particular non-limiting embodiment, about +1.2 volts is applied toSL terminal72b, about 0.0 volts is applied to the othersource line terminals72aand72c(not shown) through72n+1, about 0.0 volts is applied toBL terminals74athrough74p, about 0.0 volts is applied toWL terminals70athrough70n, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1. This will placerepresentative memory cells450a,450c,450d, and450finto a holding state. These voltage levels are exemplary only may vary substantially as a matter of design choice and processing technology node and are in no way limiting.
• As illustrated inFIGS. 63 and 64A through 64P, the charge stored in the floatingbody24 can be sensed by monitoring the cell current of thememory cell450. Ifcell450 is in a state logic-1 having holes in thebody region24, then the memory cell will have a higher cell current, compared to ifcell450 is in a state logic-0 having no holes inbody region24. A sensing circuit typically connected toBL terminal74 ofmemory array480 can then be used to determine the data state of the memory cell. Examples of the read operation are described with reference to Yoshida, Ohsawa-1, and Ohsawa-2 discussed above.
• The read operation can be performed by applying the following bias condition to memory cell450: a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70, zero voltage is applied to the selectedSL terminal72, and zero voltage is applied to thesubstrate terminal78. The unselected BL terminals will remain at zero voltage, the unselected WL terminals will remain at zero voltage, and the unselected SL terminals will remain at positive voltage.
• The bias conditions for an exemplary embodiment for a read operation for theexemplary memory array480 are shown inFIG. 63, while the bias conditions during a read operation for selectedrepresentative memory cell450aare further illustrated inFIGS. 64A through 64B and the bias conditions during a read operation for the seven cases illustrated by unselectedrepresentative memory cells450bthrough450hduring read operations are further shown inFIGS. 64C through 64P. In particular, the bias conditions for unselectedrepresentative memory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedrepresentative memory cell450aare shown inFIGS. 64C through 64D. The bias conditions for unselectedrepresentative memory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedrepresentative memory cell450aare shown inFIGS. 64E through 64F. The bias conditions for unselectedrepresentative memory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedrepresentative memory cell450aare shown inFIGS. 64G through 64H.FIGS. 64I through 64J show the bias conditions for unselectedrepresentative memory cell450esharing thesame WL terminal70abut neither thesame SL terminal72 norBL terminal74 as the selectedrepresentative memory cell450a.FIGS. 64K through 64L show the bias conditions for unselectedrepresentative memory cell450fsharing thesame SL terminal72bbut neither thesame WL terminal70 norBL terminal74 as the selectedrepresentative memory cell450a. The bias conditions for unselectedrepresentative memory cell450gsharing thesame BL terminal74aas the selectedrepresentative memory cell450abut not thesame WL terminal70 norSL terminal72 is shown inFIGS. 64M through 64N. The bias condition forrepresentative memory cell450hnot sharing any control terminals as the selectedrepresentative memory cell450ais shown inFIGS. 64O through 64P.
• In one particular non-limiting and exemplary embodiment illustrated inFIGS. 63, 64A and 64B, the bias conditions for selectedrepresentative memory cell450aand are shown. In particular, about 0.0 volts is applied to the selectedSL terminal72b, about +0.4 volts is applied to the selectedbit line terminal74a, about +1.2 volts is applied to the selectedword line terminal70a, and about 0.0 volts is applied to substrate terminal78 (not shown inFIG. 64B).
• In the remainder ofexemplary array480, the unselectedbit line terminals74bthrough74premain at 0.0 volts, the unselectedword line terminals70bthrough70nremain at 0.0 volts, and theunselected SL terminals72aand72c(not shown inFIG. 63) through72n+1 remain at +1.2 volts.FIGS. 64C through 64P show in more detail the unselectedrepresentative memory cells450b-450hinmemory array480. It is noteworthy that these voltage levels are exemplary only may vary substantially as a matter of design choice and processing technology node, and are in no way limiting.
• As shown inFIGS. 63, 64C and 64D,representative memory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the representative selectedmemory cell450a, both the BL and SL terminal are positively biased. The potential difference between the BL and SL terminals (i.e. the emitter and collector terminals of the bipolar device30) is lower compared to the memory cells in the holding mode, reducing the base current flowing to the floatingbody24. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 63, 64E and 64F,representative memory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedrepresentative memory cell450a, both theWL terminal72band theSL terminal72 are grounded with the BL terminal positively biased. As a result,memory cell450cwill still be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24; while memory cells in state logic-0 will remain in neutral state.
• As shown inFIGS. 63, 64G and 64H,representative memory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedrepresentative memory cell450a, both theSL terminal72bandBL terminal74bare grounded with theWL terminal70aat +1.2V. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlyrepresentative memory cell450dis no longer in holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 63, 64I and 64J,representative memory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedrepresentative memory cell450a, the SL terminal remains positively biased. As a result,memory cell450ewill still be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24; while memory cells in state logic-0 will remain in the neutral state.
• As shown inFIGS. 63, 64K and 64L,representative memory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedrepresentative memory cell450a, both theSL terminal72 andBL terminal74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cells450fis no longer in holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 63, 64M and 64N,representative memory cell450gsharing thesame BL terminal74abut not thesame WL terminal70 norSL terminal72 as the selectedrepresentative memory cell450a, a positive voltage is applied to theBL terminal74. Less base current will flow into the floatingbody24 due to the smaller potential difference betweenSL terminal72 and BL terminal74 (i.e. the emitter and collector terminals of the n-p-n bipolar device30). However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 63, 64O and 64P,representative memory cells450hnot sharing WL, BL, and SL terminals as the selectedrepresentative memory cell450a, both theSL terminal72 will remain positively charged and the BL terminal remain grounded (FIGS. 64O-64P). As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24; while memory cells in state logic-0 will remain in the neutral state.
• It is noteworthy that the voltage levels described in all the different cases above are exemplary only may vary substantially from embodiment to embodiment as a matter of both design choice and processing technology node, and are in no way limiting.
• A two row write logic-0 operation of thecell450 is now described with reference toFIG. 65. A negative bias may be applied to the back bias terminal (i.e. SL terminal72), zero potential may be applied toWL terminal70, zero voltage may be applied toBL terminal72 andsubstrate terminal78. Theunselected SL terminal72 will remain positively biased. Under these conditions, the p-n junction between floatingbody24 and buried well22 of the selectedcell50 is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −0.5 volts is applied toterminal72, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminal74 and78. However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above.
• InFIG. 65, the selectedSL terminal72bis biased at about −0.5V while theunselected SL terminals72a, and72c(not shown) through72n+1 are biased at about +1.2V, theWL terminals70athrough70nare biased at about 0.0V, theBL terminals74athrough74pare biased at about 0.0V and thesubstrate terminals78athrough78n+1 are biased at about 0.0V. In some embodiments where the substrate is really a well in another substrate (not shown), the substrate terminals may be biased at about −0.5V to avoid unwanted current from the selectedSL terminal72b. This condition causes all of thememory cells450 coupled toSL terminal72b, including the selectedrepresentative memory cells450a,450c,450d, and450f, to be written to the logic-0 state.
• FIGS. 65, 66A and 66B show an example of bias conditions for the selected andunselected memory cells450 during a two row write logic-0 operation inmemory array480. For the selected memory cells, includingrepresentative memory cells450a,450c,450dand450f, the negative bias applied toSL terminal72 causes large potential difference between floatingbody24 and buried wellregion22. This causes the hole charge in the floatingbody24 to be discharged as discussed above. Because the buried well22 is shared amongmultiple memory cells50, allmemory cells450 sharing thesame SL terminal72 will be written into state logic-0.
• An example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-nbipolar devices30 ofunselected memory cells450, includingrepresentative memory cells450b,450e,450gand450h, during write logic-0 operations are illustrated inFIGS. 66A through 66B. Since the write logic-0 operation only involves a negative voltage to the selectedSL terminal72, the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero or negative voltage, and the unselected SL terminal positively biased.
• As illustrated inFIG. 67, a single column write logic-0 operation can be performed by applying a negative bias to theBL terminal74 as opposed to the SL terminal72 (as inFIGS. 65, 66A, and 66B). TheSL terminal72 will be positively biased, while zero voltage is applied to thesubstrate terminal78, and zero voltage is applied to theWL terminal70. Under these conditions, all memory cells sharing thesame BL terminal74 will be written into state logic-0 while all theother memory cells450 in thearray480 will be in the holding state.
• InFIG. 67, selected BL terminal74amay be biased at about −1.2V while theunselected BL terminals74bthrough74pmay be biased at about 0.0V, theWL terminals70athrough70nmay be biased at about 0.0V, thesource line terminals72athrough27n+1 may be biased at +1.2V, and thesubstrate terminals78athrough78n+1 may be biased at 0.0V. This condition causes all of thememory cells450 coupled toBL terminal74a, including the selectedrepresentative memory cells450a,450b,450c, and450g, to be written to the logic-0 state while the remainingmemory cells450, including unselectedrepresentative memory cells450d,450e,450f, and450h, to be in a holding operation. These voltage levels are exemplary only may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.
• As illustrated inFIGS. 68 and 69A through 69P, a single cell write logic-0 operation that allows for individual bit writing can be performed by applying a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, and zero voltage tosubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between floatingbody24 andbit line region16 is forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write logic-0 disturb toother memory cells450 in thememory array480, the applied potential can be optimized as follows: if the floatingbody24 potential of state logic-1 is referred to V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell450a: a potential of about 0.0 volts toSL terminal72b, a potential of about −0.2 volts toBL terminal74a, a potential of about +0.5 volts is applied toWL terminal70a, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1; while about +1.2 volts is applied tounselected SL terminals72aand72c(not shown) through72n+1, about 0.0 volts is applied tounselected BL terminals74bthrough74p, and about 0.0 volts is applied tounselected WL terminals70bthrough70n.FIG. 68 shows the bias condition for the selected andunselected memory cells450 inmemory array480. However, these voltage levels are exemplary only may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.
• The bias conditions of the selectedrepresentative memory cell450aunder write logic-0 operation are further elaborated and are shown inFIGS. 69A through 69B. As discussed above, the potential difference between floatingbody24 and bit line region16 (connected toBL terminal74a) is now increased, resulting in a higher forward bias current than the base hole current generated by the n-p-nbipolar devices30 formed by buriedwell region22, floatingbody24, and bitline region16. The net result is that holes will be evacuated from floatingbody24.
• Theunselected memory cells450 during write logic-0 operations are shown inFIGS. 69C through 69P: The bias conditions formemory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedmemory cell450aare shown inFIGS. 69C through 69D. The bias conditions formemory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedmemory cell450aare shown inFIGS. 69E through 69F. The bias conditions formemory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedmemory cell450 are shown inFIGS. 69G through 69H.FIGS. 69I through 69J show the bias conditions formemory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedmemory cell450a.FIGS. 69K through 69L show the bias conditions formemory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedmemory cell450a. The bias conditions for memory cells sharing thesame BL terminal74aas the selectedmemory cell450abut not thesame WL terminal70 nor SL terminal72 (e.g. memory cell450g) are shown inFIGS. 69M through 69N, while the bias condition for memory cells not sharing the same WL, SL, andBL terminals70,72, and74 respectively as the selectedmemory cell450a(e.g. memory cell450h) is shown inFIG. 69O through 69P.
• The floatingbody24 potential of memory cells sharing theWL terminal70 as the selected memory cell will increase due to capacitive coupling fromWL terminal70 by ΔV_FB. For memory cells in state logic-0, the increase in the floatingbody24 potential is not sustainable as the forward bias current of the p-n diodes formed by floatingbody24 andjunction16 will evacuate holes from floatingbody24. As a result, the floatingbody24 potential will return to the initial state logic-0 equilibrium potential. For memory cells in state logic-1, the floatingbody24 potential will initially also increase by ΔV_FB, which will result in holes being evacuated from floatingbody24. After the positive bias on theWL terminal70 is removed, the floatingbody24 potential will decrease by ΔV_FB. If the initial floatingbody24 potential of state logic-1 is referred to as V_FB1, the floatingbody24 potential after the write logic-0 operation will become V_FB1−ΔV_FB. Therefore, the WL potential needs to be optimized such that the decrease in floating body potential ofmemory cells50 in state logic-1 is not too large. For example, the maximum floating body potential due to the coupling from the WL potential cannot exceed V_FB1/2.
• As shown inFIGS. 69C through 69D, for unselectedrepresentative memory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedmemory cell450a, a negative bias is applied to the BL terminal while the SL terminal is positively biased. The potential difference between the BL and SL terminals (i.e. the emitter and collector terminals of the bipolar device30) is greater compared to the memory cells in the holding mode. As a result, the forward bias current of the p-n diode formed by floatingbody24 andbit line region16 is balanced by higher base current of thebipolar device30. As a result,memory cell450bwill still be at holding mode. Thus, whenmemory cell450bis in state logic-1 it will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24, and whenmemory cell450bis in state logic-0 thebipolar device30 will remain off leaving the floatingbody24 charge level in a neutral state.
• As shown inFIGS. 69E through 69F, for unselectedrepresentative memory cell450csharing thesame SL terminal72band BL terminal74A but not thesame WL terminal70 as the selectedmemory cell450a, theSL terminal72 is now grounded with the BL terminal now negatively biased. As a result, the p-n diode formed between floatingbody24 andbit line region16 will be forward biased. For memory cells in state logic-0, the increase in the floatingbody24 potential will not change the initial state logic-0 as there is initially no hole stored in the floatingbody24. For memory cells in state logic-1, the net effect is that the floatingbody24 potential after write logic-0 operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential ofmemory cells50 in state logic-1 is not too large. For example, the −V_FB1/2 is applied to theBL terminal74. For memory cells in the logic-0 state, thebipolar device30 remains off leaving the cell in the logic-0 state.
• As shown inFIGS. 69G through 69H, for unselectedrepresentative memory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedmemory cell450a, both theSL terminal72 andBL terminal74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cells450dis no longer in holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 69I through 69J, for unselectedrepresentative memory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedmemory cell450a, the SL terminal is positively biased. As a result,memory cell450ewill still be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• As shown inFIGS. 69K through 69L, for unselectedrepresentative memory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedmemory cell450a, both theSL terminal72 andBL terminal74 are grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cells450fis no longer in holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• As shown inFIGS. 69M through 69N, for unselectedrepresentative memory cell450gsharing thesame BL terminal74abut not thesame WL terminal70 norSL terminal72, a negative bias is applied to the BL terminal while the SL terminal remains positively biased. The potential difference between the BL and SL terminals (i.e. the emitter and collector terminals of the bipolar device30) is greater compared to the memory cells in the holding mode. As a result, the forward bias current of the p-n diode formed by floatingbody24 andbit line region16 is balanced by higher base current of thebipolar device30. As a result,memory cell450gwill still be at holding mode. Thus memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• As shown inFIGS. 69O through 69P, for unselectedrepresentative memory cell450hnot sharing WL, BL, andSL terminals70,74, and72 respectively as the selectedmemory cell450a, both theSL terminal72 will remain positively charged and the BL terminal will remain grounded. As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• Several different types of a write logic-0 operation have been described as examples illustrating the present invention. While exemplary voltage levels have been given, the actual voltages used in practice may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.
• A write logic-1 operation can be performed onmemory cell450 by means of impact ionization as described for example with reference to Lin cited above, or by means of a band-to-band tunneling (GIDL) mechanism, as described for example with reference to Yoshida cited above.
• Illustrated inFIG. 70, is an example of the bias condition of the selectedmemory cell450ainmemory array480 under a band-to-band tunneling (GIDL) write logic-1 operation. The negative bias applied to theWL terminal70aand the positive bias applied to theBL terminal74aof the selectedrepresentative memory cell450aresult in hole injection to the floatingbody24 of the selectedmemory cell450 as discussed above with reference to Yoshida. TheSL terminal72 and thesubstrate terminal78 are grounded during the write logic-1 operation.
• As further illustrated inFIGS. 71A and 71B, in one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell450a: a potential of about 0.0 volts is applied toSL terminal72b, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about −1.2 volts is applied toWL terminal70a, and about 0.0 volts is applied to substrate terminal78 (not shown inFIG. 71B). This bias condition bends the energy bands upward in the portion ofbit line region16 near thegate60 in selectedrepresentative memory cell450acreating GIDL current on the bit line (electrons) while injecting holes into the floatingbody24 charging it up to a logic-1 level.
• Also shown inFIG. 70, the following bias conditions are applied to the unselected terminals: about +1.2 volts is applied tounselected SL terminals72aand72c(not shown) through72n+1, about 0.0 volts is applied tounselected BL terminals74bthrough74p, a potential of about 0.0 volts is applied tounselected WL terminals70bthrough70n+1, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1.
• The unselected memory cells during write logic-1 operations are shown inFIGS. 71C through 71O: The bias conditions formemory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedmemory cell450aare shown inFIGS. 71C through 71D. The bias conditions formemory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedmemory cell450aare shown inFIGS. 71E through 71F. The bias conditions formemory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedmemory cell450aare shown inFIGS. 71G through 71H.FIGS. 71I through 71J show the bias conditions formemory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedmemory cell450a.FIGS. 71K through 71L show the bias conditions formemory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedmemory cell450a. The bias conditions for memory cells sharing thesame BL terminal74aas the selectedmemory cell450abut not thesame WL terminal70 nor SL terminal72 (e.g. memory cell450g) are shown inFIGS. 71M through 71N, while the bias condition for memory cells not sharing the WL, SL, andBL terminals70,72 and74 respectively, as the selectedmemory cell450a(e.g. memory cell450h) are shown inFIG. 71O through 71P.
• As shown inFIGS. 71C through 71D, for unselectedrepresentative memory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedmemory cell450a, both BL and SL terminals are positively biased. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450bis no longer in holding mode. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As shown inFIGS. 71E through 71F, for unselectedrepresentative memory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedmemory cell450a, theSL terminal72 is now grounded with the BL terminal now positively biased. As a result,memory cell450cwill be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24 and memory cells in state logic-0 will remain in the neutral state.
• As shown inFIGS. 71G through 71H, for unselectedrepresentative memory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedmemory cell450a, both theSL terminal72 andBL terminal74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450dis not in a holding mode. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As shown inFIGS. 71I through 71J, for unselectedrepresentative memory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedmemory cell450a, the SL terminal remains positively biased. As a result,memory cell450ewill still be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24, and while memory cells in state logic-0 will remain in a neutral state.
• As shown inFIGS. 71K through 71L, for unselectedrepresentative memory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedmemory cell450a, both theSL terminal72 andBL terminal74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450fis no longer in a holding mode. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As shown inFIGS. 71M through 71N, for unselectedrepresentative memory cell450gsharing thesame BL terminal74abut not thesame WL terminal70 norSL terminal72, a positive bias is applied to the BL terminal and the SL terminal. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450gis no longer in a holding mode. However, because write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As shown inFIGS. 71O through 71P, for unselectedrepresentative memory cell450hnot sharing WL, BL, andSL terminals70,74 and72 respectively as the selected memory cell, theSL terminal72n+1 will remain positively charged and theBL terminal74band theWL terminal70nare grounded. As can be seen,memory cell450hwill be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• Illustrated inFIG. 72, is an example of the bias condition of the selectedmemory cell450ainmemory array480 under an impact ionization write logic-1 operation. The positive bias applied to theWL terminal70aand the positive bias applied to theBL terminal74aof the selectedrepresentative memory cell450aresults in hole injection to the floatingbody24 of the selectedmemory cell450 as discussed above with reference to Lin cited above. TheSL terminal72band thesubstrate terminals78athrough78n+1 are grounded during the write logic-1 operation.
• As further illustrated inFIG. 72, in one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell450a: a potential of about 0.0 volts is applied toSL terminal72b, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about +1.2 volts is applied toWL terminal70a, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1. This bias condition causes selectedrepresentative memory cell450ato conduct current due to the impact ionization mechanism discussed with reference to Lin cited above. The combination of +1.2V on word line terminal and +1.2V onbit line terminal74aturns on thebipolar device30 inrepresentative memory cell450aregardless of its prior logic state and generating sufficient hole charge in its floatingbody24 to place it in the logic-1 state.
• Also shown inFIG. 72, the following bias conditions are applied to the unselected terminals: about +1.2 volts is applied tounselected SL terminals72aand72c(not shown) through72n+1, about 0.0 volts is applied tounselected BL terminals74bthrough74p, a potential of about 0.0 volts is applied tounselected WL terminals70bthrough70n+1, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1.
• For unselectedrepresentative memory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedmemory cell450a, both BL and SL terminals are positively biased. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450bis no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For unselectedrepresentative memory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedmemory cell450a, theSL terminal72bis now grounded with the BL terminal now positively biased. As a result,memory cell450cwill be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• For unselectedrepresentative memory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedmemory cell450a, both theSL terminal72 andBL terminal74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450dis not in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For unselectedrepresentative memory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedmemory cell450a, the SL terminal remains positively biased. As a result,memory cell450ewill still be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24, and while memory cells in state logic-0 will remain in a neutral state. There is a possible write disturb issue withmemory cell450ein this case which will be discussed in more detail below in conjunction withFIGS. 73A through 73B.
• For unselectedrepresentative memory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedmemory cell450a, both theSL terminal72 andBL terminal74 are now grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450fis no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For unselectedrepresentative memory cell450gsharing thesame BL terminal74abut not thesame WL terminal70 norSL terminal72, a positive bias is applied to theBL terminal74aand theSL terminal72n+1. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450gis no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For unselectedrepresentative memory cell450hnot sharing WL, BL, andSL terminals70,74 and72 respectively as the selectedmemory cell450a, theSL terminal72n+1 will remain positively charged and theBL terminal74band theWL terminal70nare grounded. As can be seen,memory cell450hwill be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate holes current to replenish the charge in floatingbody24; while memory cells in state logic-0 will remain in neutral state.
• FIGS. 73A and 73B illustrate the bias conditions ofrepresentative memory cell450eunder the bias conditions shown inFIG. 72.Memory cell450eis coupled toword line terminal70abiased at +1.2V,bit line terminal74bbiased at 0.0V, andsource line terminal72abiased at +1.2V. The concern is that the floatingbody region24 ofmemory cell450eboosted by capacitive coupling fromword line70awhile having 1.2 volts of bias across it—albeit of the opposite voltage potential of selectedrepresentative memory cell450a. Ifbipolar device30 were to turn on under these conditions, a write disturb condition (writing an unwanted logic-1 in an unselected memory cell) would occur with a logic-1 being written into unselectedmemory cell450e.
• One solution to the write disturb inrepresentative memory cell450eis to designmemory cell450 such that the impact ionization is less efficient at generating charge carriers when thesource line terminal72 is positively biased than it is in the case when thebit line terminal74 is positively biased using techniques known in the art. This creates enough current to placerepresentative memory cell450ein a holding mode while generating a larger current sufficient for writing a logic-1 inmemory cell450a.
• Alternatively, a different set of bias conditions may be used as illustrated inFIG. 37 which shows another example of writing logic-1 into selectedmemory cell450ainmemory array480 using impact ionization. As inFIG. 72, the positive bias applied to theWL terminal70aand the positive bias applied to theBL terminal74aof the selectedrepresentative memory cell450aresults in hole injection to the floatingbody24 of the selectedmemory cell450 as discussed above with reference to Lin cited above. TheSL terminal72band thesubstrate terminals78athrough78n+1 are grounded during the write logic-1 operation. The difference in this write logic-1 operation are the bias conditions of theunselected bit lines74bthrough74pand the unselected source lines72aand72c(not shown) through72n+1.
• As further illustrated inFIG. 74, in one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell450a: a potential of about 0.0 volts is applied toSL terminal72b, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about +1.2 volts is applied toWL terminal70a, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1. This bias condition causes selectedrepresentative memory cell450ato conduct current due to the impact ionization mechanism discussed with reference to Lin cited above. The combination of +1.2V on word line terminal and +1.2V onbit line terminal74aturns on thebipolar device30 inrepresentative memory cell450aregardless of its prior logic state and generating sufficient hole charge in its floatingbody24 to place it in the logic-1 state.
• Also shown inFIG. 74, the following bias conditions are applied to the unselected terminals: about +0.6 volts is applied tounselected SL terminals72aand72c(not shown) through72n+1, about +0.6 volts is applied tounselected BL terminals74bthrough74p, a potential of about 0.0 volts is applied tounselected WL terminals70bthrough70n+1, and about 0.0 volts is applied tosubstrate terminals78athrough78n+1.
• For unselectedrepresentative memory cell450bsharing thesame WL terminal70aand BL terminal74abut not thesame SL terminal72 as the selectedmemory cell450a, both BL and SL terminals are positively biased with a larger bias applied to the BL than the SL. As a result,bipolar device30 is on andmemory cell450bis in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• For unselectedrepresentative memory cell450csharing thesame SL terminal72band BL terminal74abut not thesame WL terminal70 as the selectedmemory cell450a, theSL terminal72bis now grounded with the BL terminal now positively biased. As a result,memory cell450cwill be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• For unselectedrepresentative memory cell450dsharing thesame WL terminal70aandSL terminal72bbut not thesame BL terminal74 as the selectedmemory cell450a, theSL terminal72bis now grounded and theBL terminal74bhas a slight positive bias. As a result,memory cell450dwill be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• For unselectedrepresentative memory cell450esharing thesame WL terminal70abut not thesame SL terminal72 norBL terminal74 as the selectedmemory cell450a, theSL terminal72aand theBL terminal74bboth have a slight positive bias. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450eis no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body. This also eliminates the potential write disturb condition forrepresentative memory cell450epresent with the bias conditions ofFIGS. 35, 36A and 36B.
• For unselectedrepresentative memory cell450fsharing thesame SL terminal72bbut not thesame WL terminal70 norBL terminal74 as the selectedmemory cell450a, theSL terminal72bis grounded andBL terminal74bhas a small positive bias. As a result,memory cell450fwill be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• For unselectedrepresentative memory cell450gsharing thesame BL terminal74abut not thesame WL terminal70 norSL terminal72, a positive bias is applied to theBL terminal74aand a smaller positive bias is applied toSL terminal72n+1. As a result,memory cell450gwill be in a holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device30 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in the neutral state.
• For unselectedrepresentative memory cell450hnot sharing WL, BL, andSL terminals70,74 and72 respectively as the selectedmemory cell450a, theSL terminal72n+1 and theBL terminal74bwill have a slight positive bias while theWL terminal70nis grounded. As a result, there is no potential difference between the emitter and collector terminals of the n-p-nbipolar device30 and consequentlymemory cell450eis no longer in a holding mode. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• Different structures and methods of operation have been discussed with respect toexemplary memory array480 comprised of a plurality ofmemory cells450. Many other embodiments are possible within the scope of the invention. For example, regions of the first conductivity type may be changed from p-type to n-type and regions of the second conductivity type may be changed from n-type to p-type combined with a reversal of the polarities of the bias voltages for various operations. The bias levels themselves are exemplary only and will vary from embodiment to embodiment as a matter of design choice.Memory array480 may be altered so that the outside rows share asource line72 with the adjacent row and have adedicated word line70. Many other embodiments will readily suggest themselves to persons skilled in the art, thus the invention is not to be limited in any way except by the appended claims.
• It is noteworthy thatmemory cell250V constructed using either of thefin structures52 and52A described in conjunction withFIGS. 56 through 58B can be used to replacememory cell450 inmemory array480 with shared word lines with or without shared source lines and will function in a manner similar to that described formemory cell450. Many other modifications may also made toarray450. For example, the first and second conductivity types may be reversed in eithermemory cell450 ormemory cell250V with reversal of the relative polarities of the applied voltages. All of the voltage levels described are exemplary only and will vary from embodiment to embodiment as a matter of design choice. Thus the invention is not to be limited in any way.
• FIG. 75A shows another embodiment of thememory device450, in whichadjacent regions16, which are separated by insulatinglayer28, share a common connection toBL terminal74 throughcontact64. By sharing a common connection to theBL terminal74, a more compact memory cell can be obtained as only one contact is required for each twomemory cells450.
• Another embodiment ofmemory cell450 is shown inFIG. 75B, wherebit line region16 andcontact64 are now shared between twoadjacent memory cells450. Isolation of the adjacent floatingbody24 regions of a first conductivity type is achieved through both insulatingregion33 andbit line region16 of a second conductivity type.
• FIGS. 76A through 76O describe a method ofmanufacturing memory cell450 as shown inFIG. 75B created using, in part, a replacement insulator technique like that described in S_Kim and Oh discussed above to create insulatingregion33.
• A method ofmanufacturing memory cell450 as shown inFIG. 75B will be described with reference toFIGS. 76A through 76AA. These 27 figures are arranged in groups of three related views, with the first figure of each group being a top view, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a horizontal cross section of the top view in the first figure of the group designated II-II′. ThusFIGS. 76A, 76D, 76G, 76J, 76M, 76P, 76S, 76V, and 76Y are a series of top views of thememory cell450 at various stages in the manufacturing process,FIGS. 76B, 76E, 76H, 76K, 76N, 76Q, 76T, 76W, and76Z are their respective vertical cross sections labeled I-I′, andFIGS. 76C, 76F, 76I, 76L, 76O, 76R, 76U, 76X, and 76AA are their respective horizontal cross sections labeled II-II′. Identical reference numbers from earlier drawing figures appearing inFIGS. 76A through 76AA represent similar, identical, or analogous structures as previously described in conjunction with the earlier drawing figures. Here “vertical” means running up and down the page in the top view diagram and “horizontal” means running left and right on the page in the top view diagram. In the physical embodiment ofmemory cell450, both cross sections are “horizontal” with respect to the surface of the semiconductor device.
• As illustrated inFIGS. 76A through 76C, a thin conductive region202 (e.g. 300 A in an exemplary 130 nm process, though this will vary with embodiments in different process technologies and geometries) is grown on the surface ofsubstrate12. Theconductive region202 is comprised of a different material from the materials of thesubstrate region12 so that it may be selectively etched away later without simultaneous unwanted etching ofsubstrate12. For example, theconductive region202 could be made of silicon germanium (SiGe) material, whilesubstrate12 could be made of silicon.
• As illustrated inFIGS. 76D through 76F, a lithography process is then performed to pattern theconductive region202. Subsequently,layer202 is etched, followed by anotherconductive region204 growth. As an example, the thickness ofregion204 is about 500 A in an exemplary 130 nm process.Region204 may comprise of the samematerials forming substrate12, for example silicon. A planarization step can then be performed to ensure a planar surface. The resulting structure can be seen inFIGS. 76D through 76F.
• As illustrated inFIGS. 76G through 76H, a trench formation process is then performed, which follows a similar sequence of steps as shown inFIGS. 2A through2I, i.e. formation ofsilicon oxide220,polysilicon222, andsilicon nitride224 layers, followed by lithography patterning and etch processes.Trench216 is etched such that the trench depth is deeper than that oftrench208. For example, thetrench208 depth is about 1200 A, while thetrench216 depth is about 2000 A in an exemplary 130 nm process. The resulting structures are shown inFIGS. 76G through 76I.
• As illustrated inFIGS. 76J through 76L, this is then followed by silicon oxidation step, which will grow silicon oxide films intrench208 andtrench216. For example, about 4000 A silicon oxide can be grown in an exemplary 130 nm process. A chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface. A silicon dry etching step can then be performed so that the remaining silicon oxide layer height is about 300 A from the silicon surface in an exemplary 130 nm process. Thesilicon nitride layer224 and thepolysilicon layer222 can then be removed, followed by a wet etch process to remove silicon oxide layer220 (and a portion of the silicon oxide films formed in the area offormer trench208 and trench216).FIGS. 76J through 76L show the insulatinglayers26 and28 formed following these steps.
• As illustrated inFIGS. 76M through 76O, an oxide etch is then performed to recess theoxide regions26 and28 (for example by about 1000 A) to expose theconductive region202. A wet etch process is then performed to selectively removeregion202 leaving angap203 under an overhanging portion ofregion204. The resulting structures following these steps are shown inFIGS. 76M through 76O.
• As illustrated inFIGS. 76P through 76R, the resultinggap region203 is then oxidized to form a buriedoxide region33. Recessing insulatingregion26 down to the surface ofsubstrate12 allows access for the etch ofregion202 to formgap203 and then subsequent oxide growth ingap203 to form buriedoxide region33. The overhanging portion ofregion204 constrains the oxide growth ingap space203 to keep the buriedoxide region33 from growing to the surface. The resulting structures are shown inFIGS. 76P through 76R.
• As illustrated inFIGS. 76S through 76U, an oxide deposition of about 1000 A is then performed followed by a planarization process. This is then followed by an ion implantation step to form the buriedwell region22. The ion implantation energy is optimized such that the buriedlayer region22 is formed shallower than the bottom of the insulatinglayer26. As a result, the insulatinglayer26 isolates buriedlayer region22 between adjacent cells. On the other hand, the buriedlayer region22 is formed such that insulatinglayers28 and33 do not isolate buriedlayer region22, allowing buriedlayer region22 to be continuous in the direction of II-II′ cross section line. Following these steps, the resulting structures are shown inFIGS. 76S through 76U.
• As illustrated inFIGS. 76V through 76X, a silicon oxide layer (or high-dielectric materials)62 is then formed on the silicon surface (e.g. about 100 A in an exemplary 130 nm process), followed by a polysilicon (or metal)gate60 deposition (e.g. about 500 A in an exemplary 130 nm process). A lithography step is then performed to form the pattern for the gate and word line, followed by etching of the polysilicon and silicon oxide layers where they are not waned. The resulting structure is shown inFIGS. 76V-76X.
• As illustrated inFIGS. 76Y through 76AA, another ion implantation step is then performed to form thebit line region16 of a second conductivity type (e.g. n-type conductivity). Thegate60 and the insulatinglayers26 and28 serve as masking layer for the implantation process such that regions of second conductivity are not formed outsidebit line region16. This is then followed by backend process to form contact and metal layers.
• FIGS. 77A through 77F illustrate an embodiment of a Gateless Half Transistor memory cell.Memory cell550 according to the present invention eliminates the gate terminal present in earlier memory cells such asmemory cell250 allowing a more compact layout since some design rules like gate-to-contact-spacing no longer affect the minimum cell size.
• Present inFIGS. 77A through 77F aresubstrate12 of the first conductivity type, buriedlayer22 of the second conductivity type,bit line region16 of the second conductivity type, region of thesecond conductivity type20, region of thefirst conductivity type21, buriedlayer region22, floatingbody24 of the first conductivity type, insulatingregions26 and28,source line terminal72, andsubstrate terminal78 all of which perform substantially similar functions inmemory cell550 as in previously discussedembodiment memory cell250. The primary difference betweenmemory cell550 andmemory cell250 previously discussed is the absence ofgate60 andgate insulator62. As in other embodiments, there is no contact to the buriedlayer22 at thesemiconductor surface14 inside the boundary ofmemory cell550.
• The manufacturing ofmemory cell550 is substantially similar to the manufacturing ofmemory cell250 described in conjunction withFIGS. 36A through 36U, except that instead of a lithographic step for forminggate60, a different lithographic step is needed to patternbit line region16 for implantation or diffusion.
• FIG. 77A illustrates a top view ofmemory cell550 with several near neighbors.
• FIG. 77B illustrates a top view asingle memory cell550 with vertical cut line I-I′ and horizontal cut line II-II′ for the cross sections illustrated inFIGS. 77C and 77D respectively.
• FIG. 77E shows howmemory cell550 may have its buriedlayer22 coupled to sourceline terminal72 throughregion20 of the second conductivity type and itssubstrate12 coupled tosubstrate terminal78 through region offirst conductivity type21.
• FIG. 77F showsexemplary memory array580 which will be used in subsequent drawing figures to illustrate the various operations that may be performed onmemory cell550 when arranged in an array to create a memory device.Array580 comprises in partrepresentative memory cells550a,550b,550cand550d. In operations where a single memory cell is selected,representative memory cell550awill represent the selected cell while the otherrepresentative memory cells550b,550cand550dwill represent the various cases of unselected memory cells sharing a row, sharing a column, or sharing neither a row or a column respectively with selectedrepresentative memory cell550a. Similarly in the case of operations performed on a single row or column,representative memory cell550awill always be on the selected row or column.
• While the drawing figures show the first conductivity type as p-type and the second conductivity type as n-type, as with previous embodiments the conductivity types may be reversed with the first conductivity type becoming n-type and the second conductivity type becoming p-type as a matter of design choice in any particular embodiment.
• The memory cell states are represented by the charge in the floatingbody24, which modulates the intrinsic n-p-nbipolar device230 formed by buriedwell region22, floatingbody24, and BLbit line region16. Ifcell550 has holes stored in thebody region24, then the memory cell will have a higher bipolar current (e.g. current flowing from BL to SL terminals during read operation) compared to ifcell550 does not store holes inbody region24.
• The positive charge stored in thebody region24 will decrease over time due to the p-n diode leakage formed by floatingbody24 andbit line region16 and buriedlayer22 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells of the array.
• An entire array holding operation is illustrated inFIG. 78A while a single row holding operation is illustrated inFIG. 78B. The holding operation can be performed in a manner similar to the holding operation formemory cell250 by applying a positive bias to the back bias terminal (i.e. SL terminal72) while groundingterminal74 andsubstrate terminal78. If floatingbody24 is positively charged (i.e. in a state logic-1), the n-p-nbipolar transistor230 formed by BLbit line region16, floatingbody24, and buried wellregion22 will be turned on.
• A fraction of the bipolar transistor current will then flow into floating region24 (usually referred to as the base current) and maintain the state logic-1 data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by buriedwell region22, floatingregion24, and bitline region16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofSL terminal72 to the base current flowing into the floatingregion24.
• For memory cells in state logic-0 data, the bipolar device will not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in state logic-0 will remain in state logic-0.
• A periodic pulse of positive voltage can be applied to theSL terminal72 as opposed to applying a constant positive bias to reduce the power consumption of thememory cell550.
• An example of the bias condition for the holding operation is hereby provided: zero voltage is applied toBL terminal74, a positive voltage is applied toSL terminal72, and zero voltage is applied to thesubstrate terminal78. In one particular non-limiting embodiment, about +1.2 volts is applied toterminal72, about 0.0 volts is applied toterminal74, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary from embodiment to embodiment as a matter of design choice.
• In the entire array holding operation ofFIG. 78A, all of thesource line terminals72athrough72nare biased at +1.2V, all of the bit lines74athrough74pare biased to 0.0V, and all of thesource terminals78athrough78nare biased to 0.0V. This places all of the cells inmemory array580 in the hold state.
• In the single row hold operation ofFIG. 78B, selectedsource line terminal72ais biased at +1.2V while the unselectedsource line terminals72b(not shown) through72nare biased at 0.0V, all of the bit lines74athrough74pare biased to 0.0V, and all of thesource terminals78athrough78nare biased to 0.0V. This places all of the selected cells inmemory array280 in the hold state.
• A single memory cell read operation is illustrated inFIGS. 79 and 80A through 80H. The read operation formemory cell550 can be performed by sensing the current of thebipolar device230 by applying the following bias condition: a positive voltage is applied to the selectedBL terminal74, zero voltage is applied to the selectedSL terminal72, and zero voltage is applied to thesubstrate terminal78. The positive voltage applied to the selected BL terminal is less than or equal to the positive voltage applied to the SL terminal during holding operation. The unselected BL terminals will remain at zero voltage and the unselected SL terminals will remain at positive voltage.
• FIG. 79 shows the bias condition for the selectedmemory cell550aandunselected memory cells550b,550c, and550dinmemory array280. In this particular non-limiting embodiment, about 0.0 volts is applied to the selected SL terminal72awhile about 0.0V is applied to the unselectedsource line terminals72b(not shown) through72n, about +1.2 volts is applied to the selected BL terminal74awhile 0.0V is applied to the unselectedbit line terminals74bthrough74p, and about 0.0 volts is applied tosubstrate terminals78athrough78n. These voltage levels are exemplary only and may vary from embodiment to embodiment.
• InFIGS. 80A and 80B, the bias conditions for selectedrepresentative memory cell550aare shown. In this particular non-limiting embodiment, about 0.0 volts is applied to the selected SL terminal72a, about +1.2 volts is applied to the selected BL terminal74a, and about 0.0 volts is applied to substrate terminal78 (not shown). This causes current to flow through intrinsicbipolar device230 if the floating body is positively charged and no current to flow if the floating body is discharged since thebipolar device230 is off.
• The unselected memory cells during read operations are shown inFIGS. 80C through 80H. The bias conditions for memory cells sharing the same row (e.g. memory cell550b) are shown inFIGS. 80C and 80D. The bias conditions for memory cells sharing the same column (e.g. memory cell550c) as the selectedmemory cell550aare shown inFIGS. 80E and 80F. The bias conditions for memory cells sharing neither the same row nor the same column as the selectedmemory cell550a(e.g. memory cell550d) are shown inFIG. 80G-80H.
• As illustrated inFIGS. 80C and 80D, formemory cell550bsharing the same row as the selectedmemory cell550a, theSL terminal72aand theBL terminal74pare both biased to 0.0V and consequently these cells will not be at the holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As illustrated inFIGS. 80E and 80F, formemory cell550csharing the same column as the selectedmemory cell550a, a positive voltage is applied to theBL terminal74aandSL terminal72n. No base current will flow into the floatingbody24 because there is no potential difference betweenSL terminal72 and BL terminal74 (i.e. the emitter and collector terminals of the n-p-n bipolar device230). However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As illustrated inFIGS. 80G and 80H, formemory cell550dsharing neither the same row nor the same column as the selectedmemory cell550a, both theSL terminal72nwill remain positively charged and theBL terminal74premain grounded.Representative memory cell550dwill be in the holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device230 will generate hole current to replenish the charge in floatingbody24, while memory cells in state logic-0 will remain in neutral state.
• The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used.
• FIG. 81 illustrates a single row write logic-0 operation whileFIGS. 82A and 82B illustrate the biasing conditions and operation of unselectedrepresentative memory cell550c. InFIG. 81 the selectedrow SL terminal72ais biased negatively at about −0.5V while the unselectedrow SL terminals72b(not shown) through72nare biased at about 0.0V, all theBL terminals74athrough74pare biased at 0.0V, and all thesubstrate terminals78athrough78nare biased at 0.0V. This causes the selectedcells550 likerepresentative memory cells550aand550bto have their bipolar devices turn on due to forward bias on the floatingbody24 to buriedlayer22 junction evacuating the holes from the floatingbody24.
• FIGS. 82A and 82B show the operation of unselectedrepresentative memory cell550cwhich in this case is representative of all thememory cells550 inmemory array280 not on the selected row.Memory cell550chas itsSL terminal72nat +1.2V and itsBL terminal74aat 0.0V which corresponds to the holding operation described above in conjunction withFIGS. 78A and 78B.
• A write logic-0 operation can also be performed on a column basis by applying a negative bias to theBL terminal74 as opposed to theSL terminal72. TheSL terminal72 will be zero or positively biased, while zero voltage is applied to thesubstrate terminal78. Under these conditions, all memory cells sharing thesame BL terminal74 will be written into state logic-0 and all the other cells will be in a holding operation.
• The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used.
• A write logic-1 operation can be performed onmemory cell550 through impact ionization as described for example with reference to Lin above.
• An example of the bias condition of the selectedmemory cell550aunder impact ionization write logic-1 operation is illustrated inFIG. 83 andFIGS. 84A through 84B. A positive bias is applied to theBL terminal74, while zero voltage is applied to the selectedSL terminal72 andsubstrate terminal78. The positive bias applied to theBL terminal74 is greater than the positive voltage applied to theSL terminal72 during holding operation. The positive bias applied to the BL terminal is large enough to turn onbipolar device230 regardless of the initial state of the data in selectedmemory cell550a. This results in a base hole current to the floatingbody24 of the selectedmemory cell550acharging it up to a logic-1 state.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell550a: a potential of about 0.0 volts is applied to selected SL terminal72a, a potential of about +2.0 volts is applied to selected BL terminal74a, and about 0.0 volts is applied tosubstrate terminals78athrough78n. The following bias conditions are applied to the unselected terminals: about +1.2 volts is applied toSL terminals72b(not shown) through72n, and about 0.0 volts is applied toBL terminals74bthrough74p.FIG. 83 shows the bias condition for the selected and unselected memory cells inmemory array580. The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used.
• The unselected memory cells during write logic-1 operations are shown inFIGS. 84C through 84H. The bias conditions for memory cells sharing the same row (e.g. memory cell550b) are shown inFIGS. 84C through 84D, the bias conditions for memory cells sharing the same column as the selectedmemory cell550a(e.g. memory cell550c) are shown inFIGS. 84E through 84F, and the bias conditions formemory cells550 not sharing the same row nor the same column as the selectedmemory cell550a(e.g. memory cell550d) are shown inFIGS. 84G through 84H.
• As shown inFIGS. 84C and 84D, forrepresentative memory cell550bsharing the same row as the selectedmemory cell550a,SL terminal72aandBL terminal74pare be grounded.Bipolar device230 will be off and thememory cell550bwill not be at the holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As shown inFIGS. 84E and 84F, forrepresentative memory cell550csharing the same column as the selectedmemory cell550a, a greater positive voltage is applied to theBL terminal74aand a lesser positive voltage is applied toSL terminal72n. Less base current will flow into the floatingbody24 than in selectedmemory cell550abecause of the lower potential difference betweenSL terminal72 and BL terminal74 (i.e. the emitter and collector terminals of the n-p-n bipolar device230). However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• As shown inFIGS. 84G and 84H, forrepresentative memory cell550dsharing neither the same column nor the same row as the selectedmemory cell550a, theSL terminal72 is positively charged and the BL terminal is grounded.Representative memory cell550dwill be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 because the intrinsicbipolar device230 will generate hole current to replenish the charge in floatingbody24 and where memory cells in state logic-0 will remain in neutral state.
• The various voltage bias levels above are exemplary only. They will vary from embodiment to embodiment as a function of both design choice and the process technology used. Also, the first conductivity type may be changed from p-type to n-type and the second conductivity type may be changed from n-type to p-type, and the polarities of the applied biases may be reversed. Thus the invention is not to be limited in any way except by the appended claims.
• A vertical stack of alternating conductive regions of first conductivity type and second conductivity type has been described in J_Kim discussed above, where a gate is overlaid surrounding thebody region24 on two sides. By removing the gates, a more compact memory cell than that reported in J_Kim can be obtained as inmemory cell350 discussed below.
• FIGS. 85A through 85F illustrate another embodiment of a Gateless Half Transistor memory cell. By allowing thebit line region16 to completely cover the floatingbody region24 inmemory cell650, some design rules like minimum-diffusion-to-insulator-spacing (the space from16 to26 in memory cell550) no longer affects the cell size. Present inFIGS. 85A through 85F aresubstrate12 of the first conductivity type, buriedlayer22 of the second conductivity type,bit line region16 of the second conductivity type, region of thesecond conductivity type20, region of thefirst conductivity type21, floatingbody24 of the first conductivity type, buriedlayer region22, insulatingregions26 and28,source line terminal72, andsubstrate terminal78 all of which perform substantially similar functions inmemory cell650 as in previously discussedembodiment memory cell550. The primary difference betweenmemory cell650 andmemory cell550 previously discussed is thatbit line region16 completely covers a (now smaller) floatingbody region24 allowing for a more compact memory cell. As in other embodiments, there is no contact to the buriedlayer22 at thesemiconductor surface14 inside the boundary ofmemory cell650.
• The manufacturing ofmemory cell650 is substantially similar to the manufacturing ofmemory cell250 described in conjunction withFIGS. 36A through 36U andmemory cell550 described in conjunction withFIGS. 77A through 77F above, except thatbit line region16 may be formed by an implantation process formed on the material making upsubstrate12 according to any of implantation processes known and typically used in the art. Alternatively, solid state diffusion or epitaxial growth process may also be used to formbit line region16.
• FIG. 85A illustrates a top view ofmemory cell650 with several near neighbors.
• FIG. 85B illustrates a top view asingle memory cell650 with vertical cut line I-I′ and horizontal cut line II-II′ for the cross sections illustrated inFIGS. 85C and 85D respectively.
• FIG. 85E shows howmemory cell650 may have its buriedlayer22 coupled to sourceline terminal72 throughregion20 of the second conductivity type and itssubstrate12 coupled tosubstrate terminal78 throughregion21 of the first conductivity type.
• FIG. 87F showsexemplary memory array680 comprisingmultiple memory cells650 when arranged in an array to create a memory device. The circuit operation ofmemory cell650 is substantially identical to that ofmemory cell550 and will not be discussed further.
• While the drawing figures show the first conductivity type as p-type and the second conductivity type as n-type, as with previous embodiments the conductivity types may be reversed with the first conductivity type becoming n-type and the second conductivity type becoming p-type as a matter of design choice in any particular embodiment.
• An alternate method of operatingmemory cells250,350, and450, which utilizes the silicon controlled rectifier (SCR) principle discussed above with reference to Widjaja, is now described.
• As shown inFIG. 86, inherent inmemory cells250,350 and450 is a P1-N2-P3-N4 silicon controlled rectifier (SCR) device formed by two interconnectedbipolar devices32 and34, withsubstrate78 functioning as the P1 region, buriedlayer22 functioning as the N2 region,body region24 functioning as the P3 region and bitline region16 functioning as the N4 region. In this example, thesubstrate terminal78 functions as the anode and terminal74 functions as the cathode, whilebody region24 functions as a p-base to turn on the SCR device. Ifbody region24 is positively charged, the silicon controlled rectifier (SCR) device formed by the substrate, buried well, floating body, and the BL junction will be turned on and ifbody region24 is neutral, the SCR device will be turned off.
• The holding operation can be performed by applying the following bias: zero voltage is applied toBL terminal74, zero or negative voltage is applied toWL terminal70, and a positive voltage is applied to thesubstrate terminal78, while leavingSL terminal72 floating. Under these conditions, ifmemory cell250 is in memory/data state logic-1 with positive voltage in floatingbody24, the SCR device ofmemory cell250 is turned on, thereby maintaining the state logic-1 data. Memory cells in state logic-0 will remain in blocking mode, since the voltage in floatingbody24 is not substantially positive and therefore floatingbody24 does not turn on the SCR device. Accordingly, current does not flow through the SCR device and these cells maintain the state logic-0 data. Thosememory cells250 that are commonly connected tosubstrate terminal78 and which have a positive voltage inbody region24 will be refreshed with a logic-1 data state, while thosememory cells250 that are commonly connected to thesubstrate terminal78 and which do not have a positive voltage inbody region24 will remain in blocking mode, since their SCR device will not be turned on, and therefore memory state logic-0 will be maintained in those cells. In this way, allmemory cells250 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This process occurs automatically, upon application of voltage to thesubstrate terminal78, in a parallel, non-algorithmic, efficient process. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminal74, a voltage of about −1.0 volts is applied toterminal70, and about +0.8 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships there between.
• As illustrated inFIG. 87, a read operation can be performed by applying a positive voltage to thesubstrate terminal78, a positive voltage (lower than the positive voltage applied to the substrate terminal78) toBL terminal74, a positive voltage toWL terminal70, while leavingSL terminal72 floating. Ifcell250ais in a state logic-1 having holes in thebody region24, the silicon controlled rectifier (SCR) device formed by the substrate, buried well, floating body, and the BL junction will be turned on and a higher cell current (flowing from thesubstrate terminal78 to the BL terminal74) is observed compared to whencell250 is in a state logic-0 having no holes inbody region24. A positive voltage is applied toWL terminal70ato select a row in the memory cell array80 (e.g., seeFIG. 87), while negative voltage is applied toWL terminals70b(not shown) through70nfor any unselected rows. The negative voltage applied reduces the potential of floatingbody24 through capacitive coupling in the unselected rows and turns off the SCR device of eachcell250 in each unselected row. In one particular non-limiting embodiment, about +0.8 volts is applied tosubstrate terminals78athrough78n, about +0.5 volts is applied to terminal70a(for the selected row), and about +0.4 volts is applied to selectedbit line terminal74a, about −1.0 volts is applied to unselectedword line terminals70b(not shown) through70n, and about +0.8 volts is applied to unselectedbit line terminals74bthrough74. However, these voltage levels may vary.
• For memory cells sharing the same row as the selected memory cell (e.g. cell250b), both the BL and substrate terminals are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For memory cells sharing the same column as the selected memory cell (e.g. cell250c), thesubstrate terminal78 remains positively biased while theBL terminal74 is positively biased (at lower positive bias than that applied to the substrate terminal78). As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 while memory cells in state logic-0 will remain in neutral state.
• For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell250d), both the BL and substrate terminals are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because read operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• The silicon controlled rectifier device of selectedmemory cell250acan be put into a state logic-1 (i.e., performing a write logic-1 operation) as described with reference toFIG. 88. The following bias is applied to the selected terminals: zero voltage is applied toBL terminal74, a positive voltage is applied toWL terminal70, and a positive voltage is applied to thesubstrate terminal78, whileSL terminal72 is left floating. The positive voltage applied to theWL terminal70 will increase the potential of the floatingbody24 through capacitive coupling and create a feedback process that turns the SCR device on. Once the SCR device ofcell250 is in conducting mode (i.e., has been “turned on”) the SCR becomes “latched on” and the voltage applied toWL terminal70 can be removed without affecting the “on” state of the SCR device. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminal74, a voltage of about +0.5 volts is applied toterminal70, and about +0.8 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the voltages applied, as described above, e.g., the voltage applied to terminal78 remains greater than the voltage applied toterminal74.
• For memory cells sharing the same row as the selected memory cell (e.g. cell250b), thesubstrate terminal78 is positively biased. However, because theBL terminal74 is also positively biased, there is no potential difference between the substrate and BL terminals and the SCR is off. Consequently these cells will not be at the holding mode. However, because the write logic-1 operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For memory cells sharing the same column as the selected memory cell (e.g. cell250c), thesubstrate terminal78 remains positively biased while theBL terminal74 is now grounded. As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 while memory cells in state logic-0 will remain in neutral state.
• For memory cells not sharing the same row nor the same column as the selected memory cell (e.g. cell250d), both the BL and substrate terminals are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because the write logic-1 operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• A write logic-0 operation to selectedmemory cell250ais described with reference toFIG. 89. The silicon controlled rectifier device is set into the blocking (off) mode by applying the following bias: zero voltage is applied toBL terminal74a, a positive voltage is applied toWL terminal70a, and zero voltage is applied to thesubstrate terminal78, while leavingSL terminal72afloating. Under these conditions the voltage difference between anode and cathode, defined by the voltages atsubstrate terminal78 andBL terminal74, will become too small to maintain the SCR device in conducting mode. As a result, the SCR device ofcell250awill be turned off. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminal74, a voltage of about +0.5 volts is applied toterminal70, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• For memory cells sharing the same row as the selected memory cell (e.g. cell250b), thesubstrate terminal78 is grounded and the SCR will be off. Consequently these cells will not be at the holding mode. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For memory cells sharing the same column as the selected memory cell (e.g. cell250c), thesubstrate terminal78 is positively biased while theBL terminal74ais now grounded. As can be seen, these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 while memory cells in state logic-0 will remain in neutral state.
• For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell250d), both theBL terminal74pandsubstrate terminal78 are positively biased and the SCR is off. Consequently these cells will not be at the holding mode. However, because the write logic-0 operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• While one illustrative embodiment and method of use of the SCR operation ofmemory cell250 has been described, other embodiments and methods are possible. For example, the first and second conductivity types may be reversed so that the first conductivity type is n-type and the second conductivity is p-type making the SCR a N1-P2-N3-P4 device and reversing the polarity of applied voltages. Voltages given in the various example operations are illustrative only and will vary from embodiment to embodiment as a matter of design choice. Whilesubstrate12 is called a substrate for continuity of terminology and simplicity of presentation,substrate12 may alternately be a well in either another well or a true substrate in a structure similar to that described in conjunction withFIG. 43B above. Bysubstrate12 being a well instead of a true substrate, manipulating the voltage level ofsubstrate12 as required in some SCR operations is facilitated. Many other alternative embodiments and methods are possible, thus the illustrative examples given are not limiting in any way.
• A novel semiconductor memory with an electrically floating body memory cell is achieved. The present invention also provides the capability of maintaining memory states employing parallel non-algorithmic periodic refresh operation. As a result, memory operations can be performed in an uninterrupted manner Many embodiments of the present invention have been described. Persons of ordinary skill in the art will appreciate that these embodiments are exemplary only to illustrate the principles of the present invention. Many other embodiments will suggest themselves to such skilled persons after reading this specification in conjunction with the attached drawing figures.
• Referring now toFIG. 91, amemory cell750 according to an embodiment of the present invention is shown. Thecell750 is fabricated on a silicon-on-insulator (SOI)substrate12 having a first conductivity type (such as p-type conductivity), which consists of buried oxide (BOX)layer22.
• Afirst region16 having a second conductivity type, such as n-type, for example, is provided insubstrate12 and is exposed atsurface14. Asecond region18 having the second conductivity type is also provided insubstrate12, and is also exposed atsurface14. Additionally,second region18 is spaced apart from thefirst region16 as shown inFIG. 1. First andsecond regions16 and18 may be formed by an implantation process formed on the material making upsubstrate12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first andsecond regions16 and18.
• Afloating body region24 having a first conductivity type, such as p-type conductivity type, is bounded bysurface14, first andsecond regions16,18, buriedoxide layer22, andsubstrate12. Thefloating body region24 can be formed by an implantation process formed on the material making upsubstrate12, or can be grown epitaxially. Agate60 is positioned in between theregions16 and18, and above thesurface14. Thegate60 is insulated fromsurface14 by aninsulating layer62.Insulating layer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell750 further includes word line (WL)terminal70 electrically connected togate60, source line (SL)terminal72 electrically connected toregion16, bit line (BL)terminal74 electrically connected toregion18, andsubstrate terminal78 electrically connected tosubstrate12 at a location beneathinsulator22. Amemory array780 having a plurality ofmemory cells750 is schematically illustrated inFIG. 92A.
• The operation of a memory cell has been described (and also describes the operation of memory cell750) for example in “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002, which is hereby incorporated herein, in its entirety, by reference thereto. The memory cell states are represented by the charge in thefloating body24. Ifcell750 has holes stored in thefloating body region24, then thememory cell750 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to whencell750 does not store holes infloating body region24.
• The charge stored in thefloating body24 can be sensed by monitoring the cell current of thememory cell750. Ifcell750 is in a state “1” having holes in thefloating body region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current (e.g. current flowing from BL to SL terminals), compared to ifcell750 is in a state “0” having no holes infloating body region24. A sensing circuit/read circuitry90 typically connected toBL terminal74 of memory array780 (e.g., see readcircuitry90 inFIG. 92B) can then be used to determine the data state of the memory cell. Examples of such read operations are described in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003 and U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor”, both of which are hereby incorporated herein, in their entireties, by reference thereto. An example of a sensing circuit is described in Oshawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
• A read operation can be performed by applying the following bias conditions: a positive voltage is applied to theselected BL terminal74, and a positive voltage greater than the positive voltage applied to theselected BL terminal74 is applied to theselected WL terminal70, zero voltage is applied to theselected SL terminal72, and zero voltage is applied to thesubstrate terminal78. The unselected BL terminals will remain at zero voltage, the unselected WL terminals will remain at zero or negative voltage, and the unselected SL terminals will remain at zero voltage.
• In one particular non-limiting embodiment, about 0.0 volts is applied to theselected SL terminal72, about +0.4 volts is applied to theselected terminal74, about +1.2 volts is applied to theselected terminal70, and about 0.0 volts is applied tosubstrate terminal78. Theunselected terminals74 remain at 0.0 volts, theunselected terminals70 remain at 0.0 volts, at theunselected SL terminals72 remain at 0.0 volts.FIG. 93 shows the bias conditions for theselected memory cell750aandunselected memory cells750b,750c, and750dinmemory array780.FIG. 94A also shows and example of bias conditions of theselected memory cell750a. However, these voltage levels may vary.
• The bias conditions on unselected memory cells during the exemplary read operation described above with regard toFIG. 93 are shown inFIGS. 94B-94D. The bias conditions for memory cells sharing the same row (e.g. memory cell750b) and those sharing the same column (e.g. memory cell750c) as theselected memory cell750aare shown inFIG. 94B andFIG. 94C, respectively, while the bias condition for memory cells not sharing the same row nor the same column as the selected memory cell750 (e.g. memory cell750d) is shown inFIG. 94D.
• For memory cells sharing the same row as the selected memory cell (e.g. memory cell750b), theWL terminal70 is positively biased, but because theBL terminal74 is grounded, there is no potential difference between the BL and SL terminals and consequently these cells are turned off (seeFIG. 94B).
• For memory cells sharing the same column as the selected memory cell (e.g. memory cell750c), a positive voltage is applied to theBL terminal74. However, since zero or negative voltage is applied to theunselected WL terminal70, these memory cells are also turned off (seeFIG. 94C).
• Formemory cells750 not sharing the same row nor the same column as the selected memory cell (e.g. memory cell750d), both WL and BL terminals are grounded. As a result, these memory cells are turned off (seeFIG. 94D).
• An exemplary write “0” operation of thecell750 is now described with reference toFIG. 95. A negative bias is applied toSL terminal72, zero or negative potential is applied toWL terminal70, zero voltage is applied toBL terminal74 and zero voltage is applied tosubstrate terminal78. The unselected SLterminal72 remains grounded. Under these conditions, the p-n junction betweenfloating body24 andregion16 of theselected cell750 is forward-biased, evacuating any holes from thefloating body24. In one particular non-limiting embodiment, about −1.2 volts is applied toterminal72, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminal74 and78. However, these voltage levels may vary, while maintaining the relative relationship between the applied bias, as described above.
• An example of bias conditions of the selected andunselected memory cells750 during a write “0” operation is illustrated inFIGS. 96A-96B. Because a write “0” operation only involves a negative voltage applied to theselected SL terminal72, the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero or negative voltage, and the unselected SL terminal at about 0.0 volts.
• Alternatively, a write “0” operation can be performed by applying a negative bias to theBL terminal74 as opposed to theSL terminal72. TheSL terminal72 will be grounded, while zero voltage is applied to thesubstrate terminal78, and zero or negative voltage is applied to theWL terminal70. Under these conditions, all memory cells sharing thesame BL terminal74 will be written into state “0” as shown inFIG. 97.
• The write “0” operation referred to above with regard toFIGS. 95-97 has a drawback in that allmemory cells750 sharing either thesame SL terminal72 or thesame BL terminal74 will be written to simultaneously and as a result, does not allow individual bit writing, i.e. writing to asingle cell750 memory bit. To write multiple data todifferent memory cells750, write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.
• An alternative write “0” operation that allows for individual bit writing can be performed by applying a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, and zero voltage tosubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between24 andregion18 is forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells750 in thememory array780, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell750a: a potential of about 0.0 volts toSL terminal72, a potential of about −0.2 volts toBL terminal74, a potential of about +0.5 volts is applied toterminal70, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied tounselected SL terminal72, about 0.0 volts is applied tounselected BL terminal74, about 0.0 volts is applied tounselected WL terminal70, and about 0.0 volts is applied to unselectedterminal78.FIG. 98 shows the bias conditions in the above-described example, for the selected and unselected memory cells inmemory array780. However, these voltage levels may vary.
• The bias conditions of the selectedmemory cell750aunder the write “0” operation described with regard toFIG. 98 are further elaborated and shown inFIG. 99A. As described, the potential difference between floatingbody24 and region18 (connected to BL terminal74) is shown inFIG. 99A as having increased, resulting in a forward bias current which evacuates holes from the floatingbody24.
• Examples of bias conditions on theunselected memory cells750 during write “0” operations described with regard toFIG. 8 are shown inFIGS. 99B-99D. The bias conditions for memory cells sharing the same row (e.g. memory cell750b) are illustrated inFIG. 99B, and the bias conditions for memory cells sharing the same column (e.g. memory cell750c) as the selectedmemory cell750aare shown inFIG. 99C, while the bias conditions for memory cells not sharing the same row nor the same column (e.g. memory cell750d) as the selectedmemory cell750aare shown inFIG. 99D.
• The floatingbody24 potential of memory cells sharing the same row as the selected memory cell (seeFIG. 99B) will increase by ΔV_FBdue to capacitive coupling fromWL terminal70. For memory cells in state “0”, the increase in the floatingbody24 potential is not sustainable as the forward bias current of the p-n diodes formed by floatingbody24 andjunctions16 and18 will evacuate holes from floatingbody24. As a result, the floatingbody24 potential will return to the initial state “0” equilibrium potential. For memory cells in state “1”, the floatingbody24 potential will initially also increase by ΔV_FB, which will result in holes being evacuated from floatingbody24. After the positive bias on theWL terminal70 is removed, the floatingbody24 potential will decrease by ΔV_FB. If the initial floatingbody24 potential of state “1” is referred to as V_FB1, the floatingbody24 potential after the write “0” operation will become V_FB1−ΔV_FB. Therefore, the WL potential needs to be optimized such that the decrease in floating body potential ofmemory cells750 in state “1” is not too large. For example, the maximum floating body potential due to the coupling from the WL potential cannot exceed V_FB1/2.
• For memory cells sharing the same column as the selected memory cell, a negative voltage is applied to the BL terminal74 (seeFIG. 99C), resulting in an increase in the potential difference between floatingbody24 andregion18 connected to theBL terminal74. As a result, the p-n diode formed between floatingbody24 andjunction18 will be forward biased. For memory cells in state “0”, the increase in the floatingbody24 potential will not change the initial state “0” as there is initially no hole stored in the floatingbody24. For memory cells in state “1”, the net effect is that the floatingbody24 potential after write “0” operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential ofmemory cells750 in state “1” is not too large. For example, a potential of −V_FB1/2 can be applied to theBL terminal74.
• As to memory cells not sharing the same row nor the same column as the selected memory cell, zero voltage is applied to theSL terminal72, zero voltage is applied to theBL terminal74, and zero or negative voltage is applied toWL terminal70, and zero voltage is applied to substrate terminal78 (seeFIG. 99D). As a result, holes will not be evacuated from floatingbody region24.
• A write “1” operation can be performed onmemory cell750 through impact ionization as described, for example, in “A New 1T DRAM Cell with Enhanced Floating Body Effect”, Lin and Chang, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
• An example of the bias conditions of the selectedmemory cell750 under a write “1” operation using band-to-band tunneling is illustrated inFIGS. 100 and 101A. The negative bias applied to theWL terminal70 and the positive bias applied to theBL terminal74 results in electron tunneling which results in electron flow to theBL terminal74, generating holes which subsequently are injected to the floatingbody24 of the selectedmemory cell750. TheSL terminal72 and thesubstrate terminal78 are grounded during the write “1” operation.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell750a: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about −1.2 volts is applied toWL terminal70, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied toWL terminal70, and about 0.0 volts is applied tosubstrate terminal78.FIG. 100 shows the bias conditions for the selected and unselected memory cells inmemory array780. However, these voltage levels may vary.
• Examples of bias conditions of the unselected memory cells during write “1” operations of the type described above with regard toFIG. 100 are shown inFIGS. 101B-101D. The bias conditions for memory cells sharing the same row (e.g. memory cell750b) are shown inFIG. 101B and the bias conditions for memory cells sharing the same column as the selectedmemory cell750a(e.g. memory cell750c) are shown inFIG. 101C. The bias conditions formemory cells750 not sharing the same row nor the same column as the selectedmemory cell750a(e.g. memory cell750d) are shown inFIG. 101D.
• For memory cells sharing the same row as the selected memory cell, bothterminals72 and74 are grounded, while about −1.2 volts is applied to WL terminal70 (seeFIG. 101B). There is no hole injection into the floatingbody24 ofmemory cell750bas there is not enough potential difference for band-to-band tunneling to occur.
• For memory cells sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal74 (seeFIG. 101C). No hole injection will occur for these memory cells as theWL terminal70 is being grounded.
• Formemory cells750 not sharing the same row or the same column as the selected memory cell, both theSL terminal72 and theBL terminal74 remain grounded (seeFIG. 101D). Consequently, no write operations will occur to these memory cells.
• An example of the bias conditions of the selectedmemory cell750 under a write “1” operation using an impact ionization write “1” operation is illustrated inFIGS. 102 and 103A-103D. A positive bias is applied to the selectedWL terminal70, zero voltage is applied to allSL terminals72, a positive bias applied to the selectedBL terminal74, while thesubstrate terminal78 of the selected cell is grounded. These condition cause hole injection to the floatingbody24 of the selected memory cell (e.g. cell750ainFIG. 103A).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell750a: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about +1.2 volts is applied to the selectedWL terminal70, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied tounselected SL terminal72, about 0.0 volts is applied tounselected BL terminal74, a potential of about 0.0 volts is applied tounselected WL terminal70, and about 0.0 volts is applied to unselectedsubstrate terminal78.FIG. 103A shows the bias conditions for the selected memory cell in the example described above.FIG. 103B shows the bias conditions for memory cells sharing the same row as the selected memory cell in the example described above with regard toFIG. 102.FIG. 103C shows the bias conditions for memory cells sharing the same column as the selected memory cell in the example described above with regard toFIG. 102.FIG. 103D shows the bias conditions for memory cells that share neither the same row nor the same column as the selected memory cell in the example described above with regard toFIG. 102. However, these voltage levels may vary.
• If floatingbody region24 stores a positive charge, the positive charge stored will decrease over time due to the diode leakage current of the p-n junctions formed between the floatingbody24 andregions16 and18, respectively, and due to charge recombination. A positive bias can be applied to region16 (connected to SL terminal72) and/or to region18 (connected to BL terminal74), while zero or negative voltage is applied toWL terminal70 andsubstrate terminal78.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell750: a potential of about +1.2 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of 0.0 volts is applied toWL terminal70, and 0.0 volts is applied tosubstrate terminal78. Under these conditions, the p-n junctions formed between the floatingbody24 andregions16 and18 are reverse biased, improving the lifetime of the positive charge stored in the floatingbody region24.
• The connection betweenregion16 of thememory cell750 and theSL terminal72 and the connection betweenregion18 of thememory cell750 and theBL terminal74 are usually made through conductive contacts, which for example could be made of polysilicon or tungsten.FIG. 104 showscontact71 connectingregion16 and theSL terminal72 andcontact73 connectingregion18 and theBL terminal74. Many difficulties arise with contact formation. For example, separation between the contact and other electrodes (e.g. the gate electrode or neighboring contacts) must be provided to avoid electrical shorts between neighboring conductive regions. Difficulties related to contact formation and some potential solutions are described for example in U.S. Patent Application Publication No. 2010/0109064, titled “Semiconductor Device and Manufacturing Method Thereof”, which is hereby incorporated herein, in its entirety, by reference thereto.
• To simplify the manufacturing of thememory cell750 and to reduce the size of thememory750, adjacent memory cells can be designed to share a common region16 (and SL terminal72) or a common region18 (and BL terminal74). For example, as shown in FIG. 105, U.S. Pat. No. 6,937,516, “Semiconductor Device” to Fazan and Okhonin, which is hereby incorporated herein, in its entirety, by reference thereto, shows an arrangement where adjacent memory cells sharecommon contacts50 and52. This reduces the number of contacts from two contacts per memory cell (when adjacent contacts are not shared between adjacent memory cells) to where the number of contacts of memory cells in connection equals the number of memory cells plus one. For example, inFIG. 105, the number of interconnected memory cells (the cross section shows memory cells interconnected in the same column) is four and the number of contacts is five.
• The present invention provides a semiconductor memory device having a plurality of floating body memory cells which are connected either in series to from a string, or in parallel to form a link. The connections between the memory cells are made to reduce the number of contacts for each memory cell. In some embodiments, connections between control lines, such as source line or bit line, to the memory cells are made at the end or ends of a string or link of several memory cells, such that memory cells not at the end are “contactless” memory cells, because no contacts are provided on these cells to connect them to control lines. Rather, they are in direct contact with other memory cells that they are immediately adjacent to. Because several memory cells are connected either in series or in parallel, a compact memory cell can be achieved.
• FIG. 106A shows a cross-sectional schematic illustration of amemory string500 that includes a plurality of memory cells750 (750a-750ninFIG. 106A, although there may be more or fewer cells750), whileFIG. 106B shows a top view of thememory cell array780, which shows twostrings500 ofmemory cells750 between theSL terminal72 andBL terminal74. Eachmemory string500 includes a plurality ofmemory cells750 connected in a NAND architecture, in which the plurality ofmemory cells750 are serially connected to make one string of memory cells. In a series connection, the same current flows through each of thememory cells750, from theBL terminal74 to theSL terminal72, or vice versa.String500 includes “n”memory cells750, where “n” is a positive integer, which typically ranges between eight and sixty-four (although this number could be lower than eight (as low as two) or higher than sixty-four), and in at least one example, is sixteen. Theregion18 of a second conductivity at one end of the memory string is connected to theBL terminal74, while thesource region16 of a second conductivity at the other end of the memory string is connected to theSL terminal72. AlthoughFIG. 106B schematically illustrates an array of two strings, it should be noted that the present invention is not limited to two strings.
• Eachmemory cell transistor750 includes a floatingbody region24 of a first conducting type, and first and second regions20 (corresponding to first andsecond regions16 and18 in the single cell embodiments ofcell750 described above) of a second conductivity type, which are spaced apart from each other and define a channel region. A buriedinsulator layer22 isolates the floatingbody region24 from thebulk substrate12. Agate60 is positioned above the surface of floatingbody24 and is in between the first andsecond regions20. An insulatinglayer62 is provided betweengate60 and floatingbody24 to insulategate60 from floatingbody24. As can be seen inFIGS. 106A-106B, connections to the controllines SL terminal72 andBL terminal74 are only made at the ends of thestring500. Connection betweenSL terminal72 andregion16 is made throughcontact71 and connection betweenBL terminal74 andregion18 is made throughcontact73. No contacts are made to theregions20 of thememory cells750 inmemory string500, resulting in contactless memory cells intermediate of the end memory cells. In some embodiments, the transistors at the end of the string500 (e.g.,cells750aand750ninFIG. 106A) may be configured as access transistors to thememory string500, wherein the charges stored in the associated floating bodies24 (in theFIG. 106A example,24aand24n) are not read.
• FIG. 107 shows an equivalent circuit representation of thememory array780 ofFIG. 106B. InFIG. 107, the memory cells are arranged in a grid, with the rows of the memory array being defined by theWL terminals70, while the columns are defined by theBL terminals74. Within each column,multiple memory cells750 are serially connected forming thestring500. Adjacent columns are separated by columns of isolation26 (seeFIG. 106B), such as shallow trench isolation (STI).
• A read operation is described with reference toFIGS. 108 and 109A-109B. The read operation can be performed by applying the following bias conditions, wherememory cell750cis being selected in this example: a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70, zero voltage is applied to the selectedSL terminal72, and zero voltage is applied to thesubstrate terminal78. Theunselected BL terminals74 will remain at zero voltage and theunselected SL terminals72 will remain at zero voltage. A positive voltage greater than the positive voltage applied to the selectedWL terminal70cis applied to passingWL terminals70a,70b,70k,70m, and70n(seeFIGS. 108 and 109A-109B). Passing WL terminals are connected to the gates of the passing cells, i.e. the unselected cells which are serially connected to the selectedmemory cell750c(e.g. memory cells750a,750b,7501,750m, and750ninFIG. 108). The voltages applied to the gate of the passing cells are such that the passing transistors are turned on, irrespective of the potentials of their floating body regions. The passing cells need to be turned on because in a series connection, the current flows from theBL terminal74 to SL terminal72 (or vice versa) thereby flowing through each of thememory cells750. As a result, the passing cells will pass the potentials applied to theSL terminal72 andBL terminal74 to the source and drainregions20band20cof the selectedcell750c. For example, thememory cell750nwill pass the voltage applied to theBL terminal74 toregion20mconnected tocell750n(and750m), whichmemory cell750mwill subsequently pass to theregion201 connected tocell7501. The adjacent passing memory cells will subsequently pass the voltage applied toBL terminal74 until the voltage reachesregion20cof the selectedcell750c.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell750c: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +0.4 volts is applied toBL terminal74, a potential of about +1.2 volts is applied to selectedWL terminal70, about +3.0 volts is applied to passingWL terminals70, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to SL terminal72 (i.e.,unselected SL terminal72 not shown inFIG. 109A), about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied toWL terminal70 that are not passing WL terminals (not shown inFIG. 109A), and about 0.0 volts is applied tosubstrate terminal78.FIGS. 108 and 109A-109B show bias condition for the selected and unselected memory cells inmemory array780. However, these voltage levels may vary.
• Under these conditions, about +1.2 volts will be applied to thegate60 of the selectedcell750cand about 0.0 volts and 0.4 volts will be passed to theregions20band20cof the selectedcells750c, similar to the read condition described inFIG. 94A. As described, the passing cells are biased so that its channels are conducting, and therefore the current flowing from theBL terminal74 andSL terminal72 of thestring500 is then determined by the potential of the floatingbody region24 of the selectedcell750c. Ifcell750cis in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently be conducting a larger current compared to ifcell750cis in a state “0” having no holes in floatingbody region24.
• A sensing circuit/read circuitry90 typically connected toBL terminal74 of memory array780 (e.g., see readcircuitry90 inFIG. 109B) can be used to determine the data state of the memory cell. An example of a sensing circuit is described in Ohsawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
• A write “0” operation is described with reference toFIGS. 110-111. Bias conditions shown include: zero voltage applied to theSL terminal72, zero voltage applied to theWL terminals70, and negative voltage applied to theBL terminal74, while thesubstrate terminal78 is grounded. Under these conditions, the p-n junctions between floatingbodies24 andregions20 of the respective memory cells instring500 are forward-biased, evacuating any holes from each floatingbody24. In one particular non-limiting embodiment, about −1.2 volts is applied toterminal74, about 0.0 volts is applied toterminal70, about 0.0 volts is applied toterminal72 and about 0.0 volts is applied toterminal78. Alternatively, a positive voltage can be applied to theWL terminals70 to ensure that the negative voltage applied to theBL terminal74 is passed to all the memory cells instring500. However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above.
• An alternative write “0” operation that allows for individual bit writing is shown inFIGS. 112A-112B. This write “0” operation can be performed by applying a negative voltage toBL terminal74, zero voltage toSL terminal72, zero voltage tosubstrate terminal78, and a positive voltage to passing WL terminals. The selected WL terminal is initially grounded until the voltages applied toSL terminal72 andBL terminal74 reach theregions20band20c, respectively, of the selectedmemory cell750c. Subsequently, the potential of the selected WL terminal70 (70cin this example) is raised to a positive voltage higher than the positive voltage applied to passing WL terminals. Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell750cinFIGS. 112A-112B) and consequently the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. The passing cells (e.g. memory cell7501,750m, and750n) will pass the negative voltage applied to theBL terminal74 to theregion20cof thememory cell750c, while passingcells750aand750bwill pass zero voltage applied to theSL terminal72 to theregion20bof thememory cell750c. Under these conditions, the bias conditions of the selectedmemory cell750cwill be similar to the conditions described inFIG. 99A. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between24candregion20cis forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells750 in thememory array780, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to V_FB1, then the voltage applied to the selectedWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. The voltage applied to WL terminal of the passing cells is optimized such that it is high enough to pass the negative voltage applied to theBL terminal74, but cannot be too high to prevent the potential of the floatingbody24 of the passing cells becoming too high, which will result in holes being evacuated from the passing cells that are in state “1”. A higher positive voltage can be applied to passing WL terminals passing zero voltage applied to the SL terminal72 (e.g. passing WL terminals to the left ofselected WL terminal70c, i.e.70aand70binFIG. 112A) than the voltage applied to passing WL terminals passing negative voltage applied to the BL terminal74 (e.g. passing WL terminals to the right ofselected WL terminal70c). This is because the higher voltage applied to terminal72 (compared to the negative voltage applied to terminal74) may require a higher passing gate voltage for the passing transistors to be turned on.
• In one particular non-limiting embodiment, the following bias conditions are applied to the memory string500: a potential of about 0.0 volts is applied toSL terminal72, a potential of about −0.2 volts is applied toBL terminal74, a potential of about +0.5 volts is applied to selectedterminal70, a potential of about +0.2 volts is applied to passingWL terminals70 and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied tounselected SL terminal72, about 0.0 volts is applied tounselected BL terminal74, about 0.0 volts is applied to unselected (but not passing)WL terminal70, and about 0.0 volts is applied to unselectedterminal78.FIG. 112A shows the bias conditions for the selected and passing memory cells in selectedmemory string500, whileFIG. 112B shows the bias conditions for selected and unselected memory cells inmemory array780 wherememory cell750cis the selected cell. However, these voltage levels may vary.
• Under these bias conditions, a positive voltage will be applied to thegate60 of the selectedcell750c, while a negative voltage applied to theBL terminal74 will be passed to theregion20cof the selectedcell750c, and zero voltage applied to theSL terminal72 will be passed to theregion20bof the selectedcell750c. This condition is similar to the condition described inFIG. 99A, which will result in hole evacuation out of the floatingbody24 of thecell750c.
• A write “1” operation can be performed onmemory cell750 through impact ionization as described for example in Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or by a band-to-band tunneling mechanism, as described for example in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
• An example of bias conditions of a selectedmemory cell750 during a band-to-band tunneling write “1” operation is illustrated inFIGS. 113A and113B. A negative bias is applied to the selectedWL terminal70, a positive voltage is applied to the passingWL terminals70, zero voltage is applied to the SL terminal72 (and to all SL terminals72), and a positive bias is applied to the selected BL terminal74 (zero voltage is applied to unselected BL terminals74), while thesubstrate terminal78 is grounded. These conditions cause hole injection to the floatingbody24 of the selected memory cell (e.g. cell750cinFIGS. 113A-113B).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory string500: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about −1.2 volts is applied to the selectedWL terminal70, about +3.0 volts is applied to the passingWL terminals70, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied to unselected (but not passing) WL terminal70 (not shown inFIG. 113B), and about 0.0 volts is applied tosubstrate terminal78.FIG. 113A shows the bias conditions for the selected and passing memory cells in selectedmemory string500, whileFIG. 113B shows the bias conditions for the selected and unselected memory cells inmemory array780, wherememory cell750cis the selected cell. However, these voltage levels may vary.
• Under these bias conditions, a negative voltage will be applied to thegate60 of the selectedcell750c, while a positive voltage applied to theBL terminal74 will be passed to theregion20cof the selectedcell750c, and zero voltage applied to theSL terminal72 will be passed to theregion20bof the selectedcell750c. This condition is similar to the condition described inFIG. 101A, which will result in hole injection to the floatingbody24 of thecell750c.
• An example of the bias conditions of the selectedmemory cell750 under an impact ionization write “1” operation is illustrated inFIGS. 114A-114B. A positive bias is applied to the selectedWL terminal70, a positive voltage more positive than the positive voltage applied to the selectedWL terminal70 is applied to the passingWL terminals70, zero voltage is applied to the SL terminal72 (both the selectedSL terminal72 as well as all other SL terminals72), and a positive bias is applied to the selected BL terminal74 (zero voltage is applied to the unselected BL terminals74), while thesubstrate terminal78 is grounded. These conditions cause hole injection to the floatingbody24 of the selected memory cell (e.g. cell750cinFIGS. 114A-114B).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory string500: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about +1.2 volts is applied to the selectedWL terminal70, about +3.0 volts is applied to the passingWL terminals70, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals (i.e., terminals in strings other than the string that the selected cell is in): about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied to WL terminal70 (not shown inFIG. 114B), and about 0.0 volts is applied tosubstrate terminal78.FIG. 114A shows the bias conditions for the selected and passing memory cells in selectedmemory string500, whileFIG. 114B shows bias conditions for selected and unselected memory cells in memory array780 (withmemory cell750cas the selected cell). However, these voltage levels may vary.
• A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to thememory cell750, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to thememory cell750, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
• For example, using band-to-band hot hole injection, a positive voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, a negative voltage is applied to the selectedWL terminal70, a positive voltage is applied to the passing WL terminals, and zero voltage is applied to thesubstrate terminal78. Positive voltages of different amplitudes are applied toBL terminal74 to write different states to floatingbody24. This results in different floatingbody potentials24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied toBL terminal74. In one particular non-limiting embodiment, the write operation is performed by applying the following bias conditions: a potential of about 0.0 volts is applied toSL terminal72, a potential of about −1.2 volts is applied to the selectedWL terminal70, about +3.0 volts is applied to the passing WL terminals, and about 0.0 volts is applied tosubstrate terminal78, while the potential applied toBL terminal74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied toBL terminal74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever state ofstates 00, 01, 10 or 11 is desired is achieved), then the multi write operation is concluded. If the desired state is not achieved, then the voltage applied toBL terminal74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.
• Thestring500 may be provided as planar cells, such as the embodiments described above with reference toFIGS. 91 and 106A, or may be provided as fin-type, three-dimensional cells, such as those illustrated inFIGS. 115A-115B, for example. Other variations, modifications andalternative cells750 may be provided without departing from the scope of the present invention and its functionality.
• Referring now toFIG. 23 above, amemory cell150 according to an embodiment of the present invention is shown. Thecell150 is fabricated on abulk substrate12 having a first conductivity type (such as p-type conductivity). A buriedlayer22 of a second conductivity type (such as n-type conductivity) is also provided in thesubstrate12 and buried in thesubstrate12, as shown.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can be grown epitaxially.
• Afirst region16 having the second conductivity type is provided insubstrate12 andfirst region16 is exposed atsurface14. Asecond region18 having the second conductivity type is also provided insubstrate12, is also exposed atsurface14 and is spaced apart from thefirst region16. First andsecond regions16 and18 may be formed by an implantation process formed on the material making upsubstrate12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first andsecond regions16 and18.
• A floatingbody region24 having a first conductivity type, such as p-type conductivity type, is bounded bysurface14, first andsecond regions16,18, insulatinglayers26, and buriedlayer22. Insulating layers26 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 insulatecell150 from neighboringcells150 whenmultiple cells150 are joined in anarray180. The floatingbody region24 can be formed by an implantation process formed on the material making upsubstrate12, or can be grown epitaxially. Agate60 is positioned in between theregions16 and18, and above thesurface14. Thegate60 is insulated fromsurface14 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell150 further includes word line (WL) terminal70 electrically connected togate60, source line (SL) terminal72 electrically connected toregion16, bit line (BL) terminal74 electrically connected toregion18, buried well (BW) terminal76 connected to buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12 at a location beneathinsulator22.
• The operation of amemory cell150 has been described for example in Ranica et al., “Scaled 1T-Bulk Devices Built withCMOS 90 nm Technology for Low-cost eDRAM Applications”, pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005 and application Ser. No. 12/797,334, titled “Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor”, both of which are hereby incorporated herein, in their entireties, by reference thereto.
• Memory cell states are represented by the charge in the floatingbody24. Ifcell150 has holes stored in the floatingbody region24, then thememory cell150 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to whencell150 does not store holes in floatingbody region24.
• As shown inFIG. 25 above, inherent in this embodiment of thememory cell150 are n-p-nbipolar devices130a,130bformed by buriedwell region22, floatingbody24, and SL andBL regions16,18. A holding operation can be performed by utilizing the properties of the n-p-nbipolar devices130a,130bthrough the application of a positive back bias to theBW terminal76 while groundingterminal72 and/orterminal74. If floatingbody24 is positively charged (i.e. in a state “1”), thebipolar transistor130aformed bySL region16, floatingbody24, and buried wellregion22 andbipolar transistor130bformed byBL region18, floatingbody24, and buried wellregion22 will be turned on.
• A fraction of the bipolar transistor current will then flow into floating region24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing thebipolar devices130a,130bformed by buriedwell layer22, floatingregion24, andregions16/18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofBW terminal76 to the base current flowing into the floatingregion24.
• For memory cells in state “0” data, thebipolar devices130a,130bwill not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in state “0” will remain in state “0”.
• An example of the bias conditions applied tocell150 to carry out a holding operation includes: zero voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, a positive voltage is applied to theBW terminal76, and zero voltage is applied tosubstrate terminal78. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary.
• FIG. 116A shows an energy band diagram of the intrinsic n-p-n bipolar device130 when the floatingbody region24 is positively charged and a positive bias voltage is applied to the buriedwell region22. The dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor130. The Fermi levels are located in the band gap between thesolid line17 indicating the top of the valance band (the bottom of the band gap) and thesolid line19 indicating the bottom of the conduction band (the top of the band gap). The positive charge in the floatingbody region24 lowers the energy barrier of electron flow into the floating body region24 (i.e., the base region of the n-p-n bipolar device). Once injected into the floatingbody region24, the electrons will be swept into the buried well region22 (connected to BW terminal76) due to the positive bias applied to the buriedwell region22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theBW terminal76 while the resulting hot holes will subsequently flow into the floatingbody region24. This process restores the charge on floatingbody24 to its maximum level and will maintain the charge stored in the floatingbody region24 which will keep the n-p-n bipolar transistor130 on for as long as a positive bias is applied to the buriedwell region22 throughBW terminal76.
• If floatingbody24 is neutrally charged (the voltage on floatingbody24 being equal to the voltage on grounded bit line region16), a state corresponding to state “0”, the bipolar device will not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in the state “0” will remain in the state “0”.
• FIG. 116B shows an energy band diagram of the intrinsic n-p-n bipolar device130 when the floatingbody region24 is neutrally charged and a bias voltage is applied to the buriedwell region22. In this state the energy level of the band gap bounded bysolid lines17A and19A is different in the various regions of n-p-n bipolar device130. Because the potential of the floatingbody region24 and thebit line region16 are equal, the Fermi levels are constant, resulting in an energy barrier between thebit line region16 and the floatingbody region24.Solid line23 indicates, for reference purposes, the energy barrier between thebit line region16 and the floatingbody region24. The energy barrier prevents electron flow from the bit line region16 (connected to BL terminal74) to the floatingbody region24. Thus the n-p-n bipolar device130 will remain off.
• Although the embodiment discussed inFIGS. 25, 116A and 116B refers to bipolar devices130 as n-p-n transistors, persons of ordinary skill in the art will readily appreciate that by reversing the first and second connectivity types and inverting the relative values of the appliedvoltages memory cell150 could include a bipolar device130 which is a p-n-p transistor. Thus the choice of an n-p-n transistor as an illustrative example for simplicity of explanation inFIGS. 25, 116A and 116B is not limiting in any way. In addition, the discussions in regard toFIGS. 25, 116A and 116B usebipolar device130bformed bybit line region18, floatingbody region24, and buried wellregion22, and the same principles also apply tobipolar device130aformed bysource line region16, floatingbody region24 and buried wellregion22.
• The charge stored in the floatingbody24 can be sensed by monitoring the cell current of thememory cell150. Ifcell150 is in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current (e.g. current flowing from BL to SL terminals), compared to ifcell150 is in a state “0” having no holes in floatingbody region24. Examples of the read operation is described in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003; Ohsawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating body Cell”, pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005; and U.S. Pat. No. 7,301,803 “Bipolar reading technique for a memory cell having an electrically floating body transistor”, which are hereby incorporated herein, in their entireties, by reference thereto.
• A read operation can be performed oncell150 by applying the following bias conditions: zero voltage is applied to theBW terminal76, zero voltage is applied toSL terminal72, a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70, while zero voltage is applied tosubstrate terminal78. Whencell150 is in anarray180 of cells150 (e.g., seeFIG. 117), theunselected BL terminals74 will remain at zero voltage and theunselected WL terminals70 will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied toterminal72, about +0.4 volts is applied to the selected terminal74a, about +1.2 volts is applied to the selected terminal70a, about 0.0 volts is applied toterminal76, and about 0.0 volts is applied toterminal78, as illustrated inFIG. 117.
• A write “0” operation of thecell150 is now described with reference toFIG. 118. In this example, to write “0” tocell150, a negative bias is applied toSL terminal72, zero voltage is applied toBL terminal74, zero or negative voltage is applied toWL terminal70, zero or positive voltage is applied toBW terminal76, and zero voltage is applied tosubstrate terminal78. TheSL terminal72 for theunselected cells150 that are not commonly connected to the selectedcell150awill remain grounded. Under these conditions, the p-n junctions (junction between24 and16) are forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −1.2 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, about 0.0 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above. Under these conditions, all memory cells sharing thesame SL terminal72 will be written into state “0”.
• A write “0” operation can also be performed by applying a negative bias to theBL terminal74 as opposed to theSL terminal72. TheSL terminal72 will be grounded, while zero or positive voltage is applied toBW terminal76, zero voltage is applied to thesubstrate terminal78, and zero or negative voltage is applied to theWL terminal70. Under these conditions, all memory cells sharing thesame BL terminal74 will be written into state “0”.
• The write “0” operations referred to above with regard toFIG. 118 have a drawback in that allmemory cells150 sharing either thesame SL terminal72 or thesame BL terminal74 will be written to simultaneously and as a result, these operations do not allow individual bit writing, i.e. writing to asingle cell150 memory bit. To write multiple data todifferent memory cells150, write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.
• An alternative write “0” operation, which, unlike the previous write “0” operations described above with regard toFIG. 118, allows for individual bit write, can be performed by applying a positive voltage toWL terminal70, a negative voltage toBL terminal74, zero or positive voltage toSL terminal72, zero or positive voltage toBW terminal76, and zero voltage tosubstrate terminal78, an example of which is illustrated inFIG. 119. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction (junction between24 and18) is forward-biased, evacuating any holes from the floatingbody24. The applied bias to selectedWL terminal70 and selectedBL terminal74 can potentially affect the states of theunselected memory cells150 sharing the same WL or BL terminal as the selectedmemory cell150. To reduce undesired write “0” disturb toother memory cells150 in thememory array180, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to as V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. This will minimize the floatingbody24 potential change in theunselected cells150 in state “1” sharing the same BL terminal as the selectedcell150 from V_FB1to V_FB1/2. Formemory cells150 in state “0” sharing the same WL terminal as the selectedcell150, unless the increase in floatingbody24 potential is sufficiently high (i.e., at least V_FB/3, see below), then both n-p-nbipolar devices130aand130bwill not be turned on, or so that the base hold current is low enough that it does not result in an increase of the floatingbody24 potential over the time during which the write operation is carried out (write operation time). It has been determined according to the present invention that a floatingbody24 potential increase of V_FB/3 is low enough to suppress the floatingbody24 potential increase. A positive voltage can be applied toSL terminal72 to further reduce the undesired write “0” disturb onother memory cells150 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied toWL terminal70 and zero voltage applied toBL terminal74.
• In one particular non-limiting embodiment, for the selectedcell150 a potential of about 0.0 volts is applied toterminal72, a potential of about −0.2 volts is applied toterminal74, a potential of about +0.5 volts is applied toterminal70, about 0.0 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. For the unselected cells not sharing the same WL terminal or BL terminal with the selectedmemory cell150, about 0.0 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, about 0.0 volts is applied toterminal76, and about 0.0 volts is applied toterminal78.FIG. 119 shows the aforementioned bias conditions for the selectedmemory cell150 andother cells150 in thearray180. However, these voltage levels may vary.
• A write “1” operation can be performed onmemory cell150 through impact ionization as described for example in Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or a band-to-band tunneling mechanism, as described for example in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
• An example of the bias conditions of the selectedmemory cell150 under a band-to-band tunneling write “1” operation is illustrated inFIG. 120A. The negative bias applied to the WL terminal70 (70ainFIG. 120A) and the positive bias applied to the BL terminal74 (74ainFIG. 120A) results in hole injection to the floatingbody24 of the selected memory cell150 (150ainFIG. 120A). The SL terminal72 (72ainFIG. 120A) and the substrate terminal78 (78ainFIG. 120A) are grounded during the write “1” operation, while zero or positive voltage can be applied to BW terminal76 (76ainFIG. 120A) (positive voltage can be applied to maintain the resulting positive charge on the floatingbody24 as discussed in the holding operation above). The unselected WL terminals70 (70ninFIG. 31A) and unselected BL terminals74 (74ninFIG. 120A) will remain grounded.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell150a: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about −1.2 volts is applied toWL terminal70, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied toWL terminal70, about 0.0 volts is applied to BW terminal76 (or +1.2 volts so that unselected cells are in the holding operation) and about 0.0 volts is applied tosubstrate terminal78.FIG. 120A shows the bias condition for the selectedmemory cell150. However, these voltage levels may vary.
• FIG. 120B shows bias conditions of the selected (150a) and unselected (150b,150c,150d)memory cells150 during an impact ionization write “1” operation. A positive voltage is applied to the selected WL terminal70 (i.e.,70ainFIG. 120B) and a positive voltage is applied to the selected BL terminal74 (i.e.,74ainFIG. 120B), with the SL terminal72 (i.e.,72ainFIG. 120B), the BW terminal76 (i.e.,76ainFIG. 120B), and the substrate terminal78 (i.e.,78ainFIG. 120B) are grounded. This condition results in a lateral electric field in the channel region sufficient to create hot electrons, which subsequently create electron and hole pairs, with the holes being subsequently injected to the floatingbody region24 of the selected memory cell. Theunselected WL terminals70 and unselectedBL terminals74 are grounded, while the unselected BW terminal can be grounded or a positive voltage can be applied thereto to maintain the states of the unselected cells.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell150a: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about +1.2 volts is applied toWL terminal70, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied toWL terminal70, about 0.0 volts is applied to BW terminal76 (or +1.2 volts so that unselected cells are in the holding operation) and about 0.0 volts is applied tosubstrate terminal78.FIG. 120B shows the bias conditions for the selectedmemory cell150. However, these voltage levels may vary.
• FIG. 121A shows a cross-sectional schematic illustration of amemory string520 that includes a plurality ofmemory cells150 connected in series, whileFIG. 121B shows a top view of amemory cell array180, which shows two strings ofmemory cells520 between theSL terminal72 andBL terminal74. AlthoughFIG. 121B schematically illustrates an array of two strings, it should be noted that the present invention is not limited to two strings, as one string, or more than two string can be made in the same manner as described. Eachmemory string520 includes a plurality ofmemory cells150 connected in a NAND architecture, in which the plurality ofmemory cells150 are serially connected to make one string of memory cells. In a series connection, the same current flows through each of thememory cells150, from theBL terminal74 to theSL terminal72, or vice versa.String520 includes “n”memory cells150, where “n” is a positive integer, which typically ranges between 8 and 64, and in at least one example, is 16. However,string520 could have less than eight cells (as low as two) or greater than sixty-four cells. Theregion18 of a second conductivity at one end of the memory string is connected to theBL terminal74, while thesource region16 of a second conductivity at the other end of the memory string is connected to theSL terminal72.
• Eachmemory cell transistor150 includes a floatingbody region24 of a first conducting type, and first and second regions20 (corresponding to first andsecond regions16 and18 in the single cell embodiments ofcell150 described above) of a second conductivity type, which are spaced apart from each other and define a channel region.Regions20 of adjacent memory cells within astring520 are connected together by the conductingregion64.
• A buriedlayer22 isolates the floatingbody region24 from thebulk substrate12, while insulatinglayers26 isolate the floatingbody region24 betweenadjacent memory cells150. Agate60 is positioned above the surface of floatingbody24 and is in between the first andsecond regions20. An insulatinglayer62 is provided betweengate60 and floatingbody24 to insulategate60 from floatingbody24.
• FIG. 121C shows an equivalent circuit representation of amemory array180 that includesstrings520aand520bas well as additional strings. InFIG. 121C, the memory cells are arranged in a grid, with the rows of thememory array180 being defined by theWL terminals70, while the columns are defined by theBL terminals74. Within each column,multiple memory cells150 are serially connected forming thestring520. Adjacent columns are separated by columns of isolation, such as shallow trench isolation (STI).
• The memory cell operations ofmemory string520 will be described as follows. As will be seen, the operation principles of this embodiment of thememory string520 will follow the operation principles ofmemory string500 described above, where theback bias terminal76 available inmemory string520 can be used to perform holding operation. In some embodiments, the transistors at the end of the string520 (e.g.,cells150aand150ninFIG. 121A) may be configured as access transistors to thememory string520, wherein the charges stored in the associated floating bodies24 (floatingbodies24aand24nin the example ofFIG. 121A) are not read.
• A read operation is described with reference toFIGS. 122, 123A and 123B. The read operation can be performed by applying the following bias conditions, wherememory cell150cwithin thememory string520ais being selected (as shown inFIG. 122): a positive voltage is applied to the selectedBL terminal74, and a positive voltage greater than the positive voltage applied to the selectedBL terminal74 is applied to the selectedWL terminal70, zero voltage is applied to the selectedSL terminal72, zero or positive voltage is applied toBW terminal76, and zero voltage is applied to thesubstrate terminal78. Theunselected BL terminals74 will remain at zero voltage and theunselected SL terminals72 will remain at zero voltage as shown inFIG. 123A. A positive voltage greater than the positive voltage applied to the selectedWL terminal70cis applied to passingWL terminals70a,70b,701,70m, and70n(seeFIGS. 122 and 123A-123B). Passing WL terminals are connected to the gates of the passing cells, i.e. the unselected cells which are serially connected to the selectedmemory cell150c(e.g. memory cells150a,150b,150l,150m, and150ninFIG. 122). The voltages applied to the gates of the passing cells are such that the passing transistors are turned on, irrespective of the potentials of their floating body regions. The passing cells need to be turned on because in a series connection, the current flows from theBL terminal74 to the SL terminal72 (or vice versa) wherein current flows through each of thememory cells150. As a result, the passing cells will pass the potentials applied to theSL terminal72 andBL terminal74 to the source and drainregions20band20cof the selectedcell150c. For example, thememory cell150nwill pass the voltage applied to theBL terminal74 toregion20mconnected tocell150n(and150m), whichmemory cell150mwill subsequently pass to theregion201 connected to cell150l, etc. The adjacent passing memory cells sequentially pass the voltage applied toBL terminal74 until it reachesregion20cof the selectedmemory cell50c.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell150: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +0.4 volts is applied toBL terminal74, a potential of about +1.2 volts is applied to selectedWL terminal70, about +3.0 volts is applied to passingWL terminals70, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied to WL terminal70 (but not passing WL terminal), about 0.0 volts is applied to BW terminal76 (or +1.2 volts is applied toBW terminal76 to maintain the states of the unselected memory cells), and about 0.0 volts is applied tosubstrate terminal78.FIGS. 123A-123B show the bias conditions for the selected and unselected memory cells inmemory array180. However, these voltage levels may vary.
• Under these conditions, about +1.2 volts will be applied to thegate60cand about 0.0 volts and 0.4 volts will be passed to theregions20band20cof the selectedcell150c, similar to the read condition described inFIG. 117. As described, the passing cells are biased so that their channels are conducting, and therefore the current flowing from theBL terminal74 andSL terminal72 of thestring520 is then determined by the potential of the floatingbody region24 of the selectedcell150c. Ifcell150cis in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently be conducting a larger current compared to ifcell150 is in a state “0” having no holes in floatingbody region24.
• The current flow from theBL terminal74 toSL terminal72 can then be measured or sensed using aread circuitry90 attached toBL terminal74 as illustrated inFIG. 123B. The memory state can then be determined by comparing it with a reference value generated by areference generator circuitry92 coupled to a reference cell inmemory string520R as shown inFIG. 123B.
• A write “0” operation is described with reference toFIGS. 124-125, where the following bias conditions are applied: zero voltage to theSL terminal72, zero voltage to theWL terminals70, and negative voltage to theBL terminal74, while theBW terminal76 andsubstrate terminal78 are grounded. Under these conditions, the p-n junctions between floatingbody24 andregions20 of the memory cells instring520 are forward-biased, evacuating any holes from the floatingbodies24. In one particular non-limiting embodiment, about −1.2 volts is applied toterminal74, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminals72,76, and78. A positive voltage can also be applied to theWL terminals70 to ensure that the negative voltage applied to theBL terminal74 is passed to all the memory cells instring520. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• An alternative write “0” operation that allows for individual bit writing is illustrated inFIGS. 126-127 and can be performed by applying a negative voltage toBL terminal74, zero voltage toSL terminal72, zero voltage toBW terminal76, zero voltage tosubstrate terminal78, and a positive voltage to passing WL terminals. The selected WL terminal is initially grounded until the voltages applied toSL terminal72 andBL terminal74 reach theregions20band20c, respectively, of selectedmemory cell150c. Subsequently, the potential of the selectedWL terminal70 is raised to a positive voltage higher than the positive voltage applied to passing WL terminals. Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell150cinFIGS. 126-127) and consequently the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. The passing cells (e.g. memory cell150l,150m, and150n) will pass the negative voltage applied to theBL terminal74 to theregion20cof thememory cell150c, while passingcells150aand150bwill pass zero voltage applied to theSL terminal72 to theregion20bof thememory cell150c, similar to the conditions described in regard toFIG. 119. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between floatingbody region24candregion20cis forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells150 in thememory array180, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to V_FB1, then the voltage applied to the selectedWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. The voltage applied to WL terminal of the passing cells is optimized such that it is high enough to pass the negative voltage applied to theBL terminal74, but cannot be too high to prevent the potential of the floatingbody24 of the passing cells becoming too high, which will result in holes being evacuated from the passing cells that are in state “1”. A higher positive voltage can be applied to passing WL terminals passing zero voltage applied to the SL terminal72 (e.g. passing WL terminals to the left ofselected WL terminal70c, i.e.70aand70binFIG. 126) than the voltage applied to passing WL terminals passing negative voltage applied to the BL terminal74 (e.g. passing WL terminals to the right ofselected WL terminal70c). This is because the higher voltage applied to terminal72 (compared to the negative voltage applied to terminal74) may require a higher passing gate voltage for the passing transistors to be turned on.
• In one particular non-limiting embodiment, the following bias conditions are applied to the memory string520: a potential of about 0.0 volts toSL terminal72, a potential of about −0.2 volts toBL terminal74, a potential of about +0.5 volts is applied to selectedterminal70, a potential of about +0.2 volts is applied to passingWL terminals70, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied tounselected SL terminal72, about 0.0 volts is applied tounselected BL terminal74, about 0.0 volts is applied to BW terminal76 (or +1.2 volts is applied toBW terminal76 to maintain the states of the unselected memory cells), about 0.0 volts is applied to unselected (but not passing)WL terminal70, and about 0.0 volts is applied to unselectedterminal78.FIGS. 126-127 show the bias conditions for the selected and unselected memory cells inmemory array180 wherememory cell150cis the selected cell. However, these voltage levels may vary.
• Under these bias conditions, a positive voltage will be applied to thegate60 of the selectedcell150c, while a negative voltage applied to theBL terminal74 will be passed to theregion20cof the selectedcell150c, and zero voltage applied to theSL terminal72 will be passed to theregion20bof the selectedcell150c. This condition is similar to the condition described in regard toFIG. 119, and results in hole evacuation out of the floatingbody24cof thecell150c.
• A write “1” operation can be performed onmemory cell150 through impact ionization as described for example in Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, which was incorporated by reference above, or a write “1” operation can be performed through a band-to-band tunneling mechanism, as described for example in Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
• An example of bias conditions on a selectedmemory cell150 under a band-to-band tunneling write “1” operation is illustrated inFIGS. 128 and 129. A negative bias is applied to the selectedWL terminal70, a positive voltage is applied to the passingWL terminals70, zero voltage is applied to theSL terminal72, and a positive bias applied to theBL terminal74, zero voltage is applied to theBW terminal76, while thesubstrate terminal78 is grounded. This condition results in hole injection to the floatingbody24 of the selected memory cell (e.g. cell150cinFIGS. 128-129).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell150c: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about −1.2 volts is applied to the selectedWL terminal70, about +3.0 volts is applied to the passingWL terminals70, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied to WL terminal70 (but not passing WL terminal), about 0.0 volts is applied to BW terminal76 (or +1.2 volts is applied to maintain the states of the unselected memory cells), and about 0.0 volts is applied tosubstrate terminal78.FIG. 129 shows the bias conditions for the selected and unselected memory cells inmemory array180 wherememory cell150cis the selected cell. However, these voltage levels may vary.
• Under these bias conditions, a negative voltage will be applied to thegate60 of the selectedcell150c, while a positive voltage applied to theBL terminal74 will be passed to theregion20cof the selectedcell150c, and zero voltage applied to theSL terminal72 will be passed to theregion20bof the selectedcell150c. This condition is similar to the condition described inFIG. 120A, and results in hole injection to the floatingbody24cof thecell150c.
• An example of the bias conditions on the selectedmemory cell150 under an impact ionization write “1” operation is illustrated inFIGS. 130A-130B. A positive bias is applied to the selectedWL terminal70, a positive voltage more positive than the positive voltage applied to the selectedWL terminal70 is applied to the passingWL terminals70, zero voltage is applied to theSL terminal72, a positive bias is applied to theBL terminal74, and zero voltage is applied toBW terminal76, while thesubstrate terminal78 is grounded. These conditions result in hole injection to the floatingbody24 of the selected memory cell (e.g. cell150cinFIGS. 130A-130B).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell150c: a potential of about 0.0 volts is applied toSL terminal72, a potential of about +1.2 volts is applied toBL terminal74, a potential of about +1.2 volts is applied to the selectedWL terminal70, about +3.0 volts is applied to the passingWL terminals70, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied toSL terminal72, about 0.0 volts is applied toBL terminal74, a potential of about 0.0 volts is applied to WL terminal70 (but not passing WL terminal), about 0.0 volts is applied to BW terminal76 (or +1.2 volts is applied toBW terminal76 to maintain the states of the unselected memory cells), and about 0.0 volts is applied tosubstrate terminal78.FIG. 130B shows the bias conditions for the selected and unselected memory cells in memory array180 (withmemory cell150cas the selected cell). However, these voltage levels may vary.
• A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to thememory cell150, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to thememory cell150, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
• For example, using band-to-band hot hole injection, a positive voltage is applied toBL terminal74, zero voltage is applied toSL terminal72, a negative voltage is applied to the selectedWL terminal70, a positive voltage is applied to the passing WL terminals, zero voltage is applied to theBW terminal76 and zero voltage is applied to thesubstrate terminal78. Positive voltages of different amplitudes are applied toBL terminal74 to write different states to floatingbody24. This results in different floatingbody potentials24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied toBL terminal74. In one particular non-limiting embodiment, the write operation is performed by applying the following bias conditions: a potential of about 0.0 volts is applied toSL terminal72, a potential of about −1.2 volts is applied to the selectedWL terminal70, about +3.0 volts is applied to the passing WL terminals, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78, while the potential applied toBL terminal74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied toBL terminal74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever state of 00, 01, 10 or 11 is the desired state has been achieved), then the multi write operation is concluded. If the desired state has not been achieved, then the voltage applied toBL terminal74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.
• Thestring520 may be constructed from a plurality of planar cells, such as the embodiments described above with reference toFIGS. 23 and 121A, or may be constructed from fin-type, three-dimensional cells, such as illustrated inFIGS. 32-33 above. Other variations, modifications andalternative cells150 may be provided without departing from the scope of the present invention and its functionality.
• Another embodiment ofmemory array880 is described with reference toFIGS. 131A-131B, whereFIG. 131A shows a top view of thememory array880 consisting of two strings ofmemory cells540 between theSL terminal72 andBL terminal74, andFIG. 131B shows the cross section of amemory string540. AlthoughFIG. 131A schematically illustrates an array of two strings, it should be noted that the present invention is not limited to two strings, as more than two, or even only one string could be provided.
• Eachmemory string540 ofarray880 includes a plurality ofmemory cells850 connected in a NAND architecture, in which the plurality ofmemory cells850 are serially connected to make one string of memory cells.String540 includes “n”memory cells850, where “n” is a positive integer, which typically ranges between 8 and 64, and in at least one example, is 16. However, this embodiment, like the embodiment above is not limited to the stated range, as fewer than eight or more than sixty-four cells could be included in a string. Theregion18 of a second conductivity at one end of the memory string is connected to theBL terminal74 throughcontact73, while thesource region16 of a second conductivity at the other end of the memory string is connected to theSL terminal72 throughcontact71. In some embodiments, the transistors at the ends of the string540 (e.g.,cells850aand850nin the example ofFIG. 131B) may be configured as access transistors to thememory string540, and charged stored in the associated floating bodies24 (24aand24nin the example ofFIG. 131B) are not read.
• Referring toFIG. 131B, thememory cell850 includes asubstrate12 of a first conductivity type, such as p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. A buriedlayer22 of a second conductivity type such as n-type, for example, is provided in thesubstrate12.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can also be grown epitaxially on top ofsubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top by region16 (orregion18 or region20) of the second conductivity type and insulatinglayer62, on the sides by region16 (orregion18 or region20) of the second conductivity type and insulatinglayers30 and26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayer30 and the region16 (orregion18 or region20) of the second conductivity type insulate the floatingbody region24 along the I-I′ direction as shown inFIG. 131B, while insulatinglayer28 insulates the floatingbody region24 along the II-II′ direction as shown inFIG. 131A.
• Regions16,18, and20 having a second conductivity type, such as n-type, for example, are provided insubstrate12 and are exposed atsurface14.Regions16,18, and20 may be formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formregions16,18, and20. Althoughregions16,18, and20 have the same conductivity type (for example n-type), the dopant concentration forming these regions can be (but need not necessarily be) different. InFIGS. 131A and 131B,regions16 and18 are located at the ends of thememory string540, whileregions20 are located inside thememory string540, isolating adjacent floatingbody regions24 ofadjacent memory cells850.
• Agate60 is positioned above the surface of floatingbody24 and is in between the first and second regions20 (or betweenregion16 andregion20 or betweenregion18 and region20). Thegate60 is insulated from floatingbody region24 by an insulatinglayer62.
• Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Memory string540 further includes word line (WL)terminals70 electrically connected togates60, source line (SL) terminal72 electrically connected toregion16, bit line (BL) terminal74 electrically connected toregion18, buried layer (BW) terminal76 connected to buriedlayer22, andsubstrate terminal78 electrically connected tosubstrate12.
• TheBW terminal76 connected to the buriedlayer region22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor.
• A method ofmanufacturing memory array880 will be described with reference toFIGS. 132A-132U. These figures are arranged in groups of three related views, with the first figure of each group being a top view ofmemory cell850, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a vertical cross section of the top view in the first figure of the group designated II-II′.
• Turning now toFIGS. 132A through 132C, the first steps of the process can be seen starting with growing a thickconductive region202 comprised of a different material from the materials forming thesubstrate region12. Theconductive region202 can be selectively etched without removing thesubstrate region12. For example, theconductive region202 could be made of silicon germanium (SiGe) material, whilesubstrate12 could be made of silicon, although materials for both of these layers may vary.
• As shown inFIGS. 132D through 132F, apattern30′ covering the areas to become insulator region30 (as shown in the final structures inFIGS. 132S through132U) is formed using a lithography process. Theconductive region202 is then etched following the lithography pattern.
• Referring toFIGS. 132G through 132I, aconductive region204 comprising for example the same material forming thesubstrate12 is grown (like, for example, silicon). A chemical mechanical polishing step can then be performed to polish the resulting films so that the silicon surface is flat. Subsequently, a thin layer ofsilicon oxide206 is grown on the surface offilm204. This is followed by a deposition of apolysilicon layer208 and thensilicon nitride layer210.
• Next, a pattern is formed for use in opening the areas to becomeinsulator regions28. The pattern can be formed using a lithography process. This is then followed by dry etching of thesilicon nitride layer210,polysilicon layer208,silicon oxide layer206, andsilicon layer204, creatingtrench212, as shown inFIGS. 132J and 132L (trenches212 are not visible in the view ofFIG. 132K).
• A wet etch process that selectively removes theregion202 is then performed, leaving gaps that are mechanically supported byregion204 The resulting gap regions are then oxidized to form buriedoxide regions30 as shown inFIGS. 132N and 132O. Subsequently, the remainingsilicon nitride layer210,polysilicon layer208, andsilicon oxide layer206 are then removed, followed by a silicon oxide deposition process and a chemical mechanical polishing step to planarize the resulting silicon oxide film, resulting in the siliconoxide insulator region28 as shown inFIGS. 132M and 132O. Alternatively, the silicon deposition step can be performed prior to the removal of thesilicon nitride layer210,polysilicon layer208 andsilicon oxide layer206.
• Referring toFIGS. 132P through 132R, an ion implantation step is next performed to form the buriedlayer region22. Subsequently a silicon oxide layer (or high-dielectric material layer)62 is formed on the silicon surface (FIGS. 132Q-132R), followed by polysilicon (or metal)layer214 deposition (FIGS. 132Q-132R).
• A pattern covering the area to be made intogate60 is next made, such as by using a lithography process. The pattern forming step is followed by dry etching of the polysilicon (or metal)layer214 and silicon oxide (or high dielectric materials)layer62. An ion implantation step is then performed to form theregions20 of the second conductivity type (e.g. n-type). Theconductive region204 underneath thegate region60 is protected from the ion implantation process and is now bounded byregions20, insulatinglayer30 and insulatinglayer28 on the sides, and by buriedlayer22 from thesubstrate12, and by insulatinglayer62 at the surface, forming the floating body region24 (seeFIG. 132T). This is then followed by backend process to form contact and metal layers (not shown in figures).
• Another embodiment of memory array is shown asmemory array980 inFIG. 133, whereinmemory array980 comprises a link connecting a plurality ofmemory cells950 in parallel.FIG. 134A shows a top view ofmemory cell950 in isolation, withFIGS. 134B and 134C showing sectional views of thememory cell950 taken along lines I-I′ and II-II′ respectively.
• Referring toFIGS. 134B and 134C together, thecell950 is fabricated on silicon on insulator (SOI)substrate12 of a first conductivity type such as a p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. A buriedinsulator layer22, such as buried oxide (BOX), is provided in thesubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top by insulatinglayer62, on the sides byregions20 of a second conductivity type and insulatinglayers26, and on the bottom by buriedlayer22. Insulating layers26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 insulatecell950 from neighboringcells950 whenmultiple cells950 are joined in anarray980 to make a memory device as illustrated inFIGS. 133 and 135.
• Regions20 having a second conductivity type, such as n-type, for example, are provided insubstrate12 and are exposed atsurface14.Regions20 may be formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formregions20.
• Agate60 is positioned above the floatingbody region24 andregions20. Thegate60 is insulated from floatingbody region24 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Region20 is continuous (electrically conductive) in the direction along the II-II′ direction (referring toFIG. 134A) and can be used to connectseveral memory cells950 in parallel as shown in the equivalent circuit representation of thememory array980 inFIGS. 47 and 49 (whereregions20 are connected to bet line (BL)terminals74. Connections betweenregions20 and bit line (BL)terminals74aand74bcan be made throughcontacts73 at the edge of the parallel connections (seeFIG. 133). An adjacent pair ofcontinuous regions20 can be used to connect a link ofcells950 in parallel.Cell950 further includes word line (WL) terminal70 electrically connected togate60 andsubstrate terminal78 electrically connected to substrate12 (seeFIGS. 134B-134C). In a parallel connection, the voltage applied to theBL terminals74 is about the same across all memory cells950 (small differences might occur due to voltage drop along the bit lines) and the current will only flow through the selectedmemory cell950.
• Because it is possible to minimize the number of connections to BL terminals by making them only at the edge of the parallel connections, the number of contacts can be reduced, for example to two contacts, for each parallel connection. No contacts are made to theregions20 of thememory cells950 that are not at the edge of the parallel connections inmemory array980, resulting in contactless memory cells in locations that are not at the edge (end). The number of contacts can be increased to reduce the resistance of the parallel connections if desired.
• A read operation is described with reference toFIGS. 136-137, wherememory cell950bis being selected (as shown inFIG. 136). The following bias conditions may be applied: a positive voltage is applied toBL terminal74b, zero voltage is applied toBL terminal74c, a positive voltage is applied toWL terminal70b, and zero voltage is applied tosubstrate terminal78. The unselected BL terminals (e.g. BL terminal74a,74d, . . . ,74pinFIG. 136) are left floating, the unselected WL terminals (e.g. WL terminal70a,70m,70ninFIG. 136) will remain at zero voltage, and the unselectedsubstrate terminal78 will remain at zero voltage. Alternatively, the unselected BL terminals to the right ofBL terminal74c(where zero voltage is applied to) can be grounded. A positive voltage of the same amplitude as that applied toBL terminal74bcan be applied to the unselected BL terminals to the left ofBL terminal74b. Because theregion20b(connected toBL terminal74b) is shared with theadjacent cell950a, the unselected BL terminals to the left ofBL terminal74b(where a positive voltage is applied to) need to be left floating or have a positive voltage applied thereto to prevent any parasitic current flowing fromBL terminal74bto the BL terminals to the left ofBL terminal74b. Alternatively, the bias conditions onBL terminals74band74c(connected toregions20 of the selectedmemory cell950b) may be reversed.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell950b: a potential of about +0.4 volts is applied toBL terminal74b, a potential of about 0.0 volts is applied toBL terminal74c, a potential of about +1.2 volts is applied toWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected WL terminals, about 0.0 volts is applied to unselected substrate terminals, while the unselected BL terminals are left floating.
• As shown inFIG. 137, about +1.2 volts are applied to thegate60b, about 0.4 volts are applied to theregion20b(connected toBL terminal74b), about 0.0 volts are applied toregion20c(connected toBL terminal74c), and about 0.0 volts are applied tosubstrate12 of selectedmemory cell950b. The current flowing fromBL terminal74btoBL terminal74cwill then be determined by the potential of the floatingbody region24 of the selectedcell950b.
• Ifcell950bis in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently be conducting a larger current compared to ifcell950bis in a state “0” having no holes in floatingbody region24. The cell current can be sensed by, for example, a sense amplifier circuit connected toBL terminal74b.
• A write “0” operation is described with reference toFIGS. 138-139, where the following bias conditions are applied: zero voltage to theWL terminals70, and negative voltage to theBL terminal74b, while thesubstrate terminal78 is grounded. Under these conditions, the p-n junction between floatingbody24 andregion20bof thememory cell950 is forward-biased, evacuating any holes from the floatingbody24. Theunselected BL terminals74 can be left floating or grounded, theunselected WL terminals70 will remain at zero voltage, and the unselectedsubstrate terminal78 will remain at zero voltage.
• In one particular non-limiting embodiment, about −1.2 volts is applied to terminal74b, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above. BecauseBL terminal74bis connected toseveral memory cells950, all memory cells connected toBL terminal74bwill be written to state “0”, as indicated by the memory cells inside the dashed lines inFIG. 138.
• An alternative write “0” operation that allows for more selective bit writing is shown inFIGS. 140-141 and can be performed by applying a negative voltage toBL terminal74b, zero voltage tosubstrate terminal78, and a positive voltage toWL terminal70b. The unselected WL terminals will remain at zero voltage, the unselected BL terminals will be left floating or grounded, and the unselectedsubstrate terminal78 will remain at zero voltage.
• Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell950aand950binFIG. 140, see alsogate60binFIG. 141) and consequently the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74b, the p-n junction between24 andregion20bis forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells950 in thememory array980, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to V_FB1, then the voltage applied to the selectedWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74b. Under these conditions,memory cell950aand950bwill be written to state “0” (compared to the previous write “0” described above, which results in all memory cells sharing thesame BL terminal74bto be written to state “0”).
• In one particular non-limiting embodiment, the following bias conditions are applied to the memory cell950: a potential of about −0.2 volts toBL terminal74b, a potential of about +0.5 volts is applied to selectedWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; whileunselected BL terminals74 are left floating, about 0.0 volts is applied tounselected WL terminal70, and about 0.0 volts is applied to unselectedterminal78.FIG. 140 shows the bias conditions for the selected and unselected memory cells inmemory array980 wherememory cells950aand950bare the selected cells. However, these voltage levels may vary.
• An example of the bias conditions on a selectedmemory cell950bunder an impact ionization write “1” operation is illustrated inFIGS. 142-143. A positive bias is applied to the selectedWL terminal70b, zero voltage is applied to theBL terminal74c, a positive bias applied to theBL terminal74b, while thesubstrate terminal78 is grounded. This condition results in a lateral electric field sufficient to generate energetic electrons, which subsequently generate electron-hole pairs, followed by hole injection to the floatingbody24 of the selected memory cell (e.g. cell950binFIGS. 142-143). The unselected WL terminals (e.g. WL terminal70a,70c,70m, and70ninFIG. 142) are grounded, the unselected BL terminals (e.g. BL terminal74a,74d,74m,74n,74o, and74pinFIG. 142) are left floating, and the unselectedsubstrate terminal78 is grounded. Alternatively, the unselected BL terminals to the right ofBL terminal74c(where zero voltage is applied to) can be grounded. A positive voltage of the same amplitude as that applied toBL terminal74bcan be applied to the unselected BL terminals to the left ofBL terminal74b. Because theregion20b(connected toBL terminal74b) is shared with theadjacent cell950a, the unselected BL terminals to the left ofBL terminal74b(where a positive voltage is applied to) need to be left floating or applied a positive voltage to prevent any parasitic current flowing fromBL terminal74bto the BL terminals to the left ofBL terminal74b, which can cause undesired write “1” operations to at least oneunselected memory cell950.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell950b: a potential of about 0.0 volts is applied toBL terminal74c, a potential of about +1.2 volts is applied toBL terminal74b, a potential of about +1.2 volts is applied to the selectedWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: a potential of about 0.0 volts is applied to unselected WL terminals70 (e.g. WL terminals70a,70m, and70ninFIG. 142), about 0.0 volts is applied tosubstrate terminal78, and the unselected BL terminals74 (e.g. BL terminals74c,74d,74m,74n,74o, and74pinFIG. 142) are left floating.FIGS. 142-143 show the bias conditions for the selected and unselected memory cells in memory array980 (withmemory cell950bas the selected cell). However, these voltage levels may vary. Alternatively, the bias conditions onBL terminals74band74c(connected toregions20 of the selectedmemory cell950b) may be reversed.
• FIG. 144 schematically illustrates a memory array according to another embodiment of the present invention.Memory array1080 includes a plurality ofmemory cells1050.FIG. 145A shows a top view ofmemory cell1050 in isolation, withFIGS. 145B and 145C showing sectional views of thememory cell1050 taken along lines I-I′ and II-II′ ofFIG. 145A, respectively.
• Referring toFIGS. 145B and 145C together, thecell1050 includes asubstrate12 of a first conductivity type such as a p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. A buriedlayer22 of a second conductivity type such as n-type, for example, is provided in thesubstrate12.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can be grown epitaxially on top ofsubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top byregions20 and insulatinglayer62, on the sides by insulatinglayers26, and on the bottom by buriedlayer22. Insulating layers26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 insulatecell1050 from neighboringcells1050 whenmultiple cells1050 are joined in anarray1080 to make a memory device as illustrated inFIG. 144.
• Regions20 having a second conductivity type, such as n-type, for example, are provided insubstrate12 and are exposed atsurface14.Regions20 are formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formregions20.
• Agate60 is positioned above the floatingbody region24,regions20 and insulatinglayers26. Thegate60 is insulated from floatingbody region24 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Region20 is continuous (electrically conductive) in the direction along the II-II′ direction (referring toFIG. 145A) and can be used to connectseveral memory cells1050 in parallel as shown in the equivalent circuit representation of thememory array1080 inFIGS. 144 and 146 (where theregions20 are connected to bit line (BL) terminals74). Connections betweenregions20 and bit line (BL)terminals74aand74bcan be made throughcontacts73 at the edge of the parallel connections (seeFIG. 144). An adjacent pair ofcontinuous regions20 can be used to connect a link ofcells1050 in parallel. In a parallel connection, the voltage applied to theBL terminals74 is about the same across all memory cells1050 (small differences might occur due to voltage drop along the bit lines) and the current will only flow through the selectedmemory cell1050.Cell1050 further includes word line (WL) terminal70 electrically connected togate60, buried well (BW) terminal76 connected to buriedlayer22, andsubstrate terminal78 electrically connected to substrate12 (seeFIGS. 145B-145C).
• Because it is possible to make connections to BL terminals only at the edge of the parallel connections, the number of contacts can be reduced, for example to two contacts, for each parallel connection. No contacts to the memory cells that are not at the edge of the parallel connection are necessary, as these are contactless memory cells that are continuously linked byregions20. The number of contacts can be increased to reduce the resistance of the parallel connections if desired.
• A read operation of the embodiment ofFIGS. 144-145C is described with reference toFIGS. 147-148, wherememory cell1050bis being selected (as shown inFIG. 147). The following bias conditions may be applied: a positive voltage is applied toBL terminal74a, zero voltage is applied toBL terminal74b, a positive voltage is applied toWL terminal70b, zero voltage is applied toBW terminal76 and zero voltage is applied tosubstrate terminal78. The unselected BL terminals (e.g.BL terminal74c,74d, . . . ,74pinFIG. 147) will remain at zero voltage, the unselected WL terminals (e.g. WL terminal70a,70m,70ninFIG. 147) will remain at zero voltage, theunselected BW terminals76 will remain at zero voltage (or a positive bias can be applied to maintain the states of the unselected memory cells), and theunselected substrate terminals78 will remain at zero voltage. Alternatively, the bias conditions onBL terminals74aand74b(connected toregions20 of the selectedmemory cell1050b) may be reversed.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell1050b: a potential of about +0.4 volts is applied toBL terminal74a, a potential of about 0.0 volts is applied toBL terminal74b, a potential of about +1.2 volts is applied toWL terminal70b, about 0.0 volts is applied toBW terminal76 and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected BL terminals, about 0.0 volts is applied to unselected WL terminals, about 0.0 volts is applied to unselected BW terminals (or +1.2 volts is applied toBW terminal76 to maintain the states of the unselected memory cells), and about 0.0 volts is applied to unselected substrate terminals.
• As shown inFIG. 148, about +1.2 volts will be applied to thegate60b(connected to terminal70b), about 0.4 volts will be applied to theregion20a(connected toBL terminal74a), about 0.0 volts will be applied toregion20b(connected toBL terminal74b), about 0.0 volts will be applied to buriedlayer22, and about 0.0 will be applied tosubstrate12 of selectedmemory cell1050b. The current flowing from BL terminal74atoBL terminal74bwill then be determined by the potential of the floatingbody region24 of the selectedcell1050b.
• Ifcell1050bis in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently be conducting a larger current compared to ifcell1050bis in a state “0” having no holes in floatingbody region24. The cell current can be sensed by, for example, a sense amplifier circuit connected toBL terminal74a.
• A write “0” operation is described with reference toFIGS. 149-150, where the following bias conditions are applied: zero voltage to theBL terminal74b, zero voltage to theWL terminals70, and negative voltage to theBL terminal74a, while theBW terminal76 andsubstrate terminal78 are grounded. Under these conditions, the p-n junction between floatingbody24 andregion20aof thememory cell1050 is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −1.2 volts is applied to terminal74a, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminals76 and78. However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above. Alternatively, the write “0” operation can be achieved by reversing the bias conditions applied toBL terminals74aand74b.
• An alternative write “0” operation that allows for individual bit writing are shown inFIGS. 151-152 and can be performed by applying a negative voltage toBL terminal74a, zero voltage toBL terminal74b, zero voltage toBW terminal76, zero voltage tosubstrate terminal78, and a positive voltage toWL terminal70. Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell1050binFIGS. 151-152) and consequently the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74a, the p-n junction between24 andregion20ais forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells1050 in thememory array1080, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to V_FB1, then the voltage applied to the selectedWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74a.
• In one particular non-limiting embodiment, the following bias conditions are applied to thememory cell1050b: a potential of about 0.0 volts toBL terminal74b, a potential of about −0.2 volts toBL terminal74a, a potential of about +0.5 volts is applied to selectedWL terminal70b, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied tounselected BL terminals74, about 0.0 volts is applied to BW terminal76 (or +1.2 volts is applied toBW terminal76 to maintain the states of the unselected memory cells), about 0.0 volts is applied tounselected WL terminal70, and about 0.0 volts is applied to unselectedterminal78.FIGS. 151-152 show the bias conditions for the selected and unselected memory cells inmemory array1080 wherememory cell1050bis the selected cell. However, these voltage levels may vary. Alternatively, the write “0” operation can be achieved by reversing the bias conditions applied toBL terminals74aand74b.
• An example of the bias conditions on a selectedmemory cell1050bundergoing a band-to-band tunneling write “1” operation is illustrated inFIGS. 153 and 154. A negative bias is applied to the selectedWL terminal70b, zero voltage is applied to theBL terminal74b, a positive bias is applied to theBL terminal74a, zero voltage is applied to theBW terminal76, and thesubstrate terminal78 is grounded. These conditions cause electrons flow to theBL terminal74a, generating holes which subsequently are injected into the floatingbody region24.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell1050b: a potential of about 0.0 volts is applied toBL terminal74b, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about −1.2 volts is applied to the selectedWL terminal70b, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected BL terminals (e.g. BL terminals74c,74d,74m,74n,74o, and74pinFIG. 153), a potential of about 0.0 volts is applied to unselected WL terminals70 (e.g. WL terminals70a,70m, and70ninFIG. 153), about 0.0 volts is applied to unselected BW terminals76 (or +1.2 volts is applied to maintain the states of the unselected memory cells), and about 0.0 volts is applied to unselectedsubstrate terminals78.FIGS. 153-154 show the bias conditions for the selected and unselected memory cells inmemory array1080 wherememory cell1050bis the selected cell. However, these voltage levels may vary. Alternatively, the write “1” operation can be achieved by reversing the bias conditions applied toBL terminals74aand74b.
• An example of the bias conditions on a selectedmemory cell1050bundergoing an impact ionization write “1” operation is illustrated inFIGS. 155-156. A positive bias is applied to the selectedWL terminal70b, zero voltage is applied to theBL terminal74b, a positive bias is applied to theBL terminal74a, zero voltage is applied toBW terminal76, and thesubstrate terminal78 is grounded. These conditions cause a lateral electric field sufficient to generate energetic electrons, which subsequently generate electron-hole pairs, followed by hole injection into the floatingbody24 of the selected memory cell (e.g. cell1050binFIGS. 155-156).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell1050b: a potential of about 0.0 volts is applied toBL terminal74b, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about +1.2 volts is applied to the selectedWL terminal70b, about 0.0 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected BL terminals74 (e.g. BL terminals74c,74d,74m,74n,74o, and74pinFIG. 155), a potential of about 0.0 volts is applied to unselected WL terminals70 (e.g. WL terminals70a,70m, and70ninFIG. 155), about 0.0 volts is applied to BW terminal76 (or +1.2 volts is applied toBW terminal76 to maintain the states of the unselected memory cells), and about 0.0 volts is applied tosubstrate terminal78.FIGS. 155-156 show the bias conditions for the selected and unselected memory cells in memory array1080 (withmemory cell1050bas the selected cell). However, these voltage levels may vary. Alternatively, the write “1” operation can be achieved by reversing the bias conditions applied toBL terminals74aand74b.
• FIG. 157 shows an alternative embodiment ofmemory array1090, whereadjacent regions20 are connected to acommon BL terminal74 through aconductive region64. The operation ofmemory array1090 is similar to that ofmemory array980 fabricated on a silicon on insulator (SOI) surface, whereregions20 are shared between twoadjacent memory cells950.
• FIG. 158A shows another embodiment of a memory array, referred to as1180.Memory array1180 comprises a plurality ofmemory cells1150.FIG. 158B shows amemory cell1150 in isolation whileFIGS. 158C and 158D show sectional views of thememory cell1150 ofFIG. 158B taken along lines I-I′ and II-II′ ofFIG. 158B, respectively.
• Memory cell1150 includes asubstrate12 of a first conductivity type such as a p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. A buriedlayer22 of a second conductivity type such as n-type, for example, is provided in thesubstrate12.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can be grown epitaxially on top ofsubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top byregion16 and insulatinglayer62, on the sides by insulatinglayers26 and28, and on the bottom by buriedlayer22, seeFIGS. 158C-158D. Insulatinglayers26 and28 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulatinglayers26 and28 insulatecell1150 from neighboringcells1150 whenmultiple cells1150 are joined in anarray1180 to make a memory device as illustrated inFIG. 158A. Insulatinglayer26 insulate bothbody region24 and buriedregion22 of adjacent cells (seeFIG. 158C), while insulatinglayers28 insulate neighboringbody regions24, but not the buriedlayer22, allowing the buriedlayer22 to be continuous (i.e. electrically conductive) in one direction (along the II-II′ direction as shown inFIG. 158D).
• Aregion16 having a second conductivity type, such as n-type, for example, is provided insubstrate12 and is exposed atsurface14.Region16 is formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process can be used to formregion16.Region16 is continuous (electrically conductive) in the direction along the II-II′ direction (referring toFIG. 158B) and can be used to connectseveral memory cells1150 in parallel like shown in the equivalent circuit representation of thememory array1180 inFIG. 159.
• Agate60 is positioned in between theregion16 and insulatinglayer26 and above the floatingbody region24. Thegate60 is insulated from floatingbody region24 by an insulatinglayer62, seeFIG. 158C. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Contact between bit line (BL) terminal74aandregion16 and contact between source line (SL) terminal72aand buriedlayer22 can be made at the edge of the parallel connections.Cell1150 further includes word line (WL) terminal70 electrically connected togate60 andsubstrate terminal78 electrically connected tosubstrate12. Region16 (connected to BL terminal74) and buried layer22 (connected to SL terminal72) can be used to connect a link ofcells1150 in parallel. In a parallel connection, the voltage applied to theSL terminal72 andBL terminal74 is about the same for all memory cells1150 (small differences might occur due to voltage drop along the bit lines) and the current will only flow through the selectedmemory cell1150.
• FIG. 159 shows an equivalent circuit representation ofmemory array1180, where a plurality ofmemory cells1150 are connected in parallel. Because it is possible to make connections to SL and BL terminals at only the edge of the parallel connections, the number of contacts can be reduced, for example to two contacts, for each parallel connection. No contacts are made to theregions16 and22 of thememory cells1150, except for thosecells1150 at the edge of the parallel connections inmemory array1180. Thus, thosecells1150 not at the edge of the parallel connections are contactless memory cells. Of course, the number of contacts can be increased to reduce the resistance of the parallel connections if desired.
• FIG. 160A shows an equivalent circuit representation ofmemory cell1150, consisting of a n-p-nbipolar device30 formed by buriedwell region22, floatingbody24, andregion16, with agate60 coupled to the floatingbody region24.
• A holding operation can be performed by utilizing the properties of the n-p-nbipolar devices30 through the application of a positive back bias to theSL terminal72 while groundingterminal74. If floatingbody24 is positively charged (i.e. in a state “1”), the bipolar transistor formed byBL region16, floatingbody24, and buried wellregion22 will be turned on.
• A fraction of the bipolar transistor current will then flow into floating region24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing thebipolar device30 formed by buriedwell layer22, floatingregion24, andregion16 to be a low-gain, (i.e., as near to 1:1 as practical) bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out ofSL terminal72 to the base current flowing into the floatingregion24.
• For memory cells in state “0” data, thebipolar device30 will not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in state “0” will remain in state “0”.
• An example of the bias conditions applied tocell1150 to carry out a holding operation includes: zero voltage is applied toBL terminal74, a positive voltage is applied toSL terminal72, zero or negative voltage is applied toWL terminal70, and zero voltage is applied tosubstrate terminal78. In one particular non-limiting embodiment, about +1.2 volts is applied toterminal72, about 0.0 volts is applied toterminal74, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary.
• FIG. 160B shows an energy band diagram of the intrinsic n-p-nbipolar device30 ofFIG. 160B when the floatingbody region24 is positively charged and a positive bias voltage is applied to the buriedwell region22. The dashed lines indicate the Fermi levels in the various regions of then-p-n transistor30. The Fermi level is located in the band gap between thesolid line17 indicating the top of the valance band (the bottom of the band gap) and thesolid line19 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. The positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floatingbody region24, the electrons will be swept into the buried well region22 (connected to SL terminal72) due to the positive bias applied to the buriedwell region22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theSL terminal72 while the resulting hot holes will subsequently flow into the floatingbody region24. This process restores the charge on floatingbody24 to its maximum level and will maintain the charge stored in the floatingbody region24 which will keep the n-p-nbipolar transistor30 on for as long as a positive bias is applied to the buriedwell region22 throughSL terminal72.
• If floatingbody24 is neutrally charged (i.e., the voltage on floatingbody24 being substantially equal to the voltage on grounded bit line region16), a state corresponding to state “0”, the bipolar device will not be turned on, and consequently no base hole current will flow into floatingregion24. Therefore, memory cells in the state “0” will remain in the state “0”.
• FIG. 160C shows an energy band diagram of the intrinsic n-p-nbipolar device30 ofFIG. 160A when the floatingbody region24 is neutrally charged and a bias voltage is applied to the buriedwell region22. In this state the energy level of the band gap bounded bysolid lines17A and19A is different in the various regions of n-p-nbipolar device30. Because the potentials of the floatingbody region24 and thebit line region16 are substantially equal, the Fermi levels are constant, resulting in an energy barrier between thebit line region16 and the floatingbody region24.Solid line23 indicates, for reference purposes, the energy barrier between thebit line region16 and the floatingbody region24. The energy barrier prevents electron flow from the bit line region16 (connected to BL terminal74) to the floatingbody region24. Thus the n-p-nbipolar device30 will remain off.
• To perform the holding operation, a periodic pulse of positive voltage can be applied to the back bias terminals ofmemory cells1150 throughSL terminal72 as opposed to applying a constant positive bias, thereby reducing the power consumption of thememory cells1150.
• Although for description purposes, thebipolar devices30 in the embodiment ofFIGS. 160A through 160C have been described as n-p-n transistors, persons of ordinary skill in the art will readily appreciate that by reversing the first and second connectivity types and inverting the relative values of the appliedvoltages memory cell1150 could comprise abipolar device30 which is a p-n-p transistor. Thus the choice of an n-p-n transistor as an illustrative example for simplicity of explanation inFIGS. 160A through 160C is not limiting in any way.
• A read operation is described with reference toFIGS. 161-162, wherememory cell1150bis being selected (as shown inFIG. 161). The following bias conditions may be applied: a positive voltage is applied toBL terminal74a, zero voltage is applied toSL terminal72a, a positive voltage is applied toWL terminal70b, and zero voltage is applied tosubstrate terminal78. The unselected BL terminals (e.g.BL terminal74b,74c, . . . ,74pinFIG. 161) remain at zero voltage, the unselected SL terminals (e.g. SL terminals72b,72c, . . . ,72pinFIG. 161) remain at zero voltage, the unselected WL terminals (e.g. WL terminal70a,70m,70ninFIG. 161) remain at zero voltage, and the unselectedsubstrate terminal78 remains at zero voltage. Alternatively, a positive voltage can be applied to the unselected BL terminals connected to the buried layer region to maintain the states of the unselected memory cells.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell1150b: a potential of about +0.4 volts is applied toBL terminal74a, a potential of about 0.0 volts is applied toSL terminal72a, a potential of about +1.2 volts is applied toWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected BL terminals (or +1.2 volts can be applied to SL terminals connected to the buried layer region to maintain the states of the unselected memory cells), about 0.0 volts is applied to unselected WL terminals, and about 0.0 volts is applied to unselected substrate terminals.
• As shown inFIG. 162, about +1.2 volts will be applied to thegate60b, about 0.4 volts will be applied to the region16 (connected toBL terminal74a), about 0.0 volts will be applied to buried layer region22 (connected toSL terminal72a), about 0.0 volts will be applied to buriedlayer22, and about 0.0 will be applied tosubstrate12 of selectedmemory cell1150b. The current flowing from BL terminal74atoSL terminal72awill then be determined by the potential of the floatingbody region24 of the selectedcell1150b.
• Ifcell1150bis in a state “1” having holes in the floatingbody region24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently will conduct a larger current compared to ifcell1150bis in a state “0” having no holes in floatingbody region24. The cell current can be sensed by, for example, a sense amplifier circuit connected toBL terminal74a.
• Alternatively, the read operation can be performed by reversing the conditions applied toBL terminal74 andSL terminal72.
• A write “0” operation is described with reference toFIGS. 163-164, where the following bias conditions are applied: zero voltage to theSL terminal72a, zero voltage to theWL terminals70, negative voltage to theBL terminal74a, and thesubstrate terminal78 is grounded. Under these conditions, the p-n junction between floatingbody24 andregion16 of thememory cell1150 is forward-biased, evacuating any holes from the floatingbody24. Allmemory cells1150 sharing thesame BL terminal74awill be written to state “0”. The unselected WL terminals, unselected BL terminals, unselected SL terminals, and unselected substrate terminals are grounded.
• In one particular non-limiting embodiment, about −1.2 volts is applied to terminal74a, about 0.0 volts is applied toSL terminal72a, about 0.0 volts is applied toterminal70, and about 0.0 volts is applied tosubstrate terminal78. The unselected BL terminals74 (e.g. BL terminals74b,74c, . . . ,74o, and74p) will remain at 0.0 volts, the unselected SL terminals74 (e.g. SL terminals72b,72c, . . . ,72o, and72p) will remain at 0.0 volts, and the unselectedsubstrate terminal78 will remain at 0.0 volts. However, these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above.
• Alternatively the write “0” operation can be achieved by reversing the bias condition applied toBL terminals74 andSL terminals72.
• An alternative write “0” operation that allows for individual bit writing is shown inFIGS. 165-166, and can be performed by applying a negative voltage toBL terminal74a, zero voltage toSL terminal72a, zero voltage tosubstrate terminal78, and a positive voltage toWL terminal70. Under these conditions, a positive voltage will be applied to the gate of the selected memory cell (e.g. memory cell1150binFIGS. 165-166) and consequently the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74a, the p-n junction between24 andregion16 is forward-biased, evacuating any holes from the floatingbody24. To reduce undesired write “0” disturb toother memory cells1150 in thememory array1180, the applied potential can be optimized as follows: if the floatingbody24 potential of state “1” is referred to V_FB1, then the voltage applied to the selectedWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74a.
• In one particular non-limiting embodiment, the following bias conditions are applied to the memory cell1150: a potential of about 0.0 volts toSL terminal72a, a potential of about −0.2 volts toBL terminal74a, a potential of about +0.5 volts is applied to selectedWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied tounselected BL terminals74, about 0.0 volts is applied to unselected SL terminals, about 0.0 volts is applied tounselected WL terminal70, and about 0.0 volts is applied to unselectedterminal78. Alternatively, a positive voltage, for example of +1.2 volts, can be applied tounselected SL terminals72 connected to the buriedlayer region22 to maintain the states of the unselected memory cells.FIGS. 165-166 show the bias condition for the selected and unselected memory cells inmemory array1180 wherememory cell1150bis the selected cell. However, these voltage levels may vary.
• Alternatively, the write “0” operation described above can be achieved by reversing the bias condition applied toBL terminals74 andSL terminals72.
• An example of the bias condition of the selectedmemory cell1150bunder band-to-band tunneling write “1” operation is illustrated inFIGS. 167 and 168. A negative bias is applied to the selectedWL terminal70b, zero voltage is applied to theSL terminal72a, and a positive bias applied to theBL terminal74a, while thesubstrate terminal78 is grounded. This condition results in electrons flow to theBL terminal74a, generating holes which subsequently are injected to the floatingbody region24.
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell1150b: a potential of about 0.0 volts is applied toSL terminal72a, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about −1.2 volts is applied to the selectedWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected BL terminals (e.g. BL terminals74b,74c, . . . ,74o, and74pinFIG. 167), about 0.0 volts is applied to unselected SL terminals (e.g. SL terminals72b,72c, . . . ,72o, and72pinFIG. 167), a potential of about 0.0 volts is applied to unselected WL terminal70 (e.g. WL terminals70a,70m, and70ninFIG. 167), and about 0.0 volts is applied tosubstrate terminal78. A positive voltage of about +1.2 volts can alternatively be applied (either continuously, or intermittently in pulse fashion as described above, to reduce power consumption) to unselected SL terminals connected to the buriedlayer region22 to maintain the states of the unselected memory cells).FIGS. 167-168 show the bias conditions for the selected and unselected memory cells inmemory array1180 wherememory cell1150bis the selected cell. However, these voltage levels may vary.
• An example of the bias conditions on the selectedmemory cell1150bunder impact ionization write “1” operation is illustrated inFIGS. 169-170. A positive bias is applied to the selectedWL terminal70b, zero voltage is applied to theSL terminal72a, a positive bias is applied to theBL terminal74a, and thesubstrate terminal78 is grounded. These conditions result in a lateral electric field sufficient to generate energetic electrons, which subsequently generate electron-hole pairs, followed by hole injection to the floatingbody24 of the selected memory cell (e.g. cell1150binFIGS. 169-170).
• In one particular non-limiting embodiment, the following bias conditions are applied to the selectedmemory cell1150b: a potential of about 0.0 volts is applied toSL terminal72a, a potential of about +1.2 volts is applied toBL terminal74a, a potential of about +1.2 volts is applied to the selectedWL terminal70b, and about 0.0 volts is applied tosubstrate terminal78; while the following bias conditions are applied to the unselected terminals: about 0.0 volts is applied to unselected BL terminals74 (e.g. BL terminals74b,74c, . . . ,74o, and74pinFIG. 169), about 0.0 volts is applied to unselected SL terminals72 (e.g. SL terminals72b,72c, . . . ,72o, and72pinFIG. 169), a potential of about 0.0 volts is applied to unselected WL terminals70 (e.g. WL terminals70a,70m, and70ninFIG. 169), and about 0.0 volts is applied tosubstrate terminal78. A positive voltage of about +1.2 volts can alternatively (either continuously, or intermittently in pulse fashion as described above, to reduce power consumption) be applied tounselected SL terminals72 connected to the buriedlayer region22 to maintain the states of the unselected memory cells).FIGS. 169-170 show the bias conditions on the selected and unselected memory cells in memory array1180 (withmemory cell1150bas the selected cell). However, these voltage levels may vary.
• Alternatively, the write “1” operations under band-to-band tunneling and impact ionization mechanisms described above can be achieved by reversing the bias conditions applied toBL terminals74 andSL terminals72.
• Thearray1180 may be constructed from a plurality of planar cells, such as the embodiments described above with reference toFIGS. 158C and 158D, or, alternatively, may be constructed from fin-type, three-dimensional cells. Other variations, modifications and alternative cells may be provided without departing from the scope of the present invention and its functionality.
• From the foregoing it can be seen that with the present invention, a semiconductor memory with electrically floating body is achieved. The present invention also provides the capability of maintaining memory states or parallel non-algorithmic periodic refresh operations. As a result, memory operations can be performed in an uninterrupted manner. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed. While the present invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, process, process step or steps, to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto.
• The present invention provides a semiconductor memory having both volatile and non-volatile functionality, which combines the properties of Flash EPROM and DRAM. When power is applied, the non-volatile DRAM operates like a regular DRAM cell. As a result, its performance (speed, power, and reliability) is comparable to a regular DRAM cell. During power shutdown (or during backup operations that can be performed at regular intervals), the content of the volatile memories is loaded into the non-volatile memories (hereto referred as the shadowing process). After power is restored, the content of the non-volatile memories is restored to the volatile memories (hereto referred as the restore process).
• FIG. 171 is aflowchart100 illustrating operation of a memory device according to an embodiment of the present invention. Atevent102, when power is first applied to the memory device, the memory device is placed in an initial state, in a volatile operational mode and the nonvolatile memory is set to a predetermined state, typically set to have a positive charge. Atevent104, while power is still on, the memory device of the present invention operates in the same manner as a conventional DRAM (dynamic random access memory) memory cell, i.e., operating as volatile memory. However, during power shutdown, or when power is inadvertently lost, or any other event that discontinues or upsets power to the memory device of the present invention, the content of the volatile memory is loaded into non-volatile memory atevent106, during a process which is referred to here as “shadowing” (event106), and the data held in the volatile memory is lost. Shadowing can also be performed during backup operations (in which case, data held in volatile memory is not lost), which may be performed at regular intervals duringDRAM operation104 periods, and/or at any time that a user manually instructs a backup. During a backup operation, the content of the volatile memory is copied to the non-volatile memory while power is maintained to the volatile memory so that the content of the volatile memory also remains in volatile memory. Alternatively, because the volatile memory operation consumes more power than the non-volatile storage of the contents of the volatile memory, the device can be configured to perform the shadowing process anytime the device has been idle for at least a predetermined period of time, thereby transferring the contents of the volatile memory into non-volatile memory and conserving power. As one example, the predetermined time period can be about thirty minutes, but of course, the invention is not limited to this time period, as the device could be programmed with virtually any predetermined time period.
• After the content of the volatile memory has been moved during a shadowing operation to nonvolatile memory, the shutdown of the memory device occurs (when it is not a backup operation, as power is no longer supplied to the volatile memory. At this time, the memory device functions like a Flash EPROM (erasable, programmable read-only memory) device in that it retains the stored data in the nonvolatile memory. Upon restoring power atevent108, the content of the nonvolatile memory is restored by transferring the content of the non-volatile memory to the volatile memory in a process referred to herein as the “restore” process, after which, upon resetting the memory device atevent110, the memory device is again set to theinitial state102 and again operates in a volatile mode, like a DRAM memory device,event104.
• In an alternative embodiment/use, a memory device of the present invention can restore the content of the non-volatile memory to the volatile memory upon power restoration and operate in a volatile mode, without first resetting the memory device. In this alternative embodiment, the volatile operation is performed independent of the non-volatile memory data.FIG. 172 shows anotheroperation flow chart200 of the memory device according to an embodiment of the present invention. Atevent202, while power is on, the memory device of the present invention operates in the same manner as a volatile memory cell. During power shutdown, or when power is inadvertently lost, or any other event that discontinues or upsets power to the memory device of the present invention, the non-volatile memory is reset to a predetermined state atevent204. This is then followed by the shadowingoperation206, where the content of the volatile memory is loaded into non-volatile memory.
• After the content of the volatile memory has been moved during a shadowing operation to nonvolatile memory, the shutdown of the memory device occurs (unless the shadowing process performed was a backup operation, as power is no longer supplied to the volatile memory. At this time, the memory device functions like a Flash EPROM (erasable, programmable read-only memory) device in that it retains the stored data in the nonvolatile memory.
• Upon restoring power atevent208, the content of the nonvolatile memory is restored by transferring the content of the non-volatile memory to the volatile memory in a process referred to herein as the “restore” process, after which, the memory device again operates in a volatile mode, like a DRAM memory device,event202.
• In an alternative embodiment/use, the non-volatile memory reset operation is not performed. This is useful, for example, in the case where the non-volatile memory is used to store “permanent data”, which is data that does not change in value during routine use. For example, the non-volatile storage bits can be used to store applications, programs, etc. and/or data that is not frequently modified, such as an operating system image, multimedia files, etc.
• FIG. 173A schematically illustrates an embodiment of amemory cell1250 according to the present invention. Thecell1250 includes asubstrate12 of a first conductivity type, such as a p-type conductivity type, for example.Substrate12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, or other semiconductor materials known in the art. Thesubstrate12 has asurface14. Afirst region16 having a second conductivity type, such as n-type, for example, is provided insubstrate12 and is exposed atsurface14. Asecond region18 having the second conductivity type is also provided insubstrate12, which is exposed atsurface14 and which is spaced apart from thefirst region16. First andsecond regions16 and18 are formed by an implantation process formed on the material making upsubstrate12, according to any of implantation processes known and typically used in the art.
• A buriedlayer22 of the second conductivity type is also provided in thesubstrate12, buried in thesubstrate12, as shown.Region22 is also formed by an ion implantation process on the material ofsubstrate12. Abody region24 of thesubstrate12 is bounded bysurface14, first andsecond regions16,18 and insulating layers26 (e.g. shallow trench isolation (STI)), which may be made of silicon oxide, for example. Insulatinglayers26 insulatecell1250 from neighboringcells1250 whenmultiple cells1250 are joined to make a memory device. Atrapping layer60 is positioned in between theregions16 and18, and above thesurface14. Trappinglayer60 may be made of silicon nitride, silicon nanocrystal, or high-K dielectric materials or other dielectric materials. Thetrapping layer60 functions to store non-volatile memory data. Trappinglayer60 allows having multiple physically separatedstorage locations62a,62bper cell, resulting in a multi-bit non-volatile functionality. This can be accomplished by applying a first charge viaregion16 to store non-volatile data atstorage location62aand by applying a second charge viaregion18 to store non-volatile data atstorage location62b, as described in detail below.
• Acontrol gate64 is positioned above trappinglayer60 such thattrapping layer60 is positioned betweencontrol gate64 andsurface14, as shown.Control gate64 is typically made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell1250 includes five terminals: word line (WL) terminal70, source line (SL) terminal72, bit line (BL)terminal74, buried well (BW) terminal76, andsubstrate terminal78.Terminal70 is connected to controlgate64.Terminal72 is connected tofirst region16 andterminal74 is connected tosecond region18. Alternatively, terminal72 can be connected tosecond region18 and terminal74 can be connected tofirst region16.Terminal76 is connected to buriedlayer22.Terminal78 is connected tosubstrate12.
• FIG. 173B shows anexemplary array1280 ofmemory cells1250 arranged in rows and columns. Alternatively, a memory cell device according to the present invention may be provided in a single row or column of a plurality ofcells1250, but typically both a plurality of rows and a plurality of columns are provided. Present inFIG. 173B are word lines70A through70n, source lines72athrough72n,bit lines74athrough74p, andsubstrate terminal78. Each of the word lines70athrough70nis associated with a single row ofmemory cells1250 and is coupled to thegate64 of eachmemory cell1250 in that row. Similarly, each of the source lines72athrough72nis associated with a single row ofmemory cells1250 and is coupled to theregion16 of eachmemory cell1250 in that row. Each of the bit lines74athrough74pis associated with a single column ofmemory cells1250 and is coupled to theregion18 of eachmemory cell1250 in that column Buried well terminal76 andsubstrate terminal78 are present at all locations underarray1280. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals78 may be present in one or more locations as a matter of design choices. Such persons of ordinary skill in the art will also appreciate that that whileexemplary array1280 is shown as a single continuous array inFIG. 173B, that many other organizations and layouts may alternatively be created. For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray1280 may be broken into two or more sub-arrays and/or control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, and/or write amplifiers may be arrayed aroundexemplary array1280 or inserted between sub-arrays ofarray1280. Thus the exemplary embodiments, features, design options, etc. described herein are not limiting in any way.
• FIG. 173C shows another example ofarray architecture1280bof a memory cell device according to the present invention, whereinmemory cells1250 are arranged in a plurality of rows and columns.Memory cells1250 are connected such that within each row, all of thecontrol gates64 are connected in common word line terminals70 (e.g.,70,70b, . . . ,70n). Within each column, all first andsecond regions16,18 ofcells1250 in that column are connected in common source and bit line terminals72 (e.g.,72a,72b, . . . ,72h) and74 (e.g.,74a,74b, . . . ,74h), respectively.
• FIG. 174 illustrates alternative write state “1” operations that can be carried out oncell1250, by performing band-to-band tunneling hot hole injection or impact ionization hot hole injection. To write state “1” using a band-to-band tunneling mechanism, the following voltages are applied to the terminals: a positive voltage is applied toBL terminal74, a neutral voltage is applied to theSL terminal72, a negative voltage is applied toWL terminal70, a positive voltage less than the positive voltage applied to theBL terminal74 is applied toBW terminal76, and a neutral voltage is applied tosubstrate terminal78. Under these conditions, holes are injected fromBL terminal74 into the floatingbody region24, leaving thebody region24 positively charged. The positive voltage applied toBL terminal74 creates a depletion region that shields the effects of any charges that are stored instorage location62b. As a result, the write state “1” operation can be performed regardless of the charge stored in thestorage location62b.
• In one particular non-limiting embodiment, a potential of about +2.0 volts is applied toterminal74, a potential of about 0.0 volts is applied toterminal72, a potential of about −1.2 volts is applied toterminal70, a potential of about +0.6 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above. Further, the voltages applied toterminals72 and74 may be reversed, and still obtain the same result. However the depletion region would instead be formed nearstorage location62a, rather than62b.
• Alternatively, to write a state “1” using an impact ionization mechanism, the following voltages are applied: a positive voltage is applied toBL terminal74, a neutral voltage is applied toSL terminal72, a positive voltage is applied toWL terminal70 and a positive voltage is applied toBW terminal76, while a neutral voltage is applied to thesubstrate terminal78. Under these conditions, holes are injected fromBL terminal74 into the floatingbody region24, leaving thebody region24 positively charged. The positive voltage applied toBL terminal74 creates a depletion region that shields the effects of any charges that are stored instorage location62b.
• In one particular non-limiting embodiment, a potential of about +2.0 volts is applied toterminal74, a potential of about 0.0 volts is applied toterminal72, a potential of about +1.2 volts is applied toterminal70, a potential of about +0.6 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above. Further, the voltages applied toterminals72 and74 may be reversed, and still obtain the same result. However the depletion region would instead be formed nearstorage location62a, rather than62b.
• Alternatively, the silicon controlled rectifier (SCR) device ofcell1250 can be put into a state “1” (i.e., by performing a write “1” operation) by applying the following bias: a neutral voltage is applied toBL terminal74, a positive voltage is applied toWL terminal70, and a positive voltage greater than the positive voltage applied toterminal70 is applied to thesubstrate terminal78, whileSL terminal72 andBW terminal76 are left floating. The positive voltage applied to theWL terminal70 will increase the potential of the floatingbody24 through capacitive coupling and create a feedback process that turns the SCR device on. Once the SCR device ofcell1250 is in conducting mode (i.e., has been “turned on”) the SCR becomes “latched on” and the voltage applied toWL terminal70 can be removed without affecting the “on” state of the SCR device. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminal74, a voltage of about +0.5 volts is applied toterminal70, and about +0.8 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the voltages applied, as described above, e.g., the voltage applied to terminal78 remains greater than the voltage applied toterminal74. This write state “1” operation can be performed regardless of the charge stored instorage location62aor62b.
• FIG. 175 illustrates a write state “0” operation that can be carried out oncell1250. To write a state “0” into floatingbody region24, a negative voltage is applied toSL terminal72, a negative voltage less negative than the negative voltage applied toterminal72 is applied toWL terminal70, 0.0 volts is applied toBL terminal74 and a positive voltage is applied toBW terminal76, while neutral voltage is applied tosubstrate terminal78. Under these conditions, the p-n junction (junction between24 and16) is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −2.0 volts is applied toterminal72, about −1.2 volts is applied toterminal70, about +0.6 volts is applied toterminal76, and about 0.0 volts is applied toterminals72 and78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above. Further, the voltages applied toterminals72 and74 may be reversed, and still obtain the same result. As can be seen, the write state “0” operation can be performed regardless of the charge stored instorage location62aor62b.
• Alternatively, a write “0” operation can be performed by putting the silicon controlled rectifier device into the blocking mode. This can be performed by applying the following bias: a positive voltage is applied toBL terminal74, a positive voltage is applied toWL terminal70, and a positive voltage greater than the positive voltage applied toterminal74 is applied to thesubstrate terminal78, while leavingSL terminal72 andBW terminal76 floating. Under these conditions the voltage difference between anode and cathode, defined by the voltages atsubstrate terminal78 andBL terminal74, will become too small to maintain the SCR device in conducting mode. As a result, the SCR device ofcell1250 will be turned off. In one particular non-limiting embodiment, a voltage of about +0.8 volts is applied toterminal74, a voltage of about +0.5 volts is applied toterminal70, and about +0.8 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above. As can be seen, the write state “0” operation can be performed regardless of the charged stored instorage location62aor62b.
• A read operation of thecell1250 is now described with reference toFIG. 176. To readcell1250, a positive voltage is applied toBL terminal74, a neutral voltage is applied toSL terminal72, a positive voltage that is more positive than the positive voltage applied toterminal74 is applied toWL terminal70 and a positive voltage is applied toBW terminal76, whilesubstrate terminal78 is grounded. Ifcell1250 is in a state “1” having holes in thebody region24, then a lower threshold voltage (gate voltage where the transistor is turned on) is observed compared to the threshold voltage observed whencell1250 is in a state “0” having no holes inbody region24. The positive voltage applied toBL terminal74 forms a depletion region aroundjunction18 that shields the effects of any charges that are stored instorage location62b. As a result, the volatile state read operation can be performed regardless of the charge stored in the non-volatile storage (in this example, the charge stored instorage location62b). In one particular non-limiting embodiment, about +0.4 volts is applied toterminal74, about +0.0 volts is applied toterminal72, about +1.2 volts is applied toterminal70, about +0.6 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• The read operation can also be performed when a positive voltage is applied toBL terminal74, a neutral voltage is applied toSL terminal72, a positive voltage that is less positive than the positive voltage applied toterminal74 is applied toWL terminal70 and a positive voltage is applied toBW terminal76, whilesubstrate terminal78 is grounded. Ifcell1250 is in a state “1” having holes in thebody region24, then a parasitic bipolar transistor formed by theSL terminal72, floatingbody24, andBL terminal74 will be turned on and a higher cell current is observed compared to whencell1250 is in a state “0” having no holes inbody region24. The positive voltage applied toBL terminal74 forms a depletion region aroundjunction18 that shields the effects of any charges that are stored instorage location62b. As a result, the volatile state read operation can be performed regardless (i.e., independently) of the charge stored in the non-volatile storage (in this example, the charge stored instorage location62b). In one particular non-limiting embodiment, about +3.0 volts is applied toterminal74, about 0.0 volts is applied toterminal72, about +0.5 volts is applied toterminal70, about +0.6 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships between the voltages applied, as described above.
• Alternatively, a positive voltage is applied to thesubstrate terminal78, a substantially neutral voltage is applied toBL terminal74, and a positive voltage is applied toWL terminal70.Terminals72 and76 are left floating.Cell1250 provides a P1-N2-P3-N4 silicon controlled rectifier device, withsubstrate78 functioning as the P1 region, buriedlayer22 functioning as the N2 region,body region24 functioning as the P3 region andregion16 or18 functioning as the N4 region. The functioning of the silicon controller rectifier device is described in further detail in application Ser. No. 12/533,661 filed Jul. 31, 2009 and titled “Methods of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle”. Application Ser. No. 12/533,661 is hereby incorporated herein, in its entirety, by reference thereto. In this example, thesubstrate terminal78 functions as the anode and terminal72 or terminal74 functions as the cathode, whilebody region24 functions as a p-base to turn on the SCR device. Ifcell1250 is in a state “1” having holes in thebody region24, the silicon controlled rectifier (SCR) device formed by the substrate, buried well, floating body, and the BL junction will be turned on and a higher cell current is observed compared to whencell1250 is in a state “0” having no holes inbody region24. A positive voltage is applied toWL terminal70 to select a row in the memory cell array, while negative voltage is applied toWL terminal70 for any unselected rows. The negative voltage applied reduces the potential of floatingbody24 through capacitive coupling in the unselected rows and turns off the SCR device of eachcell1250 in each unselected row. Thus the read operation can be performed regardless of the charge stored in the non-volatile storage. In one particular non-limiting embodiment, about +0.8 volts is applied toterminal78, about +0.5 volts is applied to terminal70 (for the selected row), and about 0.0 volts is applied toterminal72, whileterminals74 and76 are left floating. However, these voltage levels may vary.
• A holding or standby operation is described with reference toFIG. 177. Such holding or standby operation is implemented to enhance the data retention characteristics of thememory cells1250. The holding operation can be performed by applying the following bias: a substantially neutral voltage is applied toBL terminal74, a neutral or negative voltage is applied toWL terminal70, and a positive voltage is applied to thesubstrate terminal78, while leavingSL terminal72 andBW terminal76 floating. Under these conditions, ifmemory cell1250 is in memory/data state “1” with positive voltage in floatingbody24, the SCR device ofmemory cell1250 is turned on, thereby maintaining the state “1” data. Memory cells in state “0” will remain in blocking mode, since the voltage in floatingbody24 is not substantially positive and therefore floatingbody24 does not turn on the SCR device. Accordingly, current does not flow through the SCR device and these cells maintain the state “0” data. In this way, an array ofmemory cells1250 can be refreshed by periodically applying a positive voltage pulse throughsubstrate terminal78. Thosememory cells1250 that are commonly connected tosubstrate terminal78 and which have a positive voltage inbody region24 will be refreshed with a “1” data state, while thosememory cells1250 that are commonly connected to thesubstrate terminal78 and which do not have a positive voltage inbody region24 will remain in blocking mode, since their SCR device will not be turned on, and therefore memory state “0” will be maintained in those cells. In this way, allmemory cells1250 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This process occurs automatically, upon application of voltage to thesubstrate terminal78, in a parallel, non-algorithmic, efficient process. In addition, it can be seen that the holding operation can be performed regardless of the charge stored in the non-volatile storage. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminal74, a voltage of about −1.0 volts is applied toterminal70, and about +0.8 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships therebetween. Alternatively, the voltage described above as being applied to terminal74 may be applied toterminal72 and terminal74 may be left floating.
• Alternatively, the holding operation can be performed by applying the following bias: substantially neutral voltage is applied to theBL terminal74, a positive voltage is applied toSL terminal72, a positive voltage is applied toBW terminal76, and zero or negative voltage is applied toWL terminal70. Thesubstrate terminal78 can be left floating or grounded. Under these conditions, the parasitic bipolar device formed byregion16, the floatingbody region24, andregion18 will be turned on. If the floatingbody24 is in state “1’ having positive charge in thebody region24, the positive voltage applied to theSL terminal72 will result in impact ionization, which will generate electron-hole pairs. The holes will then diffuse into floatingbody24, hence replenishing the positive charge inbody region24 and maintain the “1” data state. If the floatingbody24 is in state “0”, the bipolar device formed byregion16, the floatingbody region24, andregion18 will not be turned on and therefore state “0” will be maintained in those cells. In this way, allmemory cells1250 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This mechanism is governed by the potential or charge stored in the floatingbody region24 and is independent of the potential applied to theWL terminal70. This process occurs automatically, upon application of voltage to theSL terminal72, in a parallel, non-algorithmic, efficient process. As can be seen, the holding operation can be performed regardless of the charge stored in the non-volatile storage. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminal74, a voltage of about −1.0 volts is applied toterminal70, about +0.8 volts is applied toterminal72, and about +0.6 is applied toterminal76. However, these voltage levels may vary, while maintaining the relative relationships therebetween. Alternatively, the voltage described above as being applied to terminal72 may be applied toterminal74 andterminal72 is grounded.
• Alternatively, the holding operation can be performed by applying the following bias: zero or negative voltage is applied toWL terminal70, substantially neutral voltage is applied to bothBL terminal74 andSL terminal72, and a positive voltage is applied toBW terminal76. Thesubstrate terminal78 can be left floating or grounded. Under these conditions, the parasitic bipolar device formed byregion16 or18, the floatingbody region24 and buriedlayer22 will be turned on. If the floatingbody24 is in state “1’ having positive charge in thebody region24, the positive voltage applied toBW terminal76 will result in impact ionization, which will generate electron-hole pairs. The holes will then diffuse into floatingbody24, hence replenishing the positive charge inbody region24 and maintaining the “1” data state. If the floatingbody24 is in state “0”, the bipolar device formed byregion16 or18, the floatingbody region24 and buriedlayer22 will not be turned on and therefore state “0” will be maintained in those cells. In this way, allmemory cells1250 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This mechanism is governed by the potential or charge stored in the floatingbody region24 and is independent of the potential applied to theWL terminal70. This process occurs automatically, upon application of voltage to theBW terminal76, in a parallel, non-algorithmic, efficient process. As can be seen, the holding operation can be performed regardless of the charge stored in the non-volatile storage. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toterminals72 and74, a voltage of about −1.0 volts is applied toterminal70, about +1.2 volts is applied toterminal76, and about 0.0 volts is applied toterminal78. However, these voltage levels may vary, while maintaining the relative relationships therebetween.
• When power down is detected, e.g., when a user turns off the power tocell1250, or the power is inadvertently interrupted, or for any other reason, power is at least temporarily discontinued tocell1250, or due to any specific commands by the user such as during backup operation, data stored in the floatingbody region24 is transferred to trappinglayer60 through hot electron injection. This operation is referred to as “shadowing” and is described with reference toFIGS. 178A-178B. The shadowing process can be performed to store data in the floatingbody region24 to eitherstorage location62aor62b. To perform a shadowing process to thestorage location62a, a high positive voltage is applied toSL terminal72 and a neutral or positive voltage less positive than that applied toterminal72 is applied toBL terminal74. A positive voltage is applied toterminal70 and a positive voltage is applied toterminal76. A high voltage in this case is a voltage greater than or equal to about +3 volts. In one example, a voltage in the range of about +3 to about +6 volts is applied, although it is possible to apply a higher voltage. When floatingbody24 has a positive charge/voltage, the NPN bipolar junction formed bysource drain regions16 and18 and the floatingbody24 is on and electrons flow through the memory transistor. The application of the high voltage toterminal72 energizes/accelerates electrons traveling through the floatingbody24 to a sufficient extent that they can “jump into” the storage location in thetrapping layer62anear theSL terminal72, as indicated by the arrow intostorage location62ainFIG. 178A. Accordingly, thestorage location62ain thetrapping layer60 becomes negatively charged by the shadowing process, when the volatile memory ofcell1250 is in state “1” (i.e., floatingbody24 is positively charged), as shown inFIG. 178A.
• When volatile memory ofcell1250 is in state “0”, i.e., floatingbody24 has a negative or neutral charge/voltage, the NPN junction is off and electrons do not flow in the floatingbody24, as illustrated inFIG. 178B. Accordingly, when voltages are applied to the terminals as described above, in order to perform the shadowing process, the high positive voltage applied toterminal72 does not cause an acceleration of electrons in order to cause hot electron injection into trappinglayer60, since electrons are not flowing. Accordingly, no charge injection occurs to thetrapping layer60 and it retains its charge at the end of the shadowing process, when the volatile memory ofcell1250 is in state “0” (i.e., floatingbody24 is neutral or negatively charged), as shown inFIG. 178B. As will be described in the description of reset operation, thestorage locations62 in trappinglayer60 are initialized or reset to have a positive charge during the reset operation. As a result, if the volatile memory ofcell1250 is in state “0”, thestorage location62awill have a positive charge at the end of the shadowing process.
• Note that the charge state of thestorage location62aterminal is complementary to the charge state of the floatingbody24 after completion of the shadowing process. Thus, if the floatingbody24 of thememory cell1250 has a positive charge in volatile memory, thetrapping layer60 will become negatively charged by the shadowing process, whereas if the floating body of thememory cell1250 has a negative or neutral charge in volatile memory, thestorage location62awill be positively charged at the end of the shadowing operation. The charges/states of thestorage location62anear SL terminal72 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
• In one particular non-limiting example of the shadowing process according to this embodiment, about +6 volts are applied toterminal72, about 0.0 volts are applied toterminal74, about +1.2 volts are applied toterminal70, and about +0.6 volts are applied toterminal76. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• A shadowing operation tostorage location62bnearBL terminal74 can be performed in a similar manner by reversing the voltages applied toterminals72 and74.
• In another embodiment of the shadowing operation, the following bias conditions are applied. To perform a shadowing process to thestorage location62a, a high positive voltage is applied toSL terminal72, a positive voltage is applied toWL terminal70 and a neutral voltage or a positive voltage less positive than positive voltage applied toSL terminal72 is applied toBW terminal76, while theBL terminal74 is left floating. Under this bias condition, when floatingbody24 has a positive charge/voltage, the NPN bipolar junction formed byregion16, the floatingbody24, and the buriedwell region22 is on and electrons flow through the memory transistor. The application of the high voltage toterminal72 energizes/accelerates electrons traveling through the floatingbody24 to a sufficient extent that they can “jump into” the storage location in thetrapping layer62anear theSL terminal72. Accordingly, thestorage location62ain thetrapping layer60 becomes negatively charged by the shadowing process, when the volatile memory ofcell1250 is in state “1” (i.e., floatingbody24 is positively charged).
• When volatile memory ofcell1250 is in state “0”, i.e., floatingbody24 has a negative or neutral charge/voltage, the NPN junction is off and electrons do not flow in the floatingbody24. Accordingly, when voltages are applied to the terminals as described above, electrons are not flowing and consequently no hot electron injection into thetrapping layer60 occurs. Thestorage location62ain trappinglayer60 will retain its charge at the end of the shadowing process when the volatile memory ofcell1250 is in state “0”. As will be described in the description of reset operation, thestorage locations62 in trappinglayer60 are initialized or reset to have a positive charge during the reset operation. As a result, if the volatile memory ofcell1250 is in state “0”, thestorage location62awill have a positive charge at the end of the shadowing process.
• A shadowing operation tostorage location62bnearBL terminal74 can be performed in a similar manner by reversing the voltages applied toterminals72 and74.
• When power is restored tocell1250, the state of thecell1250 as stored on trappinglayer60 is restored into floatingbody region24. The restore operation (data restoration from non-volatile memory to volatile memory) is described with reference toFIGS. 179A and 179B. Prior to the performing the restore operation/process, the floatingbody24 is set to a neutral or negative charge, i.e., a “0” state is written to floatingbody24.
• In the embodiment ofFIGS. 179A-179B, to perform the restore operation of non-volatile data stored instorage location62a, terminal72 is set to a substantially neutral voltage, a positive voltage is applied toterminal74, a negative voltage is applied toterminal70 and a positive voltage is applied toterminal76, while thesubstrate terminal78 is grounded. The positive voltage applied to terminal74 will create a depletion region, shielding the effects of charge stored instorage location62b. If thestorage location62ais negatively charged, as illustrated inFIG. 179A, this negative charge enhances the driving force for the band-to-band hot hole injection process, whereby holes are injected from the n-region18 into floatingbody24, thereby restoring the “1” state that thevolatile memory cell1250 had held prior to the performance of the shadowing operation. If thetrapping layer62ais not negatively charged, such as when thetrapping layer62ais positively charged as shown inFIG. 179B or is neutral, the hot band-to-band hole injection process will not occur, as illustrated inFIG. 179B, resulting inmemory cell1250 having a “0” state, just as it did prior to performance of the shadowing process. Accordingly, ifstorage location62ahas a positive charge after shadowing is performed, the volatile memory of floatingbody24 will be restored to have a negative charge (“0” state), but if thetrapping layer62ahas a negative or neutral charge, the volatile memory of floatingbody24 will be restored to have a positive charge (“1” state).
• A restore operation of non-volatile data stored instorage location62bcan be performed in a similar manner to that described above with regard tostorage location62a, by reversing the voltages applied toterminals72 and74, and by applying all other conditions the same.
• After the restore operation is completed, the state of the trapping layers60 can be reset to an initial state. The reset operation ofnon-volatile storage location62ais described with reference toFIG. 180. A high negative voltage is applied toterminal70, a neutral or positive voltage is applied toterminal72, a positive voltage is applied toterminal76, and zero voltage is applied tosubstrate terminal78, whileterminal74 is left floating. Under these conditions, electrons will tunnel fromstorage location62ato the n⁺ junction region16. As a result, thestorage location62awill be positively charged.
• In one particular non-limiting example of the reset process according to this embodiment, about −18 volts are applied toterminal70, about 0.0 volts are applied toterminal72, about +0.6 volts are applied toterminal76, and about 0.0 volts are applied toterminal78, whileterminal74 is left floating. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• A reset operation onnon-volatile storage location62bcan be performed in a similar manner to that described above with regard tostorage location62a, by reversing the voltages applied toterminals72 and74, and by applying all other conditions the same.
• A reset operation can be performed simultaneously on bothstorage locations62aand62bby applying a high negative voltage toterminal70, a neutral or positive voltage toterminals72 and74, and a positive voltage toterminal76, while groundingterminal78.
• In one particular non-limiting example of the reset process according to this embodiment, about −18 volts are applied toterminal70, about 0.0 volts are applied toterminals72,74 and78, and about +0.6 volts are applied toterminal76. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• In another embodiment of the memory cell operation, the trapping charge is reset/reinitialized to a negative initial state. To reset thestorage location62a, the following bias conditions are applied: a high positive voltage is applied toWL terminal70, a neutral voltage is applied toterminal72, a positive voltage is appliedBW terminal76, and zero voltage is applied toterminal78, whileterminal74 is left floating. Under these conditions, electrons will tunnel from the n⁺ junction region16 tostorage location62a. As a result, thestorage location62awill be negatively charged.
• In one particular non-limiting example of the reset process according to this embodiment, about +18 volts are applied toterminal70, about 0.0 volts are applied toterminals72 and78, about +0.6 volts are applied toterminal76, whileterminal74 is left floating. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• A reset operation onnon-volatile storage location62bcan be performed in a similar manner to that described above with regard tostorage location62a, by reversing the voltages applied toterminals72 and74, and by applying all other conditions the same.
• A reset operation can be performed simultaneously on bothstorage locations62aand62bby applying a high positive voltage toterminal70, a neutral or positive voltage toterminals72 and74, a positive voltage toBW terminal76, and zero voltage toterminal78.
• In one particular non-limiting example of the reset process according to this embodiment, about +18 volts are applied toterminal70, about 0.0 volts are applied toterminals72,74 and78, and about +0.6 volts are applied toterminal76. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
• In another embodiment of the shadowing operation according to the present invention, the following bias conditions are applied. To perform a shadowing process to thestorage location62a, a high positive voltage is applied toSL terminal72, a neutral or positive voltage is applied toBL terminal74, a negative voltage is applied toWL terminal70, a neutral voltage is applied toBW terminal76, and a neutral voltage is applied tosubstrate terminal78. Under these bias conditions, when floatingbody24 has a positive charge/voltage, the NPN bipolar junction formed byregions16 and18 and the floatingbody24 is on and electrons flow through the memory transistor. The application of the high voltage toterminal72 energizes/accelerates electrons traveling through the floatingbody24, creating electron-hole pairs through impact ionization. The negative voltage applied to theWL terminal70 creates an attractive electric field for hot holes injection to thestorage location62anear theSL terminal72.
• Accordingly, thestorage location62ain thetrapping layer60 becomes positively charged by the shadowing process, when the volatile memory ofcell1250 is in state “1” (i.e., floatingbody24 is positively charged).
• When volatile memory ofcell1250 is in state “0”, i.e., floatingbody24 has a negative or neutral charge/voltage, the NPN junction is off and electrons do not flow in the floatingbody24. Accordingly, when voltages are applied to the terminals as described above, electrons are not flowing and consequently no hot holes injection into thetrapping layer60 occurs. Thestorage location62ain trappinglayer60 will retain the negative charge at the end of the shadowing process when the volatile memory ofcell1250 is in state “0”.
• Accordingly, if floatingbody24 has a positive charge, thestorage location62awill have a positive charge after the shadowing operation is performed. Conversely, if floatingbody24 has a negative charge, thestorage location62awill have a negative charge after the shadowing operation is performed.
• A shadowing operation tostorage location62bnearBL terminal74 can be performed in a similar manner to that described above with regard tostorage location62a, by reversing the voltages applied toterminals72 and74, and by applying all other conditions the same.
• In another embodiment of the shadowing operation, the following bias conditions are applied. To perform a reset process to thestorage location62a, a high positive voltage is applied toSL terminal72, a negative voltage is applied toWL terminal70 and zero voltage is applied toBW terminal76, while theBL terminal74 is left floating and thesubstrate terminal78 is grounded. Under these bias conditions, when floatingbody24 has a positive charge/voltage, the NPN bipolar junction formed byregion16, the floatingbody24, and the buriedwell region22 is on and electrons flow through the memory transistor. The application of the high voltage toterminal72 energizes/accelerates electrons traveling through the floatingbody24, creating electron-hole pairs through impact ionization. The negative voltage applied to theWL terminal70 creates an attractive electric field for hot holes injection to thestorage location62anear theSL terminal72. Accordingly, thestorage location62ain thetrapping layer60 becomes positively charged by the shadowing process, when the volatile memory ofcell1250 is in state “1” (i.e., floatingbody24 is positively charged).
• When volatile memory ofcell1250 is in state “0”, i.e., floatingbody24 has a negative or neutral charge/voltage, the NPN junction is off and electrons do not flow in the floatingbody24. Accordingly, when voltages are applied to the terminals as described above, electrons are not flowing and consequently no hot holes injection into thetrapping layer60 occurs. Thestorage location62ain trappinglayer60 will retain the negative charge at the end of the shadowing process when the volatile memory ofcell1250 is in state “0”.
• Accordingly, if floatingbody24 has a positive charge, thestorage location62awill have a positive charge after the shadowing operation is performed. Conversely, if floatingbody24 has a negative charge, thestorage location62awill have a negative charge.
• A shadowing operation tostorage location62bnearBL terminal74 can be performed in a similar manner to that described above with regard tostorage location62a, by reversing the voltages applied toterminals72 and74, and by applying all other conditions the same.
• In another embodiment of the restore operation, terminal72 is set to a substantially neutral voltage, a positive voltage is applied toterminal74, a positive voltage less positive than positive voltage applied toterminal74 is applied toterminal70, a positive voltage is applied toterminal76 and zero voltage is applied toterminal78. The positive voltage applied to terminal74 will create a depletion region, shielding the effects of charge stored instorage location62b. If thestorage location62ais positively charged, this positive charge enhances the driving force for the impact ionization process to create hot hole injection from the n-region18 into floatingbody24, thereby restoring the “1” state that thevolatile memory cell1250 had held prior to the performance of the shadowing operation. If thetrapping layer62ais not positively charged, no impact ionization process will occur, resulting inmemory cell1250 having a “0” state, just as it did prior to performance of the shadowing process. Accordingly, ifstorage location62ahas a positive charge after shadowing is performed, the volatile memory of floatingbody24 will be restored to have a positive charge (“1” state), but if thetrapping layer62ahas a negative charge, the volatile memory of floatingbody24 will be restored to have a neutral charge (“0” state).
• A restore operation of non-volatile data stored instorage location62bcan be performed in a similar manner to that described above with regard tostorage location62a, by reversing the voltages applied toterminals72 and74, and by applying all other conditions the same.
• FIG. 181A schematically illustrates another embodiment of amemory cell1250S according to the present invention. Thecell1250S includes asubstrate112 of a first conductivity type, such as a p-type conductivity type, for example.Substrate112 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, or other semiconductor materials known in the art. Thesubstrate112 has asurface114. Afirst region116 having a second conductivity type, such as n-type, for example, is provided insubstrate112 and is exposed atsurface114. Asecond region118 having the second conductivity type is also provided insubstrate112, which is exposed atsurface114 and which is spaced apart from thefirst region116. First andsecond regions116 and118 are formed by an implantation process formed on the material making upsubstrate112, according to any of implantation processes known and typically used in the art.
• A buriedinsulator layer122, such as buried oxide (BOX) is also provided in thesubstrate112, buried in thesubstrate112, as shown. Abody region124 of thesubstrate112 is bounded bysurface114, first andsecond regions116,118, and the buriedinsulator layer122. Atrapping layer160 is positioned in between theregions116 and118, and above thesurface114. Trappinglayer160 may be made of silicon nitride, silicon nanocrystal, or high-K dielectric materials or other dielectric materials. Thetrapping layer160 functions to store non-volatile memory data. Trappinglayer160 allows having two physically separatedstorage locations162a,162bper cell, resulting in a multi-bit non-volatile functionality.
• Acontrol gate164 is positioned above trappinglayer160 such thattrapping layer160 is positioned betweencontrol gate164 andsurface114, as shown.Control gate164 is typically made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell1250S includes four terminals: word line (WL)terminal170, bit line (BL)terminals172 and174, andsubstrate terminal178.Terminal170 is connected to controlgate164.Terminal172 is connected tofirst region116 and terminal174 is connected tosecond region118. Alternatively, terminal172 can be connected tosecond region118 and terminal174 can be connected tofirst region116.
• FIG. 181B shows an example of anarray architecture1280S of a memory cell device according to an embodiment of the present invention, whereinmemory cells1250S are arranged in a plurality of rows and columns. Alternatively, a memory cell device according to the present invention may be provided in a single row or column of a plurality ofcells1250S, but typically, both a plurality of rows and a plurality of columns are provided.Memory cells1250S are connected such that within each row, all of thecontrol gates164 are connected in a common word line terminal170 (e.g.,170a,170b, . . . ,170n, depending upon which row is being referred to). Within each column, all first andsecond regions116,118 ofcells1250S in that column are connected in common bit line terminals172 (e.g.,172a,172b, . . . ,172e) and174 (e.g.,174a,174b, etc.).
• Because eachcell1250S is provided with a buriedinsulator layer122 that, together withregions116 and118, bound the lower and side boundaries of floatingbody124, insulatinglayers26 are not required to bound the sides of the floatingbody24, in contrast to that of the embodiment ofFIG. 173A. Because insulatinglayers26 are not required bycells1250S, less terminals are required for operation of thememory cells1250S in an array ofsuch cells1250S assembled into a memory cell device. Because theadjacent cells1250S are not isolated by insulatinglayer26,adjacent regions116,118 are also not isolated by insulatinglayer26. Accordingly asingle terminal172 or174 can be used to function asterminal174 forregion118 of one of a pair ofadjacent cells1250S, and, by reversing the polarity thereof, can also be used to function asterminal172 forregions116 of the other of the pair ofadjacent cells1250S, whereinregion118 of thefirst cell1250S of thepair contacts region116 of thesecond cell1250S of the pair. For example, inFIG. 181B, terminal174acan be operated to function asterminal174 forregion118 of cell1250Sa with voltage applied according to a first polarity. By reversing the polarity of the voltage applied to terminal174a, terminal174acan be operated to function asterminal172 forregion116 of cell1250Sb. By reducing the number of terminals required in a memory cell device, as allowed by this described arrangement, a memory device according to this embodiment of the present invention can be manufactured to have a smaller volume, relative to a memory cell device of the same capacity that requires a pair ofterminals172,174 for each cell that is separate and distinct from theterminals172,174 of adjacent cells in the row.
• FIGS. 182-184 show another embodiment ofmemory cell1250V according to the present invention. In this embodiment,cell1250V has afin structure252 fabricated onsubstrate212, so as to extend from the surface of the substrate to form a three-dimensional structure, withfin252 extending substantially perpendicularly to, and above the top surface of thesubstrate212.Fin structure252 is conductive and is built on buriedwell layer222.Region222 is also formed by an ion implantation process on the material ofsubstrate212. Buried well layer222 insulates the floatingsubstrate region224, which has a first conductivity type, from thebulk substrate212.Fin structure252 includes first andsecond regions216,218 having a second conductivity type. Thus, the floatingbody region224 is bounded by the top surface of thefin252, the first andsecond regions216,218 the buried well layer222, and insulating layers226 (see insulatinglayers226 inFIG. 184). Insulatinglayers226 insulatecell1250V from neighboringcells1250V whenmultiple cells50 are joined to make a memory device.Fin252 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
• Device1250V further includesgates264 on two opposite sides of the floatingsubstrate region224 as shown inFIG. 182. Alternatively,gates264 can enclose three sides of the floatingsubstrate region224 as shown inFIG. 183.Gates264 are insulated from floatingbody224 by trappinglayer260.Gates264 are positioned between the first andsecond regions16,18, adjacent to the floatingbody24.
• Device1250V includes several terminals: word line (WL) terminal70, source line (SL) terminal72, bit line (BL)terminal74, buried well (BW)terminal76 andsubstrate terminal78.Terminal70 is connected to thegate264.Terminal72 is connected tofirst region216 and terminal74 is connected tosecond region218. Alternatively, terminal72 can be connected tosecond region218 and terminal74 can be connected tofirst region216.Terminal76 is connected to buriedlayer222 and terminal78 is connected tosubstrate212.FIG. 184 illustrates the top view of thememory cell1250V shown inFIG. 182.
• Up until this point, the descriptions ofcells1250,1250S,1250V have been in regard to binary cells in which the data memories, both volatile (e.g.,24,124,224) and non-volatile (e.g.,62a,62b,162a,162b,262aand262bare binary, meaning that each memory storage location either stores a state “1” or a state “0”. In alternative embodiments, any of thememory cells1250,1250S,1250V can be configured to function as multi-level cells, so that more than one bit of data can be stored in one storage location of a cell. Thus, for example, one or more ofvolatile memory24,124,224;non-volatile memory62a,162a,262a; and/ornon-volatile memory62b,162b,262bcan be configured to store multiple bits of data.
• FIG. 185A illustrates the states of a binary memory storage, relative to threshold voltage, wherein a threshold voltage less than or equal to a predetermined voltage (in one example, the predetermined voltage is 0 volts, but the predetermined voltage may be a higher or lower voltage) inmemory cell1250,1250S,1250V is interpreted as state “1”, and a voltage greater than the predetermined voltage inmemory cell1250,1250S or1250V is interpreted as state “0”.
• FIG. 185B illustrates an example of voltage states of a multi-level storage wherein two bits of data can be stored in any or each ofstorage locations24,124,224,62a,62b,162a,162b,262a,262b. In this case, a threshold voltage less than or equal to a first predetermined voltage (e.g., 0 volts or some other predetermined voltage) and greater than a second predetermined voltage that is less than the first predetermined voltage (e.g., about −0.5 volts or some other voltage less than the first predetermined voltage) inmemory cell1250,1250S,1250V is interpreted as state “10”, a voltage less than or equal to the second predetermined voltage is interpreted as state “11”, a voltage greater than the first predetermined voltage and less than or equal to a third predetermined voltage that is greater than the first predetermined voltage (e.g., about +0.5 volts or some other predetermined voltage that is greater than the first predetermined voltage) is interpreted to be state “01” and a voltage greater than the third predetermined voltage is interpreted as state “00”. Further details about multi-level operation can be found in co-pending, commonly owned application Ser. No. 11/996,311 filed Nov. 29, 2007. Application Ser. No. 11/996,311 is hereby incorporated herein, in its entirety, by reference thereto.
• While the present invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, process, process step or steps, to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto.
• FIG. 186A illustrates the schematic cross-sectional view ofmemory cell1350 according to the present invention, respectively.Memory cell1350 includes asubstrate12 of a first conductivity type such as p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention,substrate12 can be the bulk material of the semiconductor wafer. In other embodiments,substrate12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, thesubstrate12 will usually be drawn as the semiconductor bulk material as it is inFIG. 186A.
• A buriedlayer22 of a second conductivity type such as n-type, for example, is provided in thesubstrate12.Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can also be grown epitaxially on top ofsubstrate12.
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top bybit line region16,source line region18, and insulatinglayer62, on the sides by insulatinglayers26, and on the bottom by buriedlayer22. Floatingbody24 may be the portion of theoriginal substrate12 above buriedlayer22 if buriedlayer22 is implanted. Alternatively, floatingbody24 may be epitaxially grown. Depending on how buriedlayer22 and floatingbody24 are formed, floatingbody24 may have the same doping assubstrate12 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.
• Insulating layers26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers26 insulatescell1350 from neighboringcells1350 whenmultiple cells1350 are joined in anarray1380 to make a memory device. The bottom of insulatinglayer26 may reside inside the buriedregion22 allowing buriedregion22 to be continuous as shown inFIG. 186A. Alternatively, the bottom of insulatinglayer26 may reside below the buriedregion22 as shown in the cross-sectional view of another embodiment ofmemory cell1350 inFIG. 186B. This requires a shallower insulatinglayer28, which insulates the floatingbody region24, but allows the buriedlayer22 to be continuous in the perpendicular direction of the cross-sectional view shown inFIG. 186B. For simplicity, onlymemory cell1350 with continuous buriedregion22 in all directions will be shown from hereon.
• Abit line region16 having a second conductivity type, such as n-type, for example, is provided in floatingbody region24 and is exposed atsurface14.Bit line region16 is formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region16.
• Asource line region18 having a second conductivity type, such as n-type, for example, is also provided in floatingbody region24 and is exposed atsurface14.Source line region18 is formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formsource line region18.
• Memory cell1350 is asymmetric in that the area ofsource line region18 is larger than that ofbit line region16. The largersource line region18 results in a higher coupling between thesource line region18 and floatinggate60, as compared to the coupling between thebit line region16 and the floatinggate60.
• A floatinggate60 is positioned in between thebit line region16 andsource line region18 and above the floatingbody region24. The floatinggate60 is insulated from floatingbody region24 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The floatinggate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell1350 is a single polysilicon floating gate memory cell. As a result,cell1350 is compatible with typical complementary metal oxide semiconductor (CMOS) processes. The floatinggate60 polysilicon materials can be deposited and formed in conjunction with the gates of logic transistors. This is compared for example with stacked gate Flash memory device, where a second polysilicon gate (e.g. a control gate) is stacked above a polysilicon floating gate (see for example FIG. 4.6 on p. 197 in “Nonvolatile Semiconductor Memory Technology”, W. D. Brown and J. E. Brewer “Brown”), which is hereby incorporated herein, in its entirety, by reference thereto. Such stacked gate memory cell typically require dual (or more) polysilicon layer processing, where the first polysilicon (e.g. floating gate) is deposited and formed, followed by the formation of a second polysilicon (e.g. control gate) layer.
• Cell1350 includes several terminals: bit line (BL) terminal74 electrically connected to bitline region16, source line (SL) terminal72 electrically connected to sourceline region18, buried well (BW) terminal76 electrically connected to buriedlayer22, andsubstrate terminal78 electrically connected to thesubstrate12. There is no electrical connection to floatinggate60. As a result, floatinggate60 is floating and is used as the non-volatile storage region.
• FIG. 186C illustrates the equivalent circuit representation ofmemory cell1350. Inherent inmemory cell1350 are metal-oxide-semiconductor (MOS)transistor20, formed bybit line region16, floatinggate60,source line region18, and floatingbody region24, andbipolar devices30aand30b, formed by buriedwell region22, floatingbody region24, and bitline region16 orsource line region18, respectively.
• Also inherent inmemory device1350 isbipolar device30c, formed bybit line region16, floatingbody24, andsource line region18. For drawings clarity,bipolar device30cis shown separately inFIG. 186D.
• FIG. 186E illustrates anexemplary memory array1380 of memory cells1350 (four exemplary instances ofmemory cell1350 being labeled as1350a,1350b,1350cand1350d) arranged in rows and columns. In many, but not necessarily all, of the figures whereexemplary array1380 appears,representative memory cell1350awill be representative of a “selected”memory cell1350 when the operation being described has one (or more in some embodiments) selectedmemory cells1350. In such figures,representative memory cell1350bwill be representative of anunselected memory cell1350 sharing the same row as selectedrepresentative memory cell1350a,representative memory cell1350cwill be representative of anunselected memory cell1350 sharing the same column as selectedrepresentative memory cell1350a, andrepresentative memory cell1350dwill be representative of amemory cell1350 sharing neither a row or a column with selectedrepresentative memory cell1350a.
• Present inFIG. 186E aresource lines72athrough72n,bit lines74athrough74p, buried wellterminals76athrough76n, andsubstrate terminal78. Each of the source lines72athrough72nis associated with a single row ofmemory cells1350 and is coupled to thesource line region18 of eachmemory cell1350 in that row. Each of the bit lines74athrough74pis associated with a single column ofmemory cells1350 and is coupled to thebit line region16 of eachmemory cell1350 in that column.
• Substrate12 is present at all locations underarray1380. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals78 may be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that whileexemplary array1380 is shown as a single continuous array inFIG. 186E, that many other organizations and layouts are possible. For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray1380 may be broken into two or more sub-arrays, and/or control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed aroundexemplary array1380 or inserted between sub-arrays ofarray1380. Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.
• FIG. 187 shows aflowchart100 describing the operation of thememory device1350. Atevent102, when power is first applied to the memory device, the memory device is placed in an initial state, where the nonvolatile memory portion of the device is set to a predetermined state. Atevent104, thememory device1350 operates in the volatile operational mode. During power shutdown, or when power is inadvertently lost, or any other event that discontinues or upsets power to thememory device1350, the content of the volatile memory is loaded into the non-volatile memory portion atevent106, during a process which is referred to here as “shadowing”. A shadowing operation can also be performed during backup operations, which may be performed at regular intervals duringvolatile operation104 periods, and/or at any time that a user manually instructs a backup. During a backup operation, the content of the volatile memory is copied to the non-volatile memory while power is maintained to the volatile memory so that the content of the volatile memory also remains in volatile memory. Alternatively, because the volatile memory operation consumes more power than the non-volatile storage of the contents of the volatile memory, the device can be configured to perform the shadowing process anytime the device has been idle for at least a predetermined period of time, thereby transferring the contents of the volatile memory into non-volatile memory and conserving power. As one example, the predetermined time period can be about thirty minutes, but of course, the invention is not limited to this time period, as the device could be programmed with virtually any predetermined time period that is longer than the time period required to perform the shadowing process with careful consideration of the non-volatile memory reliability.
• After the content of the volatile memory has been moved during a shadowing operation, the shutdown of thememory device1350 occurs, as power is no longer supplied to the volatile memory. At this time, the memory device retains the stored data in the nonvolatile memory. Upon restoring power atevent108, the content of the nonvolatile memory is restored by transferring the content of the nonvolatile memory to the volatile memory in a process referred to herein as the “restore” process, after which, upon resetting the memory device atevent110, thememory device1350 may be reset to theinitial state102 and again operates in a volatile mode atevent104.
• In one embodiment, the non-volatile memory (e.g. the floating gate60) is initialized to have a positive charge atevent102. When power is applied tocell1350,cell1350 stores the memory information (i.e. data that is stored in memory) as charge in the floatingbody24 of thememory device1350. The presence of the electrical charge in the floatingbody24 modulates the current flow through the memory device1350 (from theBL terminal74 to the SL terminal72). The current flowing through thememory device1350 can be used to determine the state of thecell1350. Because the non-volatile memory element (e.g. the floating gate60) is initialized to have a positive charge, any cell current differences are attributed to the differences in charge of the floatingbody24.
• Several operations can be performed tomemory cell1350 during volatile mode: holding, read, write logic-1 and write logic-0 operations.
• FIG. 188 shows the holding operation onmemory array1380, which consists of a plurality ofmemory cells1350. The holding operation is performed by applying a positive back bias to theBW terminal76, and zero bias on theBL terminal74 andSL terminal72. The positive back bias applied to the buried layer region connected to the BW terminal will maintain the state of thememory cell1350 that it is connected to.
• From the equivalent circuit representation ofmemory cell1350 shown inFIG. 186C, inherent in thememory cell1350 is n-p-nbipolar devices30aand30bformed by buried well region22 (the collector region), floating body24 (the base region), and bitline region16 or source line region18 (the emitter region), respectively.
• FIG. 189A shows the energy band diagram of the intrinsic n-p-nbipolar device30awhen the floatingbody region24 is positively charged and a positive bias voltage is applied to the buriedwell region22. The energy band diagram of then-p-n device30bis similar to the one shown inFIG. 189A, with the source line region18 (connected to SL terminal72) replacing the bit line region16 (connected to BL terminal74). The dashed lines indicate the Fermi levels in the various regions of then-p-n transistor30a. The Fermi level is located in the band gap between thesolid line17 indicating the top of the valence band (the bottom of the band gap) and thesolid line19 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. If floatingbody24 is positively charged, a state corresponding to logic-1, thebipolar transistors30aand30bwill be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floatingbody region24, the electrons will be swept into the buried well region22 (connected to BW terminal76) due to the positive bias applied to the buriedwell region22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theBW terminal76 while the resulting hot holes will subsequently flow into the floatingbody region24. This process restores the charge on floatingbody24 and will maintain the charge stored in the floatingbody region24 which will keep the n-p-nbipolar transistors30aand30bon for as long as a positive bias is applied to the buriedwell region22 throughBW terminal76.
• If floatingbody24 is neutrally charged (the voltage on floatingbody24 being equal to the voltage on grounded bit line region16), a state corresponding to logic-0, no current will flow through then-p-n transistors30aand30b. Thebipolar devices30aand30bwill remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
• FIG. 189B shows the energy band diagram of the intrinsic n-p-nbipolar device130awhen the floatingbody region24 is neutrally charged and a bias voltage is applied to the buriedwell region22. In this state the energy level of the band gap bounded bysolid lines17A and19A is different in the various regions of n-p-nbipolar device30a. Because the potential of the floatingbody region24 and thebit line region16 is equal, the Fermi levels are constant, resulting in an energy barrier between thebit line region16 and the floatingbody region24.Solid line23 indicates, for reference purposes, the energy barrier between thebit line region16 and the floatingbody region24. The energy barrier prevents electron flow from the bit line region16 (connected to BL terminal74) to the floatingbody region24. Thus the n-p-nbipolar device30 will remain off.
• In the holding operation described inFIG. 188, there is no individually selected memory cell. Rather cells are selected in rows by the buried wellterminals76athrough76nand may be selected as individual rows, as multiple rows, or as all of therows comprising array1380.
• In one embodiment the bias condition for the holding operation formemory cell1350 is: 0 volts is applied toBL terminal74, 0 volts is applied toSL terminal72, a positive voltage like, for example, +1.2 volts is applied toBW terminal76, and 0 volts is applied to thesubstrate terminal78. In other embodiments, different voltages may be applied to the various terminals ofmemory cell1350 as a matter of design choice and the exemplary voltages described are therefore not limiting.
• The read operation of thememory cell1350 andarray1380 of memory cells will described in conjunction withFIGS. 190A and 190B. Any sensing scheme known in the art can be used withmemory cell1350. Examples include, for example, the sensing schemes disclosed in “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002) (“Ohsawa-1”) and “An 18.5 ns 128 Mb SOI DRAM with a Floating Body Cell”, Ohsawa et al., pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005 (“Ohsawa-2”), both of which are hereby incorporated herein, in their entireties, by reference thereto.
• The amount of charge stored in the floatingbody24 can be sensed by monitoring the cell current of thememory cell1350. Ifmemory cell1350 is in a logic-1 state having holes in thebody region24, then the memory cell will have a higher cell current (e.g. current flowing from theBL terminal74 to SL terminal72), compared to ifcell1350 is in a logic-0 state having no holes in floatingbody region24. A sensing circuit typically connected toBL terminal74 can then be used to determine the data state of the memory cell.
• A read operation may be performed through an active bit line high (seeFIG. 190A) or an active source line high (seeFIG. 190B) scheme. In an active bit line high, a positive bias is applied to the selectedBL terminal74, zero voltage is applied to the selectedSL terminal72, zero or positive voltage is applied to the selectedBW terminal76 and zero voltage is applied to thesubstrate terminal78.
• In one exemplary embodiment, about 0.0 volts is applied to the selected SL terminal72a, about +0.4 volts is applied to the selectedbit line terminal74a, about +1.2 volts is applied to the selected buried well terminal76a, and about 0.0 volts is applied tosubstrate terminal78. All unselectedbit line terminals74bthrough74phave 0.0 volts applied or left floating, theunselected SL terminals72bthrough72phave +0.4 volts applied or left floating, while theunselected BW terminals76bthrough76pcan be grounded or have +1.2 volts applied to maintain the states of theunselected cells1350, and 0.0 volts is applied to thesubstrate terminal78.FIG. 190A shows the bias conditions for the selectedrepresentative memory cell1350aand three unselectedrepresentative memory cells1350b,1350c, and1350dinmemory array1380, each of which has a unique bias condition. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
• In an active source line high, a positive bias is applied to the selectedSL terminal72, zero voltage is applied to the selectedBL terminal74, zero or positive voltage is applied to the selectedBW terminal76 and zero voltage is applied to thesubstrate terminal78.
• In one exemplary embodiment, about +0.4 volts is applied to the selected SL terminal72a, about 0.0 volts is applied to the selectedbit line terminal74a, about +1.2 volts is applied to the selected buried well terminal76a, and about 0.0 volts is applied tosubstrate terminal78. All unselectedbit line terminals74bthrough74phave +0.4 volts applied or left floating, theunselected SL terminals72bthrough72phave 0.0 volts applied or left floating, while theunselected BW terminals76bthrough76pcan be grounded or have +1.2 volts applied to maintain the states of theunselected cells1350, and 0.0 volts is applied to thesubstrate terminal78.FIG. 190B shows the bias conditions for the selectedrepresentative memory cell1350aand three unselectedrepresentative memory cells1350b,1350c, and1350dinmemory array1380, each of which has a unique bias condition. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
• A write logic-0 operation of anindividual memory cell1350 is now described with reference toFIGS. 191A and 191B. InFIG. 191A, a negative voltage bias is applied to theSL terminal72, a zero voltage bias is applied toBL terminal74, zero or positive voltage is applied to the selectedBW terminal76 and zero voltage is applied to thesubstrate terminal78. Under these conditions, the p-n junction between floatingbody24 andsource line region18 of the selectedcell1350 is forward-biased, evacuating any holes from the floatingbody24. Because theSL terminal72 is shared amongmultiple memory cells1350, logic-0 will be written into allmemory cells1350 includingmemory cells1350aand1350bsharing thesame SL terminal72asimultaneously.
• In one particular non-limiting embodiment, about −0.5 volts is applied to sourceline terminal72, about 0.0 volts is applied tobit line terminal74, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• InFIG. 191B, a negative voltage bias is applied to theBL terminal74, a zero voltage bias is applied toSL terminal72, zero or positive voltage is applied to the selectedBW terminal76 and zero voltage is applied to thesubstrate terminal78. Under these conditions, the p-n junction between floatingbody24 andbit line region16 of the selectedcell1350 is forward-biased, evacuating any holes from the floatingbody24. Because theBL terminal74 is shared amongmultiple memory cells1350 inmemory array1380, logic-0 will be written into allmemory cells1350 includingmemory cells1350aand1350csharing thesame BL terminal74asimultaneously.
• In one particular non-limiting embodiment, about −0.5 volts is applied tobit line terminal74, about 0.0 volts is applied to sourceline terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• Both write logic-0 operations referred to above each has a drawback that allmemory cells1350 sharing either the same SL terminal72 (the first type—row write logic-0) or thesame BL terminal74 will (the second type—column write logic-0) be written to simultaneously and as a result, does not allow writing logic-0 toindividual memory cells1350. To write arbitrary binary data todifferent memory cells1350, a write logic-0 operation is first performed on all the memory cells to be written followed by one or more write logic-1 operations on the bits that must be written to logic-1.
• FIGS. 192A and 192B describe write logic-1 operations using active bit line high scheme and active source line high scheme, respectively. Under active bit line high scheme, the following bias condition is applied: a positive voltage is applied to the selectedBL terminal74, zero voltage is applied to the selectedSL terminal72, zero or positive voltage is applied to the selectedBW terminal76 and zero voltage is applied to thesubstrate terminal78. A positive voltage less than the positive voltage applied to the selectedBL terminal74 is applied to the unselected SL terminals72 (e.g. SL terminals72bthrough72ninFIG. 192A), while zero voltage is applied to the unselected BL terminals74 (e.g. BL terminals74bthrough74pinFIG. 192A). Alternatively, the unselected SL and BL terminals can be left floating.
• Because the floatinggate60 is positively charged, electrons will flow through the selectedmemory cell1350afrom theSL terminal72ato theBL terminal74a. The bias conditions on the selected terminals are configured such that theMOS device20 of the selectedcell1350ais in saturation (i.e. the voltage applied to theBL terminal74 is greater than the difference between thevoltage floating gate60 and the threshold voltage of the MOS device20). As a result, electrons will be accelerated in the pinch-off region of theMOS device20, creating hot carriers in the vicinity of thebit line region16. The generated holes will then flow into the floatingbody24, putting thecell1350ato the logic-1 state.
• In one particular non-limiting embodiment, about +1.2 volts is applied to the selectedbit line terminal74, about 0.0 volts is applied to sourceline terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied to the unselectedbit line terminal74 and about +0.4 volts is applied to the unselectedsource line terminal72. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• For memory cells sharing the same row as the selected memory cell (e.g. cell1350b), both the BL and SL terminals are grounded and no current will flow through. These cells will be at the holding mode with a positive voltage applied to theBW terminal76.
• For memory cells sharing the same column as the selected memory cell (e.g. cell1350c), the positive bias applied to the unselected SL terminal will turn off theMOS device20 of these cells. Consequently, no current will flow through. A smaller holding current will flow through these cells because of the smaller difference between theBW terminal76 and theSL terminal72. However, because write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell1350d), the SL terminal is positively biased while the BL terminal is grounded. However, the positive bias applied to the SL terminal is kept low enough so that no impact ionization occurs. These cells will be at the holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 while memory cells in state logic-0 will remain in neutral state.
• FIG. 192B illustrates the write logic-1 operation under the active source line high scheme, where the following bias condition is applied: a positive voltage is applied to the selectedSL terminal72, zero voltage is applied to the selectedBL terminal74, zero or positive voltage is applied to the selectedBW terminal76 and zero voltage is applied to thesubstrate terminal78. A positive voltage less than the positive voltage applied to the selectedSL terminal72 is applied to the unselected BL terminals74 (e.g. BL terminals74bthrough74pinFIG. 192B), while zero voltage is applied to the unselected SL terminals72 (e.g. SL terminals72bthrough72ninFIG. 192B). Alternatively, the unselected SL and BL terminals can be left floating.
• The positive charge on the floatinggate60 combined with the capacitive coupling from thesource line region18 will turn on theMOS device20 of the selectedcell1350a. As a result, electrons will flow through the selectedmemory cell1350afrom theBL terminal74ato theSL terminal72a. The bias conditions on the selected terminals are configured such that theMOS device20 of the selectedcell1350ais in saturation (i.e. the voltage applied to theSL terminal72 is greater than the difference between thevoltage floating gate60 and the threshold voltage of the MOS device20). As a result, electrons will be accelerated in the pinch-off region of theMOS device20, creating hot carriers in the vicinity of thesource line region18. The generated holes will then flow into the floatingbody24, putting thecell1350ato the logic-1 state.
• In one particular non-limiting embodiment, about +1.2 volts is applied to the selectedsource line terminal72, about 0.0 volts is applied to the selectedbit line terminal74, about 0.0 volts or +1.2 volts is applied toBW terminals76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied to the unselectedsource line terminals72 and about +0.4 volts is applied to the unselectedbit line terminals74. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• For memory cells sharing the same row as the selected memory cell (e.g. cell1350b), the positive bias applied to the unselected BL terminal will turn off theMOS device20 of these cells. Consequently, no current will flow through. A smaller holding current will flow through these cells because of the smaller difference between theBW terminal76 and theSL terminal72. However, because the write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
• For memory cells sharing the same column as the selected memory cell (e.g. cell1350c), both the BL and SL terminals are grounded and no current will flow through. These cells will be at the holding mode with a positive voltage applied to theBW terminal76.
• For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell1350d), the BL terminal is positively biased while the SL terminal is grounded. However, the positive bias applied to the BL terminal is kept low enough so that no impact ionization occurs. These cells will be at the holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody24 while memory cells in state logic-0 will remain in neutral state.
• When power down is detected, e.g., when a user turns off the power tocell1350, or the power is inadvertently interrupted, or for any other reason, power is at least temporarily discontinued tocell1350, data stored in the floatingbody region24 is transferred to floatinggate60. This operation is referred to as “shadowing” and is described with reference toFIGS. 193A-193C.
• FIGS. 193A-193C illustrate an embodiment of operation ofcell1350 to perform a volatile to non-volatile shadowing process, which operates by a hot electron injection process. To perform a shadowing process, the following bias conditions are applied: a positive voltage is applied to theSL terminal72, zero voltage is applied to theBL terminal74, zero or positive voltage is applied to theBW terminal76, and zero voltage is applied to thesubstrate terminal78.
• In one particular non-limiting embodiment, about +6.0 volts is applied to thesource line terminal72, about 0.0 volts is applied tobit line terminal74, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 193B illustrates the cross section ofcell1350 during a shadowing process when floatingbody24 is positively charged. When floatingbody24 has a positive charge/voltage, theMOS device20 and thebipolar device30care on, and electrons flow from thebit line region16 to the source line region18 (in the direction of the arrow shown inFIG. 193B). The application of the positive voltage to terminal72 atsource line region18 energizes/accelerates electrons traveling through the floatingbody24 to a sufficient extent that they can “jump over” the oxide barrier between floatingbody24 and floatinggate60, so that electrons enter floating gate60 (as indicated by the arrow into floatinggate60 inFIG. 193B). Accordingly, floatinggate60 becomes negatively charged by the shadowing process, when the volatile memory ofcell1350 is in logic-1 state (i.e., floatingbody24 is positively charged), as shown inFIG. 193B.
• FIG. 193C illustrates the cross section ofcell1350 during a shadowing process when floatingbody24 is neutral. When floatingbody24 is neutral, theMOS device20 and thebipolar device30care off, and no electrons flow through thecell1350. Accordingly, floatinggate60 retains its positive charge at the end of the shadowing process, when the volatile memory ofcell1350 is in logic-0 state (i.e., floatingbody24 is neutral), as shown inFIG. 193C.
• A positive voltage less than the positive voltage on theSL terminal72 can also be applied to theBL terminal74 to ensure that onlymemory cells1350 with positive floatingbody24 is conducting current during shadowing operation.
• Note that upon the completion of the shadowing operation, the charge state of the floatinggate60 is complementary to that of the floatingbody24. Thus, if the floatingbody24 of thememory cell1350 has a positive charge in volatile memory, the floatinggate60 will become negatively charged by the shadowing process, whereas if the floatingbody24 of thememory cell1350 has a negative or neutral charge in volatile memory, the floatinggate layer60 will be positively charged at the end of the shadowing operation. The charges/states of the floatinggates60 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
• When power is restored tocell1350, the state of thecell1350 as stored on floatinggate60 is restored into floatingbody region24. The restore operation (data restoration from non-volatile memory to volatile memory) is described with reference toFIGS. 194A-194C. Prior to the restore process, the floatingbodies24 are set to neutral state, which is the state of the floating bodies when power is removed from thememory device1350. To perform the restore process, the following bias conditions are applied: a positive voltage is applied to theBL terminal74, zero voltage is applied to theSL terminal72, zero or positive voltage is applied to theBW terminal76, and zero voltage is applied to thesubstrate terminal78.
• In one particular non-limiting embodiment, about +3.0 volts is applied to thebit line terminal74, about 0.0 volts is applied to sourceline terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 194B illustrates the cross section ofcell1350 during restore process when floatinggate60 is negatively charged. The negative charge on the floatinggate60 and the positive voltage onBL terminal74 create a strong electric field between thebit line region16 and the floatingbody region24 in the proximity of floatinggate60. This bends the energy band sharply upward near the gate and bit line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floatingbody region24 and become the hole charge that creates the logic-1 state. This process is well known in the art as band-to-band tunneling or gate induced drain leakage (GIDL) mechanism and is illustrated in for example in “A Design of a Capacitor-less 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003 (“Yoshida”) (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4), which is hereby incorporated herein, in its entirety, by reference thereto.
• FIG. 194C illustrates the cross section ofcell1350 during restore process when floatinggate60 is positively charged. The positive charge on the floatinggate60 and thebit line region16 do not result in strong electric field to drive hole injection into the floatingbody24. Consequently, the floatingbody24 will remain in neutral state.
• It can be seen that if floatinggate60 has a positive charge after shadowing is performed, the volatile memory of floatingbody24 will be restored to have a neutral charge (logic-0 state), but if the floatinggate60 has a negative charge, the volatile memory of floatingbody24 will be restored to have a positive charge (logic-1 state), thereby restoring the original state of the floatingbody24 prior to the shadowing operation. Note that this process occurs non-algorithmically, as the state of the floatinggate60 does not have to be read, interpreted, or otherwise measured to determine what state to restore the floatingbody24 to. Rather, the restoration process occurs automatically, driven by electrical potential differences. Accordingly, this process is orders of magnitude faster than one that requires algorithmic intervention.
• After restoring the memory cell(s)1350, the floating gate(s)60 is/are reset to a predetermined state, e.g., a positive state, so that each floatinggate60 has a known state prior to performing another shadowing operation. The reset process operates by the mechanism of band-to-band tunneling hole injection to the floating gate(s)60, as illustrated inFIG. 195.
• The reset mechanism follows a similar mechanism as the restore process. A negatively charged floatinggate60 will result in an electric field generating hot holes. The majority of the resulting hot holes are injected into the floatingbody24 and a smaller portion will be injected into the floatinggate60. The hole injection will only occur incells1350 with negatively charged floatinggate60. As a result, all floatinggates60 will be initialized to have a positive charge by the end of the reset process.
• In one particular non-limiting embodiment, about +3.0 volts is applied to thebit line terminal74, about 0.0 volts is applied to sourceline terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way. The bias condition is similar to that of the restore operation. However, because the amount of holes injected into the floatinggate60 is a smaller portion than those injected into the floatingbody24, the reset operation proceeds more slowly than the restore operation. A negative voltage can also be applied to eithersource line terminal72 or buried well terminal76 to ensure that no holes are accumulated inmemory cells1350 with positively charged floatinggate60.
• Thememory cell1350 can be manufactured in several manners.FIGS. 196 and 197 provide examples of manufacturing processes to obtainmemory cell1350. The figures are arranged in groups of three related views, with the first figure of each group being a top view, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated I-I′, and the third figure of each group being a horizontal cross section of the top view in the first figure of the group designated II-II′. ThusFIGS. 196A, 196D, 196G, 196J, 196M, 196P and 197A, 197D, 197G, 197J, 197M and 197P are a series of top views of thememory cell1350 at various stages in the manufacturing process,FIGS. 196B, 196E, 196H, 196K, 196N and 196Q and 197B, 197E, 197H, 197K, 197N and 197Q are their respective vertical cross sections labeled I-I′, andFIGS. 196C, 196F, 196I, 196L, 196O and 196R and 197C, 197F, 197I, 197L, 197O and 197R are their respective horizontal cross sections labeled II-II′. Identical reference numbers fromFIGS. 186 through 195 appearing inFIGS. 196 and 197 represent similar, identical or analogous structures as previously described in conjunction with the earlier drawing figures. Here “vertical” means running up and down the page in the top view diagram and “horizontal” means running left and right on the page in the top view diagram. In a physical embodiment ofmemory cell1350, both cross sections are vertical with respect to the surface of the semiconductor device.
• FIGS. 196A through 196C show the first steps of the process. In an exemplary 130 nanometer (nm) process a thinsilicon oxide layer82 with a thickness of about 100 A may be grown on the surface ofsubstrate12. This may be followed by a deposition of about 200 A ofpolysilicon layer84. This in turn may be followed by deposition of about 1200 Asilicon nitride layer86. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other numbers of, thicknesses of, and combinations ofprotective layers82,84 and86 may be used as a matter of design choice. A pattern opening the areas to becometrench80 may be formed using a lithography process. Then thesilicon oxide82,polysilicon84,silicon nitride86 layers may be subsequently patterned using the lithography process and then may be etched, followed by a silicon etch process, creatingtrench80.
• As shown inFIGS. 196D through 196F, this may be followed by a silicon oxidation step, which will grow silicon oxide films intrench80 which will become insulatinglayer26. In an exemplary 130 nm process, about 4000 A silicon oxide may be grown. A chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface. In other embodiments the top of insulatinglayer26 may have different height relative to the silicon surface. Thesilicon nitride layer86 and thepolysilicon layer84 may then be removed which may then be followed by a wet etch process to remove silicon oxide layer82 (and a portion of the silicon oxide films formed in the area of former trench80). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other insulating layer materials, heights, and thicknesses as well as alternate sequences of processing steps may be used as a matter of design choice.
• As shown inFIGS. 196G through 196I, an ion implantation step may then be performed to form the buriedlayer region22 of a second conductivity (e.g. n-type conductivity). The ion implantation energy is optimized such that the bottom of the buriedlayer region22 is formed deeper than the bottom of the insulatinglayer26.Buried layer22 isolates the eventual floatingbody region24 of the first conductivity type (e.g., p-type) from thesubstrate12.
• As shown inFIGS. 196J through 196L, a silicon oxide or high-dielectric materialgate insulation layer62 may then be formed on the silicon surface (e.g. about 100 A in an exemplary 130 nm process), which may then be followed by a polysilicon ormetal gate60 deposition (e.g. about 500 A in an exemplary 130 nm process).
• As shown inFIGS. 196M through 196O, a lithography step may then be performed to pattern thelayers62 and60 to open the areas to becomesource line region18. This may then be followed by etching of the polysilicon and silicon oxide layers. An ion implantation step may then be performed to form thesource line region18 or a second conductivity (e.g. n-type conductivity). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other gate and gate insulation materials with different thicknesses may be used a matter of design choice.
• As shown inFIGS. 196P through 196R, another lithography step may then be performed to pattern thelayers62 and60 to open the areas to becomebit line region16. This may then be followed by etching of the polysilicon and silicon oxide layers. An ion implantation step may then be performed to form thebit line region16 or a second conductivity (e.g. n-type conductivity). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other gate and gate insulation materials with different thicknesses may be used a matter of design choice.
• An alternative manufacturing process ofcell1350 is provided inFIGS. 197A through 197R. The process sequence depicted inFIGS. 197A through 197R involves only one lithography patterning and etching sequence to define the floatinggate60 of thememory cell1350. Therefore, this process sequence is compatible with the standard complementary metal-oxide-semiconductor (CMOS) process. The higher capacitive coupling between thesource line region18 and the floatinggate60 is achieved through the extension of the floatinggate60 into the area ofsource line region18 as shown in the final structure ofcell1350 inFIGS. 197P through 197R. As will be observed, the width of the floatinggate60 extension into thesource line region18 is configured such that subsequent implant processes will result in a continuous channel region under thegate60. Roizin cited above teaches an example of a CMOS-compatible process sequence to manufacture a floating gate non-volatile memory cell.
• The initial steps of the alternative process are similar to the sequence shown inFIGS. 196A through 196C.FIGS. 197A through 197C show the first steps of the process. In an exemplary 130 nanometer (nm) process a thinsilicon oxide layer82 with a thickness of about 100 A may be grown on the surface ofsubstrate12. This may be followed by a deposition of about 200 A ofpolysilicon layer84. This in turn may be followed by deposition of about 1200 Asilicon nitride layer86. Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other numbers of, thicknesses of, and combinations ofprotective layers82,84 and86 may be used as a matter of design choice. A pattern opening the areas to becometrench80 may be formed using a lithography process. Then thesilicon oxide82,polysilicon84,silicon nitride86 layers may be subsequently patterned using the lithography process and then may be etched, followed by a silicon etch process, creatingtrench80.
• As shown inFIGS. 197D through 197F, this may be followed by a silicon oxidation step, which will grow silicon oxide films intrench80 which will become insulatinglayer26. In an exemplary 130 nm process, about 4000 A silicon oxide nay be grown. A chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface. In other embodiments the top of insulatinglayer26 may have different height relative to the silicon surface. Thesilicon nitride layer86 and thepolysilicon layer84 may then be removed which may then be followed by a wet etch process to remove silicon oxide layer82 (and a portion of the silicon oxide films formed in the area of former trench80). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other insulating layer materials, heights, and thicknesses as well as alternate sequences of processing steps may be used as a matter of design choice.
• As shown inFIGS. 197G through 197I, an ion implantation step may then be performed to form the buriedlayer region22 of a second conductivity (e.g. n-type conductivity). The ion implantation energy is optimized such that the bottom of the buriedlayer region22 is formed deeper than the bottom of the insulatinglayer26.Buried layer22 isolates the eventual floatingbody region24 of the first conductivity type (e.g., p-type) from thesubstrate12.
• As shown inFIGS. 197J through 197L, a silicon oxide or high-dielectric materialgate insulation layer62 may then be formed on the silicon surface (e.g. about 100 A in an exemplary 130 nm process), which may then be followed by a polysilicon ormetal gate60 deposition (e.g. about 500 A in an exemplary 130 nm process). Other process geometries like, for example, 250 nm, 180 nm, 90 nm, 65 nm, etc., may be used. Similarly, other gate and gate insulation materials with different thicknesses may be used a matter of design choice.
• As shown inFIGS. 197M through 197O, a lithography step may then be performed to pattern thelayers62 and60 to open the areas to becomebit line region16 andsource line region18. This may then be followed by etching of the polysilicon and silicon oxide layers. Contrary to the previous process sequence shown inFIGS. 196A through 196R, only one lithography and etch sequence is required as the areas of both bitline region16 andsource line region18 are defined simultaneously.
• FIGS. 197P through 197R show the subsequent ion implantation steps of a second conductivity type (e.g. n-type conductivity). In the area around thebit line region16, because the floatinggate region60 is relatively long, the ion implant does not penetrate into the area under the floating gate60 (seeFIG. 197Q). In the area around thesource line region18, because the floatinggate60 region is relatively narrow, the ion implant will penetrate into the area under the floatinggate60, resulting in a continuoussource line region18 under the floating gate60 (seeFIG. 197R). As a result, a metal-oxide-semiconductor (MOS) capacitor is formed in the floatinggate60 extension region into thesource line region18.
• FIG. 198 shows a cross section of an alternative embodiment ofmemory cell1350. Thecell1350 is similar to that shown inFIG. 186A or 186B, with agap region17 formed near the area ofbit line region16. As a result, there is no overlap between the floatinggate60 and thebit line region16. The operation of thecell1350 is similar to what has already been described inFIGS. 187 through 195. The volatile memory operation proceeds in the same manner, where the charge in the floatingbody24 modulating the properties ofcell1350 during volatile operation. However, the efficiency of the shadowing process can be increased due to the presence of thegap17. “Optimization of a Source-Side-Injection FAMOS Cell for Flash EPROM Applications”, D. K. Y. Liu et al., pp. 315-318, Technical Digest, International Electron Device Meeting 1991 (“Liu”), for example, describes an improvement of hot electron injection efficiency into a floating gate in a non-volatile memory cell.
• As described inFIGS. 193A through 193C, the following bias conditions are applied to perform a shadowing operation: a positive voltage is applied to theSL terminal72, zero voltage is applied to theBL terminal74, zero or positive voltage is applied to theBW terminal76, and zero voltage is applied to thesubstrate terminal78.
• In one particular non-limiting embodiment, about +6.0 volts is applied to thesource line terminal72, about 0.0 volts is applied tobit line terminal74, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• When floatingbody24 has a positive charge/voltage, theMOS device20 and thebipolar device30care on, and electrons flow from thebit line region16 to the source line region18 (in the direction of the arrow shown inFIG. 199A). Because of thegap17 in the area of thebit line region16, a large lateral electric field—which results from the voltage difference applied between thesource line region18 andbit line region16—will be developed. This lateral electric field will energize/accelerate electrons traveling through the floatingbody24 to a sufficient extent that they can “jump over” the oxide barrier between floatingbody24 and floatinggate60. A large vertical field—resulting from the potential difference between floatinggate60, which partly is due to the coupling from thesource line region18, and thesurface14—also exist. As a result, electrons enter floating gate60 (as indicated by the arrow into floatinggate60 inFIG. 199A). Accordingly, floatinggate60 becomes negatively charged by the shadowing process, when the volatile memory ofcell1350 is in logic-1 state (i.e., floatingbody24 is positively charged), as shown inFIG. 199A.
• FIG. 199B illustrates the cross section ofcell1350 during shadowing process when floatingbody24 is neutral. When floatingbody24 is neutral, theMOS device20 and thebipolar device30care off, and no electrons flow through thecell1350. Accordingly, floatinggate60 retains its positive charge at the end of the shadowing process, when the volatile memory ofcell1350 is in logic-0 state (i.e., floatingbody24 is neutral), as shown inFIG. 199B.
• Upon the completion of the shadowing operation, the charge state of the floatinggate60 is complementary to that of the floatingbody24. Thus, if the floatingbody24 of thememory cell1350 has a positive charge in volatile memory, the floatinggate60 will become negatively charged by the shadowing process, whereas if the floatingbody24 of thememory cell1350 has a negative or neutral charge in volatile memory, the floatinggate layer60 will be positively charged at the end of the shadowing operation. The charges/states of the floatinggates60 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
• FIGS. 200A-200C describe the restore operation when power is restored tocell1350. The restore operation restores the state of thecell1350 from the floatinggate60 into floatingbody region24. Prior to the restore process, the floatingbodies24 are set to neutral state, which is the state of the floating bodies when power is removed from thememory device1350. To perform the restore process, the following bias conditions are applied: a positive voltage is applied to theSL terminal72, zero or positive voltage is applied to theBW terminal76, and zero voltage is applied to thesubstrate terminal78, while theBL terminal74 is left floating.
• In one particular non-limiting embodiment, about +3.0 volts is applied to thesource line terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78, while thebit line terminal74 is left floating. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. For example, a positive voltage can be applied tobit line terminal74 to prevent any current flow through the channel region ofcell1350 during restore operation. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 200B illustrates the cross section ofcell1350 during a restore process when floatinggate60 is negatively charged. The negative charge on the floatinggate60 and the positive voltage onSL terminal72 create a strong electric field between thesource line region18 and the floatingbody region24 in the proximity of floatinggate60. This bends the energy band sharply upward near the gate and source line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floatingbody region24 and become the hole charge that creates the logic-1 state. This process is well known in the art as band-to-band tunneling or gate induced drain leakage (GIDL) mechanism and is illustrated in for example in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above. TheBL terminal74 is left floating or a positive voltage is applied thereto to prevent current from flowing through the channel region ofcell1350, which may result in impact ionization in allcells1350 when not prevented.
• FIG. 200C illustrates the cross section ofcell1350 during restore process when floatinggate60 is positively charged. The positive charge on the floatinggate60 and thebit line region16 do not result in strong electric field to drive hole injection into the floatingbody24. Consequently, the floatingbody24 will remain in neutral state.
• It can be seen that if floatinggate60 has a positive charge after shadowing is performed, the volatile memory of floatingbody24 will be restored to have a neutral charge (logic-0 state), but if the floatinggate60 has a negative charge, the volatile memory of floatingbody24 will be restored to have a positive charge (logic-1 state), thereby restoring the original state of the floatingbody24 prior to the shadowing operation. Note that this process occurs non-algorithmically, as the state of the floatinggate60 does not have to be read, interpreted, or otherwise measured to determine what state to restore the floatingbody24 to. Rather, the restoration process occurs automatically, driven by electrical potential differences. Accordingly, this process is orders of magnitude faster than one that requires algorithmic intervention.
• After restoring the memory cell(s)1350, the floating gate(s)60 is/are reset to a predetermined state, e.g., a positive state, so that each floatinggate60 has a known state prior to performing another shadowing operation. The reset process operates by the mechanism of band-to-band tunneling hole injection to the floating gate(s)60, as illustrated inFIG. 201.
• The reset mechanism follows a similar mechanism as the restore process. A negatively charged floatinggate60 will result in an electric field generating hot holes. The majority of the resulting hot holes are injected into the floatingbody24 and a smaller portion will be injected into the floatinggate60. The hole injection will only occur incells1350 with negatively charged floatinggate60. As a result, all floatinggates60 will be initialized to have a positive charge by the end of the reset process.
• In one particular non-limiting embodiment, about +3.0 volts is applied to thesource line terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78, while thebit line terminal74 is left floating. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way. The bias condition is similar to that of the restore operation. However, because the amount of holes injected into the floatinggate60 is a smaller portion than those injected into the floatingbody24, the reset operation proceeds more slowly than the restore operation. A negative voltage can also be applied to the buried well terminal76 to ensure that no holes are accumulated inmemory cells1350 with positively charged floatinggate60, while a positive voltage can also be applied to thebit line terminal74 to prevent current to flow through the channel region ofcell1350.
• FIG. 202 illustrates a cross-sectional view ofmemory cell1450 according to another embodiment of the present invention.Memory cell1450 includes asubstrate112 of a first conductivity type such as p-type, for example.Substrate112 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention,substrate112 can be the bulk material of the semiconductor wafer. In other embodiments,substrate112 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, thesubstrate112 will usually be drawn as the semiconductor bulk material as it is inFIG. 202.
• A buriedlayer122 of a second conductivity type such as n-type, for example, is provided in thesubstrate112.Buried layer122 may be formed by an ion implantation process on the material ofsubstrate112. Alternatively, buriedlayer122 can also be grown epitaxially on top ofsubstrate112.
• A floatingbody region124 of the first conductivity type, such as p-type, for example, is bounded on top bybit line region116,source line region118, and insulatinglayers162 and166, on the sides by insulatinglayers126, and on the bottom by buriedlayer122. Floatingbody124 may be the portion of theoriginal substrate112 above buriedlayer122 if buriedlayer122 is implanted. Alternatively, floatingbody124 may be epitaxially grown. Depending on how buriedlayer122 and floatingbody124 are formed, floatingbody124 may have the same doping assubstrate112 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.
• Insulating layers126 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulatinglayers126 insulatecell1450 from neighboringcells1450 whenmultiple cells1450 are joined in anarray1480 to make a memory device. The bottom of insulatinglayer126 may reside inside the buriedregion122 allowing buriedregion122 to be continuous as shown inFIG. 202A. Alternatively, the bottom of insulatinglayer126 may reside below the buriedregion22 as shown inFIG. 202B. This requires a shallower insulating layer128, which insulates the floatingbody region124, but allows the buriedlayer122 to be continuous in the perpendicular direction of the cross-sectional view shown inFIG. 202B. For simplicity, onlymemory cell1450 with continuousburied region122 in all directions will be shown from hereon.
• Abit line region116 having a second conductivity type, such as n-type, for example, is provided in floatingbody region124 and is exposed atsurface114.Bit line region116 is formed by an implantation process formed on the material making upsubstrate112, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region116.
• Asource line region118 having a second conductivity type, such as n-type, for example, is also provided in floatingbody region124 and is exposed atsurface114.Source line region118 is formed by an implantation process formed on the material making upsubstrate112, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region118.
• Memory cell1450 is asymmetric in that the area ofsource line region118 is larger than that ofbit line region116. The largersource line region118 results in a higher coupling between thesource line region118 and floatinggate160, compared to if the area of thesource line region118 is about the same as that of thebit line region116.
• A floatinggate160 is positioned in between thesource line region118 and the insulatinggap region168, and above the floatingbody region124. The floatinggate160 is insulated from floatingbody region124 by an insulatinglayer162. Insulatinglayer162 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The floatinggate160 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Aselect gate164 is positioned in between thebit line region116 and the insulatinggap region168, and above the floatingbody region124. Theselect gate164 is insulated from floatingbody region124 by an insulatinglayer166. Insulatinglayer166 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Theselect gate164 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Cell1450 is another example of single polysilicon floating gate memory cell because bothselect gate164 and floatinggate160 may be formed in a single polysilicon deposition step during fabrication process, along with the formation of logic transistors gate. The formation of thegap168 may require additional processing steps as the dimension of the gap is typically smaller than what can be resolved by lithography tools.
• Cell1450 includes several terminals: word line (WL) terminal170 electrically connected to selectgate164, bit line (BL) terminal174 electrically connected to bitline region116, source line (SL) terminal172 electrically connected to sourceline region118, buried well (BW) terminal176 electrically connected to buriedlayer122, andsubstrate terminal178 electrically connected tosubstrate112. There is no electrical connection to floatinggate160. As a result, floatinggate160 is floating and is used as the non-volatile storage region.
• FIG. 203 illustrates the equivalent circuit representation ofmemory cell1450. Inherent inmemory cell1450 are metal-oxide-semiconductor (MOS)transistor120ain series withMOS transistor120b, formed bybit line region116,select gate164, floatinggate160,source line region118, and floatingbody region124.Select gate164 and floatinggate160 control the channel region ofcell1450 underneath the respective gates. Also present inmemory cell1450 arebipolar devices130aand130b, formed by buriedwell region122, floatingbody region124, and bitline region116 orsource line region118, respectively.
• FIG. 204 illustrates anexemplary memory array1480 of memory cells1450 (four exemplary instances ofmemory cell1450 being labeled as1450a,1450b,1450cand1450d) arranged in rows and columns. In many, but not necessarily all, of the figures whereexemplary array1480 appears,representative memory cell1450awill be representative of a “selected”memory cell1450 when the operation being described has one (or more in some embodiments) selectedmemory cells1450. In such figures,representative memory cell1450bwill be representative of anunselected memory cell1450 sharing the same row as selectedrepresentative memory cell1450a,representative memory cell1450cwill be representative of anunselected memory cell1450 sharing the same column as selectedrepresentative memory cell1450a, andrepresentative memory cell1450dwill be representative of amemory cell1450 sharing neither a row or a column with selectedrepresentative memory cell1450a.
• Present inFIG. 204 areword lines170athrough170n, source lines172athrough172n,bit lines174athrough174p, buried wellterminals176athrough176n, andsubstrate terminal178. Each of the word lines170athrough170nandsource lines172athrough172nis associated with a single row ofmemory cells1450 and is coupled to theselect gate164 andsource line region118 of eachmemory cell1450 in that row, respectively. Each of thebit lines174athrough174pis associated with a single column ofmemory cells1450 and is coupled to thebit line region116 of eachmemory cell1450 in that column.
• Substrate112 is present at all locations underarray1480. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals178 may be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that whileexemplary array1480 is shown as a single continuous array inFIG. 204, that many other organizations and layouts are possible, For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray1480 may be broken into two or more sub-arrays, and/or control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed aroundexemplary array1480 or inserted between sub-arrays ofarray1480. Thus the exemplary embodiments, features, design options, etc., described are not limiting in any way.
• The operation ofmemory device1450 is similar to that ofmemory device1350 shown inFIG. 187. Atevent102, when power is first applied to the memory device, the memory device is placed in an initial state, where the nonvolatile memory portion of the device is set to a predetermined state. Atevent104, thememory device1450 operates in the volatile operational mode, where the state of thecell1450 is stored in the floatingbody124. During power shutdown, or when power is inadvertently lost, or any other event that discontinues or upsets power to thememory device1450, the content of the volatile memory is “shadowed” into the non-volatile memory portion atevent106. At this time, the memory device retains the stored data in the nonvolatile memory. Upon restoring power atevent108, the content of the nonvolatile memory is “restored” by transferring the content of the nonvolatile memory to the volatile memory, followed by resetting the memory device atevent110.
• In one embodiment, the non-volatile memory (e.g. the floating gate160) is initialized to have a positive charge atevent102. When power is applied tocell1450,cell1450 stores the memory information (i.e. data that is stored in memory) as charge in the floatingbody124 of thememory device1450. The presence of the electrical charge in the floatingbody124 modulates the current flow through the memory device1450 (from theBL terminal174 to the SL terminal172). The current flowing through thememory device1450 can be used to determine the state of thecell1450. Because the non-volatile memory element (e.g. the floating gate160) is initialized to have a positive charge, any cell current differences are attributed to the differences in charge of the floatingbody124.
• Several operations can be performed tomemory cell1450 during volatile mode: holding, read, write logic-1 and write logic-0 operations.
• FIG. 205 shows the holding operation onmemory array1480, which consists of a plurality ofmemory cells1450. The holding operation is performed by applying a positive back bias to theBW terminal176, and zero bias on theWL terminal170,SL terminal172,BL terminal174, and thesubstrate terminal178. The positive back bias applied to the buried layer region connected to the BW terminal will maintain the state of thememory cell1450 that it is connected to.
• From the equivalent circuit representation ofmemory cell1450 shown inFIG. 203, inherent in thememory cell1450 is n-p-nbipolar devices130aand130bformed by buried well region122 (the collector region), floating body124 (the base region), and bitline region116 or source line region118 (the emitter region), respectively.
• The principle of the holding operation forcell1450 is similar to that ofcell1350. If floatingbody124 is positively charged, a state corresponding to logic-1, thebipolar transistors130aand130bwill be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floatingbody region124, the electrons will be swept into the buried well region122 (connected to BW terminal176) due to the positive bias applied to the buriedwell region122. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theBW terminal176 while the resulting hot holes will subsequently flow into the floatingbody region124. This process restores the charge on floatingbody124 and will maintain the charge stored in the floatingbody region124 which will keep the n-p-nbipolar transistors130aand130bon for as long as a positive bias is applied to the buriedwell region122 throughBW terminal176.
• If floatingbody124 is neutrally charged (the voltage on floatingbody124 being equal to the voltage on groundedbit line region116 or source line region118), a state corresponding to logic-0, no current will flow through then-p-n transistors130aand130b. Thebipolar devices130aand130bwill remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
• In the holding operation described inFIG. 205, there is no individually selected memory cell. Rather cells are selected in rows by the buried wellterminals176athrough176nand may be selected as individual rows, as multiple rows, or as all of therows comprising array1480.
• In one embodiment the bias conditions for the holding operation formemory cell1450 are: 0 volts is applied toWL terminal170,SL terminal172,BL terminal174, andsubstrate terminal178, and a positive voltage like, for example, +1.2 volts is applied toBW terminal176. In other embodiments, different voltages may be applied to the various terminals ofmemory cell1450 as a matter of design choice and the exemplary voltages described are not limiting in any way.
• FIG. 206 illustrates a read operation performed on selectedmemory cell1450a. The read operation may be performed by applying the following bias conditions: a positive bias is applied to the selected WL terminal170a, a positive voltage is applied to the selected BL terminal174a, zero voltage is applied to theSL terminals172, a positive voltage is applied to theBW terminals176, and zero voltage is applied to thesubstrate terminal178.
• In one exemplary embodiment, about +1.2 volts is applied to the selected WL terminal170a, about 0.0 volts is applied to the selected SL terminal172a, about +0.4 volts is applied to the selectedbit line terminal174a, about +1.2 volts is applied to the selected buried well terminal176, and about 0.0 volts is applied tosubstrate terminal178. All unselectedword line terminals170bthrough170nhave 0.0 volts applied,bit line terminals174bthrough174phave 0.0 volts applied, theunselected SL terminals172bthrough172phave 0.0 volts applied, while theunselected BW terminals176bthrough176ncan be grounded or have +1.2 volts applied to maintain the states of theunselected cells1450, and 0.0 volts is applied to thesubstrate terminal178.FIG. 206 shows the bias conditions for the selectedrepresentative memory cell1450aand three unselectedrepresentative memory cells1450b,1450c, and1450dinmemory array1480, each of which has a unique bias condition. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
• If the floatingbody region124 of the selectedcell1450ais positively charged (i.e. thecell1450ais in logic-1 state), the threshold voltage of theMOS transistor120aand120bof selectedcell1450awill be lower (compared to if the floatingbody region124 is neutral), and a higher current will flow from thebit line region116 to thesource line region118 of the selectedcell1450a. Because the floatinggate160 is positively charged during volatile operation, the observed cell current difference between cells in logic-0 and logic-1 states will originate from the difference in the potential of the floatingbody124.
• For memory cells sharing the same row as the selected memory cell (e.g. cell1450b), both the BL and SL terminals are grounded and no current will flow through. These cells will be at the holding mode with a positive voltage applied to theBW terminal176.
• For memory cells sharing the same column as the selected memory cell (e.g. cell1450c), the zero voltage applied to the unselected WL terminal will turn off theMOS transistor120aof these cells. Consequently, no current will flow through. A smaller holding current will flow through these cells because of the smaller difference between theBW terminal176 and theBL terminal174. However, because write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body124 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell1450d), the WL, BL, and SL terminals are grounded. These cells will be at the holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody124 while memory cells in state logic-0 will remain in neutral state.
• A write logic-0 operation of anindividual memory cell1450 is now described with reference toFIGS. 207A through 207C. InFIG. 207A, a negative voltage bias is applied to the selected SL terminal172 (i.e.,172ainFIG. 207A), a zero voltage bias is applied toWL terminal170 andBL terminal174, zero or positive voltage is applied to the selectedBW terminal176 and zero voltage is applied to thesubstrate terminal178. Under these conditions, the p-n junction between floatingbody124 andsource line region118 of the selectedcell1450 is forward-biased, evacuating any holes from the floatingbody124. Because theSL terminal172 is shared amongmultiple memory cells1450, logic-0 will be written into allmemory cells1450 includingmemory cells1450aand1450bsharing thesame SL terminal172asimultaneously.
• In one particular non-limiting embodiment, about −1.2 volts is applied to the selectedsource line terminal172, about 0.0 volts is applied toword line terminal170 andbit line terminal174, about 0.0 volts or +1.2 volts is applied toBW terminal176, and about 0.0 volts is applied tosubstrate terminal178. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• InFIG. 207B, a negative voltage bias is applied to the selected BL terminal174 (i.e.,174ainFIG. 207B), a zero voltage bias is applied toWL terminal170 andSL terminal172, zero or positive voltage is applied to the selectedBW terminal176 and zero voltage is applied to thesubstrate terminal178. Under these conditions, the p-n junction between floatingbody124 andbit line region116 of the selectedcell1450 is forward-biased, evacuating any holes from the floatingbody124. Because theBL terminal174 is shared amongmultiple memory cells1450 inmemory array1480, logic-0 will be written into allmemory cells1450 includingmemory cells1450aand1450csharing the same BL terminal174asimultaneously.
• In one particular non-limiting embodiment, about −1.2 volts is applied to the selectedbit line terminal174, about 0.0 volts is applied toword line terminal170 andsource line terminal172, about 0.0 volts or +1.2 volts is applied toBW terminal176, and about 0.0 volts is applied tosubstrate terminal178. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• Both write logic-0 operations referred to above have a drawback that allmemory cells1450 sharing either the same SL terminal172 (the first type—row write logic-0) or thesame BL terminal174 will (the second type—column write logic-0) are written to simultaneously and as a result, do not allow writing logic-0 toindividual memory cells1450. To write arbitrary binary data todifferent memory cells1450, a write logic-0 operation is first performed on all the memory cells to be written followed by one or more write logic-1 operations on the bits that must be written to logic-1.
• A third type of write logic-0 operation that allows for individual bit writing is illustrated inFIG. 207C and can be performed onmemory cell1450 by applying a positive voltage toWL terminal170, a negative voltage to the selectedBL terminal174, zero voltage toSL terminal172, zero or positive voltage toBW terminal176, and zero voltage tosubstrate terminal178. Under these conditions, the floatingbody124 potential will increase through capacitive coupling from the positive voltage applied to the selectedWL terminal170. As a result of the floatingbody124 potential increase and the negative voltage applied to the selectedBL terminal174, the p-n junction between124 andbit line region116 is forward-biased, evacuating any holes from the floatingbody124.
• To reduce undesired write logic-0 disturb toother memory cells1450 in thememory array1480, the applied potential can be optimized as follows: if the floatingbody124 potential of state logic-1 is referred to as V_FB1, then the voltage applied to theWL terminal170 is configured to increase the floatingbody124 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal174. Additionally, either ground or a slightly positive voltage may also be applied to theBL terminals174 ofunselected memory cells1450 that do not share thesame BL terminal174 as the selectedmemory cell1450, while a negative voltage may also be applied to theWL terminals170 ofunselected memory cells1450 that do not share thesame WL terminal170 as the selectedmemory cell1450.
• As illustrated inFIG. 207C, the following bias conditions are applied to the selectedrepresentative memory cell1450ainexemplary memory array1480 to perform an individual write logic-0 operation exclusively inrepresentative memory cell1450a: a potential of about 0.0 volts to SL terminal172a, a potential of about −0.2 volts to BL terminal174a, a potential of about +1.2 volts is applied toword line terminal170a, a potential of about +1.2 volts is applied to buried well terminal176a, and about 0.0 volts is applied tosubstrate terminal178. In the rest ofarray1480, about 0.0 volts is applied to unselected WL terminals (includingWL terminals170band170n), about 0.0 volts (or possibly a slightly higher positive voltage) is applied to unselected BL terminals174 (including BL terminal174band174p), about 0.0 volts is applied to unselected SL terminals172 (including SL terminal172band172n), and about +1.2 volts is applied to unselected BW terminals176 (including BW terminal176band176n). Persons of ordinary skill in the art will appreciate that the voltage levels inFIG. 207C are illustrative only and that different embodiments will have different voltage levels as a matter of design choice.
• A write logic-1 operation may be performed onmemory cell1450 through impact ionization as described, for example in “A New 1T DRAM Cell with Enhanced Floating Body Effect”, Lin and Chang, pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, (“Lin”) which is hereby incorporated herein, in its entirety, by reference thereto, or through a band-to-band tunneling mechanism (also known as Gate Induced Drain Leakage or GIDL), as described, for example with reference to Yoshida cited above. An example of a write logic-1 operation using the GIDL method is described in conjunction withFIG. 208A while an example of a write logic-1 operation using the impact ionization method is described in conjunction withFIG. 208B.
• InFIG. 208A, an example of the bias conditions of thearray1480 including selectedrepresentative memory cell1450aduring a band-to-band tunneling write logic-1 operation is shown. The negative bias applied to the WL terminal170aand the positive bias applied to the BL terminal174aresults in hole injection to the floatingbody124 of the selectedrepresentative memory cell1450a. The SL terminal172aand thesubstrate terminal178 are grounded during the write logic-1 operation while a positive bias is applied to the BW terminal176ato maintain holding operation to the unselected cells.
• The negative voltage on WL terminal170 couples the voltage potential of the floatingbody region124 inrepresentative memory cell1450adownward. This combined with the positive voltage on BL terminal174acreates a strong electric field between thebit line region116 and the floatingbody region124 in the proximity of gate160 (hence the “gate induced” portion of GIDL) in selectedrepresentative memory cell1450a. This bends the energy bands sharply upward near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current (hence the “drain leakage” portion of GIDL), while the holes are injected into floatingbody region124 and become the hole charge that creates the logic-1 state. This process is well known in the art and is illustrated in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above.
• In one particular non-limiting embodiment, about −1.2 volts is applied toword line terminal170a, about +1.2 volts is applied tobit line terminal174a, about 0.0 volts is applied to sourceline terminal172a, about 0.0 volts or +1.2 volts is applied toBW terminal176, and about 0.0 volts is applied tosubstrate terminal178. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 208B shows a write logic-1 operation using the impact ionization method. In this case, both thegate160 andbit line116 of thememory cell1450 to be written are biased at a positive voltage. This causes impact ionization current to flow charging the floatingbody124 to the logic-1 state regardless of the data originally stored in the cell.
• In the exemplary embodiment shown inFIG. 208B, the selectedword line terminal170ais biased at about +1.2V while the unselectedword line terminals170bthrough170nare biased at about 0.0V, the selectedbit line terminal174ais also biased at about +1.2V while the unselectedbit line terminals174bthrough174pare biased at about 0.0V, the selectedsource line172ais biased at about 0.0V, the buried wellterminals176 are biased at about 0.0V or +1.2V (to maintain the states of the unselected cells), and thesubstrate terminal178 is biased at about 0.0V. These voltage bias levels are exemplary only and will vary from embodiment to embodiment and are thus in no way limiting.
• The following bias conditions to perform a shadowing operation are illustrated inFIG. 209: a positive voltage is applied to the selectedSL terminal172, a positive voltage is applied to the selectedWL terminal170, zero voltage is applied to the selectedBL terminal174, zero or positive voltage is applied to theBW terminal176, and zero voltage is applied to thesubstrate terminal178.
• In one particular non-limiting embodiment, about +6.0 volts is applied to thesource line terminal172, about +1.2 volts is applied toWL terminal170, about 0.0 volts is applied tobit line terminal174, about 0.0 volts or +1.2 volts is applied toBW terminal176, and about 0.0 volts is applied tosubstrate terminal178. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 210A shows a cross section of the memory cell when floatingbody124 is positively charged during a shadowing operation. When floatingbody124 has a positive charge/voltage, theMOS device120ais turned on. The surface potential under theMOS device120awill be equal to the smaller of the voltage applied to theBL terminal174 and the difference between the gate voltage applied to theWL terminal170 and the threshold voltage of theMOS device120a. The positive voltage applied to the source line118 (through the SL terminal172) will be capacitively coupled to the floatinggate160. As a result, the surface potential under theMOS device120bwill increase and depending on the positive charge stored in the floatinggate160, will be close to the potential applied to thesource line region118. Consequently, a strong lateral electric field will be developed around thegap region168. This lateral electric field will energize/accelerate electrons traveling from thebit line region116 to the source line region118 (both theMOS devices120aand120bare turned on) to a sufficient extent that they can “jump over” the oxide barrier between floatingbody124 and floatinggate160. A large vertical field—resulting from the potential difference between floatinggate160, which is due partly to the coupling from thesource line region118, and thesurface114—also exist. As a result, electrons enter floating gate160 (as indicated by the arrow into floatinggate160 inFIG. 210A). Accordingly, floatinggate160 becomes negatively charged by the shadowing process, when the volatile memory ofcell1450 is in logic-1 state (i.e., floatingbody124 is positively charged), as shown inFIG. 210A.
• FIG. 210B illustrates a cross section ofcell1450 during a shadowing process when floatingbody124 is neutral. When floatingbody124 is neutral, the threshold voltage of theMOS device120ais higher (compared to when the floatingbody124 is positively charged) and theMOS device120ais turned off. Therefore, no electrons flow through thecell1450. Accordingly, floatinggate160 retains its positive charge at the end of the shadowing process, when the volatile memory ofcell1450 is in logic-0 state (i.e., floatingbody124 is neutral), as shown inFIG. 210B.
• Upon the completion of the shadowing operation, the charge state of the floatinggate160 is complementary to that of the floatingbody124. Thus, if the floatingbody124 of thememory cell1450 has a positive charge in volatile memory, the floatinggate160 will become negatively charged by the shadowing process, whereas if the floatingbody124 of thememory cell1450 has a negative or neutral charge in volatile memory, the floatinggate layer160 will be positively charged at the end of the shadowing operation. The charges/states of the floatinggates160 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
• FIG. 211 describes a restore operation when power is restored tocell1450. The restore operation restores the state of thecell1450 from the floatinggate160 into floatingbody region124. Prior to the restore process, the floatingbodies124 are set to neutral state, which is the state of the floating bodies when power is removed from thememory device1450. To perform the restore process, the following bias conditions are applied: a positive voltage is applied to theSL terminal172, zero voltage is applied to theWL terminal170 andBL terminal174, zero or positive voltage is applied to theBW terminal176, and zero voltage is applied to thesubstrate terminal178.
• In one particular non-limiting embodiment, about +1.2 volts is applied to thesource line terminal172, about 0.0 volts is applied to theword line terminal170 andbit line terminal174, about 0.0 volts or +1.2 volts is applied toBW terminal176, and about 0.0 volts is applied tosubstrate terminal178. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. For example, a positive voltage can be applied tobit line terminal174 or a negative voltage can be applied toword line170 to ensure that no current flows through the channel region ofcell1450 during restore operation. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 212A illustrates a cross section ofcell1450 during a restore process when floatinggate160 is negatively charged. The negative charge on the floatinggate160 and the positive voltage onSL terminal172 create a strong electric field between thesource line region118 and the floatingbody region124 in the proximity of floatinggate160. This bends the energy band sharply upward near the gate and source line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floatingbody region124 and become the hole charge that creates the logic-1 state. This process is well known in the art as band-to-band tunneling or gate induced drain leakage (GIDL) mechanism and is illustrated in for example in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above. TheBL terminal174 is grounded or applied a positive voltage to prevent current to flow through the channel region ofcell1450.
• FIG. 212B illustrates a cross section ofcell1450 during a restore process when floatinggate160 is positively charged. The positive charge on the floatinggate160 and thesource line region118 do not result in strong electric field to drive hole injection into the floatingbody124. Consequently, the floatingbody124 will remain in neutral state.
• It can be seen that if floatinggate160 has a positive charge after shadowing is performed, the volatile memory of floatingbody124 will be restored to have a neutral charge (logic-0 state), but if the floatinggate160 has a negative charge, the volatile memory of floatingbody124 will be restored to have a positive charge (logic-1 state), thereby restoring the original state of the floatingbody124 prior to the shadowing operation. Note that this process occurs non-algorithmically, as the state of the floatinggate160 does not have to be read, interpreted, or otherwise measured to determine what state to restore the floatingbody124 to. Rather, the restoration process occurs automatically, driven by electrical potential differences. Accordingly, this process is orders of magnitude faster than one that requires algorithmic intervention.
• After restoring the memory cell(s)1450, the floating gate(s)160 is/are reset to a predetermined state, e.g., a positive state as illustrated inFIGS. 213A and 213B, so that each floatinggate160 has a known state prior to performing another shadowing operation. The reset process operates by the mechanism of band-to-band tunneling hole injection to the floating gate(s)160, as illustrated inFIG. 213A, or by electron tunneling from the floating gate(s)160 as illustrated inFIG. 213B.
• The reset mechanism illustrated inFIG. 213A follows a similar mechanism as the restore process. A negatively charged floatinggate160 will result in an electric field generating hot holes. The majority of the resulting hot holes are injected into the floatingbody124 and a smaller portion will be injected into the floatinggate160. A higher potential can be applied to theSL terminal172 to increase the speed of the reset operation if desired. The hole injection will only occur incells1450 with negatively charged floatinggate160. As a result, all floatinggates160 will be initialized to have a positive charge by the end of the reset process.
• In one particular non-limiting embodiment (seeFIG. 213A), about +3.0 volts is applied to thesource line terminal172, about 0.0 volts is applied toword line terminal170 andbit line terminal174, about 0.0 volts or +1.2 volts is applied toBW terminal176, and about 0.0 volts is applied tosubstrate terminal178. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way. The bias condition is similar to that of the restore operation. However, because the amount of holes injected into the floatinggate160 is smaller than the amount injected into the floatingbody124, the reset operation proceeds more slowly than the restore operation. A negative voltage can also be applied to the buried well terminal176 to ensure that no holes are accumulated inmemory cells1450 with positively charged floatinggate160, while a positive voltage can also be applied to thebit line terminal174 to prevent current to flow through the channel region ofcell1450.
• FIG. 213B illustrates a reset operation by means of electron tunneling from the floatinggate160 to theselect gate164. A positive voltage is applied to theWL terminal170, while zero voltage is applied to theBL terminal174 andSL terminal172, zero voltage or a positive voltage may be applied to theBW terminal176, and zero voltage is applied to thesubstrate terminal178. The positive voltage applied to the select gate164 (through the WL terminal170) will result in high electric field across theselect gate164 and the floatinggate160, resulting in electron tunneling from the floating gate(s)160 to the select gate(s)164.
• In one particular non-limiting embodiment (seeFIG. 213B), about +12.0 volts is applied to theWL terminal170, about 0.0 volts is applied to theBL terminal174,SL terminal172, andsubstrate terminal178, and 0.0 volts or +1.2 volts is applied to theBW terminal176. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• FIG. 214 shows another embodiment ofmemory cell1450. Here, theselect gate164 may have overlap (partially or complete) with the floatinggate160. This can result in, for example, a shorter effective channel length of theMOS device120a, which in turn increases the current that may flow through thecell1450. Because of the overlap, the shorter channel length can be obtained without resorting to patterning and etching a smaller geometry during the gate patterning process, for example the process steps shown inFIGS. 197M through 197O.
• FIG. 215A illustrates a cross-sectional view of another embodiment ofmemory cell1550 according to the present invention, which includes acontrol gate240.Memory cell1550 includes asubstrate212 of a first conductivity type such as p-type, for example.Substrate212 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention,substrate212 can be the bulk material of the semiconductor wafer. In other embodiments,substrate212 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, thesubstrate212 will usually be drawn as the semiconductor bulk material as it is inFIG. 215.
• A buriedlayer222 of a second conductivity type such as n-type, for example, is provided in thesubstrate212.Buried layer222 may be formed by an ion implantation process on the material ofsubstrate212. Alternatively, buriedlayer222 can also be grown epitaxially on top ofsubstrate212.
• A floatingbody region224 of the first conductivity type, such as p-type, for example, is bounded on top bybit line region216,source line region218, and insulatinglayers262 and266, on the sides by insulatinglayers226, and on the bottom by buriedlayer222. Floatingbody224 may be the portion of theoriginal substrate212 above buriedlayer222 if buriedlayer222 is implanted. Alternatively, floatingbody224 may be epitaxially grown. Depending on how buriedlayer222 and floatingbody224 are formed, floatingbody224 may have the same doping assubstrate212 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.
• Insulating layers226 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulatinglayers226 insulatecell1550 from neighboringcells1550 whenmultiple cells1550 are joined in anarray1580 to make a memory device. The bottom of insulatinglayer226 may reside inside the buriedregion222 allowing buriedregion222 to be continuous as shown inFIG. 215A. Alternatively, the bottom of insulatinglayer226 may reside below the buriedregion222 as shown inFIG. 215B. This requires a shallower insulatinglayer228, which insulates the floatingbody region224, but allows the buriedlayer222 to be continuous in the perpendicular direction of the cross-sectional view shown inFIG. 215B. For simplicity, onlymemory cell1550 with continuousburied region222 in all directions will be shown from hereon.
• Abit line region216 having a second conductivity type, such as n-type, for example, is provided in floatingbody region224 and is exposed atsurface214.Bit line region216 may be formed by an implantation process formed on the material making upsubstrate212, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region216.
• Asource line region218 having a second conductivity type, such as n-type, for example, is also provided in floatingbody region224 and is exposed atsurface214.Source line region218 may be formed by an implantation process formed on the material making upsubstrate212, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region218.
• Unlikememory cells1350 and1450,memory cell1550 is not necessarily asymmetric as a coupling to the floatinggate260 can be obtained through thecontrol gate240.
• A floatinggate260 is positioned in between thesource line region218 and the insulatinggap region268, and above the floatingbody region224. The floatinggate260 is insulated from floatingbody region224 by an insulatinglayer262. Insulatinglayer262 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The floatinggate260 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Aselect gate264 is positioned in between thebit line region216 and the insulatinggap region268, and above the floatingbody region224. Theselect gate264 is insulated from floatingbody region224 by an insulatinglayer266. Insulatinglayer266 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Theselect gate264 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Acontrol gate240 is positioned above floatinggate260 and insulated therefrom by insulatinglayer242 such that floatinggate260 is positioned between insulatinglayer262 andsurface214 underlying floatinggate260, and insulatinglayer242 andcontrol gate240 positioned above floatinggate260, as shown.Control gate240 is capacitively coupled to floatinggate260.Control gate240 is typically made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. The relationship between the floatinggate260 andcontrol gate240 is similar to that of a nonvolatile stacked gate floating gate/trapping layer memory cell. The floatinggate260 functions to store non-volatile memory data and thecontrol gate240 is used for memory cell selection.
• Cell1550 includes several terminals: word line (WL) terminal270 electrically connected to selectgate264, bit line (BL) terminal274 electrically connected to bitline region216, source line (SL) terminal272 electrically connected to sourceline region218, control gate (CG) terminal280 electrically connected to controlgate240, buried well (BW) terminal276 electrically connected to buriedlayer222, andsubstrate terminal278 electrically connected tosubstrate212.
• FIG. 216 illustrates the equivalent circuit representation ofmemory cell1550. Inherent inmemory cell1550 are metal-oxide-semiconductor (MOS)transistor220ain series withMOS transistor220b, formed bybit line region216,select gate264, floatinggate260 andcontrol gate240,source line region218, and floatingbody region224.Select gate264 controls the channel region ofcell1550 underneath the select gate while floatinggate260 andcontrol gate240 control the channel region underneath the floatinggate260. Also present inmemory cell1550 arebipolar devices230aand230b, formed by buriedwell region222, floatingbody region224, and bitline region216 orsource line region218, respectively. The coupling of thesource line region218 to the floating gate260 (typically shown by the extension of the floatinggate260 into the source line region218) is not shown inFIG. 216 as thecell1550 may or may not require additional coupling to the floatinggate260 for its operation. For drawing simplicity, the floatinggate260 extension into thesource line region218 is not drawn.
• FIG. 217 illustrates anexemplary memory array1580 of memory cells1550 (four exemplary instances ofmemory cell1550 being labeled as1550a,1550b,1550cand1550d) arranged in rows and columns. In many, but not necessarily all, of the figures whereexemplary array1580 appears,representative memory cell1550awill be representative of a “selected”memory cell1550 when the operation being described has one (or more in some embodiments) selectedmemory cells1550. In such figures,representative memory cell1550bwill be representative of anunselected memory cell1550 sharing the same row as selectedrepresentative memory cell1550a,representative memory cell1550cwill be representative of anunselected memory cell1550 sharing the same column as selectedrepresentative memory cell1550a, andrepresentative memory cell1550dwill be representative of amemory cell1550 sharing neither a row or a column with selectedrepresentative memory cell1550a.
• Present inFIG. 217 areword line terminals270athrough270n,source line terminals272athrough272n,bit line terminals274athrough274p,control gate terminals280athrough280n, buried wellterminals276athrough276n, andsubstrate terminal278. Each of theword line terminals270athrough270n,source line terminals272athrough272n, and controlgate terminals280athrough280nare associated with a single row ofmemory cells1550 and are coupled to theselect gate264,source line region218, and controlgates240 of eachmemory cell1550 in that row, respectively. Each of thebit line terminals274athrough274pis associated with a single column ofmemory cells1550 and is coupled to thebit line region216 of eachmemory cell1550 in that column, respectively.
• Substrate212 is present at all locations underarray1580. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals278 will be present in one or more locations as a matter of design choice. Such skilled persons will also appreciate that whileexemplary array1580 is shown as a single continuous array inFIG. 217, that many other organizations and layouts are possible. For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray1580 may be broken into two or more sub-arrays, and/or control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed aroundexemplary array1580 or inserted between sub-arrays ofarray1580. Thus the exemplary embodiments, features, design options, etc., described are not limiting.
• One embodiment ofmemory device1550 operation is similar to that ofmemory device1350 shown inFIG. 187. Atevent102, when power is first applied to the memory device, the memory device is placed in an initial state, where the nonvolatile memory portion of the device is set to a predetermined state. Atevent104, thememory device1550 operates in the volatile operational mode, where the state of thecell1550 is stored in the floatingbody224. During power shutdown, or when power is inadvertently lost, or any other event that discontinues or upsets power to thememory device1550, the content of the volatile memory is “shadowed” into the non-volatile memory portion atevent106. At this time, the memory device retains the stored data in the nonvolatile memory. Upon restoring power atevent108, the content of the nonvolatile memory is “restored” by transferring the content of the nonvolatile memory to the volatile memory, followed by resetting the memory device atevent110.
• In one embodiment, the non-volatile memory (e.g. the floating gate260) is initialized to have a positive charge atevent102. When power is applied tocell1550,cell1550 stores the memory information (i.e. data that is stored in memory) as charge in the floatingbody224 of thememory device1550. The presence of the electrical charge in the floatingbody224 modulates the current flow through the memory device1550 (from theBL terminal274 to the SL terminal272). The current flowing through thememory device1550 can be used to determine the state of thecell1550. Because the non-volatile memory element (e.g. the floating gate260) is initialized to have a positive charge, any cell current differences are attributed to the differences in charge of the floatingbody224.
• Several operations can be performed tomemory cell1550 during volatile mode: holding, read, write logic-1 and write logic-0 operations.
• FIG. 218 shows a holding operation onmemory array1580, which comprises a plurality ofmemory cells1550. The holding operation is performed by applying a positive back bias to theBW terminal276, and zero bias on theWL terminal270,SL terminal272,BL terminal274,CG terminal280, and thesubstrate terminal278. The positive back bias applied to the buried layer region connected to the BW terminal will maintain the state of thememory cell1550 that it is connected to.
• From the equivalent circuit representation ofmemory cell1550 shown inFIG. 216, inherent in thememory cell1550 is n-p-nbipolar devices230aand230bformed by buried well region222 (the collector region), floating body224 (the base region), and bitline region216 or source line region218 (the emitter region), respectively.
• The principle of the holding operation forcell1550 is similar to that ofcell1350. If floatingbody224 is positively charged, a state corresponding to logic-1, thebipolar transistors230aand230bwill be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floatingbody region224, the electrons will be swept into the buried well region222 (connected to BW terminal276) due to the positive bias applied to the buriedwell region222. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theBW terminal276 while the resulting hot holes will subsequently flow into the floatingbody region224. This process restores the charge on floatingbody224 and will maintain the charge stored in the floatingbody region224 which will keep the n-p-nbipolar transistors230aand230bon for as long as a positive bias is applied to the buriedwell region222 throughBW terminal276.
• If floatingbody224 is neutrally charged (the voltage on floatingbody224 being equal to the voltage on groundedbit line region216 or source line region218), a state corresponding to logic-0, no current will flow through then-p-n transistors230aand230b. Thebipolar devices230aand230bwill remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
• In the holding operation described inFIG. 218, there is no individually selected memory cell. Rather cells are selected in rows by the buried wellterminals276athrough276nand may be selected as individual rows, as multiple rows, or as all of therows comprising array1580.
• In one embodiment the bias conditions for the holding operation onmemory cell1550 is: 0 volts is applied toWL terminal270,SL terminal272,BL terminal274,CG terminal280, andsubstrate terminal278, and a positive voltage like, for example, +1.2 volts is applied toBW terminal276. In other embodiments, different voltages may be applied to the various terminals ofmemory cell1550 as a matter of design choice and the exemplary voltages described are not limiting.
• FIG. 219 illustrates a read operation performed on selectedmemory cell1550a. The read operation may be performed by applying the following bias condition: A positive bias is applied to the selected WL terminal270a, a positive voltage is applied to the selected BL terminal274a, zero voltage is applied toCG terminals280, zero voltage is applied to theSL terminals272, a positive voltage is applied to theBW terminals276, and zero voltage is applied to thesubstrate terminal278.
• In one exemplary embodiment, about +1.2 volts is applied to the selected WL terminal270a, about 0.0 volts is applied to the selected SL terminal272a, about +0.4 volts is applied to the selectedbit line terminal274a, about 0.0 volts is applied to the selected CG terminal280a, about +1.2 volts is applied to the selected buried well terminal276, and about 0.0 volts is applied tosubstrate terminal278. All unselectedword line terminals270bthrough270nhave 0.0 volts applied,bit line terminals274bthrough274phave 0.0 volts applied, theunselected SL terminals272bthrough272phave 0.0 volts applied, theunselected CG terminals280bthrough280nhave 0.0 volts applied, while theunselected BW terminals276bthrough276ncan be grounded or have +1.2 volts applied to maintain the states of theunselected cells1550, and 0.0 volts is applied to thesubstrate terminal278.FIG. 219 shows the bias conditions for the selectedrepresentative memory cell1550aand three unselectedrepresentative memory cells1550b,1550c, and1550dinmemory array1580, each of which has a unique bias condition. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
• If the floatingbody region224 of the selectedcell1550ais positively charged (i.e. thecell1550ais in logic-1 state), the threshold voltage of theMOS transistor220aand220bof selectedcell1550awill be lower (compared to if the floatingbody region224 is neutral), and a higher current will flow from thebit line region216 to thesource line region218 of the selectedcell1550a. Because the floatinggate260 is positively charged during volatile operation, the observed cell current difference between cells in logic-0 and logic-1 states will originate from the difference in the potential of the floatingbody224.
• For memory cells sharing the same row as the selected memory cell (e.g. cell1550b), both the BL and SL terminals are grounded and no current will flow through. These cells will be at the holding mode with a positive voltage applied to theBW terminal276.
• For memory cells sharing the same column as the selected memory cell (e.g. cell1550c), the zero voltage applied to the unselected WL terminal will turn off theMOS transistor220aof these cells. Consequently, no current will flow through. A smaller holding current will flow through these cells because of the smaller difference between theBW terminal276 and theBL terminal274. However, because the write operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body224 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
• For memory cells sharing neither the same row nor the same column as the selected memory cell (e.g. cell1550d), the WL, CG, BL, and SL terminals are grounded. These cells will be at the holding mode, where memory cells in state logic-1 will maintain the charge in floatingbody224 while memory cells in state logic-0 will remain in neutral state.
• A write logic-0 operation of anindividual memory cell1550 is now described with reference toFIGS. 220A, 220B and 221. InFIG. 220A, a negative voltage bias is applied to the selectedSL terminal272, a zero voltage bias is applied toWL terminal270,BL terminal274,CG terminal280, zero or positive voltage is applied to the selectedBW terminal276 and zero voltage is applied to thesubstrate terminal278. Under these conditions, the p-n junction between floatingbody224 andsource line region218 of the selectedcell1550 is forward-biased, evacuating any holes from the floatingbody224. Because the selectedSL terminal272 is shared amongmultiple memory cells1550, logic-0 will be written into allmemory cells1550 includingmemory cells1550aand1550bsharing thesame SL terminal272asimultaneously.
• In one particular non-limiting embodiment, about −1.2 volts is applied to sourceline terminal272a, about 0.0 volts is applied toword line terminal270,bit line terminal274,control gate terminal280, about 0.0 volts or +1.2 volts is applied toBW terminal276, and about 0.0 volts is applied tosubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• InFIG. 220B, a negative voltage bias is applied to the selectedBL terminal274, a zero voltage bias is applied toWL terminal270,SL terminal272, andCG terminal280, zero or positive voltage is applied to the selectedBW terminal276 and zero voltage is applied to thesubstrate terminal278. Under these conditions, the p-n junction between floatingbody224 andbit line region216 of the selectedcell1550 is forward-biased, evacuating any holes from the floatingbody224. Because the selectedBL terminal274 is shared amongmultiple memory cells1550 inmemory array1580, logic-0 will be written into allmemory cells1550 includingmemory cells1550aand1550csharing the same BL terminal174asimultaneously.
• In one particular non-limiting embodiment, about −1.2 volts is applied tobit line terminal274a, about 0.0 volts is applied toword line terminal270,source line terminal272, and controlgate terminal280, about 0.0 volts or +1.2 volts is applied toBW terminal276, and about 0.0 volts is applied tosubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• Both write logic-0 operations referred to above have a drawback that allmemory cells1550 sharing either the same SL terminal272 (the first type—row write logic-0) or thesame BL terminal274 will (the second type—column write logic-0) are written to simultaneously and as a result, do not allow writing logic-0 toindividual memory cells1550. To write arbitrary binary data todifferent memory cells1550, a write logic-0 operation is first performed on all the memory cells to be written followed by one or more write logic-1 operations on the bits that must be written to logic-1.
• A third type of write logic-0 operation that allows for individual bit writing is illustrated inFIG. 221 and can be performed onmemory cell1550 by applying a positive voltage toWL terminal270, a negative voltage toBL terminal274, zero voltage toSL terminal272, zero voltage toCG terminal280, zero or positive voltage toBW terminal276, and zero voltage tosubstrate terminal278. Under these conditions, the floatingbody224 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal270. As a result of the floatingbody224 potential increase and the negative voltage applied to theBL terminal274, the p-n junction between224 andbit line region216 is forward-biased, evacuating any holes from the floatingbody224.
• To reduce undesired write logic-0 disturb toother memory cells1550 in thememory array1580, the applied potential can be optimized as follows: if the floatingbody224 potential of state logic-1 is referred to as V_FB1, then the voltage applied to theWL terminal270 is configured to increase the floatingbody224 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal274. Additionally, either ground or a slightly positive voltage may also be applied to theBL terminals274 ofunselected memory cells1550 that do not share thesame BL terminal274 as the selectedmemory cell1550, while a negative voltage may also be applied to theWL terminals270 ofunselected memory cells1550 that do not share thesame WL terminal270 as the selectedmemory cell1550.
• As illustrated inFIG. 221, the following bias conditions are applied to the selectedrepresentative memory cell1550ainexemplary memory array1580 to perform an individual write logic-0 operation exclusively inrepresentative memory cell1550a: a potential of about 0.0 volts to SL terminal272a, a potential of about −0.2 volts to BL terminal274a, a potential of about +1.2 volts is applied toword line terminal270a, a potential of about 0.0 volts is applied to controlgate terminal280a, a potential of about +1.2 volts is applied to buried well terminal276a, and about 0.0 volts is applied tosubstrate terminal278. In the rest ofarray1580, about 0.0 volts is applied to unselected WL terminals (includingWL terminals270band270n), about 0.0 volts (or possibly a slightly higher positive voltage) is applied to unselected BL terminals274 (including BL terminal274band274p), about 0.0 volts is applied to unselected SL terminals272 (including SL terminal272band272n), about 0.0 volts is applied to unselected CG terminals280 (including CG terminal280band280n), and about +1.2 volts is applied to unselected BW terminals276 (including BW terminal276band276n). Persons of ordinary skill in the art will appreciate that the voltage levels inFIG. 221 are illustrative only and that different embodiments will have different voltage levels as a matter of design choice.
• A write logic-1 operation may be performed onmemory cell1550 through impact ionization as described, for example, with reference to Lin cited above, or through a band-to-band tunneling mechanism (also known as Gate Induced Drain Leakage or GIDL), as described, for example with reference to Yoshida cited above. An example of a write logic-1 operation using the GIDL method is described in conjunction withFIG. 222A while an example of a write logic-1 operation using the impact ionization method is described in conjunction withFIG. 222B.
• InFIG. 222A, an example of the bias conditions of thearray1580 including selectedrepresentative memory cell1550aduring a band-to-band tunneling write logic-1 operation is shown. The negative bias applied to the WL terminal270aand the positive bias applied to the BL terminal274aresults in hole injection to the floatingbody224 of the selectedrepresentative memory cell1550a. The SL terminal272a, the CG terminal280a, and thesubstrate terminal278 are grounded during the write logic-1 operation while a positive bias is applied to the BW terminal276ato maintain holding operation to the unselected cells.
• The negative voltage on WL terminal270acouples the voltage potential of the floatingbody region224 inrepresentative memory cell1550adownward. This combined with the positive voltage on BL terminal274acreates a strong electric field between thebit line region216 and the floatingbody region224 in the proximity of select gate264 (hence the “gate induced” portion of GIDL) in selectedrepresentative memory cell1550a. This bends the energy bands sharply upward near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current (hence the “drain leakage” portion of GIDL), while the holes are injected into floatingbody region224 and become the hole charge that creates the logic-1 state. This process is well known in the art and is illustrated in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above.
• In one particular non-limiting embodiment, about −1.2 volts is applied toword line terminal270a, about +1.2 volts is applied tobit line terminal274a, about 0.0 volts is applied to sourceline terminal272aandcontrol gate terminal280a, about 0.0 volts or +1.2 volts is applied to BW terminal276a, and about 0.0 volts is applied tosubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• FIG. 222B shows a write logic-1 operation using the impact ionization method. In this case, both theselect gate264 andbit line216 of thememory cell1550 to be written are biased at a positive voltage. This causes impact ionization current to flow charging the floatingbody224 to the logic-1 state regardless of the data originally stored in the cell.
• In the exemplary embodiment shown inFIG. 222B, the selectedword line terminal270ais biased at about +1.2V while the unselectedword line terminals270bthrough270nare biased at about 0.0V, the selectedbit line terminal274ais also biased at about +1.2V while the unselectedbit line terminals274bthrough274pare biased at about 0.0V, the selectedsource line272ais biased at about 0.0V, while the unselectedsource line terminals272bthrough272nare biased at about 0.0V, all of thecontrol gate terminals280 are biased at 0.0V, the buried wellterminals276 are biased at about 0.0V or +1.2V (to maintain the states of the unselected cells), and thesubstrate terminal278 is biased at about 0.0V. These voltage bias levels are exemplary only and will vary from embodiment to embodiment and are thus in no way limiting.
• An embodiment of a shadowing operation performed oncell1550 is illustrated inFIG. 223A: a positive voltage is applied to the SL terminal272a, a positive voltage is applied to the WL terminal270a, zero voltage is applied to the BL terminal274a, a positive voltage is applied to the CG terminal280a, zero or positive voltage is applied to the BW terminal276a, and zero voltage is applied to thesubstrate terminal278.
• In one particular non-limiting embodiment, about +6.0 volts is applied to thesource line terminal272, about +1.2 volts is applied toword line terminal270, about 0.0 volts is applied tobit line terminal274, about +6.0 volts is applied to controlgate terminal280, about 0.0 volts or +1.2 volts is applied toBW terminal276, and about 0.0 volts is applied tosubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• When floatingbody224 has a positive charge/voltage, theMOS device220ais turned on. The surface potential under theMOS device220awill be equal to the smaller of the voltage applied to theBL terminal274 or the difference between the gate voltage applied to theWL terminal270 and the threshold voltage of theMOS device220a. The positive voltage applied to the control gate240 (through the CG terminal280) will be capacitively coupled to the floatinggate260. As a result, the surface potential under theMOS device220bwill increase and depending on the positive charge stored in the floatinggate260, will be close to the potential applied to thesource line region218. Consequently, a strong lateral electric field will be developed around thegap region268. This lateral electric field will energize/accelerate electrons traveling from thebit line region216 to the source line region218 (both theMOS devices220aand220bare turned on) to a sufficient extent that they can “jump over” the oxide barrier between floatingbody224 and floatinggate260. A large vertical field—resulting from the potential difference between floatinggate260, which partly is due to the coupling from thecontrol gate240 and thesource line region218, and thesurface214—also exists. As a result, electrons enter floatinggate260. Accordingly, floatinggate260 becomes negatively charged by the shadowing process, when the volatile memory ofcell1550 is in logic-1 state (i.e., floatingbody224 is positively charged).
• When floatingbody224 is neutral, the threshold voltage of theMOS device220ais higher (compared to when the floatingbody224 is positively charged) and theMOS device220ais turned off. Therefore, no electrons flow through thecell1550. Accordingly, floatinggate260 retains its positive charge at the end of the shadowing process, when the volatile memory ofcell1550 is in logic-0 state (i.e., floatingbody224 is neutral).
• Upon the completion of the shadowing operation, the charge state of the floatinggate260 is complementary to that of the floatingbody224. Thus, if the floatingbody224 of thememory cell1550 has a positive charge in volatile memory, the floatinggate260 will become negatively charged by the shadowing process, whereas if the floatingbody224 of thememory cell1550 has a negative or neutral charge in volatile memory, the floatinggate layer260 will be positively charged at the end of the shadowing operation. The charges/states of the floatinggates260 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
• Another embodiment of a shadowing operation performed oncell1550 is illustrated inFIG. 223B: a positive voltage is applied to theCG terminals280, a positive voltage is applied to theWL terminals270, zero voltage is applied to theBL terminals274, zero or positive voltage is applied to theBW terminals276, zero voltage is applied to thesubstrate terminal278, while theSL terminals272 are left floating.
• In one particular non-limiting embodiment, about +12.0 volts is applied to thecontrol gate terminal280, about +1.2 volts is applied toword line terminal270, about 0.0 volts is applied tobit line terminal274, about 0.0 volts or +1.2 volts is applied toBW terminal276, about 0.0 volts is applied tosubstrate terminal278, and thesource line terminal272 is left floating. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• When floatingbody224 has a positive charge/voltage, theMOS device220ais turned on and will pass the zero voltage applied to theBL terminal274. If the bias applied to thecontrol gate240 is large enough, a fringing electric field—for example as described in “A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40 nm Technology and Beyond”, K-T. Park et al., pp. 19-20, Digest of Technical Papers, 2006 Symposium on VLSI Technology, 2006 (which is hereby incorporated herein, in its entirety, by reference thereto, and which henceforth is referred to as “Park”)—will create an inversion region in thegap region268. As a result, the zero voltage applied to theBL terminal274 will also be passed to the channel region of theMOS device220bunderneath the floatinggate260. Due to the coupling from thecontrol gate240 to the floatinggate260, this results in a strong vertical electric field between the floatinggate260 and the channel region underneath it. The strong vertical electric field will induce electron tunneling from the channel region to the floatinggate260. Accordingly, floatinggate260 becomes negatively charged by the shadowing process, when the volatile memory ofcell1550 is in logic-1 state (i.e., floatingbody224 is positively charged).
• When floatingbody224 is neutral, the threshold voltage of theMOS device220ais higher (compared to when the floatingbody224 is positively charged) and theMOS device220ais turned off. As a result, the channel region underneath the floatinggate260 will be floating. The positive voltage applied to thecontrol gate240 will in turn increase the channel potential underneath the floatinggate260, and consequently the electric field build-up is not sufficient to result in electron tunneling to the floatinggate260. Accordingly, floatinggate260 retains its positive charge at the end of the shadowing process, when the volatile memory ofcell1550 is in logic-0 state (i.e., floatingbody224 is neutral).
• Upon the completion of the shadowing operation, the charge state of the floatinggate260 is complementary to that of the floatingbody224. Thus, if the floatingbody224 of thememory cell1550 has a positive charge in volatile memory, the floatinggate260 will become negatively charged by the shadowing process, whereas if the floatingbody224 of thememory cell1550 has a negative or neutral charge in volatile memory, the floatinggate layer260 will be positively charged at the end of the shadowing operation. The charges/states of the floatinggates260 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
• FIG. 224 illustrates a restore operation carried out when power is restored tocell1550. The restore operation restores the state of thecell1550 from the floatinggate260 into floatingbody region224. Prior to the restore process, the floatingbodies224 are set to neutral state, which is the state of the floating bodies when power is removed from thememory device1580. To perform the restore process, the following bias conditions are applied: a positive voltage is applied to theSL terminals272, zero voltage is applied to theWL terminals270,CG terminals280, andBL terminals274, zero or positive voltage is applied to theBW terminals276, and zero voltage is applied to thesubstrate terminal278.
• In one particular non-limiting embodiment, about +1.2 volts is applied to thesource line terminals272, about 0.0 volts is applied to theword line terminals270,control gate terminals280, and bitline terminals274, about 0.0 volts or +1.2 volts is applied toBW terminals276, and about 0.0 volts is applied tosubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. For example, a positive voltage can be applied tobit line terminal274 or a negative voltage can be applied toword line270 to ensure that no current flows through the channel region ofcell1550 during restore operation. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• When floatinggate260 is negatively charged, the negative charge on the floatinggate260 and the positive voltage onSL terminal272 create a strong electric field between thesource line region218 and the floatingbody region224 in the proximity of floatinggate260. This bends the energy band sharply upward near the gate and source line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floatingbody region224 and become the hole charge that creates the logic-1 state. This process is well known in the art as band-to-band tunneling or gate induced drain leakage (GIDL) mechanism and is illustrated in for example in Yoshida (specifically FIGS. 2 and 6 on page 3 and FIG. 9 on page 4) cited above. TheBL terminal274 is grounded or a positive voltage is applied thereto to prevent current to flow through the channel region ofcell1550.
• When floatinggate260 is positively charged, the positive charge on the floatinggate260 and thesource line region218 do not result in strong electric field to drive hole injection into the floatingbody224. Consequently, the floatingbody224 will remain in neutral state.
• It can be seen that if floatinggate260 has a positive charge after shadowing is performed, the volatile memory of floatingbody224 will be restored to have a neutral charge (logic-0 state), but if the floatinggate260 has a negative charge, the volatile memory of floatingbody224 will be restored to have a positive charge (logic-1 state), thereby restoring the original state of the floatingbody224 prior to the shadowing operation. Note that this process occurs non-algorithmically, as the state of the floatinggate260 does not have to be read, interpreted, or otherwise measured to determine what state to restore the floatingbody224 to. Rather, the restoration process occurs automatically, driven by electrical potential differences. Accordingly, this process is orders of magnitude faster than one that requires algorithmic intervention.
• After restoring the memory cell(s)1550, the floating gate(s)260 is/are reset to a predetermined state, e.g., a positive state as illustrated inFIGS. 225A and 225B, so that each floatinggate260 has a known state prior to performing another shadowing operation. The reset process operates by the mechanism of band-to-band tunneling hole injection to the floating gate(s)260, as illustrated inFIG. 225A, or by electron tunneling from the floating gate(s)260 as illustrated inFIG. 225B.
• The reset mechanism illustrated inFIG. 225A follows a similar mechanism as the restore process. A negatively charged floatinggate260 will result in an electric field generating hot holes. The majority of the resulting hot holes are injected into the floatingbody224 and a smaller portion will be injected into the floatinggate260. A higher potential can be applied to theSL terminal272 to increase the speed of the reset operation if desired. The hole injection will only occur incells1550 with negatively charged floatinggate260. As a result, all floatinggates260 will be initialized to have a positive charge by the end of the reset process.
• In one particular non-limiting embodiment, about +3.0 volts is applied to thesource line terminal272, about 0.0 volts is applied toword line terminal270,control gate terminal280, and bitline terminal274, about 0.0 volts or +1.2 volts is applied toBW terminal276, and about 0.0 volts is applied tosubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way. The bias condition is similar to that of the restore operation. However, because the amount of holes injected into the floatinggate260 is smaller than the amount injected into the floatingbody224, the reset operation proceeds more slowly than the restore operation. A negative voltage can also be applied to the buried well terminal276 to ensure that no holes are accumulated inmemory cells1550 with positively charged floatinggate260, while a positive voltage can also be applied to thebit line terminal274 to prevent current to flow through the channel region ofcell1550.
• FIG. 225B illustrates a reset operation by means of electron tunneling from the floatinggate260 to theselect gate264. A positive voltage is applied to theWL terminal270, a negative voltage is applied to theCG terminal280, while zero voltage is applied to theBL terminal274,SL terminal272 is left floating, zero voltage or a positive voltage may be applied to theBW terminal276, and zero voltage is applied to thesubstrate terminal278. The positive voltage applied to the select gate264 (through the WL terminal270) and the negative voltage applied to the control gate240 (through the CG terminal280) will result in high electric field across theselect gate264 and the floatinggate260, resulting in electron tunneling from the floating gate(s)260 to the select gate(s)264.
• In one particular non-limiting embodiment, about +1.2 volts is applied to theWL terminal270, about −12.0 volts is applied to theCG terminal280, about 0.0 volts is applied to theBL terminal274,SL terminal272 is left floating, about 0.0 volts or +1.2 volts is applied to theBW terminal276, and about 0.0 volts is applied to thesubstrate terminal278. These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. For example, theBL terminal274 may also be left floating. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
• An alternative embodiment of thememory device1550,operation200 is illustrated inFIG. 226. Thecontrol gate240 of thecell1550 can be used to “shield” the charge stored in the floatinggate260. As a result, thevolatile operation104 can be performed without first resetting the state of the floatinggate260. During power shutdown, areset operation110 is first performed, followed by the shadowing operation to transfer the state of the floatingbody224 to the floatinggate260. Upon restoring power atevent108, the content of the nonvolatile memory is “restored” to the volatile memory, and the memory device can immediately be placed into thevolatile memory operation104. This reduces the “start-up” time of thememory device1550, i.e. the time between power up and when thememory device1550 is available for volatile memory operation, by moving thereset operation110 to the power shutdown operation.
• To “shield” the charge stored in the floatinggate260, a positive bias is applied to the control gate240 (through the CG terminal280) during volatile mode operations, for example during the volatile read operation and write logic-1 operation using the impact ionization mechanism.
• FIG. 227 illustrates an example of bias conditions for an alternative read operation performed on selectedmemory cell1550a. The read operation may be performed by applying the following bias conditions: a positive voltage is applied to the selected WL terminal270a, a positive voltage is applied to the selected BL terminal274a, a positive voltage is applied to CG terminal280a, zero voltage is applied to theSL terminals272, a positive voltage is applied to theBW terminals276, and zero voltage is applied to thesubstrate terminal278.
• In one exemplary embodiment, about +1.2 volts is applied to the selected WL terminal270a, about 0.0 volts is applied to the selected SL terminal272a, about +0.4 volts is applied to the selectedbit line terminal274a, about +5.0 volts is applied to the selected CG terminal280a, about +1.2 volts is applied to the selected buried well terminal276, and about 0.0 volts is applied tosubstrate terminal278. All unselectedword line terminals270bthrough270nhave 0.0 volts applied,bit line terminals274bthrough274phave 0.0 volts applied, theunselected SL terminals272bthrough272phave 0.0 volts applied, theunselected CG terminals280bthrough280nhave 0.0 volts applied, while theunselected BW terminals276bthrough276ncan be grounded or have +1.2 volts applied to maintain the states of theunselected cells1550, and 0.0 volts is applied to thesubstrate terminal278. Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
• The positive voltage applied on the selectedCG terminal280 will create an inversion region underneath the floatinggate260, regardless of the charge stored in the floatinggate260. As a result, theMOS device220bwill be on, and thememory cell1550 conductance will be determined by theMOS device220a. The threshold voltage of theMOS device220awill in turn be modulated by the charge stored in the floatingbody224. A positively charged floatingbody224 will result in a lower threshold voltage of theMOS device220acompared to if the floating body is neutral.
• FIG. 228 shows an alternative write logic-1 operation using the impact ionization method. In this case, a positive bias is applied to the control gate240 (through the CG terminal280). This causes impact ionization current to flow charging the floatingbody224 to the logic-1 state regardless of the stored in the floatinggate260.
• In the exemplary embodiment shown inFIG. 228, the selectedword line terminal270ais biased at about +1.2V while the unselectedword line terminals270bthrough270nare biased at about 0.0V, the selectedbit line terminal274ais also biased at about +1.2V while the unselectedbit line terminals274bthrough274pare biased at about 0.0V, the selectedsource line272aandunselected source lines272bthrough272nare each biased at about 0.0V, thecontrol gate terminals280ais biased at +5.0V while the unselectedcontrol gate terminals280bthrough280nare biased at about 0.0V, the buried wellterminals276 are biased at about 0.0V or +1.2V (to maintain the states of the unselected cells), and thesubstrate terminal278 is biased at about 0.0V. These voltage bias levels are exemplary only and may vary from embodiment to embodiment and are thus not limiting.
• Other volatile mode operations performed onmemory cell1550 are relatively independent of the charge stored on floatinggate260. For example, the write logic-0 operations largely depends on the potential difference between the floatingbody224 and the bit line region216 (or the source line region218). In these operations, the control gate may be grounded, or a positive bias may also be applied similar to the read and write logic-1 operations described inFIGS. 227 and 228, respectively.
• In another embodiment ofmemory cell1550, alternative non-volatile storage material can be used. The descriptions above use floating gate polysilicon as the non-volatile storage material. Charge trapping material, for example made of silicon nanocrystal or silicon nitride, may also be used as non-volatile storage material. Whether a floatinggate260 or atrapping layer260 is used, the function is the same, in that they hold data in the absence of power and the mode of operations described above may be performed. The primary difference between the floatinggate260 and thetrapping layer260 is that the floatinggate260 is a conductor, while thetrapping layer260 is an insulator layer.
• Thememory cells1350,1450, and1550 described above can also be fabricated on a silicon-on-insulator (SOI) substrate.FIGS. 229A through 229C illustratememory cells1350S,1450S, and1550S, in which the floating bodies are bounded at the bottom by aninsulator region22S,122S, and222S, respectively.
• FIG. 229A illustrates a schematic cross-sectional view ofmemory cell1350S.Memory cell1350S includes a silicon-on-insulator (SOI)substrate12 of a first conductivity type such as p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials.Substrate12 consists of a buriedinsulator22S, such as buried oxide (BOX).
• A floatingbody region24 of the first conductivity type, such as p-type, for example, is bounded on top bybit line region16,source line region18, and insulatinglayer62, and on the bottom by buriedinsulator22S.
• Abit line region16 having a second conductivity type, such as n-type, for example, is provided in floatingbody region24 and is exposed atsurface14.Bit line region16 may be formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region16.
• Asource line region18 having a second conductivity type, such as n-type, for example, is also provided in floatingbody region24 and is exposed atsurface14.Source line region18 may be formed by an implantation process formed on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to formbit line region18.
• A fully-depleted SOI substrate, such as shown inFIG. 229A, eliminates the need of an insulator layer to insulatecell1350S from neighboringcells1350S whenmultiple cells1350S are joined in an array to make a memory device. Thebit line region16 and thesource line region18 are shared with neighboringcells1350S. In a partially-depleted SOI surface (not shown), an insulator, such as shallow trench isolation (STI), may be used to insulatecell1350S from neighboringcells1350S.
• The operation of thememory cell1350S is similar to that of thememory cell1350. However, due to the absence of the buried well region incell1350S, a holding operation (performed by applying a positive bias on the buried well terminal on cell1350) cannot be performed oncell1350S. A periodic refresh operation, to refresh the state of thecell1350S, can be performed by applying a positive bias on thesource line region18, such as described in “Autonomous Refresh of Floating Body Cell (FBC)”, T. Ohsawa et al., pp. 1-4, IEEE International Electron Devices Meeting 2008 (“Ohsawa-2”), which is hereby incorporated herein, in its entirety, by reference thereto.
• FIGS. 229B and 229C illustratecell1450S and1550S fabricated on a silicon-on-insulator substrate, where buriedinsulator122S/222S, such as for example buried oxide (BOX), bound the floatingbody substrate124/224 at the bottom. Most of thedescriptions regarding cells1450/1550 also apply to thecells1450S/1550S. Similarly, due to the absence of the buried well region incells1450S/1550S, a holding operation (performed by applying a positive bias on the buried well terminal oncell1450/1550) cannot be performed oncell1450S/1550S. A periodic refresh operation, to refresh the state of thecell1450S/1550S, can be performed by applying a positive bias on thesource line region118/218.
• Memory cells1350,1450, and1550 may also comprise a fin structure as shown inFIGS. 230A through 230C. Similarly,memory cells1350S,1450S and1550S may also alternatively comprise a fin structure.
• FIG. 230A illustrates a schematic cross-sectional view ofmemory cell1350V.Memory cell1350V has afin structure52 fabricated onsubstrate12, so as to extend from the surface of the substrate to form a three-dimensional structure, withfin52 extending substantially perpendicular to and above the top surface of thesubstrate12.Fin structure52 is conductive and is built on buried well layer22 which is itself built on top ofsubstrate12. Alternatively, buried well22 could be a diffusion insidesubstrate12 with the rest of thefin52 constructed above it, or buried well22 could be a conductive layer on top ofsubstrate12 connected to all theother fin52 structures in a manner similar tomemory cell1350 described above.Fin52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
• Buried well layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buried well layer22 may be grown epitaxially abovesubstrate22. Buried well layer22, which has a second conductivity type (such as n-type conductivity type), insulates the floatingbody region24, which has a first conductivity type (such as p-type conductivity type), from thebulk substrate12 also of the first conductivity type.Fin structure52 includesbit line region16 andsource line region18 having a second conductivity type (such as n-type conductivity type). Similar tomemory cell1350,cell1350V is also asymmetric, for example by having a higher capacitive coupling from thesource line region18 to the floatinggates60.Memory cell1350V further includes floatinggates60 on two opposite sides of the floatingsubstrate region24 insulated from floatingbody24 by insulatinglayers62. Floatinggates60 are positioned between thebit line region16 and thesource line region18, adjacent to the floatingbody24.
• Thus, the floatingbody region24 is bounded by the top surface of thefin52, the facing side and bottom ofbit line region16 andsource line region18, top of the buried welllayer22, and insulating layers26 (as shown in the schematic top-view ofcell1350V inFIG. 230B) and62. Insulatinglayers26 insulatecell1350V from neighboringcells1350V whenmultiple cells1350V are joined to make a memory array.
• As shown inFIG. 230C, analternate fin structure1350V can be constructed. In this embodiment, floatinggates60 and insulatinglayers62 can enclose three sides of the floatingsubstrate region24. The presence of the floatinggate60 on three sides allows better control of the charge in floatingbody region24.
• Memory cell1350V can be used to replacememory cell1350 in an array similar toarray1380 having similar connectivity between the cells and the array control signal terminals. In such a case, the hold, read and write operations are similar to those in the lateral device embodiments described earlier formemory cell1350 inarray1380. As with the other embodiments, the first and second conductivity types can be reversed as a matter of design choice. As with the other embodiments, many other variations and combinations of elements are possible, and the examples described in no way limit the present invention. In addition,memory cell1350V may also be fabricated on a silicon-on-insulator (SOI) substrate.
• FIGS. 230D and 230E illustratecell1450V and1550V comprising fins152/252. Most of thedescriptions regarding cells1450/1550 also apply to thecells1450V/1550V. Reference numbers previously referred to in earlier drawing figures have the same, similar, or analogous functions as in the earlier described embodiments. The select gates, floating gates, and control gates oncells1450V/1550V may also enclose all sides of the floatingsubstrate regions124/224. In addition,memory cells1450V/1550V may also be fabricated on silicon-on-insulator (SOI) substrates.
• A novel semiconductor memory having both volatile and non-volatile functionality is achieved. Many embodiments of the present invention have been described. Persons of ordinary skill in the art will appreciate that these embodiments are exemplary only to illustrate the principles of the present invention. Many other embodiments will suggest themselves to such skilled persons after reading this specification in conjunction with the attached drawing figures. For example:
• The first and second conductivity types may be reversed and the applied voltage polarities inverted while staying within the scope of the present invention.
• While many different exemplary voltage levels were given for various operations and embodiments, these may vary from embodiment to embodiment as a matter of design choice while staying within the scope of the present invention.
• The invention may be manufactured using any process technology at any process geometry or technology node and be within the scope of the invention. Further, it should be understood that the drawing figures are not drawn to scale for ease of understanding and clarity of presentation, and any combination of layer composition, thickness, doping level, materials, etc. may be used within the scope of the invention.
• While exemplary embodiments typically showed a single memory array for the purpose of simplicity in explaining the operation of the various memory cells presented herein, a memory device employing the memory cells of the presentation may vary in many particulars in terms of architecture and organization as a matter of design choice while staying within the scope of the invention. Such embodiments may, without limitation, include features such as multiple memory arrays, segmentation of the various control lines with or without multiple levels of decoding, simultaneously performing multiple operations in multiple memory arrays or in the same arrays, employing many different voltage or current sensing circuits to perform read operations, using a variety of decoding schemes, using more than one type of memory cell, employing any sort of interface to communicate with other circuitry, and/or employing many different analog circuits known in the art to generate voltage or currents for use in performing the various operations on the memory array or arrays. Such analog circuits may without limitation be, for example, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), operational amplifiers (Op Amps), comparators, voltage reference circuits, current mirrors, analog buffers, etc.
• Thus the invention should not be limited in any way except by the appended claims.

Claims (18)

1-233. (canceled)

234. A single polysilicon floating gate semiconductor memory cell comprising:

a substrate;

a floating body region exposed at a surface of said substrate and configured to store volatile memory;

a buried layer buried in a bottom portion of said substrate;

wherein applying a bias to said buried layer results in at least two stable floating body region charge levels;

a single polysilicon floating gate configured to store nonvolatile data;

an insulating region insulating said floating body region from said single polysilicon floating gate; and

first and second regions exposed at said surface at locations other than where said floating body region is exposed;

wherein said floating gate is configured to receive transfer of data stored by the volatile memory.

235. The single polysilicon floating gate semiconductor memory cell ofclaim 234, wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.

236. The single polysilicon floating gate semiconductor memory cell ofclaim 234, wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to a coupling of the other of said first and second regions to said floating gate.

237. The single polysilicon floating gate semiconductor memory cell ofclaim 234, wherein said buried layer has a conductivity type that is different from a conductivity type of said floating body region.

238. The single polysilicon floating gate semiconductor memory cell ofclaim 234, wherein said floating body is bounded by said surface, said first and second regions and said buried layer.

239. The single polysilicon floating gate semiconductor memory cell ofclaim 234, further comprising insulating layers bounding side surfaces of said substrate.

240. The single polysilicon floating gate semiconductor memory cell ofclaim 234, wherein said floating gate overlies an area of said floating body exposed at said surface, and wherein a gap is located between said area overlaid and one of said first and second regions.

241. The single polysilicon floating gate semiconductor memory cell ofclaim 234, further comprising a select gate positioned adjacent to said single polysilicon floating gate.

242. The single polysilicon floating gate semiconductor memory cell ofclaim 236, wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.

243. The single polysilicon floating gate semiconductor memory cell ofclaim 241, wherein said select gate overlaps said floating gate.

244. A single polysilicon floating gate semiconductor memory cell comprising:

a substrate;

a floating body region for storing data as volatile memory, said floating body region having a first conductivity type;

a buried layer buried in a bottom portion of said substrate;

wherein applying a bias to said buried layer results in at least two stable floating body region charge levels; and

a single polysilicon floating gate for storing data as non-volatile memory;

wherein said floating body region stores the data stored as volatile memory independently of said data stored as non-volatile memory, and said single polysilicon floating gate stores said data stored as non-volatile memory independently of said data stored as volatile memory.

245. The single polysilicon floating gate semiconductor memory cell ofclaim 244, wherein said buried layer comprises a second conductivity type different from said first conductivity type.

246. The single polysilicon floating gate semiconductor memory cell ofclaim 245, wherein said first conductivity type is “p” type and said second conductivity type is “n” type.

247. The single polysilicon floating gate semiconductor memory cell ofclaim 244, further comprising insulating layers bounding side surfaces of said substrate.

248. The single polysilicon floating gate semiconductor cell ofclaim 244, wherein operations can be performed on said data stored as volatile memory regardless of a state of said data stored as non-volatile memory.

249. The single polysilicon floating gate semiconductor cell ofclaim 248, wherein said operations include read, write, hold, reset and shadow.

250. The single polysilicon floating gate semiconductor cell ofclaim 244, wherein operations can be performed on said data stored as non-volatile memory regardless of a state of said data stored as volatile memory.

Images