US20180138100A1 - Power module and inverter equipment - Google Patents

Abstract

The power module includes: a first metallic pattern; a plurality of power devices bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices and the first and second metallic patterns so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices. There is provided the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This is a continuation application (CA) of PCT Application No. PCT/JP2016/068675, filed on Jun. 23, 2016, which claims priority to Japan Patent Application No. P2015-135329 filed on Jul. 6, 2015 and is based upon and claims the benefit of priority from prior Japanese Patent Applications No. P2015-135329 filed on Jul. 6, 2015 and PCT Application No. PCT/JP2016/068675, filed on Jun. 23, 2016, the entire contents of each of which are incorporated herein by reference.
FIELD
• Embodiments described herein relate to a power module, and inverter equipment on which such a power module is mounted.
BACKGROUND
• Many research institutions are currently conducting research to develop Silicon Carbide (SiC) devices. SiC power devices have low on resistance as compared with Si power devices, and also include high switching speed and high temperature operation characteristics.
• Since losses (on resistance) produced by SiC devices are relatively low, a large electric current can be conducted even in SiC power modules having small area and therefore such SiC power modules can be miniaturized.
• It is well known that case type packages are adopted into such SiC power devices, and resin sealed semiconductor devices are formed by transfer molding.
• In the light of miniaturization of conventional power modules, thin type power modules have been required therefor, and Direct Bonding Copper (DBC) substrates, Direct Brazed Aluminum (DBA) substrates, or Active Metal Brazed, Active Metal Bond (AMB) substrates have been used in mounting processes.
SUMMARY
• However, there is a problem that degradation (such as a rupture) of a bonded portion occurs during a heat cycle test, when semiconductor devices (e.g. SiC power devices) are bonded on metallic substrates (e.g. DBC substrates), if a difference between the both values of coefficient of thermal expansion (CTE) is relatively large.
• The embodiments provide: a power module easy to be fabricated, capable of suppressing such a degradation of the bonded portion and improving reliability; and the inverter equipment on which such a power module is mounted.
• According to one aspect of the embodiments, there is provided a power module comprising: a first metallic pattern; a plurality of power devices configured to be bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the plurality of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices, the first metallic pattern, and the second metallic pattern so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices.
• According to another aspect of the embodiments, there is provided inverter equipment comprising a circuit in which a plurality of switching elements are connected in series between power terminals and a connection unit of the plurality of the switching elements is used as an output, wherein the inverter equipment is configured to mount at least one power module which is mentioned above as the switching elements.
• According to the embodiments, there can be provided: the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability; and the inverter equipment on which such a power module is mounted.
BRIEF DESCRIPTION OF DRAWINGS
• FIG. 1 is a bird's-eye view configuration diagram (perspective diagram) showing a principal portion of a power module according to the embodiments.
• FIG. 2 is a schematic cross-sectional structure diagram taken in the line II-II ofFIG. 1.
• FIG. 3A is a planar pattern configuration diagram showing a ceramic frame disposed on a metallic pattern, in the power module according to the embodiments.
• FIG. 3B is a schematic cross-sectional structure diagram taken in the line IIIb-IIIb ofFIG. 3A.
• FIG. 4A is a schematic cross-sectional structure diagram showing a power module with a ceramic frame, in an example of a case where no resin layer is formed thereon.
• FIG. 4B is a schematic cross-sectional structure diagram showing a power module without a ceramic frame, in an example of a case where no resin layer is formed thereon.
• FIG. 4C shows a simulation result showing a stress applied to the bonded portion being compared for each component.
• FIG. 5A is a conceptual diagram showing the component in each direction of the stress.
• FIG. 5B is a schematic cross-sectional diagram for explaining each component of the stress applied to the bonded portion.
• FIG. 6A is a schematic cross-sectional structure diagram showing a power module with a ceramic frame, in an example of a case where a resin layer is formed thereon.
• FIG. 6B is a schematic cross-sectional structure diagram showing a power module without a ceramic frame, in an example of a case where a resin layer is formed thereon.
• FIG. 6C shows a simulation result showing a stress applied to the bonded portion being compared for each component.
• FIG. 7A is a schematic cross-sectional structure diagram axisymmetrically showing a power module with a ceramic frame, in an example of a case where no resin layer is formed thereon.
• FIG. 7B is a schematic cross-sectional structure diagram axisymmetrically showing a power module without a ceramic frame, in an example of a case where no resin layer is formed thereon.
• FIG. 8A shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module with a ceramic frame, in an example of a case where no resin layer is formed thereon.
• FIG. 8B shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module without a ceramic frame, in an example of a case where no resin layer is formed thereon.
• FIG. 9A is a schematic cross-sectional structure diagram axisymmetrically showing a power module with a ceramic frame, in an example of a case where a resin layer is formed thereon.
• FIG. 9B is a schematic cross-sectional structure diagram axisymmetrically showing a power module without a ceramic frame, in an example of a case where a resin layer is formed thereon.
• FIG. 10A shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module with a ceramic frame, in an example of a case where a resin layer is formed thereon.
• FIG. 10B shows a simulation result showing a relationship between a shear stress and a distance from an axis of the power module without a ceramic frame, in an example of a case where a resin layer is formed thereon.
• FIG. 11A is a schematic cross-sectional structure diagram showing one process of a fabrication method of the power module according to the embodiments (Phase 1).
• FIG. 11B is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 2).
• FIG. 12A is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 3).
• FIG. 12B is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 4).
• FIG. 13A is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 5).
• FIG. 13B is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 6).
• FIG. 14 is a schematic cross-sectional structure diagram showing one process of the fabrication method of the power module according to the embodiments (Phase 7), in an example of a case where a heat sink is formed thereto.
• FIG. 15A is a planar pattern configuration diagram showing a ceramic frame, in a power module according to a modified example 1 of the embodiments.
• FIG. 15B is a schematic cross-sectional structure diagram taken in the line XVII-XVII ofFIG. 15A.
• FIG. 15C is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 2 of the embodiments.
• FIG. 15D is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 3 of the embodiments.
• FIG. 16A is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 4 of the embodiments.
• FIG. 16B is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 5 of the embodiments.
• FIG. 16C is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 6 of the embodiments.
• FIG. 16D is a schematic cross-sectional structure diagram showing a ceramic frame, in a power module according to a modified example 7 of the embodiments.
• FIG. 17A is a planar pattern configuration diagram showing a ceramic frame in an example of a case where one semiconductor device is mounted therein (Phase 1-1), in a power module according to a modified example 8 of the embodiments.
• FIG. 17B is a planar pattern configuration diagram showing a ceramic frame in an example of a case where two semiconductor devices are mounted therein (Phase 1-2), in the power module according to the modified example 8 of the embodiments.
• FIG. 17C is a planar pattern configuration diagram showing a ceramic frame in an example of a case where one semiconductor device is mounted therein (Phase 2), in the power module according to the modified example 8 of the embodiments.
• FIG. 17D is a planar pattern configuration diagram showing a ceramic frame in an example of a case where two semiconductor devices are mounted therein (Phase 3), in the power module according to the modified example 8 of the embodiments.
• FIG. 18 is a schematic cross-sectional structure diagram showing a power module according to anadditional embodiment 1.
• FIG. 19 is a schematic cross-sectional structure diagram showing a power module according to anadditional embodiment 2.
• FIG. 20 is a bird's-eye view (perspective diagram) showing the power module according to theadditional embodiment 2 such that a resin layer is in a transmitted state.
• FIG. 21 is a bird's-eye view configuration diagram (perspective diagram) showing a module with the built-in half-bridge, in a power module according to anadditional embodiment 3.
• FIG. 22 is a planar pattern configuration diagram showing the power module according to theadditional embodiment 3 such that a resin layer is in a transmitted state, in a 2-in-1 module (module with the built-in half-bridge).
• FIG. 23 is a circuit configuration diagram showing the 2-in-1 module (module with the built-in half-bridge) in which an SiC Metal Oxide Semiconductor Field Effect Transistor (MISFET) is applied as a semiconductor device, in the power module according to theadditional embodiment 3.
• FIG. 24 is a bird's-eye view configuration diagram (perspective diagram) showing an aspect before forming the resin layer in the module with the built-in half-bridge, in the power module according to theadditional embodiment 3.
• FIG. 25A is a circuit representative diagram of the SiC MISFET of a 1-in-1 module, which is the power module according to the embodiments.
• FIG. 253 is a circuit representative diagram of an Insulated Gate Bipolar Transistor (IGBT) of a 1-in-1 module, in the power module according to the embodiments.
• FIG. 26 is a detail circuit representative diagram of the SiC MISFET of the 1-in-1 module, which is the power module according to the embodiments.
• FIG. 27A is a circuit representative diagram of an SiC MISFET of a 2-in-1 module, which is the power module according to the embodiments.
• FIG. 27B is a circuit representative diagram of an IGBT of a 2-in-1 module, which is the power module according to the embodiments.
• FIG. 28A is a schematic cross-sectional structure diagram of an SiC MISFET, which is an example of a semiconductor device to be applied to the power module according to the embodiments.
• FIG. 28B is a schematic cross-sectional structure diagram of an IGBT, which is an example of the semiconductor device to be applied to the power module according to the embodiments.
• FIG. 29 is a schematic cross-sectional structure diagram showing an SiC MISFET including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device to be applied to the power module according to the embodiments.
• FIG. 30 is a schematic cross-sectional structure diagram of the IGBT including an emitter pad electrode EP and a gate pad electrode GP, which is an example of the semiconductor device to be applied to the power module according to the embodiments.
• FIG. 31 is a schematic cross-sectional structure diagram of an SiC Double Implanted MISFET (SiC DIMISFET), which is an example of a semiconductor device which can be applied to the power module according to the embodiments.
• FIG. 32 is a schematic cross-sectional structure diagram of an SiC Trench MISFET (SiC TMISFET), which is an example of a semiconductor device which can be applied to the power module according to the embodiments.
• FIG. 33A shows an example of a circuit configuration in which the SiC MISFET is applied as a semiconductor device, and a snubber capacitor is connected between a power terminal PL and an earth terminal (ground terminal) NL, in a circuit configuration of a three-phase alternating current (AC) inverter composed using the power module according to the embodiments.
• FIG. 33B shows an example of a circuit configuration in which the IGBT is applied as a semiconductor device, and the snubber capacitor is connected between the power terminal PL and the earth terminal (ground terminal) NL, in the circuit configuration of a three-phase AC inverter composed using the power module according to the embodiments.
• FIG. 34 is a circuit configuration diagram of a three-phase AC inverter composed using the power module according to the embodiments to which the SiC MISFET is applied as the semiconductor device.
• FIG. 35 is a circuit configuration diagram of a three-phase AC inverter composed using the power module according to the embodiments to which the IGBT is applied as the semiconductor device.
DESCRIPTION OF EMBODIMENTS
• Next, certain embodiments will now be described with reference to drawings. In the description of the following drawings, the identical or similar reference numeral is attached to the identical or similar part. However, it should be noted that the drawings are schematic and therefore the relation between thickness and the plane size and the ratio of the thickness differs from an actual thing. Therefore, detailed thickness and size should be determined in consideration of the following explanation.
• Moreover, the embodiments shown hereinafter exemplify the apparatus and method for materializing the technical idea; and the embodiments does not specify the material, shape, structure, placement, etc. of each component part as the following. The embodiments may be changed without departing from the spirit or scope of claims.
(Configuration of Power Module)
• FIG. 1 shows a bird's-eye view configuration of apower module20 according to the embodiments. Moreover,FIG. 2 shows a schematic cross-sectional structure of a principal portion taken in line II-II ofFIG. 1 in which a ceramic frame (frame member)10 is disposed at a peripheral portion of a metallic pattern (metallic substrate)3 formed on a ceramics substrate (mounting substrate)8, in thepower module20 according to the embodiments.
• Moreover, in thepower module20 according to the embodiments,FIG. 3A shows a planar pattern configuration of theceramic frame10 disposed at a peripheral portion of themetallic pattern3 on theceramics substrate8, andFIG. 3B shows a schematic cross-sectional structure taken in the line IIIb-IIIb ofFIG. 3A.
• As shown inFIGS. 1 and 2, the principal portion of thepower module20 according to the embodiments includes: aceramics substrate8; a semiconductor device (semiconductor chip)1 as a power device configured to be bonded near a center portion of themetallic pattern3 on theceramics substrate8; aceramic frame10 disposed along an edge of themetallic pattern3 on theceramics substrate8, a cross-sectional structure of theceramic frame10 configured to enclose thesemiconductor device1 being an I-shaped structure; and aresin layer14 configured to seal thesemiconductor device1 and theceramics substrate8 so as to include theceramic frame10. In each drawings, although thesemiconductor device1 is illustrated as one element, it may be composed of a plurality of elements (e.g., modules).
• Thesemiconductor device1 is bonded with solder on an upper surface of themetallic pattern3 via a bonding layer under chip (bonded portion)2, and theceramic frame10 is bonded with solder on the upper surface of themetallic pattern3 via a bonding layer underframe11 capable of solder bonding by being subjected to metal sputtering etc.
• Theresin layer14 configured to cover side surface portions of theceramics substrate8 is formed using a resin, etc., capable of transfer molding.
• A Direct Bonding Copper (DBC) substrate formed ofmetallic patterns3 and9 having 0.8 mm of thickness which are respectively composed by including Cu frames and are respectively formed on front side and back side surfaces of ceramics having 0.3 mm of thickness, for example, is used for theceramics substrate8. Instead of theceramics substrate8, it is also possible to apply substrates formed by disposing a Cu frame on an insulating sheet, metallic substrates (e.g. Cu substrate), or the like.
• Moreover, a Direct Brazed Aluminum (DBA) substrate or an Active Metal Brazed, Active Metal Bond (AMB) substrate is applicable thereto.
• Moreover, it is possible to apply not only theceramic frame10 but also metallic members etc. having a CTE value lower than a CTE value of the metallic substrate and higher than a CTE value of thesemiconductor device1, as the frame member.
• Moreover, it is also possible to apply composite materials etc. of ceramics and metal, as the frame member.
• An operation/working-effect produced by providing theceramic frame10 will now be explained, hereafter. More specifically, a result at the time of conducting a simulation (stress test) will now be explained, in thepower module20 according to the embodiments.
• FIGS. 4A-4C respectively show stresses applied to the bonded portion between thesemiconductor device1 and themetallic pattern3, comparing between a case of being provided with the ceramic frame10 (WCF: With Ceramic Frame) and a case of being provided without the ceramic frame10 (WOCF: Without Ceramic Frame), when noresin layer14 is formed thereon.FIG. 4A shows a schematic cross-sectional structure of a power module20-1ain the case of being provided with theceramic frame10,FIG. 4B shows a schematic cross-sectional structure of a power module20-1bin the case of being provided without theceramic frame10, andFIG. 4C graphically shows each component (σxx, σzz, σzx) of a simulation result of each stress.
• For each power module20-1a,20-1b, a size (width×thickness) of a cross section of themetallic pattern3 is set as 10×1, and a size (width×thickness) in a cross-sectional direction of thesemiconductor device1 is set as 5×0.25.
• In this context, a component in the direction z of a stress applied to the bonded portion CP is referred to as the vertical stress σzz, a component in the direction x of the stress applied to the bonded portion CP is referred to as the horizontal stress σxx, and a component in the direction zx of the stress applied to the bonded portion CP is referred to as the shear stress σzx, as shown inFIGS. 5A and 5B.
• In the power module20 (20-1a), it is possible to reduce the stress applied to the bonded portion CP for each component by being provided with theceramic frame10, as clearly also fromFIG. 4C. In particular, the shear stress σzx can be reduced more remarkably than other stresses σxx and σzz.
• FIGS. 6A-6C respectively show stresses applied to the bonded portion between thesemiconductor device1 and themetallic pattern3, comparing between a case of being provided with the ceramic frame10 (WCF) and a case of being provided without the ceramic frame10 (WOCF), when theresin layer14 is formed thereon.FIG. 6A shows a schematic cross-sectional structure of a power module20-2ain the case of being provided with theceramic frame10,FIG. 6B shows a schematic cross-sectional structure of a power module20-2bin the case of being provided without theceramic frame10, andFIG. 6C graphically shows each component (σxx, σzz, σzx) of a simulation result of each stress.
• In the power module20 (20-2a), it is possible to reduce the stress applied to the bonded portion CP for each component by being provided with theceramic frame10, as clearly also fromFIG. 6C. In particular, the shear stress σzx can be reduced more remarkably than other stresses σxx and σzz.
• Consequently, it is possible to reduce the shear stress σzx applied to the bonded portion CP regardless of the presence or absence of theresin layer14 by providing theceramic frame10 in thepower module20.
• Accordingly, degradation (such as a rupture) which occurs in the bonded portion CP during a heat cycle test can be suppressed by being provided with theceramic frame10, even when the difference between the CTE value of thesemiconductor device1 and the CTE value of themetallic pattern3 is relatively large.
• FIGS. 7-10 show the operation/working-effect produced by being providing theceramic frame10 in order to be further explained in detail, in thepower module20 according to the embodiments.
• FIGS. 7 and 8 respectively show stresses applied to the bonded portion between the semiconductor device (SiC)1 and the metallic pattern (Cu substrate)3, comparing between a case of being provided with the ceramic frame (SiN)10 and a case of being provided without the ceramic frame (SiN)10, when the resin layer (Resin)14 is not formed thereon.FIG. 7A shows a schematic cross-sectional structure of the power module20-1ain the case of being provided with theceramic frame10 axisymmetrically taken in the line Yc-Yc, andFIG. 7B shows a schematic cross-sectional structure of the power module20-1bin the case of being provided without theceramic frame10 axisymmetrically taken in the line Yc-Yc. Moreover,FIG. 8A shows a stress simulation result showing a relationship between a distance from the axis of the power module20-1aand a shear stress σzx, andFIG. 8B shows a stress simulation result showing a relationship between a distance from the axis of the power module20-1band a shear stress σzx.
• In the power module20-1aaxisymmetrically shown, the thickness of the cross section of theceramic frame10 is thicker than the thickness of thesemiconductor device1, and the size (width×thickness) of the cross section of theceramic frame10 is set to 2×1 (the approximately same thickness as the metallic pattern3), for example.
• In the case of the structure shown inFIG. 7B, the stress concentrates mostly on the boundary portion of the bonded portion between thesemiconductor device1 and themetallic pattern3. On the other hand, in the case of a structure shown inFIG. 7A, although the stress concentrates on the boundary portion of the bonded portion between thesemiconductor device1 and themetallic pattern3, the stress concentration is relatively relaxed.
• FIGS. 9 and 10 respectively show stresses applied to the bonded portion between the semiconductor device (SiC)1 and the metallic pattern (Cu substrate)3, comparing between a case of being provided with the ceramic frame (SiN)10 and a case of being provided without the ceramic frame (SiN)10, when the resin layer (Resin)14 is formed thereon.FIG. 9A shows a schematic cross-sectional structure of the power module20-2ain the case of being provided with theceramic frame10 axisymmetrically taken in the line Yc-Yc, andFIG. 9B shows a schematic cross-sectional structure of the power module20-2bin the case of being provided without theceramic frame10 axisymmetrically taken in the line Yc-Yc. Moreover,FIG. 10A shows a stress simulation result showing a relationship between a distance from the axis of the power module20-2aand a shear stress σzx, andFIG. 10B shows a stress simulation result showing a relationship between a distance from the axis of the power module20-2band a shear stress σzx.
• In the power modules20-2aand20-2baxisymmetrically shown, the size (width×thickness) of the cross section of theresin layer14 is set to 15×7.5.
• In the case of the structure shown inFIG. 9B, the stress concentrates mostly on the boundary portion of the bonded portion between thesemiconductor device1 and themetallic pattern3. On the other hand, in the case of a structure shown inFIG. 9A, although the stress concentrates on the boundary portion of the bonded portion between thesemiconductor device1 and themetallic pattern3, the stress concentration is relatively relaxed.
• Consequently, theceramic frame10 has a function of suppressing the shear stress σzx according to the difference between the CTE value of themetallic pattern3 and the CTE value of thesemiconductor device1. More specifically, theceramic frame10 has an effect of reducing the CTE value of Cu so that themetallic pattern3 is not shrunk.
• Accordingly, even if the transfer-mold type power module is adopted, the shear stress σzx applied to the bonded portion CP at the time of the heat cycle test, etc. can be remarkably reduced by providing theceramic frame10 having the CTE value smaller than the CTE value of Cu of themetallic pattern3 but larger than the CTE value of thesemiconductor device1, as described above.
• For example, when the CTE value of the semiconductor device (Sic)1 is approximately 3 ppm/K and the CTE value of the metallic pattern (Cu)3 is approximately 16 ppm/K, the ceramic frame (SiN)10 having the CTE value of approximately 2-10 ppm/K may be provided, in thepower module20 according to the embodiments.
• In addition, the CTE value of theresin layer14 is set as approximately 12-14 ppm/K, in thepower module20 according to the embodiments.
(Fabrication Method)
• A fabrication method of thepower module20 according to the embodiments mainly includes: forming aceramic frame10 on a peripheral portion of ametallic pattern3 on aceramics substrate8; disposing asemiconductor device1 on themetallic pattern3 inside theceramic frame10; and forming aresin layer14 configured to seal thesemiconductor device1 and theceramics substrate8 so as to include theceramic frame10.
• The fabrication method of the power module according to the embodiments will now be explained with reference toFIGS. 11-13.
• (a) Firstly, as shown inFIG. 11A, a DBC substrate formed by forming respectively Cu frames on a front side surface and a back side surface of aceramics substrate8 is prepared for as a mounting substrate. Then, ametallic pattern3 having a CTE value of approximately 16 ppm/K, and patterned metallic patterns (copper foils)5 and7 are formed on the front side surface of theceramics substrate8. A metallic pattern (metallic frame)9 is formed on the back side surface of theceramics substrate8.
  (b) Next, as shown inFIG. 11B, aceramic frame10 having a CTE value of approximately 2-10 ppm/K is formed via a bonding layer underframe11 on themetallic pattern3 on the front side surface of theceramics substrate8. A soldering layer or an adhesive layer are applicable to the bonding layer underframe11, for example.
  (c) Next, as shown inFIG. 12A, an SiC basedsemiconductor device1 having a CTE value of approximately 3 ppm is bonded with die bonding via abonding layer2 under chip on themetallic pattern3 on the front side surface of theceramics substrate8 inside theceramic frame10. For thebonding layer2 under chip, a soldering layer or an Ag sintered layer are applicable. In addition, an Ag nanoparticle layer etc. which are previously formed on a back side surface of thesemiconductor device1 may be used for thebonding layer2 under chip.
• In addition, the processing order of (b) forming aceramic frame10 on themetallic pattern3 and (c) bonding thesemiconductor device1 on themetallic pattern3 may also be reversed. Accordingly, theceramic frame10 may be formed, after bonding of thesemiconductor device1.
• (d) Next, as shown inFIG. 12B, thebonding wires4 and6 are respectively bonded to a gate electrode and a source electrode of thesemiconductor device1. In this case, thebonding wires4 and6 may respectively be bonding-connected on the patternedmetallic patterns5 and7. Thebonding wires4 and6 can be formed by including Al, AlCu, or the like, for example.
  (e) Next, as shown inFIG. 13A, blockterminal electrodes12 and13 are respectively connected via soldering layers (not shown) on themetallic patterns5 and7 patterned on the front side surface of theceramics substrate8.
  (f) Next, as shown inFIG. 13B, aresin layer14 configured to seal thesemiconductor device1 and theceramics substrate8 so as to include the inside of theceramic frame10 is formed to seal the whole of the power module. In this case, a transfer molding process is applicable to the formation of theresin layer14.
• Thepower module20 according to the embodiments includes aheat sink100 as shown inFIG. 14, for example, and theceramics substrate8 may be disposed on theheat sink100. In this case, theheat sink100 is formed by including a Cu base for heat radiation, for example. Themetallic pattern9 formed on the back side surface of theceramics substrate8 is connected to theheat sink100 via asoldering layer16 under substrate.
• In thepower module20 according to the embodiments, a simplification of the module fabrication process and a miniaturization of the module can be realized since the module fabrication can be realized without attachment of a case.
• In thepower module20 according to the embodiments, since structural members, e.g. a case, are unnecessary, the number of parts is reduced, and thereby realizing cost reduction.
• A height of theceramic frame10 is approximately 5 mm to approximately 0.2 mm, for example. Moreover, theceramic frame10 is formed in an approximately square shape. The height and width of the frame are preferable to be made as small as possible so that the chip size is suitable for the purpose of a miniaturization and a cost reduction, in the light of a sufficiently effective design calculated from the simulation result etc.
• In the case of theceramic frame10 of which the frame member is formed with ceramics, the ceramics may be formed by including: Al₂O₃, AlN, SiN, AlSiC; or SiC of which at least the front side surface has insulating property, for example. Moreover, a front side surface of Al₂O₃may be subjected to plating processing of W, Ni, the Au, or the like.
• Moreover, if forming the frame member with a metallic member, the frame member may be formed by milling etc.
• Moreover, a thickness of theresin layer14 is approximately 4.0 mm to approximately 10 mm, for example.
• Theblock terminal electrodes12 and13 may be formed by including Cu, CuMo, or the like.
• Theceramic substrate8 may be formed by including: Al₂O₃, AlN, SiN, AlSiC; or SiC of which at least the front side surface has insulating property, for example.
Modified Example 1
• FIG. 15A shows a planar pattern configuration of aceramic frame10, in the power module according to a modified example 1 of the embodiments, andFIG. 15B shows a schematic cross-sectional structure taken in the line XVII-XVII ofFIG. 15A.
• In the power module according to the modified example 1 of the embodiments, a cross-sectional structure of theceramic frame10 may have a T-shaped structure by being provided with aceramic frame10 including acap portion10A of a protruding structure, as shown inFIG. 15B. An engaging degree of theresin layer14 can be improved and thereby adhesibility thereof can be improved, by being provided with theceramic frame10 including thecap portion10A of the protruding structure.
Modified Example 2
• FIG. 15C shows a schematic cross-sectional structure of aceramic frame10, in a power module according to a modified example 2 of the embodiments.
• In the power module according to the modified example 2 of the embodiments, a cross-sectional structure of theceramic frame10 may have an inverted-L-shaped structure or Γ (gamma)-shaped structure by being provided with acap portion10B, as shown inFIG. 15C. An engaging degree of theresin layer14 can be improved and thereby adhesibility thereof can be improved, by being provided with theceramic frame10 including thecap portion10B of the protruding structure.
Modified Example 3
• FIG. 15D shows a schematic cross-sectional structure of aceramic frame10, in a power module according to a modified example 3 of the embodiments.
• Also in the power module according to the modified example 3 of the embodiments, a cross-sectional structure of theceramic frame10 may have an inverted-L-shaped structure or Γ-shaped structure by being provided with acap portion10C, as shown inFIG. 15D. An engaging degree of theresin layer14 can be improved and thereby adhesibility thereof can be improved, by being provided with theceramic frame10 including thecap portion100 of the protruding structure.
Modified Example 4
• FIG. 16A shows a schematic cross-sectional structure of aceramic frame10, in a power module according to a modified example 4 of the embodiments.
• In the power module according to the modified example 4 of the embodiments, a surface roughening process may be applied to asurface10S of aceramic frame10 having an I-shaped structure. The surface roughening process to be applied to theceramic frame10 can be realized by a sandblast processing etc. Thus, an engaging degree of theresin layer14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to thesurface10S of theceramic frame10.
Modified Example 5
• FIG. 16B shows a schematic cross-sectional structure of aceramic frame10, in a power module according to a modified example 5 of the embodiments.
• In the power module according to the modified example 5 of the embodiments, a surface roughening process may be applied to asurface10S of aceramic frame10 having a T-shaped structure, by being provided with thecap portion10A. Thus, an engaging degree of theresin layer14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to thesurface10S of theceramic frame10.
Modified Example 6
• FIG. 16C shows a schematic cross-sectional structure of aceramic frame10, in a power module according to a modified example 6 of the embodiments.
• In the power module according to the modified example 6 of the embodiments, a surface roughening process may be applied to asurface10S of aceramic frame10 having an inverted-L-shaped structure or Γ-shaped structure, by being provided with thecap portion10B. Thus, an engaging degree of theresin layer14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to thesurface10S of theceramic frame10.
Modified Example 7
• FIG. 16D shows a schematic cross-sectional structure of aceramic frame10, in a power module according to a modified example 7 of the embodiments.
• In the power module according to the modified example 7 of the embodiments, a surface roughening process may be applied to asurface10S of aceramic frame10 having an inverted-L-shaped structure or T-shaped structure, by being provided with thecap portion10C. Thus, an engaging degree of theresin layer14 can be further improved and thereby adhesibility thereof can be improved, by applying the surface roughening process to thesurface10S of theceramic frame10.
Modified Example 8
• FIGS. 17A-17D show planar pattern configurations ofceramic frames10, in a power module according to a modified example 8 of the embodiments.
• In the power module according to the modified example 8 of the embodiments, aceramic frame10aof rectangular shape, e.g. rectangle, may be adopted, as shown inFIG. 17A. Moreover, the ceramic frame is not limited to theceramic frame10aenclosing the periphery of onesemiconductor device1, but aceramic frame10benclosing the periphery of a plurality ofsemiconductor devices1A and1B as shown inFIG. 17B may be adopted.
• Moreover, a circle-shaped (e.g. circular or elliptical)ceramic frame10cmay be adopted, as shown inFIG. 17C. Moreover, a line-shaped (e.g. straight line-shaped)ceramic frame10ddisposed along a long side of themetallic pattern3 near thesemiconductor devices1A and1B, without enclosing the periphery ofsemiconductor devices1A and1B, may be adopted, as shown inFIG. 17D.
• Furthermore, theceramic frame10 is not limited to a structure of being arranged along an edge of themetallic pattern3, but theceramic frame10 may be arranged at an inner side than the edge of themetallic pattern3 as shown inFIGS. 17A-17D. Moreover, each of theceramic frames10a-10drespectively shown inFIGS. 17A-17D may not always be integral-type frame, but may be divided to be fragmentarily arranged.
• Although not illustrated, it is possible to adopt: a configuration of enclosing the periphery of the plurality of thesemiconductor devices1A and1B by a square-shapedceramic frame10 arranged along an edge of themetallic pattern3 as shown inFIG. 1; a configuration respectively enclosing the periphery of the plurality ofsemiconductor devices1 by the circle-shaped ceramic frames10c; or a configuration of arranging the line-shapedceramic frame10dat the periphery of onesemiconductor device1.
• According to the embodiments and its modified examples, it becomes possible to remarkably reduce the shear stress σzx applied to the bonded portion CP, also in the transfer-moldtype power module20 in which the difference between the CTE value of themetallic pattern3 and the CTE value of thesemiconductor device1 bonded on themetallic pattern3 is relatively large. Accordingly, it becomes possible to suppress degradation, such as destruction, due to rupturing of the bonded portion CP during a heat cycle test, etc. and also becomes possible to maintain high electrical characteristics and high thermal characteristics, and thereby to obtain an improvement in reliability.
• The power module according to the embodiments and its modified examples can be applied, in particular to various transfer-mold type power modules, e.g. IGBT modules in which IGBT chips are mounted on metallic (e.g. Cu) substrates, diode modules, MIS (Si, SiC, GaN) modules.
• Moreover, there can be provided the low-cost power module having a simplified structure, easy to be fabricated through a simplified and easy process, and capable of improving mass productivity and realizing miniaturization thereof. In addition, the power module can be easily fabricated and excellent also in mass productivity.
Additional Embodiment 1
• As apower module20 according to anadditional embodiment 1, as shown inFIG. 18, ablock terminal electrode17 may be provided therein, instead of thebonding wires4 and6.
• In this case, theblock terminal electrode17 can be disposed on a gate electrode or source electrode on the front side surface of thesemiconductor device1. Although oneblock terminal electrode17 is illustrated in an example shown inFIG. 18, a plurality of theblock terminal electrodes17 may be disposed for the gate and source electrodes. Moreover, theblock terminal electrode17 may be formed by including Cu, CuMo, or the like.
• Other configurations are the same as that of the above-mentioned present embodiments (e.g., refer toFIG. 14), it can be easily fabricated by connecting theblock terminal electrode17 on the gate electrode or source electrode on the front side surface of thesemiconductor device1 simultaneously with (or after or before) connecting theblock terminal electrodes12 and13, instead of the wire bonding.
Additional Embodiment 2
• As shown inFIGS. 19 and 20, thepower module20 according to anadditional embodiment 2 may include: a relayingsubstrate18 configured to select abonding wire19 and ablock terminal electrode23, relayingsubstrate18 disposed on themetallic pattern3 inside theceramic frame10; and ablock terminal electrode21 configured to connect between a source electrode on thesemiconductor device1 and ametallic pattern7 on theceramics substrate8.
• FIG. 19 shows a schematic cross-sectional structure of thepower module20, andFIG. 20 shows a bird's-eye view configuration of thepower module20 such that theresin layer14 is in a transmitted state.
• In this case, the relayingsubstrate18 includes a ceramics substrate, and copper foils (Cu frames) formed respectively on front side and back side surfaces of the ceramics substrate. More specifically, the relayingsubstrate18 has a DBC substrate structure. Moreover, a DBA substrate or AMB substrate may be used as the relayingsubstrate18.
• Thebonding wire19 bonding-connects between the gate electrode on thesemiconductor device1 and the copper foil on the relayingsubstrate18. Thebonding wire19 can be formed by including Al, AlCu, or the like, for example.
• Theblock terminal electrode23 is configured to connect between the copper foil on the relayingsubstrate18 and themetallic pattern5 on theceramics substrate8 respectively via soldering layers (not shown).
• Theblock terminal electrodes21 and23 may be formed by including Cu, CuMo, or the like.
• Other configurations are the same as that of the above-mentioned present embodiments (e.g., refer toFIG. 14), it can be easily fabricated by connecting the relayingsubstrate18 is in the same manner as die bonding on themetallic pattern3 inside theceramic frame10; bonding-connects thebonding wire19 between thesemiconductor device1 and the relayingsubstrates18 after bonding thesemiconductor device1 by die bonding; and respectively connecting theblock terminal electrodes21 and23 between thesemiconductor device1 and themetallic pattern7 and between the relayingsubstrate18 and themetallic pattern5 simultaneously with (or after or before) connecting theblock terminal electrode12 on themetallic pattern5.
Additional Embodiment 3
• FIG. 21 shows a bird's-eye view configuration of so-called 2-in-1 module (module with the built-in half-bridge) in which two semiconductor devices are contained in one module, in apower module200 according to anadditional embodiment 3.
• Moreover,FIG. 22 shows a planar pattern configuration of thepower module200 before forming theresin layer14, andFIG. 23 shows a circuit configuration of the 2-in-1 module to which SiC MISFETs Q1 and Q4 are applied as semiconductor devices.
• More specifically, thepower module200 according to theadditional embodiment 3 includes a configuration of a module with so-called built-in half-bridge in which two MISFETs Q1 and Q4 are built in one module.
• FIG. 22 shows an example of 4-chip of the MISFETs Q1 and 4-chip of the MISFETs Q4 respectively disposed in parallel. For example, one MISFET can mount five transistors (chip) at the maximum. Note that it is also possible to mount a part of five pieces of the chips for the diode DI thereon.
• In this case, although the module can be understood as one large transistor, one piece or a plurality of transistors (chips) may be contained therein. More specifically, although the modules include 1-in-1 module, 2-in-1 module, 4-in-1 module, 6-in-1 module, etc., for example, a module configured to vertically connect two transistors to be contained on the module is called 2-in-1 module, a module configured to wire2 sets of 2-in-1 module to be contained on the module is called 4-in-1 module, and a module configured to wire all to be contained on the module is called 6-in-1 module.
• As shown inFIG. 21, thepower module200 according to theadditional embodiment 3 includes: a positive-side power terminal P (D1) and a negative-side power terminal N (S4) disposed at a first side of theceramic substrate8 covered with theresin layer14; a gate terminal GT1 and a source sense terminal SST1 disposed at a second side adjacent to the first side; output terminals O (S1) and O (D1) disposed at a third side opposite to the first side; and a gate terminal GT4 and a source sense terminal SST4 disposed at a fourth side opposite to the second side.
• Moreover, as shown inFIG. 22, the gate terminal GT1 and the source sense terminal SST1 are connected to the signal wiring pattern GL1 for gate and the signal wiring pattern SL1 for source in the MISFET Q1; and the gate terminal GT4 and the source sense terminal SST4 are connected to the signal wiring pattern GL4 for gate and the signal wiring pattern SL4 for source in the MISFET Q4.
• As shown inFIG. 22, wires for gate GW1 and GW4 and wires for source sense SSW1 and SSW4 are respectively connected from the MISFETs Q1 and Q4 toward the gate signal wiring patterns GL1 and GL4 and the source sense signal wiring patterns SL1 and SL4 which are respectively disposed on the signal substrates24₁and24₄. Moreover, gate terminals GT1 and GT4 and source sense terminals SST1 and SST4 for external extraction are respectively connected to the signal wiring patterns GL1 and GL4 for gate and the signal wiring patterns SL1 and SL4 for source sense by soldering etc.
• As shown inFIG. 22, the signal substrates24₁and24₄are connected by soldering etc. on theceramics substrate8.
• FIG. 24 shows a bird's-eye view configuration before forming theresin layer14 after forming upper surface plate electrodes22₁and22₄, in the module with the built-in half-bridge, in thepower module200 according to theadditional embodiment 3. Note that the wires GW1 and GW4 for gate and the wires SSW1 and SSW4 for source sense are not shown inFIG. 24.
• The sources S1 and S4 of 4 chips of the MISFETs Q1 and Q4 respectively disposed in parallel are commonly connected with the upper surface plate electrodes22₁and22₄.
• Although illustration is omitted inFIGS. 21-24, diodes may be respectively connected reversely in parallel between a drain D1 and a source S1 and between a drain D4 and a source S4 of the MISFETs Q1 and Q4.
• Although the sources S1 and S4 of 4 chips of the MISFETs Q1 and Q4 disposed in parallel are commonly connected with the upper surface plate electrodes22₁and22₄in an example shown inFIGS. 21-24, the sources may be conducted to one another with the wire instead of the upper surface plate electrodes22₁and22₄.
• The positive-side power terminal P and the negative-side power terminal N, and the gate terminals GT1 and GT4 and the source sense terminals SST1 and SST4 for external extraction can be formed of Cu, for example.
• Thesignal substrates241 and244 can be formed by including a ceramics substrate. The ceramic substrate may be formed by including Al₂O₃, AlN, SiN, AlSiC, or SiC of which at least the surface is insulation, for example.
• Main wiring conductors (metallic substrates)32₁,32₄, and32_n(EP) used for electrode patterns can be formed by including Cu, Al, or the like, for example.
• Portions of pillar electrodes25₁and25₄and upper surface plate electrodes22₁and22₄configured to respectively connect between the sources S1 and S4 of the MISFETs Q1 and Q4 and the upper surface plate electrodes22₁and22₄may be formed by including CuMo, Cu, or the like, for example.
• The wires GW1 and GW4 for gate and the wires SSW1 and SSW4 for source sense can be formed by including Al, AlCu, or the like, for example.
• Wide-bandgap type elements, such as SiC based power devices (e.g. SiC DIMISFET and SiC TMISFET), or GaN based power devices (e.g. GaN based FET, High Electron Mobility Transistor (HEMT)), can be applied as the MISFETs Q1 and Q4. In some instances, power devices, e.g. Si based MISFETs and IGBT, are also applicable thereto.
• In thepower module200 according to theadditional embodiment 3, 4 chips of the MISFETs Q1 are bonded via abonding layer2 under chip on the main wiring conductor32₁in theceramic frame10₁disposed via a soldering layer etc. on the main wiring conductor32₁. Similarly, 4 chips of the MISFETs Q4 are bonded via abonding layer2 under chip on the main wiring conductor32₄in theceramic frame10₄disposed via a soldering layer etc. on the main wiring conductor32₄.
• The inside of each of theceramic frames10₁and10₄is filled up with a resin, and each of the 4 chips of the MISFETs Q1 and Q4 is sealed with the resin. Moreover, the whole module is packaged by theresin layer14 so as to include the upper surface plate electrodes22₁and22₄, etc. The whole of theresin layer14 is formed of a homogeneous material.
• In addition, the respectiveceramic frames10₁and10₄are configured to collectively contain the respective MISFETs Q1 and Q4, in the example shown inFIGS. 22 and 24, but the respectiveceramic frames10₁and10₄may be configured to individually contain the respective MISFETs Q1 and Q4.
• In the same manner as the embodiments, the principal portion of thepower module200 according to theadditional embodiment 3 includes: aceramics substrate8; MISFETs Q1 and Q4 respectively bonded to main wiring conductors32₁and32₄on theceramics substrate8;ceramic frames10₁and10₄respectively disposed on the main wiring conductor32₁and32₄, the ceramic frames10₁and10₄configured to enclose the MISFETs Q1 and Q4; andresin layers14 configured to respectively seal the MISFETs Q1 and Q4 inside theceramic frames10₁and10₄, and to respectively seal the main wiring conductors32₁and32₄and theceramics substrate8 inside theceramic frames10₁and10₄.
• Also in thepower module200 according to theadditional embodiment 3, the same resin material as that of the embodiments and its modified examples 1-8 can be applied to theresin layer14, and the same configuration of theceramic frame10 as that of the embodiments and its modified examples 1-8 can be adopted into theceramic frames10₁and10₄.
• Also in thepower module200 according to theadditional embodiment 3, theblock terminal electrodes12 and13, the relayingsubstrate18, etc. may be applied instead of the wires GW1 and GW4 for gate and the wires SSW1 and SSW4 for source sense, in order to prevent wire breaking due to a thermal stress etc. and to obtain an improvement in reliability.
• Also in thepower module200 according to theadditional embodiment 3, a simplification of the module fabrication process and a miniaturization of the module can be realized since the same fabrication method as that of the embodiments or other additional embodiments can be applied and therefore the module fabrication can be realized without attachment of a case. Also in thepower module200 according to theadditional embodiment 3, since structural members, e.g. a case, are unnecessary, the number of parts is reduced, and thereby realizing cost reduction.
• Thus, also according to theadditional embodiment 3, it becomes possible to remarkably reduce the shear stress σzx applied to the bonded portion CP, also in the transfer-moldtype power module200 in which the difference between the CTE value of the main wiring conductors32₁and32₄and the CTE value of the MISFETs Q1 and Q4 bonded on the main wiring conductors32₁and32₄is relatively large. Accordingly, also in the transfer-moldtype power module200, it becomes possible to suppress degradation, such as destruction, due to rupturing of the bonded portion during a heat cycle test, etc. and also becomes possible to maintain high electrical characteristics and high thermal characteristics, and thereby to obtain an improvement in reliability.
• Moreover, there can be provided the low-cost power module having a simplified structure, easy to be fabricated through a simplified and easy process, and capable of improving mass productivity and realizing miniaturization thereof. In addition, the power module can be easily fabricated and excellent also in mass productivity.
(Examples of Power Module)
• Hereinafter, there will now be explained examples of thepower module20 according to the embodiments. Naturally, the configuration in which theceramic frame10 is formed in the periphery of thesemiconductor device1 on themetallic pattern3 is adopted, in order to reduce the difference between the CTE value of themetallic pattern3 and the CTE value of thesemiconductor device1 also in thepower module20 explained hereinafter.
• FIG. 25A shows a schematic circuit representative of an SiC MISFET of the 1-in-1 module, which is thepower module20 according to the embodiments.FIG. 25B shows a schematic circuit representation of the IGBT of the 1-in-1 module.
• A diode DI connected in reversely parallel to the MISFET Q is shown inFIG. 25A. A main electrode of the MISFET Q is expressed with a drain terminal DT and a source terminal ST.
• Similarly, a diode DI connected in reversely parallel to the IGBT Q is shown inFIG. 25B. A main electrode of the IGBT Q is expressed with a collector terminal CT and an emitter terminal ET.
• Moreover,FIG. 26 shows a detailed circuit representative of the SiC MISFET of the 1-in-1 module, which is thepower module20 according to the embodiments.
• Thepower module20 according to the embodiments includes a configuration of 1-in-1 module, for example. More specifically, one MISFET is contained in one module, and a maximum of 5 chips (five transistors) connected in parallel to one another can be mounted in one MISFET, as an example. Note that it is also possible to mount a part of five pieces of the chips for the diode DI thereon.
• More particularly, as shown inFIG. 26, a sense MISFET Qs is connected to the MISFETQ in parallel. The sense MISFET Qs is formed as a miniaturized transistor in the same chip as the MISFET Q. InFIG. 26, reference numeral SS denotes a source sense terminal, reference numeral CS denotes a current sense terminal, and reference numeral G denotes a gate signal terminal.
• Note that, also in thesemiconductor chip1 according to the embodiments, the sense MISFET Qs is formed as a miniaturized transistor in the same chip.
• Moreover,FIG. 27A shows a circuit representative of the SiC MISFET of the 1-in-1 module, which is thepower module20T according to the embodiments.
• As shown inFIG. 27A, two MISFETs Q1 and Q4, and diodes D1 and D4 connected in reversely parallel to the MISFETs Q1 and Q4 are built in one module. InFIG. 27A, reference numeral G1 denotes a gate signal terminal of the MISFET Q1, and reference numeral S1 denotes a source terminal of the MISFET Q1. Reference numeral G4 denotes a gate signal terminal of the MISFET Q4, and reference numeral S4 denotes a source terminal of the MISFET Q4. Reference numeral P denotes a positive side power input terminal, reference numeral N denotes a negative side power input terminal, and reference numeral O denotes an output terminal.
• Moreover,FIG. 27B shows a circuit representative of the 2-in-1 module, which is thepower module20T according to the embodiments.
• As shown inFIG. 27B, two IGBTs Q1 and Q4, and diodes D1 and D4 connected in reversely parallel to the IGBTs Q1 and Q4 are built in one module. InFIG. 27B, reference numeral G1 denotes a gate signal terminal of the IGBT Q1, and reference numeral E1 denotes an emitter terminal of the IGBT Q1. Reference numeral G4 denotes a gate signal terminal of the IGBT Q4, and reference numeral E4 denotes an emitter terminal of the IGBT Q4. Reference numeral P denotes a positive side power input terminal, reference numeral N denotes a negative side power input terminal, and reference numeral O denotes an output terminal.
(Configuration Example of Semiconductor Device)
• FIG. 28A shows a schematic cross-sectional structure of anSiC MISFET110, which is an example of a semiconductor device which can be applied to thepower modules20 and20T according to the embodiments, andFIG. 28B shows a schematic cross-sectional structure of theIGBT110A.
• As shown inFIG. 28A, the schematic cross-sectional structure of theSiC MISFET110 includes: asemiconductor substrate126 composed by including an n⁻type high resistivity layer;a p body region128 formed on a front surface side of thesemiconductor substrate126; asource region130 formed on a front side surface of thep body region128; agate insulating film132 disposed on a front side surface of thesemiconductor substrate126 between thep body regions128; agate electrode138 disposed on thegate insulating film132; asource electrode134 connected to thesource region130 and thep body region128; an n⁺ drain region124 disposed on a back side surface opposite to the surface of thesemiconductor substrate126; and adrain electrode136 connected to the n⁺type drain area124.
• Although the planar-gate-type n channel vertical SiC-MISFET is disclosed inFIG. 28A, the semiconductor device may be composed by including a trench-gate-type n channel vertical SiC-TMISFET, etc., shown inFIG. 32 mentioned below. Moreover, a GaN based FET etc. can also be adopted thereinto, instead of the SiC MISFET. It is especially effective to adopt any one of an SiC-based or GaN-based power device, as thepower modules20 and20T according to the embodiments.
• Furthermore, a wide-bandgap type semiconductor of which the bandgap energy is from 1.1 eV to 8 eV, for example, can be used for the semiconductor device applicable to thepower modules20 and20T according to the embodiments.
• Similarly, as shown inFIG. 28B,IGBT110A as an example of the semiconductor device applicable to thepower modules20 and20T according to the embodiments includes: asemiconductor substrate126 composed by including an n⁻type high resistivity layer;a p body region128 formed on a front surface side of thesemiconductor substrate126; anemitter region130E formed on a front side surface of thep body region128; agate insulating film132 disposed on a front side surface of thesemiconductor substrate126 between thep body regions128; agate electrode138 disposed on thegate insulating film132; anemitter electrode134E connected to theemitter region130E and thep body region128; a p⁺ collector region124P disposed on a back side surface opposite to the surface of thesemiconductor substrate126; and acollector electrode136 connected to the p⁺ collector region124P.
• In the example shown inFIG. 28B, although thesemiconductor device110 composed by including the planar-gate-type n channel vertical IGBT is disclosed, the semiconductor device may be composed by including a trench-gate-type n channel vertical IGBT, etc.
• FIG. 29 shows a schematic cross-sectional structure of anSiC MISFET110 including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device applicable to thepower modules20 and20T according to the embodiments.
• InFIG. 29, the gate pad electrode GP is connected to thegate electrode138 disposed on thegate insulating film132, and the source pad electrode SP is connected to thesource electrode134 connected to thesource region130 and thep body region128. Moreover, as shown inFIG. 29, the gate pad electrode GP and the source pad electrode SP are disposed on aninterlayer insulating film144 for passivation which covers the surface thereof.
• In addition, microstructural transistor structure may be formed in thesemiconductor substrate126 below the gate pad electrode GP and the source pad electrode SP in the same manner as the center portion shown inFIG. 28A or 29.
• Furthermore, as shown inFIG. 29, the source pad electrode SP may be disposed to be extended onto theinterlayer insulating film144 for passivation, also in the transistor structure of the center portion.
• FIG. 30 shows a schematic cross-sectional structure of anIGBT110A including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device applied to thepower modules20 and20T according to the embodiments.
• InFIG. 30, the gate pad electrode GP is connected to thegate electrode138 disposed on thegate insulating film132, and the emitter pad electrode EP is connected to theemitter electrode134E connected to theemitter region130E and thep body region128. Moreover, as shown inFIG. 30, the gate pad electrode GP and the emitter pad electrode EP are disposed on aninterlayer insulating film144 for passivation which covers the surface thereof.
• In addition, microstructural IGBT structure may be formed in thesemiconductor substrate126 below the gate pad electrode GP and the emitter pad electrode EP in the same manner as the center portion shown inFIG. 28B or 30.
• Furthermore, as shown inFIG. 30, the emitter pad electrode EP may be disposed to be extended onto theinterlayer insulating film144 for passivation, also in the IGBT structure of the center portion.
—SiC DIMISFET—
• FIG. 31 shows a schematic cross-sectional structure of anSiC DIMISFET110, which is an example of a semiconductor device which can be applied to thepower module20T according to the embodiments.
• As shown inFIG. 31, the SiC DIMISFET applicable to thepower module20T according to the embodiments includes: asemiconductor substrate126 composed by including an n⁻type high resistivity layer;a p body region128 formed on a front surface side of thesemiconductor substrate126; an n⁺ source region130 formed on a front side surface of thep body region128; agate insulating film132 disposed on a front side surface of thesemiconductor substrate126 between thep body regions128; agate electrode138 disposed on thegate insulating film132; asource electrode134 connected to thesource region130 and thep body region128; an n⁺ drain region124 disposed on a back side surface opposite to the surface of thesemiconductor substrate126; and adrain electrode136 connected to the n⁺type drain area124.
• InFIG. 31, thep body region128 and the n⁺ source region130 formed on the front side surface of thep body region128 are formed with double ion implantation (DI), and the source pad electrode SP is connected to thesource region130 and thesource electrode134 connected to thep body region128. Moreover, a gate pad electrode GP (not shown) is connected to thegate electrode138 disposed on thegate insulating film132. Moreover, as shown inFIG. 31, the source pad electrode SP and the gate pad electrode GP (not shown) are disposed on aninterlayer insulating film144 for passivation configured to cover the front side surface thereof.
• As shown inFIG. 31, in theSiC DIMISFET110, since a depletion layer as shown with the dashed lines is formed in thesemiconductor substrate126 composed of a n⁻type high resistivity layer inserted into thep body regions128, channel resistance RJ_FETaccompanying the junction type FET (JFET) effect is formed. Moreover, as shown inFIG. 31, body diodes BD are respectively formed between thep body regions128 and thesemiconductor substrates126.
—SiC TMISFET—
• FIG. 32 shows a schematic cross-sectional structure of anSiC TMISFET110, which is an example of a semiconductor device which can be applied to thepower module20T according to the embodiments.
• As shown inFIG. 32, the SiC TMISFET applicable to thepower circuit20T according to the embodiments includes: asemiconductor substrate126N composed by including an n layer;a p body region128 formed on a front surface side of thesemiconductor substrate126N; an n⁺ source region130 formed on a front side surface of thep body region128; a trench gate electrode138TG passing through thep body region128, the trench gate electrode138TG formed in the trench formed up to thesemiconductor substrate126N via thegate insulating layer132 and theinterlayer insulating films144U and144B; asource electrode134 connected to thesource region130 and thep body region128; an n⁺type drain area124 disposed on a back side surface of thesemiconductor substrate126N opposite to the front side surface thereof; and adrain electrode136 connected to the n⁺type drain area124.
• InFIG. 32, a trench gate electrode138TG passing through thep body region128 is formed in the trench formed up to thesemiconductor substrate126N via thegate insulating layer132 and theinterlayer insulating films144U and144B; and the source pad electrode SP is connected to thesource region130 and thesource electrode134 connected to thep body region128. A gate pad electrode GP (not shown) is connected to thegate electrode138 disposed on thegate insulating film132. Moreover, as shown inFIG. 32, the source pad electrode SP and the gate pad electrode GP (not shown) are disposed on aninterlayer insulating film144U for passivation configured to cover the front side surface thereof.
• In the SiC TMISFET, channel resistance RJ_FETaccompanying the junction type FET (JFET) effect as the SiC DIMISFET is not formed. Moreover, body diodes BD are respectively formed between thep body regions128 and thesemiconductor substrates126N, in the same manner asFIG. 31.
(Application Examples for Applying Power Module)
• FIG. 33A shows an example of a circuit configuration in which the SiC MISFET is applied as a semiconductor device, and a snubber capacitor C is connected between the power terminal PL and the earth terminal (ground terminal) NL, in a circuit configuration of a three-phase AC inverter140 composed using thepower module20T according to the embodiments.
• Similarly,FIG. 33B shows an example of a circuit configuration in which the IGBT is applied as a semiconductor device, and a snubber capacitor C is connected between the power terminal PL and the earth terminal (ground terminal) NL, in a circuit configuration of a three-phase AC inverter140A composed using thepower module20T according to the embodiments.
• When connecting thepower module20T according to the embodiments to the power source E, large surge voltage Ldi/dt is produced by an inductance L included in a connection line due to a high switching speed of the SiC MISFET and IGBT. For example, the surge voltage Ldi/dt is expressed as follows: Ldi/dt=3×10⁹(A/s), where a current change di=300 A, and a time variation accompanying switching dt=100 ns.
• Although a value of the surge voltage Ldi/dt changes dependent on a value of the inductance L, the surge voltage Ldi/dt is superimposed on the power source E. Such a surge voltage Ldi/dt can be absorbed by the snubber capacitor C connected between the power terminal PL and the earth terminal (ground terminal) NL.
(Concrete Examples for Applying Power Module)
• Next, there will now be explained the three-phase AC inverter140 composed using thepower module20T according to the embodiments to which the SiC MISFET is applied as the semiconductor device, with reference toFIG. 34.
• As shown inFIG. 34, the three-phase AC inverter140 includes agate drive unit150, apower module unit152 connected to thegate drive unit150, and a three-phaseAC motor unit154. U-phase, V-phase, and W-phase inverters are respectively connected to the three-phase AC motor unit54 so as to correspond to U phase, V phase, and W phase of the three-phaseAC motor unit154, in thepower module unit152.
• In this case, thegate drive unit150 is connected to the SiC MISFETs Q1 and Q4, SiC MISFETs Q2 and Q5, and the SiC MISFETs Q3 and Q6.
• Thepower module unit152 includes the SiC MISFETs (Q1 and Q4), (Q2 and Q5), and (Q3 and Q6) having inverter configurations connected between a positive terminal (+) and a negative terminal (−) to which theconverter148 in a power supply or a storage battery (E)146 is connected. Moreover, flywheel diodes D1-D6 are respectively connected reversely in parallel between the source and the drain of the SiC MISFETs Q1-Q6.
• Next, there will now be explained the three-phase AC inverter140A composed using thepower module20T according to the embodiments to which the IGBT is applied as the semiconductor device, with reference toFIG. 35.
• As shown inFIG. 35, the three-phase AC inverter140A includes agate drive unit150A, apower module unit152A connected to thegate drive unit150A, and a three-phaseAC motor unit154A. U-phase, V-phase, and W-phase inverters are respectively connected to the three-phaseAC motor unit152A so as to correspond to U phase, V phase, and W phase of the three-phaseAC motor unit154A, in thepower module unit152A.
• In this case, thegate drive unit150A is connected to the IGBTs Q1 and Q4, IGBTs Q2 and Q5, and the IGBTs Q3 and Q6.
• Thepower module unit152A includes the IGBTs (Q1 and Q4), (Q2 and Q5), and (Q3 and Q6) having inverter configurations connected between a positive terminal (+) and a negative terminal (−) to which theconverter148A in a storage battery (E)146A is connected. Moreover, flywheel diodes D1-D6 are respectively connected reversely in parallel between the emitter and the collector of the IGBTs Q1-Q6.
• Thepower module20T according to the embodiments can be formed as any one selected from the group consist of 1-in-1 module, 2-in-1 module, 4-in-1 module, 6-in-1 module, and 7-in-1 module.
• As explained above, according to the embodiments, there can be provided: the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability; and the inverter equipment on which such a power module is mounted, also when adopting the transfer-mold type power module.
Other Embodiments
• As explained above, the embodiments have been described, as a disclosure including associated description and drawings to be construed as illustrative, not restrictive. This disclosure makes clear a variety of alternative embodiments, working examples, and operational techniques for those skilled in the art.
• Such being the case, the embodiments cover a variety of embodiments and the like, whether described or not.
INDUSTRIAL APPLICABILITY
• The power module according to the embodiments can be used for manufacturing techniques for power modules, e.g. IGBT modules, diode modules, MIS modules (Si, SiC, GaN), and the like, and can be applied to wide applicable fields, e.g. inverters for HEV/EV, inverter and converters for industrial applications, etc.

Claims (23)

What is claimed is:

1. A power module comprising:

a first metallic pattern;

a plurality of power devices configured to be bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern;

a frame member disposed so as to collectively enclose a predetermined number of the plurality of the power devices on the first metallic pattern;

a second metallic pattern disposed outside the frame member; and

a resin layer configured to seal the plurality of the power devices, the first metallic pattern, and the second metallic pattern so as to include the frame member, wherein

the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices.

2. The power module according toclaim 1, wherein

a coefficient of thermal expansion of the frame member is smaller than the coefficient of thermal expansion of the metallic pattern.

3. The power module according toclaim 1, wherein

the first metallic pattern is a copper pattern formed on a DBC substrate or a ceramics substrate.

4. The power module according toclaim 3, wherein

the frame member is ceramics, a metal, or a composite material between the ceramics and the metal, a coefficient of thermal expansion of the metal is lower than a coefficient of thermal expansion of the copper pattern.

5. The power module according toclaim 1, wherein

when a value of the coefficient of thermal expansion of the first metallic pattern is 16 ppm/K and a value of the coefficient of thermal expansion of the power device is 3 ppm/K, the frame member has a value of a coefficient of thermal expansion within a range of 2 ppm/K to 10 ppm/K.

6. The power module according toclaim 1, wherein

the frame member is disposed along an edge of the first metallic pattern.

7. The power module according toclaim 1, wherein

the frame member is disposed an inner side than an edge of the first metallic pattern.

8. The power module according toclaim 1, wherein

a planar view shape of the frame members is a rectangle shape; a circular shape; or a shape of a plurality of lines in parallel so as to sandwich the power device.

9. The power module according toclaim 1, wherein

a surface roughening process is applied to a front side surface of the frame member.

10. The power module according toclaim 1, wherein

a thickness of the frame member is substantially the same as a thickness of the first metallic pattern.

11. The power module according toclaim 1, wherein

a thickness of the frame member is thicker than the thickness of the power device.

12. The power module according toclaim 1, further comprising

a first block terminal electrode, one end of the first block terminal electrode being connected to an electrode of the power device, and the other end of the first block terminal electrode being connected to the second metallic pattern so as to get over the frame member.

13. The power module according toclaim 11, further comprising:

a relaying substrate disposed inside the frame member, the relaying substrate connected by a wire to an electrode of the power device; and

a second block terminal electrode, one end of the second block terminal electrode being connected to the relaying substrate, and the other end of the second block terminal electrode being connected to the second metallic pattern so as to get over the frame member.

14. The power module according toclaim 1, further comprising

an insulating mounting substrate, wherein

the first metallic pattern and the second metallic pattern are disposed on the mounting substrate.

15. The power module according toclaim 14, further comprising

a heat sink, wherein

the mounting substrate is disposed on the heat sink.

16. The power module according toclaim 15, wherein

the mounting substrate further comprises a third metallic pattern, the third metallic pattern disposed on a surface opposite to a surface where the first metallic pattern is disposed, and

the third metallic pattern is connected to the heat sink.

17. The power module according toclaim 14, wherein

the resin layer covers a side surface of the mounting substrate.

18. The power module according toclaim 1, wherein

a value of a coefficient of thermal expansion of the resin layer is within a range of 12 ppm/K to 14 ppm/K.

19. The power module according toclaim 1, wherein

the power device comprises one semiconductor chip selected from the group consisting of semiconductor chips of IGBT, diode, Si based MISFET, SiC based MISFET, and GaNFET.

20. The power module according toclaim 1, wherein

the first metallic pattern is one substrate selected from the group consisting of a DBA substrate and an AMB substrate.

21. The power module according toclaim 1, wherein

a cross-sectional structure of the frame member has one structure selected from the group consisting of an I-shaped structure, a T-shaped structure, an inverted-L-shaped structure, and Γ-shaped structure.

22. Inverter equipment comprising

a circuit in which a plurality of switching elements are connected in series between power terminals and a connection unit of the plurality of the switching elements is used as an output, wherein

the inverter equipment is configured to mount at least one power module according toclaim 1 as the switching elements.

23. The inverter equipment according toclaim 22, wherein

the plurality of the switching elements are connected to an external terminal, via respective pillar electrodes bonded to respective upper surfaces thereof and an upper surface plate electrode configured to commonly connect the pillar electrode predetermined.

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