US20170287791A1 - Controlling dry etch process characteristics using waferless dry clean optical emission spectroscopy - Google Patents

Abstract

Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.

Description

RELATED APPLICATIONS
• This application is based on and claims priority to U.S. Provisional Patent Application No. 61/316,021, entitled “METHOD FOR CONTROLLING DRY ETCH PROCESS CHARACTERISTICS USING WAFERLESS DRY CLEAN OPTICAL EMISSION SPECTROSCOPY” (Ref. No. TEA-136US1-PRO), filed on Mar. 31, 2016.
BACKGROUND
• One of the problems with dry etch processes for via and trench features is the variation in the etch profile during the processing of a full lot of wafers. This may be due to the build-up of carbon (C) and fluorine (F) (collectively referred to as CF)-based etch gas constituents used for passivation and etch selectivity, which are used to form specific etch profiles for patterned wafers in semiconductor processing. If these constituents are not effectively removed from the chamber to the same degree during dry clean cycles between wafers, polymer deposition can accumulate in a chamber leading to the build-up of a film layer which can lead to particle formation and peeling, and can generate defects and device failure on a wafer. In addition, ineffective or inconsistent waferless dry cleaning (WLDC) of the chamber between device wafers, can lead to varying residual CF constituents in the chamber, which subsequently are introduced during a successive dry etch process of a device wafer that affects the uniformity of etch profile characteristics from one wafer lot to the next. The wafers making up a lot.
SUMMARY OF INVENTION
• This invention relates to the optimization of a waferless dry clean (WLDC) process in order to reduce the dry etch wafer-to-wafer process variation of patterned device wafers of a lot. Optical Emission Spectroscopy (OES) is used to monitor light emission from a plasma, such as a dry cleaning process that is performed between each process wafer of a lot, to minimize deposition build-up in a plasma processing chamber. The OES of various constituents, such as chlorine (C) and fluorine (F) being exhausted during a dry clean cycle is indicative of the effectiveness of the cleaning process. The OES of the constituents can be used to gauge and optimize the WLDC process in order to improve etch wafer process control.
BRIEF DESCRIPTION OF THE DRAWINGS
• The detailed description is described with reference to accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components.
• FIG. 1 is a cross-sectional view showing an example schematic configuration of a capacitively coupled plasma (CCP) processing system in accordance with embodiments herein.
• FIG. 2 is an example schematic block diagram of an example plasma processing system implementing optical emission spectroscopy (OES) to determine OES spectra, as part of an overall monitoring system to monitor gas constituents inside the plasma chamber.
• FIG. 3 are example graphs that illustrate a peak in optical emission spectroscopy (OES) spectra of a residual constituent fluorine (F) by-product during a non-optimized WLDC clean process and the constant increase of the amount of the residual constituent over the time period of the dry clean process.
• FIG. 4 is an example flowchart that illustrates a particular dry clean process condition.
• FIG. 5 is a process chart illustrating an example process flow for monitoring and controlling a waferless dry cleaning process in a plasma processing system based on optical emission spectroscopy (OES) as described herein.
• FIG. 6 is an example graph that illustrates optical emission spectroscopy (OES) detection of an endpoint for a residual fluorine (F) by-product constituent during an optimized waferless dry clean associated with clean chamber states.
• FIG. 7 is a process chart illustrating an example process flow for optical emission spectroscopy (OES) process control.
DETAILED DESCRIPTION
• Described herein are architectures, platforms and methods for analyzing residue constituents in a waferless dry clean (WLDC) process, and in particular analysis using Optical Emission Spectroscopy (OES). A process control monitor/metric such as OES can be utilized to analyze the effectiveness of a WLDC process by evaluation of carbon (C) and fluorine (F) based wavelengths in the spectra for a batch of wafers.
• Moreover, a WLDC process can be optimized based on OES spectra of undesirable residue constituents being removed by the dry cleaning process following one particular device wafer process. Typically, an ineffective WLDC process will never show the leveling out in OES intensity for the wavelength examined of a constituent that is intended to be removed by the WLDC. However, the OES spectra of this constituent would show the leveling out in intensity once the endpoint was reached for the WLDC process; this endpoint time can be utilized for determining the ideal completion time for the WLDC process in order to optimize production throughput. In other words, by optimizing the WLDC process (e.g., minimizing the time to perform the WLDC process), optimal usage and production may be realized.
• Wet cleans of a plasma processing chamber may be routinely performed. By optimizing the WLDC process, the time or period between such wet cleans may be also be optimized. Optimization of the herein described parameters for a WLDC process can maximize the time between wet cleans. Furthermore, useful life of components in a plasma processing chamber or system may be prolonged with an optimized WLDC process.
• Furthermore, by reducing the variation in the C and F intensity levels between device wafers collectively for a wafer lot using a more optimal WLDC process, the uniformity of the etch profile characteristics of the wafer lot can be improved. Excess or inconsistent C and F constituents due to an inconsistent WLDC process can cause variations in the subsequent plasma etch performance for patterned device wafers that can lead to an insufficient critical dimension variation across patterned device wafers of a wafer lot.
• OES can be used to optimize the consistency and effectiveness of a WLDC for removing undesirable remnant constituents resulting from a device wafer etch process. Thus, OES of C and F based species in an OES spectra within a wafer lot are directly correlated to key metrics such as the etch profile uniformity of a device wafer lot. In addition, it has been found that bare silicon wafers exposed to the same etch process as a device wafer can be used to optimize the WLDC, since OES shows the same response and trends with respect to adjustment of WLDC process parameters. Examples of process parameters include, but are not limited to radio frequency (RF) or microwave power supplied to a plasma processing chamber of a plasma processing system; RF or microwave power pulse frequency supplied to the plasma processing chamber; RF or microwave pulse duty cycle to the plasma processing chamber; RF power supplied to a substrate holder in the plasma processing chamber; magnetic field of one of more magnets proximate the substrate holder; DC bias of the substrate holder; DC bias voltage supplied to at least one electrode arranged proximate the substrate holder; dry cleaning gas flow rate; wafer chuck temperature, dry cleaning gas pressure; and duration of the waferless dry cleaning process.
• Improvement in a WLDC process for removal of C and F such as using a higher oxygen plasma power may be found between either bare silicon or device wafers based on the resulting OES spectra; allowing optimization of a WLDC process without consuming high-cost device wafers. In certain implementations, a dummy substrate or wafer may be used as described herein. Therefore, an optimal time for a WLDC process may be achieved, where a minimal time is determined for such a WLDC process. Furthermore, an optimal WLDC process can enhance etch profile wafer-to-wafer uniformity for wafer lots.
• It has been found that OES can be used to optimize the consistency and effectiveness of a WLDC for removing undesirable remnant constituents resulting from a device wafer etch process. Thus, OES of C and F constituent spectra within a wafer lot are directly correlated to key metrics such as the wafer-to-wafer etch profile uniformity of a device wafer lot. In addition, it has been found that bare silicon wafers exposed to the same etch process as a device wafer, can be used to optimize the WLDC since OES shows the same response and trend with respect to adjustment of WLDC process parameters including but not limited to gas pressures, gas flows, plasma exposure time, plasma power, bias voltage, and temperature.
• For example, improvement in a WLDC process for the removal of C and F and CF polymer deposition accomplished by using a higher oxygen plasma power may be found both in bare silicon and device wafers based on a resulting OES spectra; allowing optimization of a WLDC process without consuming high-cost device production wafers. Therefore, the use of higher oxygen plasma power accelerates the time (and subsequent wafer output) and lessens the cost for optimization of a WLDC based on OES analysis to determine the optimal WLDC process or device wafers to enhance the wafer-to-wafer etch profile uniformity within the wafer lot. The use of OES spectra analysis may also be found to be indicative of cleaning effectiveness for a wide variety of etch process conditions, as the variation in undesirable remnant species for a batch of wafers can be used to predict changes in the uniformity of subsequently formed etch profiles for multiple wafers within a wafer lot.
• Furthermore, a more effective WLDC process reduces the need for additional bare silicon dummy wafers to be run between device wafers to achieve better etch process control to remove residue accumulating in a chamber or conditioning to stabilize the chamber environment; thus reducing overall process time and cost. In addition an optimal WLDC process that keeps the chamber cleaner long-term lessens the frequency of wet clean preventive maintenance cycles, which ultimately improves chamber utilization and productivity.
• In certain instances, an etch process may introduce a wide variety of gas species into the chamber such as C and F, which ultimately lead to polymer deposition within the plasma processing chamber that can form particles within the plasma processing chamber and on the wafer surface. OES spectra can be collected during the subsequent clean to evaluate the gas species removed from the chamber during a WLDC process that runs in the chamber after processing a device wafer.
• In comparison between a wafer lot having a process with a less effective WLDC process with less effective residual constituent (CF) removal, versus a wafer lot having a more effective WLDC process with more effective residual constituent (CF) removal, the less effective WLDC process may not show a leveling out of OES intensity for the F wavelength examined over WLDC process time. In contrast, the more effective WLDC process can indicate an OES endpoint for this exact same F constituent for all WLDC processes occurring between each device wafer etch process for the lot that could be categorized as a clean condition for the chamber. In addition, particle monitor wafers may be cycled through the plasma processing chamber before and after each wafer lot to analyze particle levels. A long-term benefit of a more effective WLDC process may be seen in reducing increasing trends of particle levels in a chamber, since polymer deposition can accumulate over time leading to peeling from chamber surfaces for an insufficient WLDC.
• For a more effective WLDC process, when using higher oxygen or O2 pressure, higher O2 power and higher bias voltage may significantly improve within-lot etch uniformity. A reduction in the range and standard deviation of the means of the bottom via critical dimension or CD of an etch profile across a lot of wafers may be realized with the more effective WLDC. Furthermore, a wafer lot using this more effective WLDC may also have a lower within-wafer etch uniformity for various CDs such as a bottom via width CD. Particle levels may reduce for the more effective WLDC in addition to less added defects being measured for the wafer lot with the enhanced WLDC process. A need for adding additional bare silicon dummy chamber conditioning wafers to be processed during overall wafer lot processing with a particular recipe may be eliminated, saving on overall wafer lot processing time.
• OES analysis during the WLDC processes running between device wafers for wafer lots may show the more effective WLDC process operating at higher O2 pressure, higher O2 power and with DC bias voltage. A more effective and consistent F removal from the plasma processing chamber, as the main constituent remaining after a device wafer etch process, generated from higher power oxygen radicals and ions, may create a cleaner and more consistent environment in the plasma processing chamber for successive wafers in the wafer lot. The overall within-wafer and within-lot etch uniformity can improve. A one to one correlation may be realized between the reduction of the within-lot F variation in the WLDC OES and the reduction in the standard deviation of the mean bottom CD per wafer in the lot. For example, OES WLDC processes can be used as an in-situ diagnostic to enhance etch process control, when OES WLDC processes are linked with process automation features of plasma processing systems/chambers to optimize etch uniformity in a manufacturing fab.
• In addition, other optical diagnostic methods, such as laser induced fluorescence (LIF), laser interferometry, mass spectrometry, residual gas analysis, FTIR, etc., can be used instead of OES for monitoring the WLDC process with the same or similar outcome.
• FIG. 1 shows a schematic cross-sectional view of an example of a capacitively coupled plasma (CCP) processing apparatus orplasma processing system100 in accordance with embodiments herein. It is to be understood that other processing systems can be implemented, such as radial line slot antenna (RLSA) and inductively coupled plasma (ICP) processing systems may be implemented. In particular implementations, theplasma processing system100 is used for a WLDC process, which may implement an OES spectra analysis of residual constituents, such as C and F. Furthermore, plasma analysis may be performed. In addition, endpoint analysis may be performed. Duration of the WLDC process can be a parameter that may be optimized during a WLDC process using OES data of residual constituents.
• Theplasma processing system100 may be used for multiple operations including ashing, etching, deposition, cleaning, plasma polymerization, plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD) and so forth. Plasma processing can be executed withinplasma processing chamber102, which can be a vacuum chamber made of a metal such as aluminum or stainless steel. Theplasma processing chamber102 is grounded such to ground(s)104. Theplasma processing chamber102 defines a processing vessel providing aprocess space PS106 for plasma generation. An inner wall of theplasma processing chamber102 can be coated with alumina, yttria, or other protectant. Theplasma processing chamber102 can be cylindrical in shape or have other geometric configurations.
• At a lower, central area within theplasma processing chamber102, a substrate holder or susceptor108 (which can be disc-shaped) can serve as a mounting table on which, for example, asubstrate W110 to be processed (such as a semiconductor wafer) can be mounted.Substrate W110 can be moved into theplasma processing chamber102 through loading/unloadingport112 andgate valve114.Susceptor108 forms part of a lower electrode116 (lower electrode assembly) as an example of a second electrode acting as a mounting table for mountingsubstrate W110 thereon. Specifically, thesusceptor108 is supported on asusceptor support118, which is provided at substantially a center of the bottom ofplasma processing chamber102 via an insulatingplate120. Thesusceptor support118 can be cylindrical. Thesusceptor108 can be formed of, e.g., an aluminum alloy.Susceptor108 is provided thereon with an electrostatic chuck122 (as part of the lower electrode assembly116) for holding thesubstrate W110. Theelectrostatic chuck122 is provided with anelectrode124.Electrode124 is electrically connected to DC power source126 (direct current power source). Theelectrostatic chuck122 attracts thesubstrate W110 thereto via an electrostatic force generated when DC voltage from theDC power source126 is applied to theelectrode124. DC bias of the substrate holder orsusceptor108, and DC bias voltage supplied to at least one ofelectrodes116 and124, can be parameters that may be optimized during a WLDC process using OES data of residual constituents.
• Thesusceptor108 can be electrically connected with a high-frequency power source130 via amatching unit132. This high-frequency power source130 (a second power source) can output a high-frequency voltage in a range from, for example, 2 MHz to 20 MHz. Applying high frequency bias power causes ions, in the plasma, generated in theplasma processing chamber102, to be attracted tosubstrate W110. Afocus ring134 is provided on an upper surface of thesusceptor108 to surround theelectrostatic chuck122. In addition, RF or microwave power (not shown) may be provided to theplasma processing chamber102. RF or microwave power supplied to the plasma processing chamber; RF or microwave power pulse frequency; RF or microwave pulse duty cycle; and RF power supplied to a substrate holder orsusceptor108, in theplasma processing chamber102 can be parameters that may be optimized during a WLDC process using OES data of residual constituents.
• Aninner wall member136, which can be cylindrical and formed of, e.g., quartz, is attached to the outer peripheral side of theelectrostatic chuck122 and thesusceptor support118. Thesusceptor support118 includes acoolant flow path138. Thecoolant flow path138 communicates with a chiller unit (not shown), installed outside theplasma processing chamber102.Coolant flow path138 is supplied with coolant (cooling liquid or cooling water) circulating through corresponding lines. Accordingly, a temperature of thesubstrate W110 mounted on/above thesusceptor108 can be accurately controlled. Agas supply line140, which passes through thesusceptor108 and thesusceptor support118, is configured to supply heat transfer gas to an upper surface of theelectrostatic chuck122. A heat transfer gas (also known as backside gas) such as helium (He) can be supplied between thesubstrate W110 and theelectrostatic chuck122 via thegas supply line140 to assist inheating substrate W110.
• Anexhaust path142 can be formed along an outer periphery ofinner wall member136 and an inner sidewall surface of theplasma processing chamber102. An exhaust port144 (or multiple exhaust ports) is provided in a bottom portion of theexhaust path142. Agas exhaust unit146 is connected to each exhaust port viagas exhaust line148. Thegas exhaust unit146 can include a vacuum pump such as a turbo molecular pump configured to decompress the plasma processing space within theplasma processing chamber102 to a desired vacuum condition. Thegas exhaust unit146 evacuates the inside of theplasma processing chamber102 to thereby depressurize an inner pressure thereof up to a desired degree of vacuum.
• An upper electrode150 (that is, an upper electrode assembly), is an example of a first electrode and is positioned vertically above thelower electrode116 to face thelower electrode116 in parallel. The plasma generation space orprocess space PS106 is defined between thelower electrode116 and theupper electrode150. Theupper electrode150 includes an innerupper electrode152 having a disk shape, and an outerupper electrode154 can be annular and surrounding a periphery of the innerupper electrode152. The innerupper electrode152 also functions as a processing gas inlet for injecting a specific amount of processing gas into theprocess space PS106 abovesubstrate W110 mounted on thelower electrode116.
• More specifically, the innerupper electrode152 includes electrode plate156 (which is typically circular) havinggas injection openings158. Innerupper electrode152 also includes anelectrode support160 detachably supporting an upper side of theelectrode plate156. Theelectrode support160 can be formed in the shape of a disk having substantially a same diameter as the electrode plate156 (whenelectrode plate156 is embodied as circular in shape). In alternative embodiments,electrode plate156 can be square, rectangular, polygonal, etc. Theelectrode plate156 can be formed of a conductor or semiconductor material, such as Si, SiC, doped Si, Aluminum, and so forth. Theelectrode plate156 can be integral withupper electrode150 or detachably supported byelectrode support160 for convenience in replacing a given plate after surface erosion. Theupper electrode150 can also include a cooling plate or cooling mechanism (not shown) to control temperature of theelectrode plate156.
• Theelectrode support160 can be formed of, e.g., aluminum, and can include abuffer chamber162.Buffer chamber162 is used for diffusing process gas and can define a disk-shaped space. Processing gas from a processgas supply system164 supplies gas to theupper electrode150. The processgas supply system164 can be configured to supply a processing gas for performing specific processes, such as film-forming, etching, and the like, on thesubstrate W110. The processgas supply system164 is connected with agas supply line166 forming a processing gas supply path. Thegas supply line166 is connected to thebuffer chamber162 of the innerupper electrode152. The processing gas can then move from thebuffer chamber162 to thegas injection openings158 at a lower surface thereof. A flow rate of processing gas introduced into thebuffer chamber162 can be adjusted by, e.g., by using a mass flow controller. Further, the processing gas introduced is uniformly discharged from thegas injection openings158 of the electrode plate156 (showerhead electrode) to theprocess space PS106. The innerupper electrode152 then functions in part to provide a showerhead electrode assembly. Dry cleaning gas flow rate, and dry cleaning gas pressure can be parameters that may be optimized during a WLDC process using OES data of residual constituents. Dry cleaning gases can include oxygen, an oxygen-containing gas, HCl, F2, C12, hydrogen, nitrogen, argon, SF6, C2F6, NF3, CF4, or a mixture of two or more of such gases.
• A dielectric168, having a ring shape, can be interposed between the innerupper electrode152 and the outerupper electrode154. Aninsulator170, which can be a shield member having a ring shape and being formed of, e.g., alumina, is interposed between the outerupper electrode154 and an inner peripheral wall of theplasma processing chamber102 in an air tight manner.
• The outerupper electrode154 is electrically connected with a high-frequency power source172 (first high-frequency power source) via apower feeder174, an upperpower feed rod176, and amatching unit178. The high-frequency power source172 can output a high-frequency voltage having a frequency of 13 MHz (megahertz) or higher (e.g. 60 MHz), or can output a very high frequency (VHF) voltage having a frequency of 30-300 MHz. Thispower source172 can be referred to as the main power supply as compared to a bias power supply. Thepower feeder174 can be formed into, e.g., a substantially cylindrical shape having an open lower surface. Thepower feeder174 can be connected to the outerupper electrode154 at the lower end portion thereof. Thepower feeder174 is electrically connected with the lower end portion of the upperpower feed rod176 at the center portion of an upper surface thereof. The upperpower feed rod176 is connected to the output side of thematching unit178 at the upper end portion thereof. Thematching unit178 is connected to the high-frequency power source172 and can match load impedance with the internal impedance of the high-frequency power source172. Note, however, that outerupper electrode154 is optional and embodiments can function with a single upper electrode.
• Power feeder174 can be cylindrical having a sidewall whose diameter is substantially the same as that of theplasma processing chamber102. The ground conductor180 is connected to the upper portion of a sidewall of theplasma processing chamber102 at the lower end portion thereof. The upperpower feed rod176 passes through a center portion of the upper surface of the ground conductor180. An insulating member182 is interposed at the contact portion between the ground conductor180 and the upperpower feed rod176.
• Theelectrode support160 is electrically connected with a lowerpower feed rod184 on the upper surface thereof. The lowerpower feed rod184 is connected to the upperpower feed rod176 via a connector. The upperpower feed rod176 and the lowerpower feed rod184 form a power feed rod for supplying high-frequency electric power from the high-frequency power source172 to theupper electrode150. Avariable condenser186 is provided in the lowerpower feed rod184. By adjusting the capacitance of thevariable condenser186, when the high-frequency electric power is applied from the high-frequency power source160, the relative ratio of an electric field strength formed directly under the outerupper electrode154 to an electric field strength formed directly under the innerupper electrode172 can be adjusted. The innerupper electrode152 of theupper electrode150 is electrically connected with a low pass filter (LPF)188. TheLPF188 blocks high frequencies from the high-frequency power source172 while passing low frequencies from the high-frequency power source130 to ground. A lower portion of the system, thesusceptor108, forming part of thelower electrode120, is electrically connected with a high pass filter (HPF)190. TheHPF190 passes high frequencies from the high-frequency power source172 to ground.
• High-frequency electric power in a range from about 3 MHz to 150 MHz, is applied from the high-frequency power source172 to theupper electrode150. This results in a high-frequency electric field being generated between theupper electrode150 and thesusceptor108 orlower electrode116. Processing gas delivered to processspace PS106 can then be dissociated and converted into a plasma. A low frequency electric power in a range from about 0.2 MHz to 20 MHz can be applied from the high-frequency power source130 to thesusceptor108 forming thelower electrode116. In other words, a dual frequency system can be used. As a result, ions in the plasma are attracted toward thesusceptor108, and thus anisotropy of etching is increased by ion assistance. Note that for convenience,FIG. 1 shows the high-frequency power source172 supplying power to theupper electrode150. In alternative embodiments, the high-frequency power source172 can be supplied to thelower electrode116. Thus, both main power (energizing power) and the bias power (ion acceleration power) can be supplied to the lower electrode.
• Components of theplasma processing system100 can be connected to, and controlled by, acontrol unit192, which in turn can be connected to acorresponding storage unit194 anduser interface196. Various plasma processing operations can be executed via theuser interface196, and various plasma processing recipes and operations can be stored instorage unit194. Accordingly, a given substrate can be processed within the plasma processing chamber with various microfabrication techniques. In operation, the plasma processing apparatus uses the upper and lower electrodes to generate a plasma in theprocessing space PS106. This generated plasma can then be used for processing a target substrate (such assubstrate W110 or any material to be processed) in various types of treatments such as plasma etching, chemical vapor deposition, treatment of glass material and treatment of large panels such as thin-film solar cells, other photovoltaic cells, and organic/inorganic plates for flat panel displays, etc. In certain implementations described herein, a dummy substrate, which may be a non-production wafer may be used aswafer W110.
• Thecontrol unit192 may include one or more processors, microcomputers, computing units and the like. Thestorage unit194 may include memory, and is an example of non-transitory computer-readable storage media for storing instructions which are executed by thecontrol unit192, to perform the various functions described herein. For example, thestorage unit194 may generally include both volatile memory and non-volatile memory (e.g., RAM, ROM, or the like). Memory may be referred to as memory or computer-readable storage media herein. Memory is capable of storing computer-readable, processor-executable program instructions as computer program code that may be executed by thecontrol unit190 as a particular machine configured for carrying out the operations and functions described in the implementations herein.
• Memory may further store one or more applications (not shown). The applications may include preconfigured/installed and downloadable applications. In addition, memory may store the OES spectral data used for processes as described herein.
• Theplasma processing system100 can further include aspectrometer198 and awindow199. Thespectrometer196 is used for gathering light used for process endpoint analysis and OES spectra. Thespectrometer198 may be connected to controlunit192, or other controllers/systems.
• FIG. 2 is an example schematic block diagram of an example plasma processing system implementing optical emission spectroscopy (OES) to determine OES spectra, and plasma monitoring. As discussed above, theplasma processing chamber102 provides for theprocessing space PS106 above thesubstrate W110 mounted on thelower electrode116. In a WLDC process to determine and gather OES spectra and/or endpoint calculation of residue constituents (e.g, CF), aproduction substrate W110 may be absent. In other implementations, a dummy or non-production substrate is in place forsubstrate W110.
• In this example, thespectrometer198 collects light, as represented bylight volume200. During the monitoring of OES spectra in a WLDC process,light volume200 provides for the OES spectra data, which can include OES spectra of CF constituents.
• Thespectrometer198 may be part of amonitoring system202. The monitoring system may be part of theplasma processing system100. Themonitoring system202 can be particularly used in plasma monitoring in theplasma processing chamber102. Other example systems and components that can be part ofmonitoring system202, include and are not limited to, an opticalemission spectroscopy system204, laser induced fluorescence system206,laser interferometer208,mass spectrometer210, and Fourier transform infrared (FTIR)system212. In particular, thespectrometer196 can be part of the opticalemission spectroscopy system204. The opticalemission spectroscopy system204 may acquire OES during a WLDC process.
• As discussed, a metric, such as OES spectra can be utilized to analyze the effectiveness of a WLDC process by evaluation of undesirable species or residual constituents, such as wavelengths of C and F constituents in an OES spectra for a batch or lot of wafers. Furthermore, a WLDC process can be optimized based on OES spectra of undesirable residue constituents being removed by the dry cleaning process following one particular device wafer process (in situ process). Typically, an ineffective WLDC process may not show the leveling out in OES intensity for the wavelength examined of a constituent that is intended to be removed by the WLDC process or even the feed-in dry cleaning gas such as oxygen. However, the OES spectra of this constituent can show the leveling out in intensity once the endpoint was reached for the WLDC process; this endpoint time can be utilized for determining the ideal completion time for the WLDC in order to optimize throughput. By reducing the variation in the C and F intensity levels between device wafers collectively for a lot using a more effective WLDC process, the uniformity of the etch profile characteristics of that lot can be improved such as the bottom via width (bottom critical dimension or CD). Excess or inconsistent CF or carbon densities in a chamber or polymer deposition build-up remaining from an inconsistent WLDC process can cause variations in the subsequent plasma etch performance for patterned device wafers that could lead to critical dimension variation across a lot outside the control limits for manufacturing specifications. These undesirable constituents residing in a chamber can lead to clogging of the features being etched during a subsequent device wafer etch process, which is the build-up of polymer residue in a trench or via feature which prevents uniform etching of a feature profile. Similarly, an accumulation of fluorine by-product in a chamber can lead to an increasing etch rate from one wafer to the next, since it tends to remove sidewall polymer passivation, which ultimately causes an increasing trend toward wider etch profiles. This mechanism was deemed the basis why a more effective WLDC process was found to improve wafer-to-wafer and within-wafer etch profile uniformity as well.
• FIG. 3 shows anexample graph300 that illustrate a peak in OES spectra of a residual constituent, and in particular fluorine (F). The OES spectral peak of fluorine for a particular WLDC is represented by302 ingraph300. Using the intensity vs. time trend of a particular WLDC by-product OES peak such as fluorine, which happens to be shown ingraph304, and implementing an endpoint analysis, a determination may be made as to if and when the residual constituent fluorine levels off or not in a plasma processing chamber. Fluorine residual by-product background build-up within a chamber, as measured by OES, while processing wafers of a wafer lot involving polymer shrink based dry etching may cause an increasing trend in the etch profile width CD, as sidewall polymer is being removed to a higher degree for the same given etch process for consecutively processed device wafers of a lot. An endpoint analysis that may be implemented may be found in U.S. Pat. No. 9,330,990 entitled “METHOD OF ENDPOINT DETECTION OF PLASMA ETCHING PROCESS USING MULTIVARIATE ANALYSIS” which is included in its entirety by reference.
• It is realized that the plasma processing chamber is not absolutely devoid of residual constituents, and an acceptable amount of constituents may reside in the plasma processing chamber.
• FIG. 4 shows anexample chart400 that provides optimized values for a particular dry clean process, such as a WLDC. In this example, OES spectra and endpoint analysis can be collected for residual constituent F. Several acronyms noted include: radical gas-distribution control (RDC) referring to the center to edge gas zone flow ratio/percent, brine or chiller temperature for the plasma system, direct current (DC) electrode voltage, low-frequency (LF) power, high-frequency (HF) power, and advanced temperature controlled chuck (ATCC) temperature in proximity to the substrate or wafer holder.
• A particular process is identified under the heading “Recipe” as represented by402. In this example, a WLDC process is identified as represented by404. Step406 furthers identifies the process as an oxygen (O2) clean408. A pre-set recipe time of20seconds410 is identified as the maximum WLDC process time. Other parameters as shown inchart400 may be identified for this optimized process. Such parameters can include “gas pressure”, “power”, “DC bias”, etc.
• FIG. 5 shows anexample process500 for monitoring and controlling a waferless dry cleaning process in a plasma processing system. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method, or alternate method. Additionally, individual blocks may be deleted from the method without departing from the spirit and scope of the subject matter described herein. Furthermore, the method may be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the invention.
• Atblock502, flowing a dry cleaning gas into a plasma processing chamber is performed. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock504, igniting a plasma in the plasma processing chamber to initiate a waferless dry cleaning (WLDC) process is performed. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock506, acquiring optical emission spectra (OES) data is performed. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100. In addition, in reference toFIG. 2 above, this block may be performed by the opticalemission spectroscopy system204. In other implementations, the acquiring may be a monitoring act that monitors the plasma in theplasma processing chamber102.
• Atblock508, optimizing at least one parameter of the WLDC process based on the acquired OES data. The parameters may be those described above. In addition, the parameters may be optimized in-situ or ex-situ.
• FIG. 6 shows anexample graph600 of optical emission spectroscopy (OES) detection of a residual constituent for an optimized WLDC condition. The residual constituent F is represented by theOES peak602. OES analysis is performed on residual constituent F as described herein indicating an OES endpoint by virtue of the leveling in intensity over time for this by-product. An array of OES endpoint time values604 when the residual constituent F intensity stabilizes were found with steadily shorter times as the WLDC cleaned the chamber more and more of residual etch by-products such as fluorine over the course of wafer lot processing. These values may be used as the duration as to when a WLDC process (i.e., recipe) ends. The total variation in OES intensity of this F peak at the end of the optimized WLDC condition process time is reduced by 50 percent compared to the non-optimized WLDC OES spectra noted inFIG. 3; which subsequently led to over 50 percent less wafer-to-wafer via CD width variation across the lot.
• FIG. 7 shows anexample process700 for optical emission spectroscopy (OES) process control. In particular, theprocess700 may be used for dry etch process control.Process700 can be considered an in situ process, wherein in feedback may be sent to a plasma processing system, as described in reference toFIG. 1. Adjustment may be performed based on the determined feedback data.
• The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method, or alternate method. Additionally, individual blocks may be deleted from the method without departing from the spirit and scope of the subject matter described herein. Furthermore, the method may be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the invention.
• Atblock702, a production process of a wafer lot is performed. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock704, a WLDC and OES trace data collection as described herein is performed. In reference toFIG. 1 andFIG. 2 above, this block may be performed by the described components ofplasma processing system100, andmonitoring system200.
• Atblock706, the production process of a wafer lot is continued. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock708, a WLDC and OES trace data collection as described herein is performed. In reference toFIG. 1 andFIG. 2 above, this block may be performed by the described components ofplasma processing system100, andmonitoring system200.
• Atblock710, an in situ OES data analysis is performed. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• At block712, data/signals are sent to the plasma processing system (i.e., controllers), to determine whether to adjust a WLDC process parameter based on OES intensity of the selected by-product (i.e., residual constituent) or cleaning feed gas wavelength.
• Atblock714, the production process of a wafer lot is continued. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock716, an adjustment to the WLDC process parameters may be performed. Alternatively, the same parameters may be used. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock718, the production process of a wafer lot is continued. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.
• Atblock720, the sequence is iterated until the wafer lot production is complete. In reference toFIG. 1 above, this block may be performed by the described components ofplasma processing system100.

Claims (20)

What is claimed is:

1. An in situ method of monitoring and controlling a waferless dry cleaning (WLDC) process in a plasma processing tool, the method comprising:

initiating a production process of a wafer lot;

collecting in-situ monitoring data during the production process;

performing in-situ data analysis of the wafer lot; and

adjusting parameters of the WLDC process based on the in-situ monitoring data.

2. The method ofclaim 1, wherein the in-situ monitoring data is collected by performing a method comprising:

flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system;

igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process; and

monitoring the plasma in the plasma processing chamber during the waferless dry cleaning process using a monitoring system,

wherein the monitoring system comprises an optical emission spectroscopy system, a laser induced fluorescence system, a laser interferometer, a residual gas analyzer, a mass spectrometer, or a Fourier Transform Infrared (FTIR) system.

3. The method ofclaim 1, wherein the plasma processing tool is a plasma etching system.

4. The method ofclaim 1, wherein the plasma processing tool is a plasma deposition system.

5. The method ofclaim 1, wherein the monitoring the plasma acquires optical emission spectra is performed during the waferless dry cleaning process absent production substrates present in the plasma processing chamber.

6. The method ofclaim 5, wherein the acquiring of optical emission spectra is performed with dummy substrates placed in the plasma processing chamber.

7. The method ofclaim 5, further comprising:

optimizing at least one parameter of the waferless dry cleaning process based on the acquired optical emission spectra.

8. The method ofclaim 7, wherein the at least one parameter of the waferless dry cleaning process is selected from the group consisting of:

radio frequency (RF) or microwave power supplied to the plasma processing chamber;

RF or microwave power pulse frequency;

RF or microwave pulse duty cycle;

RF power supplied to a substrate holder in the plasma processing chamber;

magnetic field of one of more magnets proximate the substrate holder;

direct current (DC) bias of the substrate holder;

DC bias voltage supplied to at least one electrode arranged proximate the substrate holder;

dry cleaning gas flow rate;

dry cleaning gas pressure; and

duration of the waferless dry cleaning process.

9. The method ofclaim 7, wherein the optimization of the at least one parameter of the waferless dry cleaning process is performed to maximize the time between wet cleans of the plasma processing chamber.

10. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed to minimize the duration of the waferless dry cleaning process.

11. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed to maximize the lifetime of a component of the plasma processing chamber.

12. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed to minimize particle generation in the plasma processing chamber.

13. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed to maximize critical dimension (CD) uniformity of a subsequently processed production substrate or lot of production substrates.

14. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed using optical emission spectra acquired with dummy substrates placed in the plasma processing chamber.

15. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed ex-situ.

16. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed in-situ.

17. The method ofclaim 7, wherein the optimizing of the at least one parameter of the waferless dry cleaning process is performed to minimize the duration of the waferless dry cleaning process.

18. A non-transitory machine-accessible storage medium having instructions stored thereon which cause a data processing system to perform a method for monitoring and controlling a waferless dry cleaning process in a plasma processing tool, the method comprising:

starting a production process of a wafer lot;

gathering in-situ monitoring data during the production process;

analyzing in-situ data of the wafer lot; and

recalculating parameters of the WLDC process based on the in-situ monitoring data.

19. The storage medium ofclaim 18, wherein the method for monitoring and controlling a waferless dry cleaning process in a plasma processing tool further comprises:

optimizing at least one parameter of the waferless dry cleaning process based on the acquired optical emission spectra.

20. The storage medium ofclaim 18, wherein the method for monitoring and controlling a waferless dry cleaning process in a plasma processing tool further comprises:

terminating the waferless dry cleaning process when the acquired optical emission spectra substantially match a predetermined target optical emission spectrum,

wherein the target optical emission spectrum is characteristic for a plasma processing chamber in a clean condition.

Images