US20170186837A1 - Deep trench capacitor with scallop profile - Google Patents

Abstract

The present disclosure relates to an integrated chip having a deep trench capacitor with serrated sidewalls defining curved depressions, and a method of formation. In some embodiments, the integrated chip includes a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate. The serrated sidewalls of the layer of conductive material increase a surface area of exterior surfaces of the layer of conductive material, thereby increasing a capacitance of the capacitor per unit of depth

Description

REFERENCE TO RELATED APPLICATION
• This Application claims priority to U.S. Provisional Application No. 62/272,220 filed on Dec. 29, 2015, the contents of which is hereby incorporated by reference in its entirety.
BACKGROUND
• The semiconductor industry has continually tried to decrease the surface area of semiconductor devices to fit more devices on a same substrate size. Vertical device structures can greatly reduce the surface area requirement for a semiconductor device. One type of vertical device that is commonly implemented in integrated chips is deep trench capacitors. Deep trench capacitors comprise one or more capacitor electrodes that extend into a trench within a semiconductor substrate. They can be used for a myriad of purposes, such as decoupling capacitors that are configured to decouple one part of an electrical circuit, such as interconnect, from another part of the circuit, for example.
BRIEF DESCRIPTION OF THE DRAWINGS
• Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
• FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated chip having a deep trench capacitor within a trench comprising serrated sidewalls defining a plurality of curved depressions.
• FIG. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated sidewalls.
• FIG. 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated sidewalls.
• FIGS. 4A-4C illustrate cross-sectional views of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated interior surfaces.
• FIGS. 5-7 illustrate a cross-sectional view of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated interior surfaces.
• FIGS. 8-13 illustrate cross-sectional views of some additional embodiments of a method of forming a deep trench capacitor within a trench having serrated sidewalls.
• FIG. 14 illustrates a flow diagram of some embodiments of a method of forming a deep trench capacitor within a trench having serrated sidewalls.
DETAILED DESCRIPTION
• The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
• Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
• Deep trench capacitors are capacitors that are formed within trenches extending into a semiconductor substrate. Typically, deep trench capacitors are formed by etching the substrate to form a trench, into which a conductive material and a dielectric material are subsequently formed. As the size of integrated chip components decreases, the depth of the deep trenches can cause a number of issues. For example, in multi-tiered three-dimensional integrated chip (3DIC) substrates are often thinned prior to bonding. However, deep trenches may inhibit substrate thinning, thereby increasing the length of inter-tier interconnections between stacked substrates. Furthermore, while the vertical sidewalls of deep trench capacitors allow for the capacitors to scale well, as the distance between the capacitors decreases it results in a weak structural integrity of the substrate along the edge due to decreasing silicon density. The decreased structural integrity can lead to integrated chip failure, which is costly to integrated chip manufacturers.
• The present disclosure relates to an integrated chip having a deep trench capacitor arranged within a trench having serrated sidewalls defining a plurality of curved depressions, and a method of formation. The curved depressions increase a surface area of capacitive electrodes of a deep trench capacitor within the trench, thereby allowing for the capacitor to have a greater capacitance per unit depth. In some embodiments, the integrated chip comprises a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.
• FIG. 1 illustrates a cross-sectional view of some embodiments of an integratedchip100 having adeep trench capacitor101 arranged within a trench comprising serrated sidewalls defining a plurality of curved depressions.
• The integratedchip100 comprises asubstrate102 having a conductive dopedregion104. In some embodiments, thesubstrate102 comprises a semiconductor material (e.g., silicon) having a first doping type (e.g., n-type). The conductive dopedregion104 may have a second doping type (e.g., p-type) that is different than the first doping type. Capacitor components are disposed in atrench106 that extends from anupper surface102uof thesubstrate102 to an underlying location within the conductivedoped region104. Thetrench106 has serrated sidewalls that respectively define a plurality ofcurved depressions108.
• Capacitor components may include a layer ofdielectric material110 is arranged within thetrench106. In some embodiments, the layer ofdielectric material110 may conformally line the serrated sidewalls of thetrench106.Conductive material112 is also arranged within thetrench106. Theconductive material112 has sidewalls comprising a plurality ofcurved protrusions114 facing the serrated sidewalls of thetrench106. In some embodiments, theconductive material112 is vertically and laterally separated from thesubstrate102 by the layer ofdielectric material110.
• In some embodiments, the conductivedoped region104 is configured to act as a first capacitor electrode (E₁) of adeep trench capacitor101. Theconductive material112 is configured to act as a second capacitor electrode (E₂), which is separated from the first electrode (E₁) by the layer ofdielectric material110 to give the deep trench capacitor101 a capacitance C. Since the capacitance C is based upon charges on the first capacitor electrode (E₁) and the second capacitor electrode (E₂), the capacitance C is proportional a surface area of interior surfaces of thetrench106 and a surface area of exterior surfaces of theconductive material112. The serrated sidewalls of thetrench106 and theconductive material112 increase a surface area of the interior surfaces of thetrench106 and the exterior surfaces of theconductive material112, thereby increasing a capacitance of thedeep trench capacitor101 per unit of depth. In other words, the serrated sidewalls allow for thedeep trench capacitor101 to have a same capacitance as a capacitor having smooth sidewalls at a lesser depth. By reducing the depth of thetrench106, thedeep trench capacitor101 can be formed in a shorter time and can be easily integrated into multi-tiered 3DIC structures.
• FIG. 2 illustrates a cross-sectional view of some additional embodiments of an integratedchip200 having a trench comprising serrated sidewalls.
• The integratedchip200 comprises atrench106 that extends from anupper surface102uof asubstrate102 to an underlying position within thesubstrate102. Thetrench106 comprises serrated sidewalls defining a plurality ofcurved depressions108. In some embodiments, the plurality ofcurved depressions108 may comprise arced depressions having substantially arced cross-sections within the sidewall of thetrench106. The arced depressions have a surface area that is proportional to lengths of the arced depressions, so that an arced depression that has an interior surface with an arc length spanning an angle of Φ will have a length204 that is equal to Φ/360°*h*3.14. For example, a semi-circular arced depression with a height h and an arc length spanning 180° (i.e., a half circle) will have a length204 (extending along a side of thetrench106 between points A and B) that is equal to 180°/360°*h*3.14=1.57*h.
• Thecurved depressions108 within the serrated sidewalls increase a sidewall length along a cross-section of thesubstrate102 relative to straight sidewalls. For example, for arced depressions comprising semicircular arced depressions a sidewall of thetrench106 will have a length206 (between points C and D) that is equal to 1.57 times adepth208 of the trench106 (e.g., allowing for a disclosed deep trench capacitor having atrench106 with adepth208 of approximately 19 um to provide for a same capacitance as a deep trench capacitor with straight trench sidewalls having a depth of approximately 30 um). The increasedlength206 increases a capacitance of a deep trench capacitor formed within thetrench106, since the capacitance is defined as: C=ε_rε₀·A/d, where A is an area of overlap of capacitor electrodes, ε_ris the relative static permittivity of a dielectric material between the capacitor electrodes, ε₀is the permittivity of free space (ε₀≈8.854×10⁻¹²F m⁻¹), and d is the distance separating the capacitor electrodes. Thus, the serrated sidewalls allow for a disclosed deep trench capacitor formed within thetrench106 to have a capacitance equal to a capacitor within a trench having straight sidewalls at a smaller trench depth.
• FIG. 3 illustrates a cross-sectional view of some additional embodiments of anintegrated chip300 having a deep trench capacitor within a trench comprising serrated sidewalls.
• Theintegrated chip300 comprises a plurality oftrenches302 respectively extending from anupper surface102uof asubstrate102 to an underlying location within thesubstrate102. In some embodiments, the plurality oftrenches302 may be arranged within a conductivedoped region104. In such embodiments, a layer ofdielectric material304 is arranged within the plurality oftrenches302, and a layer ofconductive material306 is arranged within the plurality oftrenches302 at locations separated from thesubstrate102 by the layer ofdielectric material304.
• The one ormore trenches302 comprisesidewalls302sdefining a plurality of curved depressions. In some embodiments, the one ormore trenches302 also have abottom surface308 comprising a curved profile. The one ormore trenches302 respectively define anopening303 that is arranged along theupper surface102uof thesubstrate102 and an underlying cavity in communication with theopening303. The cavity has a width, extending between opposingsidewalls302s,which generally increases (e.g., from w₂to w₂′) as a distance from theupper surface102uof thesubstrate102 decreases. In some embodiments, the one ormore trenches302 curve inward along top portion thereof (e.g., toward the opening303), so that theopening303 has a first width w₁, while the underlying cavity has second width, w₂or w₂′, that is larger than the first width w₁. The curvature of a trench causes the trench to protrude laterally outward from theopening303, so that thesubstrate102 overhangs the trench along opposing sides.
• In some embodiments, the first width w₁of theopening303 is smaller than the smallest width of the underlying cavity (i.e., w₁<w₂<w₂′). In some embodiments, the width w₂′ may be in a range of between approximately ⅙^thand approximately to 1/7^tha depth d of the one or more trenches302 (e.g., for a trench with a depth d of 19 um, w₂′ may be in a range of between approximately 2.5 um and approximately 3.5 um). In some embodiments, the width w₂may be in a range of between approximately ⅛^thand approximately to 1/9^ththe depth d of the one or more trenches302 (e.g., for a trench with a depth d of 19 um, w₂may be in a range of between approximately 2.0 and approximately 3.0 um). In some embodiments, the width w₁may be in a range of between approximately 1/11^thand approximately to 1/12^ththe depth d of the one or more trenches302 (e.g., for a trench with a depth d of 19 um, w₁may be in a range of between approximately 1.5 um and approximately 2.5 um).
• In some embodiments, thesidewalls302sof the one ormore trenches302 are angled with respect to anormal line310 that is perpendicular to theupper surface102uof thesubstrate102. In some embodiments, sidewall angles of thesidewalls302schange along a depth d of a trench. In some embodiments, the sidewall angles (with respect to normal line310) of thesidewalls302sdecrease as depths of the one ormore trenches302 increase. For example, in some embodiments, upper sections of thesidewalls302sare angled at a first angle Θ₁with respect to thenormal line310 and lower sections of thesidewalls302sare angled at a second angle Θ₂with respect to thenormal line310, wherein the second angle Θ₂is smaller than the first angle Θ₁.
• Althoughintegrated chip300 is illustrated as having a capacitor with an electrode comprising the conductivedoped region104, it will be appreciated that in alternative embodiments the conductivedoped region104 may be omitted. For example, in some alternative embodiments, the plurality oftrenches302 may not be arranged within a conductive doped region. In such embodiments, two or more layers of conductive material may be arranged within respectively ones of the plurality oftrenches302. The two or more layers of conductive material are separated by one or more layers of dielectric material and are configured to act as capacitor electrodes.
• FIGS. 4A-4C illustrate cross-sectional views of some additional embodiments of anintegrated chip400 having a deep trench capacitor within a trench comprising serrated interior surfaces.
• Theintegrated chip400 comprises a plurality oftrenches402 extending into asubstrate102. The plurality oftrenches402 comprise serrated interior surfaces defining a plurality of curved depressions. In some embodiments, the serrated interior surfaces may comprise serrated sidewalls. In some embodiment, the serrated interior surfaces may also comprise abottom surface408 having a curved profile extending between opposing sidewalls of a trench, which defines a plurality of curved depressions (e.g., arced depressions). The curved depressions along thebottom surface408 of the plurality oftrenches402 further increase a surface area of interior surfaces of a trench and a surface area of exterior surfaces of aconductive material306 within the trench.
• In some embodiments, the plurality of curved depressions may have a non-uniform depth along a depth of a trench. For example, in some embodiments, the depths of the plurality of curved depressions into thesubstrate102 may decrease as a distance from anupper surface102uof thesubstrate102 increases. For example, in afirst section404, which is shown inFIG. 4A and also incross-sectional view410 ofFIG. 4B, the curved depressions may have a first depth of d₁. In asecond section406 that is below the first section404 (i.e., that is further from theupper surface102uthan the first section404), the curved depressions may have a second depth of d₂, as shown inFIG. 4A and incross-sectional view412 ofFIG. 4C. The second depth d₂is less than the first depth d₁. For example, in some embodiments, the first depth d₁may be in a range of between approximately 100 nm and approximately 500 nm, while the second depth d₂may be in a range of between approximately 0 nm and approximately 200 nm.
• In some embodiments, as the depths of the curved depressions into thesubstrate102 decrease, a slope of the serrated sidewalls of the plurality oftrenches402 increase (i.e., as a depth of the depressions decreases, the sidewall angle of the serrated sidewalls with respect to a normal line perpendicular to theupper surface102udecreases).
• FIG. 5 illustrates a cross-sectional view of some additional embodiments of anintegrated chip500 having one or more deep trench capacitors within a trench comprising serrated interior surfaces.
• Theintegrated chip500 comprises a plurality oftrenches502 arranged within asubstrate102 and having serrated sidewalls defining a plurality of curved depressions. A first layer ofdielectric material504ais conformally arranged along the serrated sidewalls of the plurality oftrenches502. A first layer ofconductive material506ais conformally arranged along interior sidewalls of the first layer ofdielectric material504a,so that the first layer ofdielectric material504aseparates the first layer ofconductive material506afrom thesubstrate102. A second layer ofdielectric material504bis conformally arranged along interior surfaces of the first layer ofconductive material506a.A second layer ofconductive material506bis conformally arranged along interior sidewalls of the second layer ofdielectric material504b,so that the second layer ofdielectric material504bseparates the first layer ofconductive material506afrom the second layer ofconductive material506b.
• In some embodiments, theintegrated chip500 comprises a firstdeep trench capacitor501aand a seconddeep trench capacitor501b.The deep trench capacitors,501aand501b,respectively have a first electrode E₁comprising the first layer ofconductive material506a,a second electrode E₂comprising the second layer ofconductive material506b,and an intervening capacitor dielectric comprising the second layer ofdielectric material504b.In some embodiments, the first layer ofdielectric material504amay be omitted.
• FIG. 6 illustrates a cross-sectional view of some additional embodiments of anintegrated chip600 having deep trench capacitors within trenches comprising serrated interior surfaces.
• Theintegrated chip600 comprises a plurality oftrenches502 having serrated sidewalls defining a plurality of curved depressions which extend into a conductivedoped region104. A first layer ofdielectric material602ais conformally arranged along the serrated sidewalls of the plurality oftrenches502, and extends outward from the plurality oftrenches502 to locations overlying thesubstrate102. A first layer ofconductive material604ais conformally arranged along interior sidewalls of the first layer ofdielectric material602a,so that the first layer ofdielectric material602aseparates the first layer ofconductive material604afrom thesubstrate102. The first layer ofconductive material604aalso extends outward from the plurality oftrenches502 to locations overlying thesubstrate102 and the first layer ofdielectric material602a.
• In some embodiments, a second layer ofdielectric material602bis conformally arranged along interior sidewalls of the first layer ofconductive material604a,and extends outward from the plurality oftrenches502 to locations overlying thesubstrate102. A second layer ofconductive material604bis conformally arranged along interior sidewalls of the second layer ofdielectric material602b,so that the second layer ofdielectric material602bseparates the second layer ofconductive material604bfrom the first layer ofconductive material604a.The second layer ofconductive material604balso extends outward from the plurality oftrenches502 to locations overlying thesubstrate102.
• A back-end-of-the-line (BEOL) metallization stack is arranged over thesubstrate102. The BEOL metallization stack comprises a plurality of metal interconnect layers arranged within adielectric structure606 having one or more inter-level dielectric (ILD)layer606a-606b.In various embodiments, the one ormore ILD layers606a-606bmay comprise an oxide, an ultra-low k dielectric material, and/or a low-k dielectric material (e.g., SiCO). In some embodiments, the plurality of metal interconnect layers may comprise a firstconductive contact608aand a secondconductive contact608barranged within afirst ILD layer606a.The firstconductive contact608ais electrically coupled to the conductivedoped region104 and the secondconductive contact608bis electrically coupled to the second layer ofconductive material604b,thereby forming two deep trench capacitors arranged in a series connection. The plurality of metal interconnect layers further comprisemetal interconnect wires610 arranged within asecond ILD layer606band electrically coupled to one or more of the conductive contacts608a-608c.In other embodiments, additional contacts may be arranged within thefirst ILD layer606ato form alternative connection types (e.g., parallel connections, decoupled capacitors, etc.).
• FIG. 7 illustrates a cross-sectional view of some additional embodiments of anintegrated chip700 having deep trench capacitors within trenches comprising serrated interior surfaces.
• Theintegrated chip700 comprises a plurality oftrenches402 within asubstrate102, which have serrated sidewalls defining a plurality of curved depressions. A layer ofdielectric material702 is conformally arranged along the serrated sidewalls. The layer ofdielectric material702 extends outward from the plurality oftrenches402 to location overlying thesubstrate102. A layer ofconductive material704 is conformally arranged along interior sidewalls of the layer ofdielectric material702, so that the layer ofdielectric material702 separates the layer ofconductive material704 from thesubstrate102. The layer ofconductive material704 also extends outward from the plurality oftrenches402 to locations overlying thesubstrate102 and the layer ofdielectric material702.
• A plurality of metal interconnect layers are arranged within adielectric structure706 over thesubstrate102. The plurality of metal interconnect layers comprise conductive contacts708a-708carranged within afirst ILD layer706aandmetal interconnect wires710 arranged within asecond ILD layer706bover thefirst ILD layer706a.In some embodiments, the layer ofconductive material704 over thesubstrate102 is laterally separated by thedielectric structure706 to form a first segment ofconductive material704aand a second segment ofconductive material704b.In some such embodiments, a firstconductive contact708ais electrically coupled to conductivedoped region104, a secondconductive contact708bis electrically coupled to the first segment ofconductive material704a,and a thirdconductive contact708cis electrically coupled to the second segment ofconductive material704b,thereby forming two deep trench capacitors arranged in a parallel connection. In other embodiments, additional contacts may be arranged within thefirst ILD layer706ato form alternative connection types (e.g., series connections, decoupled capacitors, etc.).
• FIGS. 8-13 illustrate cross-sectionals views of some embodiments of a method of forming a deep trench capacitor within a trench comprising serrated sidewalls. It will be appreciated that elements inFIGS. 8-13 that have been described in previous embodiments have been designated with the same reference numbers for ease of understanding. While the cross-sectional-views shown inFIGS. 8-13 are described with reference to a method of forming a deep trench capacitor, it will be appreciated that the structures shown in the figures are not limited to the method of formation but rather may stand alone separate of the method.
• As shown incross-sectional view800 ofFIG. 8, a conductivedoped region808 may be formed within asubstrate802. In various embodiments, thesubstrate802 may be any type of semiconductor body (e.g., silicon, SiGe, SOI) such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers associated therewith. In some embodiments, the conductivedoped region808 may be formed by an implantation process that selectively implants thesubstrate802 with a dopant species804 (e.g., boron, phosphorous, arsenic, etc.). In some embodiments, thesubstrate802 may be selectively implanted according to a first masking layer806 (e.g., a photoresist layer, a hard mask layer, etc.). In some embodiments, after the implantation process is completed, thedopant species804 may be driven into thesubstrate802 by a high temperature thermal anneal.
• As shown incross-sectional view900 ofFIG. 9, asecond masking layer902 is formed over thesubstrate802. Thesecond masking layer902 may have one ormore openings904 corresponding to trenches that are to be subsequently formed in thesubstrate802. In some embodiments, the one ormore openings904 may overlie the conductivedoped region808. In other embodiments, the one ormore openings904 may not overlie a conductive doped region. In some embodiments, thesecond masking layer902 may comprise a hardmask layer. In some embodiments, the hardmask layer may comprise a nitride, an oxide, titanium, aluminum, tantalum, zirconium, hafnium, or some combination thereof, for example.
• As shown incross-sectional view1000 ofFIG. 10, one ormore trenches302 are formed within anupper surface102uof thesubstrate102. The one ormore trenches302 may be formed by selectively etching thesubstrate102 with a multi-step etching process. The one ormore trenches302 each define an opening arranged along anupper surface102uof thesubstrate102 and an underlying cavity. The cavity has a width that extends between opposing sidewalls, and which generally increases (e.g., w₂to w₂′) from as a distance from theupper surface102uof thesubstrate102 decreases. In some embodiments, the one ormore trenches302 curve inward along tops of the one ormore trenches302, so that the opening has a first width w₁, while the underlying cavity has a second width, w₂or w₂′, that is larger than the first width w₁.
• Thesecond masking layer902 comprisesserrated sidewall902sdefining a plurality of curved depressions. Openings within thesecond masking layer902 have widths extending between opposingserrated sidewall902s.The widths of the openings generally increase as a distance from anupper surface902uof thesecond masking layer902 decreases. For example, while the width of the openings in thesecond masking layer902 may vary due to the plurality of curved depressions, the width generally increases from a width w₁to a width w₁′ at an overlying position. In some embodiments, the width of the one ormore trenches302 is greater than the width of the openings within thesecond masking layer902 along an interface between thesubstrate102 and thesecond masking layer902.
• In some embodiments, theserrated sidewalls902smay be oriented at a non-zero angle Θ_hwith respect to anormal line310 perpendicular to theupper surface102uof thesubstrate102. The one ormore trenches302 comprise serrated sidewalls that are oriented at a non-zero angle Θ₁with respect to thenormal line310. In some embodiments, the non-zero angle Θ_his larger than the second non-zero angle Θ₁. In some embodiments, the slope of the opposing sidewalls of the one ormore trenches302 may increase (decreasing angle Θ₁with respect to normal line310) as a distance from theupper surface102uof the substrate increases.
• In some embodiments, the multi-step etching process used to form the plurality oftrenches302 may comprise a multi-step dry etch process. The multi-step dry etch process comprises a plurality of cycles that respectively perform steps of exposing the substrate to an etchant to form a curved depression within the substrate and then subsequently forming a protective layer on the substrate. Each of the plurality of cycles forms a curved depression within a sidewall of thesubstrate102. For example, a first cycle forms a first curved depression within a sidewall, a second cycle forms a second curved depression within the sidewall underlying the first curved depression, etc. In some embodiments, the etchant may comprise a dry etchant using an etching chemistry comprising tetrafluoromethane (CF₄), sulfur hexafluoride (SF₆), and/or nitrogen trifluoride (NF₃), for example. In some embodiments, the protective layer may be formed by exposing the substrate to a polymer gas (e.g., C₄F₈). In some embodiments, within a cycle a first gas may be introduced into a processing chamber to perform an etch during a first time period, the processing chamber may be purged, and then a second gas species may be in-situ (i.e., without breaking a vacuum) introduced into the process chamber to form a protective layer during a subsequent time period.
• In some embodiments, thesecond masking layer902 may be removed after the multi-step etching process is completed. In other embodiments (not shown), thesecond masking layer902 may be left in place after the multi-step etching process is completed. In such embodiments, additional layers (e.g., layers of conductive material, layers of dielectric material, ILD layers, etc.) may be subsequently formed over thesecond masking layer902.
• As shown incross-sectional view1100 ofFIG. 11, a layer ofdielectric material1102 is conformally formed along the serrated sidewalls of the one ormore trenches302. Because the layer ofdielectric material1102 is conformally formed along the serrated sidewalls, the layer ofdielectric material1102 also has serrated sidewalls. In various embodiments, the layer ofdielectric material304 may comprise an oxide or a nitride, for example. In some embodiments, the layer ofdielectric material1102 may be formed using a deposition process such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PE-CVD) process, an atomic layer deposition (ALD) process, etc. In other embodiments, the layer ofdielectric material1102 may be formed using a thermal process.
• In some embodiments, the layer ofdielectric material1102 may also be formed along anupper surface102uof thesubstrate102. In some such embodiments, an etching process may be used to pattern the layer ofdielectric material1102 over thesubstrate102. The etching process may comprise forming a masking layer (e.g., a patterned photoresist layer formed using a photolithography process) and then etching the layer ofdielectric material1102 using the masking layer. In some additional embodiments, a planarization process may be performed on the layer ofdielectric material1102 after the deposition is completed. In some embodiments, the planarization process may comprise a chemical mechanical polishing (CMP) process.
• As shown incross-sectional view1200 ofFIG. 12, a layer ofconductive material1202 is conformally formed along the serrated sidewalls of the layer ofdielectric material1102. Because the layer ofconductive material1202 is conformally formed along the serrated sidewalls of the layer ofdielectric material1102, the layer ofconductive material1202 also has serrated sidewalls. In various embodiments, the layer ofconductive material1202 may comprise a metal such as copper, aluminum, tungsten, etc. In other embodiments, the layer ofconductive material1202 may comprise doped polysilicon. In some embodiments, the layer ofconductive material1202 may be formed using a deposition process (e.g., PE-CVD, CVD, PVD, ALD, etc.) and/or a plating process (e.g., electroplating, electro-less plating, etc.).
• In some embodiments, the layer ofconductive material1202 may also be formed over upper surfaces of thesubstrate102 and the layer ofdielectric material1102. In some such embodiments, an etching process may be used to pattern the layer ofconductive material1202. In some additional embodiments, a planarization process (e.g., a CMP process) may be performed on the layer ofconductive material1202 after the deposition is completed.
• As shown incross-sectional view1300 ofFIG. 13, a plurality of conductive contacts1304a-1304bare formed within adielectric structure1302 overlying thesubstrate102. In some embodiments, the plurality of conductive contacts1304a-1304bmay be formed by depositing a first inter-level dielectric (ILD)layer1302aover thesubstrate102. Thefirst ILD layer1302ais selectively etched to form contact holes. The contact holes are then filled with a conductive material (e.g., tungsten) to form the plurality of conductive contacts1304a-1304b.A plurality ofmetal interconnect wires1306 may be subsequently formed in asecond ILD layer1302boverlying thefirst ILD layer1302a.In some embodiments, thefirst ILD layer1302amay be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). T In some embodiments, the plurality of conductive contacts1304a-1304bmay be formed using a deposition process and/or a plating process (e.g., electroplating, electro-less plating, etc.).
• FIG. 14 illustrates a flow diagram of some embodiments of amethod1400 of forming a deep trench capacitor with serrated sidewalls having a plurality of curved surfaces.
• Whilemethod1400 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
• At1402, a conductive doped region may be formed in a substrate, in some embodiments.FIG. 8 illustrates some embodiments of across-sectional view800 corresponding to act1402.
• At1404, the substrate is selectively etched to form a trench having serrated interior surfaces with a scalloped profile defining plurality of curved depressions. In some embodiments, the serrated interior surfaces may comprise sidewalls defining a first plurality of consecutively connected curved depressions. In other embodiments, the serrated interior surfaces may comprise sidewalls defining a first plurality of discrete (i.e., non-consecutive) connected curved depressions. In some embodiments, the serrated interior surfaces may comprise a bottom surface connected between opposing sidewalls and defining a second plurality of curved depressions.FIGS. 9-10 illustrate some embodiments of cross-sectional views,900 and1000, corresponding to act1404.
• At1406, a layer of dielectric material is formed within the trench.FIG. 11 illustrates some embodiments of across-sectional view1100 corresponding to act1406.
• At1408, a layer of conductive material is formed within the trench at a location separated from the substrate by the layer of dielectric material. The layer of conductive material is separated from the conductive doped region by way of the layer of dielectric material so as to form a deep trench capacitor within the trench.FIG. 12 illustrates some embodiments of across-sectional view1200 corresponding to act1408.
• In some embodiments, acts1406 and1408 may be iteratively performed to form a plurality of alternating layers of dielectric material and conductive material. In some embodiments, the plurality of layers of dielectric material and/or conductive material may be a same dielectric material and/or conductive material, while in other embodiments the plurality of layers of dielectric material and/or conductive material may be different dielectric materials and/or conductive materials.
• At1410, a metal interconnect layer is formed in a dielectric structure over substrate. The metal interconnect layer is electrically coupled to one or more layers of the conductive material and/or the conductive doped region.FIG. 13 illustrates some embodiments of across-sectional view1300 corresponding to act1410.
• Therefore, the present disclosure relates an integrated chip having a deep trench capacitor arranged within a trench comprising opposing serrated sidewalls having a plurality of curved surfaces.
• In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls. A layer of conductive material is separated from the substrate by the layer of dielectric material and has sidewalls comprising a plurality of curved protrusions. The layer of dielectric material is configured as capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.
• In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a substrate having a trench comprising serrated interior surfaces, which extends from an upper surface of the substrate to an underlying position within the substrate. The trench defines an opening along the upper surface of the substrate and an underlying cavity having a larger width than the opening. A conductive doped region surrounds the trench. A layer of dielectric material conformally lines the serrated interior surfaces, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material.
• In yet other embodiments, the present disclosure relates to a method of forming a deep trench capacitor. The method comprises selectively etching a substrate to form a trench having serrated interior surfaces defining a plurality of curved depressions. A layer of dielectric material is formed within the trench. The layer of dielectric material conformally lines the serrated interior surfaces. A layer of conductive material is formed within the trench and separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured to act as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.
• The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

What is claimed is:

1. An integrated chip, comprising:

a substrate having a trench with serrated sidewalls defining a plurality of curved depressions;

a layer of dielectric material conformally lining the serrated sidewalls; and

a layer of conductive material separated from the substrate by the layer of dielectric material and having sidewalls comprising a plurality of curved protrusions, wherein the layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.

2. The integrated chip ofclaim 1, wherein a bottom surface of the trench comprises a curved profile extending between the serrated sidewalls.

3. The integrated chip ofclaim 2, wherein the bottom surface comprises one or more curved depressions.

4. The integrated chip ofclaim 1, wherein depths of the plurality of curved depressions into the substrate decrease as a distance from an upper surface of the substrate increases.

5. The integrated chip ofclaim 1,

wherein the trench comprises an opening arranged along an upper surface of the substrate and an underlying cavity in communication with the opening; and

wherein the opening has a smaller width than the underlying cavity.

6. The integrated chip ofclaim 5, wherein the underlying cavity has a width that increases as a distance from the upper surface of the substrate decreases.

7. The integrated chip ofclaim 1, wherein the serrated sidewalls are oriented at a non-zero angle with respect to a normal line perpendicular to an upper surface of the substrate.

8. The integrated chip ofclaim 1, wherein a sidewall angle of the serrated sidewalls changes as a function of a depth of the trench.

9. The integrated chip ofclaim 1, wherein the plurality of curved depressions have depths that are non-uniform along a depth of the trench.

10. The integrated chip ofclaim 9, wherein as the depths of the curved depressions into the substrate decrease as a distance from an upper surface of the substrate increases.

11. The integrated chip ofclaim 10, wherein slopes of the serrated sidewalls increase as the depths of the curved depressions decrease.

12. The integrated chip ofclaim 1, further comprising:

a conductive doped region arranged within the substrate and surrounding the trench, wherein the second electrode comprises the conductive doped region.

13. The integrated chip ofclaim 1, further comprising:

a second layer of dielectric material conformally lining the layer of conductive material; and

a second layer of conductive material conformally lining the second layer of dielectric material, wherein the second electrode comprises the second layer of conductive material.

14. The integrated chip ofclaim 1, further comprising:

a first conductive contact arranged within an inter-level dielectric (ILD) layer and electrically coupled to the first electrode; and

a second conductive contact arranged within the inter-level dielectric (ILD) layer and electrically coupled to second electrode.

15. An integrated chip, comprising:

a substrate having a trench comprising serrated interior surfaces, which extends from an upper surface of the substrate to an underlying position within the substrate, wherein the trench defines an opening along the upper surface of the substrate and an underlying cavity having a larger width than the opening;

a conductive doped region surrounding the trench;

a layer of dielectric material conformally lining the serrated interior surfaces; and

a layer of conductive material arranged within the trench and separated from the substrate by the layer of dielectric material.

16. The integrated chip ofclaim 15, wherein a bottom surface of the trench comprises a curved surface extending between serrated sidewalls of the trench, and having one or more curved depressions.

17. The integrated chip ofclaim 16,

wherein the trench comprises a first serrated sidewall and a second serrated side; and

wherein sidewall angles of the first serrated sidewall and the second serrated sidewall change as a function of a depth of the trench.

18. The integrated chip ofclaim 15, wherein the trench curves inward along a top of the trench so that the substrate overhangs the trench along opposing sides.

19. A method of forming a deep trench capacitor, comprising:

selectively etching a substrate to form a trench having serrated interior surfaces defining a plurality of curved depressions;

forming a layer of dielectric material within the trench, wherein the layer of dielectric material conformally lines the serrated interior surfaces; and

forming a layer of conductive material within the trench and separated from the substrate by the layer of dielectric material, wherein the layer of dielectric material is configured to act as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.

20. The method ofclaim 19, wherein the serrated interior surfaces comprise sidewalls having a first plurality of curved depressions and a bottom surface connecting the sidewalls and having a second plurality of curved depressions.

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