US20170053793A1 - Method and system for sculpting spacer sidewall mask - Google Patents

Abstract

Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.

Description

BACKGROUND OF THE INVENTION
• Field of the Invention
• The present application claims the benefit of U.S. Provisional Patent Application No. 62/205,968, filed on Aug. 17, 2015, entitled “Method and System for Sculpting Spacer Sidewall Mask,” which is incorporated herein by reference in its entirety.
• The invention relates to a method and system of patterning of a film on a substrate and specifically to a method and system of enhancing the structure profile on the substrate to meet patterning objectives.
• Description of Related Art
• In semiconductor manufacturing patterning of a film on a substrate can be achieved through several methods that have evolved with time to follow Moore's law. Double patterning is the technique used to create hard mask features smaller than photolithographic capabilities by using spacer deposition to define feature dimensions. Typical double patterning (DP) techniques require a sequence of deposition over a mandrel, etch to form the spacer and another etch to remove the mandrel, with both deposition and etch tools required. There are some spatial limitations inherent in the conventional DP technique due to deposition ‘thin-ness’ limitations and pitch of the features from mandrel formation limitations.
• Self-aligned double and quadruple patterning and other patterning schemes require a spacer to be formed on the sidewall of a pre-patterned feature. The pre-patterned feature is then removed leaving the spacer as the mask for subsequent patterning. A lot has been done on self-aligned double patterning (SADP) and quadruple patterning (SAQP) for patterning scheme layout but not a lot has been done on focusing and tuning the spacer sidewall mask using reactive ion etch (RIE) for patterning. The spacer sidewall profile has a large impact on subsequent patterning steps in an integration scheme. There is a need for techniques using reactive ion etch to achieve a spacer sidewall mask profile that will help to achieve better profiles in subsequent patterning steps. There is also a need for fabricating a pattern that lands on silicon nitrate without creating a recess on the silicon nitrate, without causing an undercut in the spacer sidewall, and use current gas reactant mixtures to get high selectivity to the silicon nitrate.
SUMMARY OF THE INVENTION
• Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.
BRIEF DESCRIPTION OF THE DRAWINGS
• A more complete appreciation of the invention and many of the attendant advantages thereof will become readily apparent with reference to the following detailed description, particularly when considered in conjunction with the accompanying drawings, in which:
• FIG. 1 is an exemplary schematic of an integration scheme showing the area of interest of the present invention.
• FIG. 2A is an exemplary schematic of the oxide spacer profile of the structures using prior art methods of processing the oxide spacer without using the processes of the present invention,FIG. 2B is an exemplary schematic of the spacer profile fabricated using the present invention techniques and methods, whileFIG. 2C is an exemplary schematic of the mechanism is used to transform parallelogram-shape structures to right trapezoidal-shape structures.
• FIG. 3A is an exemplary schematic of a structure profile where process parameters are adjusted to affect the collision path of the ions in one embodiment of the present invention whereasFIG. 3B is an exemplary schematic of a structure profile fabricated where mask faceting is used to reduce bowing of the structure in one embodiment of the present invention.
• FIG. 4A is an exemplary image of structures in an incoming substrate prior to the sculpting process in an embodiment of the present invention;FIG. 4B is an exemplary image of structures in a substrate after the breakthrough etch process andFIG. 4C is an exemplary image of a substrate after the spacer oxide sculpting process.
• FIG. 5A is another exemplary image of structures in a substrate highlighting the hour-glass shape of the oxide spacer profile of the structure;FIG. 5B is an exemplary image of structures in a substrate after the breakthrough etch process and spacer sculpting process of the present invention highlighting the elimination of the hour glass-shape of the oxide spacer profile.
• FIG. 6A is an exemplary image of structures in a structure in a substrate after a breakthrough etch and sculpting processes and a 37-second main etch using HBr;FIG. 6B is an exemplary image of structures in a substrate after a breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 30-second HBr overetch;FIG. 6C is an exemplary image of structures in a substrate after a breakthrough etch and sculpting processes and a 42-second-main etch using HBr and a 30-second HBr overetch,FIG. 6D is an exemplary image of structures in a substrate after a breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 40-second HBR overetch; andFIG. 6E is an exemplary image of structures in a substrate after a breakthrough etch and sculpting processes and a 37 second main etch using HBr and a 40-second Cl2 overetch.
• FIG. 7A is an exemplary image of structures in a substrate after a breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 30-second HBr overetch where the spacer sidewall process is optimized;FIG. 7B is an exemplary image of structures in a substrate after a breakthrough etch process and the sculpting process is performed at 30 mT;FIG. 7C is an exemplary image of structures in a substrate after a breakthrough etch process and the sculpting process is performed at 500 W low frequency sculpting;FIG. 7D is an exemplary image of structures in a substrate after a breakthrough etch process and sculpting process is performed at 550 W high frequency sculpting; andFIG. 7E is an exemplary image of structures in a substrate after a breakthrough etch process and a sculpting process.
• FIG. 8 is a schematic of how the pitch imbalance is calculated.
• FIG. 9A is an exemplary image of oxide spacer structures prior to a sculpting process,FIG. 9B an exemplary image of oxide spacer structures after the main etch,FIG. 9C an exemplary image of oxide spacer structures after the main etch and over etch, andFIG. 9D is an exemplary image of oxide spacer structures after the main etch, over etch and sculpting in an embodiment of the present invention.
• FIG. 10 is an exemplary flowchart of a method processing an oxide spacer structure using a sculpting process to achieve processing objectives.
• FIG. 11 depicts an exemplary processing system to perform the sculpting process for oxide spacer structures in one embodiment of the present invention.
DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS
• In the following description, for purposes of explanation and not limitation, specific details are set forth, such as a particular geometry of a processing system, descriptions of various components and processes used therein. However, it should be understood that the invention may be practiced in other embodiments that depart from these specific details.
• Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
• Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
• “Substrate” as used herein generically refers to the object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not intended to be limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description below may reference particular types of substrates, but this is for illustrative purposes only and not limitation.
• FIG. 1 is anexemplary schematic100 of an integration scheme showing the area ofinterest120 of the present invention. The integration scheme starts with spaceroxide formation step118 where amandrel112, for example, a carbon mandrel is positioned aboveunderlying layer106 comprising amorphous silicon or a-Si108 layer above asilicon nitride layer104. Above themandrel112 is a conformalspacer oxide layer116 that will be processed with process steps in the area ofinterest120 portions of the integration scheme. Included in the area ofinterest120 are an atomic layer deposition (ALD) spacer oxide etch open step and amandrel removal step126 creating spacer structures124, and apattern transfer step130 onto thea-Si layer108 creatingspacer structures128.
• FIG. 2A is anexemplary schematic200 of the oxide spacer profile of thestructures206 using prior art methods of processing the oxide spacer whereasFIG. 2B is anexemplary schematic250 of the spacer profile when the present invention techniques and methods are used. Referring toFIG. 2A,structures206 such asstructure pair204 have a parallelogram shape. Thefirst structure212 ofstructure pair204 is leaning to the right and asecond structure216 of thestructure pair204 is leaning to the left. Referring toFIG. 2B,structures256 such asstructure pair254 comprises afirst structure262 which is a right trapezoidal shape with the slanted side on the left and asecond structure266 which is a right trapezoidal shape with the slanted side on the right.
• FIG. 2C is anexemplary schematic270 of the mechanism used to transform parallelogram-shape structures to right trapezoidal-shape structures. The gas mixture used to sculpt the oxide spacer that is on top of the amorphous Si film is HBr/CHF3/Ar and will be discussed more in relation to sculpting above. H—Br—C—F—Si—O forms a deposition as the gas etches theamorphous Si272 and theoxide spacer276. Theions274 are in contact with thespacer276 along the side wall of theoxide spacer276 and deposition will depend on the geometry of theoxide spacer276 and the angles of theoxide spacer276. Angles that are greater than 90 degrees, such as angle A, will seeless deposition280 due to less surface coverage for by-product to stick on and more surface coverage forenergetic ion274 sputtering and chemical reaction to remove the by-product. Angles that are less than 90 degrees, such as B, will seemore deposition278 due to more surface coverage for by-product to stick on with less surface coverage for energetic ion sputtering and chemical reaction to remove the by-product. The parallelogram shape structures inFIG. 1A transforms into the right trapezoidal shape structures inFIG. 3C.
• FIG. 3A is anexemplary schematic300 of a structure profile where process parameters are adjusted to affect the collision path of the ions in one embodiment of the present invention. Referring toFIG. 3A,FIG. 3A is anexemplary schematic300 of astructure profile302 where process parameters in the integration scheme are adjusted to affect the collision path of theions324 from anion source312. For example, the pressure inside the chamber and the power applied to theion source312 are adjusted to affect the collision path. A passivation step is added to the process and themask320 is sculpted to reduce the glancingangle332.
• FIG. 3B is anexemplary schematic350 of a structure profile where mask faceting is used to reduce bowing of the structure in one embodiment of the present invention. Referring toFIG. 3B,FIG. 3B is anexemplary schematic350 of astructure profile352 where themask370 height is increased to over 35% of the feature depth. A passivation step is added to the process, the passivation step using a carbon-containing polymer. Another step is performed to increase mask selectivity and themask370 is sculpted to reduce the glancing angle.
• FIG. 4A is anexemplary image400 of incoming structures on a substrate prior to the sculpting process in an embodiment of the present invention. Theimage400displays structures402 above theunderlying layer410. Thefirst structure404 of the structure pair412 has a parallelogram shape that is leaning to right and asecond structure406 of the structure pair412 has a parallelogram shape that is leaning to the left.
• FIG. 4B is anexemplary image430 of structures on a substrate after the breakthrough etch process in an embodiment of the present invention. Theimage430 displays structures432 above the underlying layer440. Thefirst structure434 of the structure pair442 has a trapezoidal shape with the slanted side on the left and a right angle side on the right. Asecond structure438 of the structure pair442 has a trapezoidal shape with the right angle side on the left and the slanted side on the right.
• FIG. 4C is anexemplary image460 of structures in a substrate after the breakthrough etch process where the spacer oxide sculpting process is performed prior to the breakthrough etch process. Theimage460 displays structure pairs472 above the underlying layer470. Thefirst structure464 of the structure pair472 has a trapezoidal shape with the slanted side on the left and a right angle side on the right. Thesecond structure468 of the structure pair472 has a trapezoidal shape with the right angle side on the left and the slanted side on the right. The right angle side of thefirst structure464 and the right angle side of thesecond structure468 are substantially straight and as such, will provide better profile results in subsequent processing of the substrate.
• FIG. 5A is anotherexemplary image500 of structures in a substrate highlighting the hour-glass shape of the oxide spacer profile of the structures522 prior to the performance of the spacer oxide sculpting process. Structure pairs504 above theunderlying layer524 show the hour-glass shapes520 when the spacer oxide sculpting process is not yet performed. The hour-glass shape530 in the structure profile of thestructure pair504 is further reinforced by the measurements made on theimage500 where the top critical dimension (CD)508 is 15.08 nm, themiddle CD512 is 12.70 nm, and thebottom CD516 is 19.05 nm.
• FIG. 5B is anexemplary image550 of structures in a substrate where the spacer sculpting process of the present invention is performed prior to the breakthrough etch process. Structures572 are above theunderlying layer574 highlight the improved profile with a straighter shape580 when the spacer oxide sculpting process is performed. In asingle structure pair554, the straighter shape580 is distinctly highlighted. The overall improvement in structure shapes is further reinforced by the measurements made on theimage550 where the top critical dimension (CD)558 is 18.23 nm, themiddle CD562 is 19.02 nm, and the bottom CD568 is 19.82 nm. The median of the critical dimensions inFIG. 5B are closer to the average CD compared to the corresponding dimensions inFIG. 5A.
• FIG. 6A,FIG. 6B,FIG. 6C,FIG. 6D, andFIG. 6E are exemplary images highlighting the use of spacer sidewall sculpting to avoid causing an undercut (hour glass shape) in the amorphous silicon layers of the substrate and creating a recess into the Si3N4 layers. Referring toFIG. 6A,FIG. 6A is anexemplary image600 ofstructures608 and612 after breakthrough etch and sculpting processes and a 37-second main etch using HBr where the undercut (hour glass shape) of theamorphous silicon layer604 was avoided and no recess in the Si3N4 layer606 was created.
• FIG. 6B is anexemplary image620 of structures in a substrate highlightingadjacent structures628 and632 after breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 30-second HBr overetch, where the undercut (hour glass shape) of theamorphous silicon layer624 was avoided and no recess in the Si3N4 layer626 was created.
• FIG. 6C is anexemplary image640 of structures in a substrate highlightingadjacent structures648 and652 after breakthrough etch and sculpting processes and a 42-second main etch using HBr and a 30-second HBr overetch, where the undercut (hour glass shape) of theamorphous silicon layer644 was avoided and no recess in the Si3N4 layer646 was created.
• FIG. 6D is anexemplary image660 of structures in a substrate highlightingadjacent structures668 and672 after breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 40-second HBR overetch where the undercut (hour glass shape) of theamorphous silicon layer664 was avoided and no recess in the Si3N4 layer666 was created.
• FIG. 6E is anexemplary image680 of structures in a substrate highlightingadjacent structures688 and672 after a breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 40-second Cl2 overetch where the undercut (hour glass shape) of theamorphous silicon layer684 was avoided and no recess in the Si3N4 layer686 was created.
• FIG. 7A,FIG. 7B,FIG. 7C,FIG. 7D, andFIG. 7E are exemplary images of structures in a substrate utilizing a spacer sidewall sculpting process highlighting control of the operating variables used in the breakthrough etch, the main etch, and the overetch processes. Referring toFIG. 7A,FIG. 7A is anexemplary image700 ofadjacent structures708 and712 in a substrate after breakthrough etch and sculpting processes and a 37-second main etch using HBr and a 30-second HBr overetch are performed where selected operating systems variables of the spacer sidewall process are optimized. Thestructures708 and712 are disposed above theamorphous silicon layer704 and the Si3N4 layer706.
• FIG. 7B is anexemplary image720 ofadjacent structures728 and732 in a substrate after breakthrough etch process and the sculpting process are performed at a pressure of about 30 mTorr while the other operating variables are held constant. Thestructures728 and732 are disposed above theamorphous silicon layer724 and the Si3N4 layer726.
• FIG. 7C is anexemplary image740 ofadjacent structures748 and752 in a substrate after breakthrough etch process and the sculpting process are performed at a power of about 500 W low frequency while the other operating variables are held constant. Thestructures748 and752 are disposed above theamorphous silicon layer744 and the Si3N4 layer746.
• FIG. 7D is anexemplary image760 ofadjacent structures772 and774 of a substrate after breakthrough etch process and sculpting process are performed at a power of about 550 W high frequency while the other operating variables are held constant. Thestructures772 and774 are disposed above theamorphous silicon layer764 and the Si3N4 layer766.
• FIG. 7E is anexemplary image780 ofadjacent structures792 and794 after breakthrough etch process and sculpting process are performed while the other operating variables are held constant. Thestructures792 and794 are disposed above theamorphous silicon layer784 and the Si3N4 layer786. The tests conducted using ranges of one or more variables while holding other variables constant indicated that best profile results were obtained using combinations of low pressure, low power applied in the chamber, and high electrostatic chuck (ESC) temperature and these results were better than expected.
• FIG. 8 is a schematic800 of how the pitch imbalance is calculated. Pitch imbalance is an integration scheme metric that is used to measure the integrated results of the various processes as well as the optimization of operating variables in the integration scheme. One objective of the sculpting steps is to minimize the pitch imbalance, i.e., get it as close to zero as much as possible. Pitch imbalance is expressed quantitatively using the following equation:
• 
  Pitch Imbalance=Sum[abs(P1−P2),abs(P2−P3),abs(P3−P4),abs(P4−P1)]  Equation 1.0
• where:
• P1=first spacer CD+first resist mandrel+second spacer CD+second resist mandrel;
• P2=second spacer CD+second resist mandrel+third spacer CD+third resist mandrel;
• P3=third spacer CD+third resist mandrel+fourth spacer CD+fourth resist mandrel; and
• P4=fourth spacer CD+fourth resist mandrel+first spacer CD+first resist mandrel.
• FIG. 9A is anexemplary image900 of pairs of oxide spacer structures, such as904 and908, above anunderlying layer912 after a breakthrough etch but prior to the sculpting process. As expected, the pair ofoxide spacer structures904 and908 had parallelogram shapes.FIG. 9B is anexemplary image920 of pairs of oxide spacer structures, for example,924 and928, above anunderlying layer932 after the sculpting process. The pair ofoxide spacer structures924 and928 had trapezoidal shapes.FIG. 9C depicts anexemplary image940 of pairs of oxide spacer structures, for example,944 and948, above theunderlying layer952 after the main etch. The pair of oxide spacer structures,944 and948, highlights the improved profile as a result of the previous sculpting process. Similarly, inFIG. 9D depicts anexemplary image960 of oxide spacer structures, for example,964 and968, above theunderlying layer972 after the over etch in an embodiment of the present invention. As mentioned above, the pair of oxide spacer structures,964 and968, highlight the improved profile of the structures as a result of the previous sculpting process in the integration scheme.
• FIG. 10 is anexemplary flowchart1000 of a method of processing an oxide spacer structure using a sculpting process to achieve integration objectives. The integration objectives can include fabricating the profile of the structures without an undercut and without a recess in the underlying layer, minimizing pitch imbalance, improving etch uniformity, reducing processing time, and the like. Integration objectives involving the profile of the structures can be measured in the extent of notching or bowing of the structure pair, straightness of the right angle sides of the trapezoidal profile, low the pitch imbalance, high structure uniformity measured by the ratio of top CD to bottom CD and/or ratio of medium CD to bottom CD, and the like.
• Referring toFIG. 10, inoperation1004, a substrate is provided having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer. Inoperation1008, a breakthrough etch process is performed including growth of a conformal native silicon oxide layer by exposing the substrate to oxygen in an atomic layer deposition (ALD) step, creating an ALD patterned structure.
• Inoperation1012, a spacer sidewall sculpting process is performed on the ALD patterned structure. Inoperation1016, an amorphous silicon main etch (ME) process on the ALD patterned structure is performed, the ME process causing a spacer oxide open and carbon mandrel removal, the process creating an ALD spacer oxide pattern.
• Inoperation1020, an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern is performed, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer.
• Inoperation1024, selected two or more integration operating variables in two or more steps involving the breakthrough process, spacer sidewall sculpting process, the amorphous silicon ME process, and the amorphous silicon ME over etch (OE) process are concurrently controlled in order to achieve integration process objectives.
• FIG. 11 depicts an exemplary processing system to perform the sculpting process for an oxide spacer structure in one embodiment of the present invention. Aplasma etching system1100 configured to perform the above identified process conditions is depicted inFIG. 11 comprising aplasma processing chamber1110,substrate holder1120, upon which asubstrate1125 to be processed is affixed, andvacuum pumping system1150.Substrate1125 can be a semiconductor substrate, a wafer, a flat panel display, or a liquid crystal display.Plasma processing chamber1110 can be configured to facilitate the generation of plasma in plasma processing region1145 in the vicinity of a surface ofsubstrate1125. An ionizable gas or mixture of process gases is introduced via agas distribution system1140. For a given flow of process gas, the process pressure is adjusted using thevacuum pumping system1150. Plasma can be utilized to create materials specific to a pre-determined materials process, and/or to aid the removal of material from the exposed surfaces ofsubstrate1125. Theplasma processing system1100 can be configured to process substrates of any desired size, such as 200 mm substrates, 300 mm substrates, or larger.
• Substrate1125 can be affixed to thesubstrate holder1120 via aclamping system1128, such as a mechanical clamping system or an electrical clamping system (e.g., an electrostatic clamping system). Furthermore,substrate holder1120 can include a heating system (not shown) or a cooling system (not shown) that is configured to adjust and/or control the temperature ofsubstrate holder1120 andsubstrate1125. The heating system or cooling system may comprise a re-circulating flow of heat transfer fluid that receives heat fromsubstrate holder1120 and transfers heat to a heat exchanger system (not shown) when cooling, or transfers heat from the heat exchanger system tosubstrate holder1120 when heating. In other embodiments, heating/cooling elements, such as resistive heating elements, or thermo-electric heaters/coolers can be included in thesubstrate holder1120, as well as the chamber wall of theplasma processing chamber1110 and any other component within theplasma processing system1100.
• Additionally, a heat transfer gas can be delivered to the backside ofsubstrate1125 via a backsidegas supply system1126 in order to improve the gas-gap thermal conductance betweensubstrate1125 andsubstrate holder1120. Such a system can be utilized when temperature control of the substrate is required at elevated or reduced temperatures. For example, the backside gas supply system can comprise a two-zone gas distribution system, wherein the helium gas-gap pressure can be independently varied between the center and the edge ofsubstrate1125.
• In the embodiment shown inFIG. 11,substrate holder1120 can comprise anelectrode1122 through which RF power is coupled to the processing plasma in plasma processing region1145. For example,substrate holder1120 can be electrically biased at a RF voltage via the transmission of RF power from aRF generator1130 through an optionalimpedance match network1132 tosubstrate holder1120. The RF electrical bias can serve to heat electrons to form and maintain plasma. In this configuration, the system can operate as a reactive ion etch (RIE) reactor, wherein the chamber and an upper gas injection electrode serve as ground surfaces. A typical frequency for the RF bias can range from about 0.1 MHz to about 110 MHz. RF systems for plasma processing are well known to those skilled in the art.
• Furthermore, the electrical bias ofelectrode1122 at a RF voltage may be pulsed using pulsedbias signal controller1131. The RF power output from theRF generator1130 may be pulsed between an off-state and an on-state, for example. Alternately, RF power is applied to the substrate holder electrode at multiple frequencies. Furthermore,impedance match network1132 can improve the transfer of RF power to plasma inplasma processing chamber1110 by reducing the reflected power. Match network topologies (e.g. L-type, L-type, T-type, etc.) and automatic control methods are well known to those skilled in the art.
• Gas distribution system1140 may comprise a showerhead design for introducing a mixture of process gases. Alternatively,gas distribution system1140 may comprise a multi-zone showerhead design for introducing a mixture of process gases and adjusting the distribution of the mixture of process gases abovesubstrate1125. For example, the multi-zone showerhead design may be configured to adjust the process gas flow or composition to a substantially peripheral region abovesubstrate1125 relative to the amount of process gas flow or composition to a substantially central region abovesubstrate1125.
• Vacuum pumping system1150 can include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to about 8000 liters per second (and greater) and a gate valve for throttling the chamber pressure. In conventional plasma processing devices utilized for dry plasma etching, a 1100 to 3000 liter per second TMP can be employed. TMPs are useful for low pressure processing, typically less than about 50 mTorr. For high pressure processing (i.e., greater than about 110 mTorr), a mechanical booster pump and dry roughing pump can be used. Furthermore, a device for monitoring chamber pressure (not shown) can be coupled to theplasma processing chamber1110.
• As mentioned above, thecontroller1155 can comprise a microprocessor, memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs toplasma processing system1100 as well as monitor outputs fromplasma processing system1100. Moreover,controller1155 can be coupled to and can exchange information withRF generator1130, pulsedbias signal controller1131,impedance match network1132, thegas distribution system1140,vacuum pumping system1150, as well as the substrate heating/cooling system (not shown), the backsidegas supply system1126, and/or theelectrostatic clamping system1128. For example, a program stored in the memory can be utilized to activate the inputs to the aforementioned components ofplasma processing system1100 according to a process recipe in order to perform a plasma assisted process, such as a plasma etch process, onsubstrate1125.
• In addition, theplasma processing system1100 can further comprise anupper electrode1170 to which RF power can be coupled fromRF generator1172 through optionalimpedance match network1174. A frequency for the application of RF power to the upper electrode can range from about 0.1 MHz to about 200 MHz. Additionally, a frequency for the application of power to the lower electrode can range from about 0.1 MHz to about 110 MHz. Moreover,controller1155 is coupled toRF generator1172 andimpedance match network1174 in order to control the application of RF power toupper electrode1170. The design and implementation of an upper electrode is well known to those skilled in the art. Theupper electrode1170 and thegas distribution system1140 can be designed within the same chamber assembly, as shown. Alternatively,upper electrode1170 may comprise a multi-zone electrode design for adjusting the RF power distribution coupled to plasma abovesubstrate1125. For example, theupper electrode1170 may be segmented into a center electrode and an edge electrode.
• Depending on the applications, additional devices such as sensors or metrology devices can be coupled to theplasma processing chamber1110 and to thecontroller1155 to collect real time data and use such real time data to concurrently control two or more selected integration operating variables in two or more steps involving deposition processes, RIE processes, pull processes, profile reformation processes, and/or pattern transfer processes of the integration scheme. Furthermore, the same data can be used to ensure integration targets including patterning uniformity (uniformity), pulldown of structures (pulldown), slimming of structures (slimming), aspect ratio of structures (aspect ratio), line width roughness, line edge roughness, and the like are achieved.
• Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the scope of the general inventive concept.

Claims (21)

What is claimed is:

1. A method of forming a spacer sidewall mask, the method comprising:

providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer;

performing a breakthrough process involving growth of a conformal native silicon oxide layer by exposing the substrate to oxygen in an atomic layer deposition (ALD) step, creating an ALD patterned structure;

performing a spacer sidewall sculpting process on the ALD patterned structure;

performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal, the process creating an ALD spacer oxide pattern, the ALD spacer oxide pattern comprising a first spacer sub-structure having a parallelogram shape leaning to the right and a second spacer sub-structure having a parallelogram shape leaning to the left; and

performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a right angle trapezoidal shape and a second sculpted sub-structure with a left angle trapezoidal shape.

2. The method ofclaim 1 wherein the spacer sidewall sculpting process utilizes HBr/CH₃F/Ar chemicals.

3. The method ofclaim 2 wherein the silicon nitrate layer comprises Si₃N₄.

4. The method ofclaim 3 wherein a glancing angle of the first sculpted pattern is changed by the spacer sculpting process such that subsequent patterning of the amorphous silicon layer only requires HBr to get etch selectivity to the Si₃N₄layer of the substrate.

5. The method ofclaim 4 wherein the spacer sidewall sculpting process is performed using a high frequency power in a range from 0 to 1,500 watts in a range from 50 to 70 MHz, a low frequency power in a range from 0 to 900 watts in a range from 11 to 15 MHz, and an active control chuck in a range from −10 to 80 degree C.

6. The method ofclaim 5 wherein the HBr flow rate is in a range from 0 to 583 sccm, CH₃F flow rate is in a range from 0 to 232 sccm, and the Ar flow rate is in a range from 0 to 1,775 sccm.

7. The method ofclaim 6 wherein a radical distribution control (RDC) of the process chamber is in a range from 5 to 95%, a temperature of an upper electrode is in a range from 40 to 80 degrees C., a temperature of a wall of the process chamber is in a range from 40 to 80 degrees C., and a temperature of a chiller in the process chamber is in a range from −10 to 80 degrees C.

8. The method ofclaim 7 wherein the spacer sidewall sculpting process is performed with a pressure in a range from 7 to 900 mTorr, for a time in a range of 10 to 30 seconds.

9. The method ofclaim 8 wherein an optimal result of the spacer sidewall sculpting process was obtained at low pressure, low power, and high electrostatic chuck (ESC) temperature.

10. The method ofclaim 9 wherein a pitch imbalance metric is used to assess improvement of the sidewall sculpting process.

11. The method ofclaim 11 wherein the pitch imbalance is a sum of an absolute value of a first pitch less a second pitch, the second pitch less a third pitch, the third pitch less a fourth pitch, and the fourth pitch less the first pitch.

12. The method ofclaim 11 wherein the pitch imbalance is substantially zero.

13. The method ofclaim 12 wherein performing the spacer sidewall sculpting process comprises a spacer sculpting stability step and a spacer sculpting etch step.

14. The method ofclaim 13 wherein the OE process did not cause a recess in the silicon nitrate layer.

15. The method ofclaim 14 wherein the OE process did not cause an undercut in amorphous silicon portion of the sculpted pattern.

16. The method ofclaim 15 wherein a ratio of a top critical dimension (CD) to a bottom CD of the first sculpted pattern is in a range from 0.92 to 1.00.

17. The method ofclaim 16 wherein a ratio of a middle CD to the bottom CD of the first sculpted pattern is in a range from 0.90 to 1.00.

18. The method ofclaim 17 wherein operating variables of the spacer sidewall sculpting process include process time, pressure, high frequency energy, low frequency energy, control chuck temperature, flow rates of etch gases, percentage radical distribution control, temperature of the upper electrode, temperature of the wall in the process chamber, and temperature of the chiller in the process chamber.

19. The method ofclaim 18 wherein selected two or more integration operating variables in two or more steps involving the breakthrough process, spacer sidewall sculpting process, the amorphous silicon ME process, and the amorphous silicon ME over etch (OE) process are concurrently controlled in order to achieve integration process objectives.

20. The method ofclaim 19 the integration objectives include fabricating the profile of the structures without an undercut and without a recess in the underlying layer, minimizing pitch imbalance, improving etch uniformity, and reducing processing time.

21. A system for forming a spacer sidewall mask, the system comprising:

a process chamber configured to perform a breakthrough process involving growth of a conformal native silicon oxide layer by exposing the substrate to oxygen in an atomic layer deposition (ALD) step, creating an ALD patterned structure, perform a spacer sidewall sculpting process on the ALD patterned structure, perform an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal, the process creating an ALD spacer oxide pattern, and perform an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a right angle trapezoidal shape and a second sculpted sub-structure with a left angle trapezoidal shape; and

a controller coupled to the process chamber, the controller configured to control selected two or more operating variables in order to achieve spacer sidewall sculpting objectives.

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