US20160364653A1 - Modular array of vertically integrated superconducting qubit devices for scalable quantum computing - Google Patents

Abstract

A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.

Description

BACKGROUND
• The present invention relates to quantum computing, and more specifically, to a modular array of vertically integrated superconducting qubit devices for scalable quantum computing.
• In one approach called circuit quantum electrodynamics, quantum computing employs active superconducting devices called qubits to manipulate and store quantum information, and resonators (e.g., as a two-dimensional (2D) planar waveguide or as a three-dimensional (3D) microwave cavity) to read out and facilitate interaction among qubits. Each superconducting qubit comprises one or more Josephson junctions shunted by capacitors in parallel with the junctions. The qubits are capacitively coupled to 2D or 3D microwave cavities. The energy associated with the qubit resides in the electromagnetic fields around the Josephson junction and especially in the vicinity of relatively larger shunt capacitance structures. To date, a major focus has been on improving lifetimes of the qubits in order to allow calculations (i.e., manipulation and readout) to take place before the information is lost to decoherence of the qubits. Currently, superconducting qubit coherence times can be as high as 100 microseconds, and efforts are being made to increase the coherence times. One area of research with respect to increasing coherence times is focused on eliminating lossy materials from areas of relatively high electromagnetic field energy density such as in the vicinity of sharp corners and edges of the thin films of which the qubits are comprised. Such materials in proximity to the qubit can include imperfections that support defects known as two-level systems (TLSs).
SUMMARY
• According to one embodiment, an assembly for a quantum computing device is provided. The assembly includes a quantum bus plane including a first set of recesses, a readout plane including a second set of recesses, and a block positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. Also, the assembly includes a plurality of qubit chips where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.
• According to one embodiment, an assembly for a quantum computing device is provided. The assembly includes a housing configured as an enclosure having a bottom part, a top part, and a block, in which the block connects the top and bottom parts. The assembly includes a quantum bus plane including a first set of recesses, and a readout plane including a second set of recesses. The block is configured to position the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. Also, the assembly includes a plurality of qubit chips where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.
• According to one embodiment, a method of configuring an assembly for a quantum computing device is provided. The method includes providing a housing configured as an enclosure having a bottom part, a top part, and a block, in which the block connects the top and bottom parts. The method includes providing a readout plane having a first set of recesses and a quantum bus plane having a second set of recesses, and assembling the readout plane opposite the quantum bus plane in a block, such that the first set of recesses opposes the second set of recesses. Also, the method includes installing a plurality of qubit chips in the block, where each of the plurality of qubit chips has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.
• In one or more embodiments, the plurality of qubit chips extends vertically in a lengthwise direction by being positioned in both the first set of recesses and the second set of recesses. The first set of recesses holds the first end of the plurality of qubit chips in the readout plane, and the second set of recesses holds the second end of the plurality of qubit chips in the quantum bus plane.
• In one or more embodiments, the first end of the plurality of qubit chips is opposite the second end. In one or more embodiments, the block is made of a superconducting material.
• In one or more embodiments, the quantum bus plane comprises a substrate with interconnect wiring on top of the substrate, and the interconnect wiring connects the plurality of qubit chips via a plurality of coupling bus resonators.
• In one or more embodiments, the readout plane comprises a substrate with fan-out wiring on top of the substrate, and the fan-out wiring individually connects each of the plurality of qubit chips to a circuit board. The circuit board individually connects each of the plurality of qubit chips to a plurality of connectors in a one-to-one relationship.
• In one or more embodiments, the block is configured to receive a first assembly comb and a second assembly comb to form an intersection, and the intersection of the first and second assembly combs forms a plurality of slots for individually accepting the plurality of qubit chips. The plurality of slots mechanically holds the plurality of qubit chips in a vertical position.
• Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
• FIG. 1 is a schematic illustrating a transparent view of part of the modular array of vertically integrated superconducting qubit chips according to an embodiment;
• FIG. 2 is a schematic illustrating a quantum bus plane design according to an embodiment;
• FIG. 3 is a schematic illustrating the readout plane in an inverted view according to an embodiment;
• FIG. 4 is a schematic of an example qubit chip according to an embodiment.
• FIGS. 5A through 5F illustrate an assembly and packaging technique for the modular array of vertically integrated superconducting qubit chips according to an embodiment, in which:
• FIG. 5A is a schematic of an assembly illustrating assembly combs for a block;
• FIG. 5B is a schematic of the assembly illustrating the assembly combs in place to form slots for orienting the superconducting qubit chips;
• FIG. 5C is a schematic of the assembly illustrating the installation of the superconducting qubit chips in the slots formed by the assembly combs;
• FIG. 5D is a schematic of the assembly illustrating installation of the readout plane in the block;
• FIG. 5E is a schematic of the assembly illustrating a view underneath the block;
• FIG. 5F is a schematic of the assembly illustrating that a pusher block applies pressure to hold the superconducting qubit chips in place;
• FIG. 6 is a method of configuring an assembly according to an embodiment; and
• FIG. 7 is a method of configuring an assembly according to an embodiment.
DETAILED DESCRIPTION
• Superconducting Josephson-junction based qubits are promising candidates for fault-tolerant quantum computing. As a solid-state technology, it has always held the potential of simpler scalability via existing integration techniques. Superconducting circuit and device fabrication can leverage well-known lithographic methods which can lead to quantum integrated processors with a high density of qubits. Furthermore, superconducting qubits operate in the microwave frequency regime, allowing for all-electrical control of the qubits and other elements which might be in the system. The other elements may include microwave resonators, active filters, quantum-limited amplifiers, etc.
• A state-of-the-art fault-tolerant quantum computing architecture which has gathered interest recently is the surface code. In the surface code, qubits are arranged in a lattice with only the nearest neighbor interactions required. For superconducting qubits, the surface code is an attractive path forward as defining multiple qubits in a nearest-neighbor lattice. Moreover, the error thresholds which are required for the surface code are within reach for superconducting qubits with the current levels of coherence. One particular physical proposal in the state-of-the-art for realizing the surface code with superconducting qubits is the skew-symmetric layout. In this lattice, each superconducting qubit is coupled to two separate linking bus resonators. The coupling of superconducting qubits with microwave resonators is known as circuit quantum electrodynamics (cQED). The microwave resonators are typically defined as planar stripline resonators but can also be modes within three-dimensional (3D) waveguide cavities.
• Although it may appear simple to design a large lattice of many superconducting qubits and stripline resonators lithographically, getting every resonator mode and every qubit to work as desired together is a challenge. For example, crosstalk between resonators and superconducting qubits as well as undesired spurious modes can result in stray couplings between quantum objects. Crosstalk is defined here as any unwanted coupling of microwave signals between qubit or resonator channels, other than those desired and defined by wiring. Furthermore, although it may appear easy to optimize parameters for a single qubit and a single cavity mode, once these individual qubits are re-arranged in a larger network and all defined on the same chip, their (collective) behavior can change and can be difficult to then debug.
• According to embodiments discussed herein, a vertically integrated multi-chip architecture is provided, with discrete superconducting chip pieces comprised of superconducting qubits and their readout resonators. The superconducting qubits, along with their readout resonators, are then all arranged to mate in a matrix sandwiched by two larger carrier chips. These two larger carrier chips serve two purposes: one purpose is to integrate multiple resonator quantum buses to couple the superconducting qubits together (thereby coupling quantum information between qubits), and the other purpose permits physical connections via fan-out wiring to explicit microwave controls. This embodiment realizes a scalable architecture for quantum computation using well-established technology, while obviating challenging silicon integration techniques, such as thru-silicon-vias (TSVs) and multi-level lithography.
• There are two physically different methods for implementing superconducting quantum processors via the circuit quantum electrodynamics (cQED) architecture, which are a 2D planar lithographic method and a 3D waveguide cavity method. The quantum processor refers to the entirety of the assembled components.
• 2D Planar Integration: The integration of qubits and resonators for 2D cQED is started via depositing superconducting films on silicon or sapphire substrates. Some typical superconducting films used are niobium (Nb), aluminum (Al), titanium nitride (TiN), and niobium nitride (NbN). Resonators (including readout resonators) are commonly defined in these superconducting films using coplanar waveguides, microstrips, coplanar striplines, or lumped element inductors and capacitors. Subsequently, superconducting qubits with Josephson junctions, such as the transmons, phase-qubits, or flux-qubits are also lithographically patterned via either electron-beam or optical lithography. Scaling up to larger quantum processors in this scheme requires a larger and larger chip to accommodate more resonators for coupling, more qubits, and more readout resonators. Using this 2D integration technique, processors up to 9 qubits have been devised in a linear chain, and 8 qubits in a latticed architecture. As the number of qubits in the 2D processor scales up, input-output (I/O) becomes increasingly challenging. In order to avoid crosstalk and integrate appropriate fan-out, technologies such as 3D integrated flip-chips, air-bridge crossovers, thru-silicon vias, and multi-layer lithography are required. As more and more of these different fabrication processes are required to scale up to larger quantum processors, the potential influence and degradation on the superconducting qubits increases rapidly. Therefore using these advanced fabrication techniques can lead to many different sources of decoherence in the qubits. For some of these processes, it could be necessary to perform them after Josephson junctions are lithographically defined. The impact and losses on Josephson junction based superconducting qubits after these processing steps are then a particular concern as to whether high coherence can continue to be preserved. Accordingly, this makes full-scale integration of a large system having a large number of qubits challenging.
• Embodiments include various features:
• 1) An array of vertical superconducting qubit chips is mounted to a silicon quantum bus plane and mounted to a separate qubit addressing and readout plane.
• 2) A quantum bus (QB) plane lithographically is defined on silicon which permits the coupling of quantum information among individual vertical superconducting qubit chips.
• 3) A readout (RO) plane couples each superconducting qubit chip's readout resonator to an integrated microwave bandwidth transmission line which follows onto a flexible circuit board thus connecting each superconducting qubit chip's readout resonator a coaxial connector for input/output (I/O).
• 4) Vertical superconducting qubit chips each contain a single superconducting qubit (also referred to as a tunnel junction, such as a Josephson junction) and on-chip readout resonator, designed in a way to effectively couple to the quantum bus plane and the readout plane. Each individual vertical superconducting qubit chip is designed to have a specific lithographically-defined coupling capacitance between the tunnel junction to the quantum bus plane on one end and between the readout resonator and the addressing transmission line of the readout plane on the other end.
• 5) All silicon elements are retained within a well-thermalized metal housing (e.g., copper) which provides mechanical support, alignment, and thermal contact.
• According to embodiments, the technique discussed herein is an approach for assembling the modular array of superconducting qubit chips into a scalable quantum processor, commensurate with latticed architectures for quantum error correction, such as the surface code.
• Now turning to the figures,FIG. 1 is a schematic illustrating a transparent view of part of the modular array of vertically integrated superconducting qubit devices according to an embodiment.FIG. 1 shows a quantum bus plane100, areadout plane102, and superconducting vertical qubit chips101. The superconductingvertical qubit chips101 are also referred to as qubit dies, qubits, etc. Thereadout plane102 and the quantum bus plane100 sandwich the qubit chips101 in between.
• FIG. 2 is a schematic illustrating a quantum bus plane design of the quantum bus plane100 according to an embodiment. The quantum bus plane design illustrates a surface code example. The quantum bus plane100 may be made of a semiconductor material as the substrate, such as, e.g., silicon, sapphire, etc. The semiconductor material hasinterconnect wiring202 deposited on top of the semiconductor material. Theinterconnect wiring202 is made of a superconducting material.
• Superconducting material may be defined as a material that can conduct electricity or transport electrons from one atom to another with no resistance when the superconducting material has reached “critical temperature” (Tc), or the temperature at which the material becomes superconductive. Conducting electricity or transporting electrons from one atom to another with no resistance means that no heat, sound, or any other form of energy would be released from the material as understood by one skilled in the art.
• The quantum bus plane100 connects eachindividual qubit chip101 viainterconnect wiring202. Theinterconnect wiring202 connects (e.g., capacitively) to eachsuperconducting qubit chip101 installed in the quantum bus plane100. Theinterconnect wiring202 includescoupling bus resonators205 positioned between each superconductingvertical qubit chip101. Particularly, superconductingvertical qubit chips101 are configured to couple together through thecoupling bus resonators205.
• To assist with securing and positioning superconductingvertical qubit chips101 on the quantum bus plane100, the quantum bus plane100 includes etchedrecesses201 at the locations to insert each of the superconducting vertical qubit chips101. The etched recesses201 are pockets that individually fit the superconductingvertical qubit chips101 into specific locations in the quantum bus plane100. The etched recesses201 in the quantum bus plane100 help to define accurate capacitive coupling between the qubit chips101 and theinterconnect wiring202. The etched recesses201 determine how deeply thevertical qubit chips101 sit into the quantum buss plane100 and thus determine the vertical separation between the capacitor pads on thequbit chip101 and those on the quantum buss plane100. The etched recesses201 are etched into the semiconductor substrate of the quantum bus plane100. Accurate vertical separation of these coupling pads is a prerequisite for achieving a precise coupling capacitance value. Thecoupling capacitor pad404 is shown inFIG. 4 and the quantum bus plane100 hascoupling pad250 in front of eachetched recess201.
• For the sake of clarity and so as not to obscureFIG. 2, only two superconductingvertical qubit chips101 are shown inFIG. 2 although it is understood that each row, e.g., rows1-4, are filled with superconducting vertical qubit chips101. One superconductingvertical qubit chip101 is shown as a code superconducting vertical qubit chip inrow1, and the other superconductingvertical qubit chip101 is a syndrome superconducting vertical qubit chip inrow2. In one implementation, each row may be filled with the same type of superconductingvertical qubit chip101. For example,row1 may be filled with code superconductingvertical qubit chips101, whilerow2 is filled with syndrome superconducting vertical qubit chips101.Row3 may be filled with code superconductingvertical qubit chips101, whilerow4 is filled with syndrome superconducting vertical qubit chips101. Although only 4 rows are shown for the sake of illustration, it is contemplated that M numerous rows may be included on the quantum bus plane100, where M is the last row. A code qubit stores quantum information for operation of the quantum processor. A syndrome qubit measures and extracts any errors in the system without corrupting the information present in the code qubit. These terms are commonly applied when discussing “surface code error correction.”
• According to an embodiment,FIG. 3 is a schematic illustrating thereadout plane102 in an inverted view.FIG. 3 shows the backside of thereadout plane102, and the backside faces the quantum bus plane100 (not shown inFIG. 3). Thereadout plane102 may be made of a semiconductor material as the substrate, such as, e.g., silicon, sapphire, etc. The semiconductor material has fan-outwiring302 deposited on top of the semiconductor material. The fan-outwiring302 may be made of a superconducting material.
• Thereadout plane102 includes etchedrecesses301 at locations to insert each of the superconducting vertical qubit chips101. Eachetched recess301 is a pocket that individually fits a single superconductingvertical qubit chip101 into a specific location in thereadout plane102, analogous to the etchedrecesses201 in the quantum bus plane100 inFIG. 2.
• The etched recesses301 in thereadout plane102 capacitively connect the superconductingvertical qubit chips101 to the fan-outwiring302 via the capacitor pads defined on the upper end of thevertical qubit chip101 and on thereadout plane102. At the upper end, thevertical qubit chip101 hascoupling capacitor pad401 as shown inFIG. 4, while thereadout plane102 has acoupling pad350 in front of each etched recesses301.
• The fan-outwiring302 hastransmission lines320. Eachtransmission line320 individually connects to a single superconductingvertical qubit chip101 in a one-to-one relationship. The etched recesses301 serve both a mechanical purpose and an electrical purpose. Mechanically, theetched recesses301 serve as a slot/pocket to insert each superconductingvertical qubit chip101. Electrically, theetched recesses301 align each superconductingvertical qubit chip101 to anindividual transmission line320 of the fan-outwiring302. The fan-outwiring302 individually couples to each superconductingvertical qubit chip101. Also, the fan-outwiring302 individually connects each superconductingvertical qubit chip101 to aflexible circuit board303. The fan-outwiring302 does not affect quantum information on the superconducting vertical qubit chips101. The fan-outwiring302 connects the superconductingvertical qubit chips101 to the outside environment (e.g., the 50 ohm (Ω) environment). Theflexible circuit board303 individually connects each superconductingvertical qubit chip101 to anindividual connector304 via the fan-outwiring302. Although theflexible circuit board303 is shown as one implementation, it is contemplated that other type of circuit boards or electrical connections may be utilized.
• Theconnectors304 individually connect the superconductingvertical qubit chips101 to external electronics (not shown). Theconnectors304 may be microwave connectors in which microwave signals may be input and qubit states can be read. Eachconnector304 has a one-to-one relationship to a single superconductingvertical qubit chip101 on thereadout plane102, such that each superconductingvertical qubit chip101 is individually addressable through asingle connector304, through theflexible circuit board303, through the fan-outwiring302, aparticular transmission line320, and through an individualetched recess301. In one implementation, theconnectors304 may coaxial cable connectors configured to connect to coaxial cables. Although not shown so as not to obscureFIG. 3, it is understood that conductive wiring runs through theflexible circuit board303 and that wiring connects theflexible circuit board303 to eachrespective connector304 as understood by one skilled in the art. The conductive wiring of theflexible circuit board303 may be made of superconducting or normal material.
• FIG. 4 is a schematic of an example superconductingvertical qubit chip101 according to an embodiment. Various details of the superconductingvertical qubit chips101 are shown inFIG. 4. The superconductingvertical qubit chips101 may have a substrate made of a semiconductor material, such as, e.g., silicon, sapphire, etc. Eachqubit chip101 is an integrated circuit. Conductive material is deposited and patterned on the substrate of the superconductingvertical qubit chips101 to form the integrated circuit. The superconductingvertical qubit chips101 are not a monolithic wafer. Rather, the superconductingvertical qubit chips101 are formed from a wafer (substrate) diced into individual qubit dies. Each diced superconductingvertical qubit chip101 includes acoupling capacitor pad401. Thecoupling capacitor pad401 is a capacitor that capacitively couples each superconductingvertical qubit chip101 to thereadout plane102 via the fan-outwiring302, when the superconductingvertical qubit chip101 is inserted in itsetched recess201. Accordingly, on one end of the superconductingvertical qubit chip101, that end is electrically connected to thereadout plane102 through thecoupling capacitor pad401 andcoupling pad350 on thereadout plane102. It is noted that, forcoupling capacitor pads401 and350 andcoupling capacitor pads404 and250, the coupling capacitors may be defined by metal pads that are at right angles to each other, with a well-defined vertical separation. The two types of coupling capacitors are quantum buss plane to lower side of qubit chip, and upper side of vertical qubit chip to readout plane. It should be understood that two metal surfaces (pads in this case) at right angles to each other, separated by some distance, define a capacitor. Embodiments exploit this fact to permit accurate coupling between circuit elements without resorting to wire bonds across right angle connections.
• Additionally, each superconductingvertical qubit chip101 includescoupling capacitor pads404. Thecoupling capacitor pads404 form a capacitor, and between the twocoupling capacitor pads404 is a tunnel junction403 (sometimes called the qubit), such as, e.g., a Josephson junction. Thecoupling capacitor pads404 form a capacitor that capacitively couples to the quantum bus plane100 via the interconnectingwiring202. Accordingly, on the opposite end to thecoupling capacitor pad401, the opposite end is electrically connected to the quantum bus plane100 through thecoupling capacitor pads404.
• The superconductingvertical qubit chip101 includesreadout resonator402. Thereadout resonator402 is configured with a resonance frequency designed to read the state of thequbit tunnel junction403. Thereadout resonator402 is positioned between thecoupling capacitor pad401 and thecoupling capacitor pads404. Thereadout resonator402 is formed of conductive material that connects thecoupling capacitor pad401 and thecoupling capacitor pads404. The conductive material is a superconducting material, which forms the circuit.
• The superconductingvertical qubit chip101 includes aground plane405 surrounding the circuit of thecoupling capacitor pad401, thecoupling capacitor pads404, and thereadout resonator402. The material of the substrate separates theground plane405 from the circuit.
• According to an embodiment, an assembly and packaging technique for the modular array of vertically integratedsuperconducting qubit chips101 is discussed below inFIGS. 5A, 5B, 5C, 5D, 5E, and 5F.FIG. 5A illustrates part of anassembly500. Theassembly500 has acopper block502. Thecopper block502 includes areadout plane slot503. Thereadout plane102 is to be inserted into thereadout plane slot503 as discussed further below. Although acopper block502 is illustrated, theblock502 may be made of other materials. Theblock502 can be constructed of a variety of materials provided they give high thermal conductivity. Examples other than copper include brass, sapphire, silicon, silver, aluminum, and/or niobium.
• Assembly combs520A and520B are utilized to orient alignment of the superconductingvertical qubit chips101 for assembly with the readout plane102 (in the etched recesses201) and quantum bus plane100 (in the etched recesses301) within thecopper block502. Both assembly combs520A and520B have teeth with predefined spacing. For example, theassembly comb520A hasteeth525A and theassembly comb520B hasteeth525B. In one implementation, the spacing of theteeth525A is larger than the spacing of theteeth525B, and the spacing of theteeth525A and525B is based on accommodating the cross-section size of the superconducting vertical qubit chips101.
• Thecopper block502 includesassembly slots501A and501B. Theassembly comb520A is inserted into theassembly slot501A, and theassembly comb520B is inserted into theassembly slot501B. One assembly slot is positioned higher than the other assembly slot such that the assembly combs520A and520B define the desired alignment slots where they cross over and under each other but do not interfere with each other when inserted into theirrespective assembly slots501A and501B.
• FIG. 5B is a schematic of theassembly500 showing the assembly combs520A and520B in place within thecopper block502 according to an embodiment.Slots525 are formed by the intersection of the assembly combs520A and520B while in thecopper block502. Theslots525 are utilized to orient the superconductingvertical qubit chip101. In particular, theslots525 are formed by the spacing of theteeth525A and525B such that theslots525 can accommodate the size of the superconducting vertical qubit chips101. In one implementation, the spacing of theslots525 may be about 5 millimeters (mm) in the x-axis and may be about 5 mm in the y-axis. In one implementation, each superconductingvertical qubit chip101 may have approximate dimensions of 8 mm tall by 2 mm wide by 0.7 mm thick.
• Also, to accommodate the size of the superconductingvertical qubit chips101, theetched recesses201 and301 may be about 0.7 mm in the x-axis and about 2 mm in the y-axis. The etched recessed201 and301 may have a depth of about 0.35 mm in the z-axis.
• FIG. 5C is a schematic of theassembly500 showing an abbreviated view inside the copper block502 (not shown) which is part of a housing550 (shown inFIG. 5F) according to an embodiment. InFIG. 5C, the abbreviated view omits certain elements in order to simplify theassembly500 for better understanding. The walls of thehousing copper block502 are removed, and only acopper base530 of thehousing550 is shown. The quantum bus plane100 is attached to and/or positioned on thecopper base530. The intersecting assembly combs520A and520B are in place (within the copper block502) forming theslots525. Aligned through theslots525, a few example superconductingvertical qubit chips101 are installed into (theetched recesses201 in) the quantum bus plane100. Theslots525 directly align to individual etchedrecesses201 below and provide a guide during installation of the superconducting vertical qubit chips101.
• FIG. 5D is a schematic of theassembly500 showing a transparent view into thecopper block502 according to an embodiment.FIG. 5D shows thereadout plane102 installed into thecopper block502 and extending outside of thecopper block502 through readoutplane housing slot585. In one implementation, the quantum bus plane100 fits into the bottom of thecopper block502. In another implementation, thecopper block502 may sit on top of the quantum bus plane100. The superconductingvertical qubit chips101 are sandwiched between thereadout plane102 and the quantum bus plane100, and the ends of the superconductingvertical qubit chips101 fit into theetched recesses201 and301 of the quantum bus plane100 andreadout plane102, respectively. For simplicity and ease of understanding, only a few superconductingvertical qubit chips101 are shown inFIG. 5D. Also, so as not to obscureFIG. 5D, the assembly combs520A and520B are not shown in this figure.
• Aboard clamp555 holds and attaches to portion of thereadout plane102 extending outside of the housing. Theboard clamp555 holds and attaches thereadout plane102 to theflexible circuit board303. Outside of thehousing550, theconnectors304 are on arigid circuit board330 and connected to theflexible circuit board303. Thecircuit board330 comprises circuits (not shown) individually connecting eachconnector304 to an individual circuit within theflexible circuit board303, as understood by one skilled in the art.
• FIG. 5E is a schematic of theassembly500 showing a view underneath thehousing500 according to an embodiment. Thecopper base530 of the housing is removed.FIG. 5E allows the bottom of the quantum bus plane100 to be viewed.
• FIG. 5E also shows thatwire bonds578 connect thereadout plane102 to theboard clamp555. Thesewire bonds578 create an electrical connection between the fan-outwiring302 on thereadout plane102 and the conductors (of whatever type) on theflexible circuit board303. Although it possible to mechanically bond theflexible circuit board303 directly to thesilicon readout plane102, those two items, however, have extremely different thermal expansion coefficients which may cause the connections to break over time.Wire bonds578 being flexible permit long-term reliability over many thermal cycles. In one implementation, the two readout planes are to be made of the same material so any dimensional changes from thermal expansion are the same for both planes.
• FIG. 5F is a schematic of theassembly500 according to an embodiment.FIG. 5F shows that apusher block570 pushes thereadout plane102 firmly against the superconducting vertical qubit chips101. Thepusher block570 is spring loaded. The constant pressure of thepusher block570 ensures that the superconductingvertical qubit chips101 stay in the etchedrecesses201 and301. The force of thepusher block570 is caused by aspring mechanism575 attached to atop cap582 of thehousing550.
• As can be seen inFIG. 5F, thehousing550 is an enclosure. Thehousing550 may be made of copper, silver, brass, silicon, sapphire, aluminum, and/or niobium. Thehousing550 includes thecopper block502, thecopper base530, thepusher block570, and thetop cap582.
• In one implementation, the assembly combs520A and520B may remain in thecopper block502 after the superconductingvertical qubit chips101 have been installed (i.e., inserted into theetched recesses201 and301 of the quantum bus andreadout planes100 and102, respectively). In another implementation, the assembly combs520A and520B may be removed from thecopper block502 after installing the superconductingvertical qubit chips101, such that the assembly combs520A and520B are not in thehousing550.
• For ease of understanding, sub-headings are provided below. The sub-headings are meant for explanation purposes and not limitation.
• Standardized Fabrication of Elements:
• Each of the discussed silicon elements, such as, e.g., the quantum bus plane100, superconductingvertical qubit chips101, andreadout plane102, use well-established lithographic technology that is time tested in the superconducting qubit community and thus understood by one skilled in the art. In one embodiment, the materials are standardized to niobium for the resonator and transmission line elements; the materials are aluminum and native aluminum oxide for the qubit junction fabrication (i.e., the qubit tunnel junction403) via standard double-angle evaporation. All lithography may be performed on high-resistivity silicon wafers with established loss parameters appropriate for qubit technology, as understood by one skilled in the art.
• Thereadout resonator402 is in on thevertical qubit chip101, and transmission line elements are any other wiring on the quantum buss plane100, thequbit chip101, and thereadout plane102. In one implementation, thereadout resonators402 may be of a different material than the wiring. In another implementation, thereadout resonators402 and wiring may be fabricated from a variety of all the same materials. In yet another implementation, thereadout resonators402 and various different portions of the wiring may be fabricated from a variety of different materials for each sub-category of function.
• Complete assembly of a scalable quantum processor with N qubits (i.e., N qubit chips101) is achieved without resorting to any multi-level lithography, inserted ground planes, cross-overs, or thru-silicon-vias (TSVs). Using current standard lithographic techniques, embodiments allow the straightforward integration of N=100 to 1000 superconductingvertical qubit chips101, taking up a space roughly the size of a deck of playing cards (e.g., 2.5×3.5 inches or 64×89 mm).
• Design of Individual Qubit Chips and Coupling Capacitance Choices:
• From electromagnetic simulations for reasonable parameters ofqubit tunnel junctions403,readout resonators402, and quantum bus planes100, it is possible to achieve the desired precise coupling capacitance values with the geometry described herein.
• Each individual superconductingvertical qubit chip101 contains a capacitor (i.e., coupling capacitor404) that couples signal to the quantum bus traces (i.e., interconnect wiring202) on the quantum bus plane100. The capacitor (coupling capacitor404) provides coupling that is appropriate for a specific universal two-qubit entangling gate. The capacitor is formed by an electrode on the lower end of thevertical qubit chip101 which couples to electrodes on the quantum buss plane100. The approximate range in this implementation for the capacitor value is around 7 to 5 femto Farads. The interconnection between the superconductingvertical qubit chip101 and the etched recesses201 (pocket) in the quantum bus plane100 is designed to minimize stray coupling between the qubit signals andground plane405.
• On the other end of the superconductingvertical qubit chip101, the interconnection with thereadout plane102 creates a specific capacitance between thereadout resonator402 and the control transmission line320 (of the fan-out wiring302) such that thereadout resonator402 has a well-defined quality factor and permits a high fidelity readout. This capacitor (i.e., coupling capacitor pad401) is formed by an electrode on the superconducting vertical qubit chip101 (qubit die) which couples to an electrode (a portion of the control transmission line320) on thereadout plane102. The approximate value of this capacitor in this implementation is around 5 to 7 femto Farads, for example.
• Each superconductingvertical qubit chip101 is metalized on the backside with superconductor material to control stray coupling and other electric fields within theprocessor housing550. The backside of the superconductingvertical qubit chip101 is opposite the circuit of thecoupling capacitor pad401, thecoupling capacitor pads404, and thereadout resonator402 on the front side.
• Note that all capacitor values and uncertainty are determined by lithographic feature sizes and depth of etches. These values are easily changed and provide for sufficient accuracy for the circuit tolerances required for embodiments.
• Design of Quantum Bus Plane:
• The fabrication process of the quantum bus plane100 can begin with standard 2D integration techniques. In one implementation, niobium is electro-sputtered onto asilicon substrate590. Multiple masks, having the quantum bus designs and having the etched recesses201 (pockets) where qubit chips101 are to be mounted, may be used for reactive ion etching (RIE) of the niobium. The quantum bus design mask defines thecoupling bus resonators205 which couple quantum information among the superconducting vertical qubit chips101. The pocket mask (for making the etched recesses201) defines the locations to etch down into the silicon for the individual superconductingvertical qubit chips101 to be mounted. The process for the pocket mask etch may be similar to most 3D integration schemes, except in this case the sputtered niobium is used as a hardmask to first define the pockets (i.e., etched recesses201). Definition of the pocket (i.e., etched recess201) in thesilicon substrate590 can be achieved using a deep silicon dry etch process, reactive ion etching (RIE), or a wet chemistry (tetramethyl ammonium hydroxide (TMAH)).
• The pockets (i.e., etched recesses201) of the quantum bus plane100 are arranged in a grid structure where successive rows are offset, one corresponding to superconducting vertical code qubit chips, and the other row corresponding to superconducting vertical syndrome qubits chips101 for error detection via measurement. Each qubit chip pocket (i.e., etched recess201) is arranged to couple to twocoupling bus resonators205 defined on the quantum bus plane100 in one implementation. Note that this arrangement is not the only way to realize the surface code, as one can also couple either three or fourcoupling bus resonators205 to a single superconductingvertical qubit chip101 in another implementation. Location accuracy of the qubit chip pockets (etched recesses201 (includingetched recesses301 in readout plane102) is determined by the lithography and depth accuracy as determined by the etch time. The pockets are formed with a chamfered or bell-mouthed opening to allow easy insertion of each superconducting vertical qubit chip101 (qubit die).
• Depending on results from scaling to larger N (i.e., a larger amount of superconducting vertical qubit chips101), the quantum bus plane100 may be admissible to more integration techniques such as TSVs for chip-mode reduction. The nuance here is that no Josephson junctions (qubits)403 need to be defined in this quantum bus plane100, so there would be minimal effect on qubit coherence with further integration of the quantum bus plane100.
• Design of Readout Plane:
• Thereadout plane102 starts off similar to the quantum bus plane100, with niobium conductors etched lithographically on asilicon substrate595.Co-planar transmission lines320 are patterned on thereadout plane102 in a fan-out configuration (i.e., fan-out wiring302) so as to bring external signals into and out of each superconductingvertical qubit chip101. Thesetransmission lines320 are defined in a coplanar waveguide, and support 50Ω microwave driving of both readout and qubit control signals.
• All thesetransmission lines320 meander through thereadout plane102 terminating on one edge inwire bond pads370. Thewire bond pads370 are on the extreme right end of the fan-outwiring302. Similar to the quantum bus plane, pockets (i.e., etched recesses301) in thereadout plane102 are likewise defined via deep etching into thesilicon substrate595 of thereadout plane102, in corresponding locations as theetched recesses201 in the quantum bus plane100 so as to accept the mounting of the individual superconducting vertical qubit chips101. These pockets (i.e., etched recesses301) may be chamfered or otherwise bell-mouthed for ease of assembly and locating of structure.
• The microwave signals for control and readout are carried off thereadout plane102 viawire bonds578 to theflexible circuit board303 which conducts to other transmission lines embedded in a separaterigid circuit board330 populated withconnectors304 leading to external components.
• Ground Planes in Quantum Bus Plane and Readout Plane Pockets:
• After etching qubit chip pockets (etchedrecesses201,301) in both the quantum bus andreadout planes100 and102 respectively, these pockets (etchedrecesses201,301) are coated with niobium via sputtering to form continuous ground plane. These ground planes are designed to mate to the ground planes405 that exist on the extreme ends of each superconductingvertical qubit chip101 to form a continuous electrostatic ground between the quantum bus andreadout planes100 and102, respectively; the continuous electrostatic ground between the quantum bus and readout planes100 and102 (respectively) serves to (1) further isolate each qubit site (i.e., locations of etchedrecesses201,301) from spurious modes, (2) isolate each qubit site (i.e., locations of etchedrecesses201,301) from adjacent qubit superconductingvertical qubit chips101, and (3) eliminate unwanted cross-talk coupling between superconducting vertical qubit chips101.
• Assembly of Modular Array Elements:
• 1. Each individual superconductingvertical qubit chip101 is located by anetched recess201 formed in the quantum bus plane100 and anetched recess301 formed thereadout plane102. In one implementation, theetched recesses201,301 are accurately formed in thesilicon substrates590,595 using a standard wet etch process.
• 2. Each individual superconductingvertical qubit chip101 is chosen for desirable electrical characteristics such as transition frequency. In some cases the syndrome qubits might be more strongly coupled to the readout wiring to enhance signal-to-noise. This would reduce coherence times on the syndrome qubits which does not in any way degrade the quantum information in the code qubits.
• 3. A pair of crossed assembly combs520A and520B is mounted to the outer housing of thecopper block502 in order to temporarily provide alignment for the superconducting vertical qubit chips101 (as shown inFIG. 5A). The assembly combs520A and520B create a series of alignment slots525 (as shown inFIG. 5B) to orient the superconductingvertical qubit chips101 which are inserted vertically from above. The superconductingvertical qubit chips101 key into theetched recesses201 in the quantum bus plane100 (as shown in5C) and are thereby (automatically) oriented to key into the correspondingetched recesses301 in the readout plane102 (as shown inFIG. 5D). Thereadout plane102 is inserted from the side viareadout plane slot503.FIG. 5E depicts theassembly500 from below and shows the assembled components with the assembly combs520A and520B omitted. Once assembled, the vertical organization of the superconductingvertical qubit chips101 constrained (and sandwiched) between the two silicon quantum bus and readout planes100 and102 (respectively) is maintained with pressure applied by thepusher block570. Thepusher block570 is spring-loaded from above via thesprings575 pressed down by the top cap582 (as shown inFIG. 5F).
• Expandable, Scalable and Replaceable Array:
• The figures associated with embodiments show a fourteen qubit chip array but the number of superconductingvertical qubit chips101 can be expanded to any arbitrary number (N). All that is required is that the quantum bus plane100 should be enlarged and the niobium wiring be replicated at all qubit sites (i.e., locations at theetched recesses201 to accommodate superconducting vertical qubit chips101) as needed. Thereadout plane102 can support manysignal transmission lines320 interleaved between each qubit site (i.e., locations at theetched recesses301 to accommodate superconducting vertical qubit chips101) to bring the signals to one edge and may require integration of dielectric cross-overs to reduce crosstalk if desired. Moreover, the further integration of thereadout plane102 and quantum bus planes100 is a minimal issue as it will neither directly affect the qubit chip fabrication process nor the qubit coherence performance.
• According to embodiments, theassembly500 includes the desirable feature that each superconductingvertical qubit chip101 may be hand-selected for the correct electrical characteristics; any member of the array of superconductingvertical qubit chips101 may be individually replaced at any time if the qubit chip's performance degrades for any reason during operation. Replacement of the superconductingvertical qubit chip101 can be accomplished without removingwire bonds578 and/or without having to unsolder any components.
• Embodiments provide a clear separation of fabrication processing steps and avoid the need for all N qubit and circuit parameters to meet specification on a single superconductingvertical qubit chip101.Qubit chips101 from multiple different fabrication runs can be combined in this type of quantum processor so that parameters such as transition frequency may be easily tailored without having to achieve a full range of accurate parameters on one silicon wafer in just one fabrication run.Individual qubit chips101 may be chosen from various different fabrication runs (wafers) and combined in the processor assembly.
• As understood by one skilled in the art, microwave signals are applied to thequbit chip101 via the readout lines to excite it into a defined state. After some later time the state of the qubits can be then read out by interrogating them at some other microwave frequency, again via the readout lines.
• FIG. 6 is amethod600 of configuring anassembly500 for a quantum computing device according to an embodiment. Reference can be made to the figures discussed herein.
• At block605, the quantum bus plane100 having a first set ofrecesses201 are provided, as depicted inFIG. 2.
• At block610, the quantum bus plane100 is positioned in theblock502, on top of thecopper base530, as seen inFIG. 5D. The alignment combs520A and520B are installed in thecopper block502 and fixed in place, creating a series of precisely aligned slots535 to accept the qubit chips101, as seen inFIG. 5B.
• Atblock615, a plurality of superconductingvertical qubit chips101 are placed/installed in theblock502, each of the plurality ofqubit chips101 has a first end positioned in the first set of recesses201 (as shown inFIG. 5C). The plurality ofqubit chips101 extend vertically in a lengthwise direction by being positioned in the first set ofrecesses201 and in theslots525 created by the alignment combs. The set ofrecesses201 holds the lower end of the plurality ofqubit chips101 in the quantum bus plane100. The first end of the plurality ofqubit chips101 is opposite the second end.
• Atblock620, thereadout plane102 with itsrecesses301 is then installed into thecopper block502 such that therecesses301 in thereadout plane102 are positioned to accept the upper end (i.e., second end) of the plurality of all the qubit chips101 which have been aligned by theslots525 created by both alignment combs520A,520B. Thereadout plane102 thus drops down over the ends of the qubit dies101 a distance equal to the depth of the recesses in thereadout plane301 and the precise mechanical alignment of all the electrical circuit elements is achieved in all three axes simultaneously. At this point the alignment combs520A and520B may either be left in place or may be removed.
• The quantum bus plane100 comprises asubstrate590 withinterconnect wiring202 on top of thesubstrate590, and theinterconnect wiring202 connects the plurality ofqubit chips101 via a plurality ofcoupling bus resonators205. Thereadout plane102 comprises asubstrate595 with fan-outwiring302 on top of thesubstrate595, and the fan-outwiring302 individually connects each of the plurality ofqubit chips101 to acircuit board330. Thecircuit board330 individually connects each of the plurality ofqubit chips101 to a plurality ofconnectors304 in a one-to-one relationship. Theblock502 is configured to receive afirst assembly comb520A and asecond assembly comb520B to form an intersection, and the intersection of the first and second assembly combs520A,520B form a plurality ofslots525 for individually accepting the plurality of qubit chips101. The plurality ofslots525 mechanically holds the plurality ofqubit chips101 in a vertical position.
• FIG. 7 is amethod700 of configuring anassembly500 for a quantum computing device according to an embodiment. Reference can be made to the figures discussed herein.
• At block705, the following parts are assembled:copper base530 andcopper block502.
• At block710 the quantum buss plane100 is installed into thecopper block502 such that the quantum buss plane100 rests on top of thecopper base530, and the quantum bus plane100 has a set of recesses201 (thereadout plane102 has a different set of recesses301). Then, the assembly combs520A and520B are installed and fixed into thecopper block502 thereby creatingalignment slots525.
• Atblock715, a plurality ofqubit chips101 are installed in theblock502, where each of the plurality ofqubit chips101 has a first end positioned in the first set ofrecesses201 using thealignment slots525 created by the assembly combs520A,520B to guide the qubit chips101 into the correct locations. Thehousing550 includes a readoutplane housing slot585. At block720, thereadout plane102 is installed into theslot585 and therecesses301 in thereadout plane102 accept the upper ends (i.e., second end) of the plurality of all the qubit chips101 which have been put in the correct locations by the alignment combs520A,520B such that thereadout plane102 drops over all of them (qubit chips101) simultaneously. The bell-mouthed nature of therecesses301 in thereadout plane102 assists in the final locating of the ends of the qubit dies101 into therecesses301. Thereadout plane102 extends through the readoutplane housing slot585 to connect to thecircuit board330, and thecircuit board330 connects to a plurality ofconnectors304.
• Thehousing550 includes a pushing mechanism configured to apply pressure to thereadout plane102, and the pressure applied to thereadout plane102 forces the plurality ofqubit chips101 to the quantum bus plane100. The pushing mechanism comprises: apusher block570 positioned on top of thereadout plane102, and aspring mechanism575 pressing downward against thepusher block570. The top part (top cap582) of thehousing550 applying a compression force to thespring mechanism575 from above.
• It will be noted that various microelectronic device fabrication methods may be utilized to fabricate the components/elements discussed herein as understood by one skilled in the art. In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
• Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.
• Removal is any process that removes material from the wafer: examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), etc.
• Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed. Patterning also includes electron-beam lithography.
• Modification of electrical properties may include doping, such as doping transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants.
• The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

Claims (25)

What is claimed is:

1. An assembly for a quantum computing device, comprising:

a quantum bus plane including a first set of recesses;

a readout plane including a second set of recesses;

a block positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses; and

a plurality of qubit chips each having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

2. The assembly ofclaim 1, wherein the plurality of qubit chips extend vertically in a lengthwise direction by being positioned in both the first set of recesses and the second set of recesses.

3. The assembly ofclaim 1, wherein the first set of recesses holds the first end of the plurality of qubit chips in the readout plane; and

wherein the second set of recesses holds the second end of the plurality of qubit chips in the quantum bus plane.

4. The assembly ofclaim 1, wherein the first end of the plurality of qubit chips is opposite the second end.

5. The assembly ofclaim 1, wherein the block is made of a superconducting material.

6. The assembly ofclaim 1, wherein the quantum bus plane comprises a substrate with interconnect wiring on top of the substrate, the interconnect wiring connecting the plurality of qubit chips via a plurality of coupling bus resonators.

7. The assembly ofclaim 1, wherein the readout plane comprises a substrate with fan-out wiring on top of the substrate, the fan-out wiring individually connecting each of the plurality of qubit chips to a circuit board.

8. The assembly ofclaim 7, wherein the circuit board individually connects each of the plurality of qubit chips to a plurality of connectors in a one-to-one relationship.

9. The assembly ofclaim 1, wherein the block is configured to receive a first assembly comb and a second assembly comb to form an intersection, the intersection of the first and second assembly combs forming a plurality of slots for individually accepting the plurality of qubit chips.

10. The assembly ofclaim 9, wherein the plurality of slots mechanically holds the plurality of qubit chips in a vertical position.

11. An assembly for a quantum computing device comprising:

a housing configured as an enclosure having a bottom part, a top part, and a block, the block connecting the top and bottom parts;

a quantum bus plane including a first set of recesses;

a readout plane including a second set of recesses, wherein the block is configured to position the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses;

a plurality of qubit chips each having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

12. The assembly ofclaim 11, wherein the housing includes a readout plane housing slot through which the readout plane extends.

13. The assembly ofclaim 12, wherein the readout plane extends through the readout plane housing slot to connect to a circuit board, the circuit board connecting to a plurality of connectors.

14. The assembly ofclaim 11, further comprising a pushing mechanism configured to apply pressure to the readout plane, the pressure applied to the readout plane forces the plurality of qubit chips to the quantum bus plane.

15. The assembly ofclaim 14, wherein the pushing mechanism comprises:

a pusher block positioned on top of the readout plane, and

a spring mechanism pressing downward against the pusher block, the top part of the housing applying a compression force to the spring mechanism from above.

16. A method of configuring an assembly for a quantum computing device, the method comprising:

providing a quantum bus plane having a first set of recesses and a readout plane having a second set of recesses;

positioning the readout plane opposite the quantum bus plane in a block, such that the first set of recesses opposes the second set of recesses; and

installing a plurality of qubit chips in the block, each of the plurality of qubit chips having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

17. The method ofclaim 16, wherein the plurality of qubit chips extend vertically in a lengthwise direction by being positioned in both the first set of recesses and the second set of recesses.

18. The method ofclaim 16, wherein the first set of recesses holds the first end of the plurality of qubit chips in the readout plane; and

wherein the second set of recesses holds the second end of the plurality of qubit chips in the quantum bus plane; and

wherein the first end of the plurality of qubit chips is opposite the second end.

19. The method ofclaim 16, wherein the quantum bus plane comprises a substrate with interconnect wiring on top of the substrate, the interconnect wiring connecting the plurality of qubit chips via a plurality of coupling bus resonators.

20. The method ofclaim 16, wherein the readout plane comprises a substrate with fan-out wiring on top of the substrate, the fan-out wiring individually connecting each of the plurality of qubit chips to a circuit board; and

wherein the circuit board individually connects each of the plurality of qubit chips to a plurality of connectors in a one-to-one relationship.

21. The method ofclaim 16, wherein the block is configured to receive a first assembly comb and a second assembly comb to form an intersection, the intersection of the first and second assembly combs forming a plurality of slots for individually accepting the plurality of qubit chips; and

wherein the plurality of slots mechanically hold the plurality of qubit chips in a vertical position.

22. A method of configuring an assembly for a quantum computing device, the method comprising:

providing a housing configured as an enclosure having a bottom part, a top part, and a block, the block connecting the top and bottom parts;

providing a readout plane having a first set of recesses and a quantum bus plane having a second set of recesses;

assembling the readout plane opposite the quantum bus plane in a block, such that the first set of recesses opposes the second set of recesses; and

installing a plurality of qubit chips in the block, each of the plurality of qubit chips having a first end positioned in the first set of recesses and having a second end positioned in the second set of recesses.

23. The method ofclaim 22, wherein the housing includes a readout plane housing slot through which the readout plane extends; and

wherein the readout plane extends through the readout plane housing slot to connect to a circuit board, the circuit board connecting to a plurality of connectors.

24. The method ofclaim 22, wherein the housing includes a pushing mechanism configured to apply pressure to the readout plane, the pressure applied to the readout plane forces the plurality of qubit chips to the quantum bus plane.

25. The method ofclaim 24, wherein the pushing mechanism comprises:

a pusher block positioned on top of the readout plane, and

a spring mechanism pressing downward against the pusher block, the top part of the housing applying a compression force to the spring mechanism from above.

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