US20160343604A1 - Substrate structure with embedded layer for post-processing silicon handle elimination - Google Patents

Abstract

The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Description

RELATED APPLICATIONS
• This application claims the benefit of U.S. provisional patent application No. 62/165,446, filed May 22, 2015, the disclosure of which is incorporated herein by reference in its entirety.
FIELD OF THE DISCLOSURE
• The present disclosure relates to a substrate structure used in semiconductor manufacturing, and more particularly to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination.
BACKGROUND
• The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high level performance in the RF technologies. RF complementary metal-oxide semiconductor (CMOS) and RF micro-electro-mechanical system (MEMS) technologies fabricated on silicon on insulator (SOI) substrates have attracted extensive attention in recent years. Fabrications of these RF technologies on SOI substrates may benefit from low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques.
• Despite the benefits of using SOI substrates and conventional semiconductor manufacturing techniques for RFCMOS and RFMEMS fabrications, it is well known in the industry that a silicon handle layer in the SOI substrate has two undesirable properties that limit the SOI's usage in critical, RF large signal applications: harmonic generations and low resistivity values. By using SOI substrates in RF fabrications, an interface between the silicon handle layer and an adjacent insulator layer will generate significant harmonic signals. RF signals of power levels employed in cellular and other wireless applications are RF signals coupled to this interface and therefore experience significant deterioration with the creation of unwanted harmonic and intermodulation products. Such spectrum degradation causes a number of significant system issues such as unwanted generation of signals in other RF bands which the system is attempting to avoid. In addition, unlike gallium arsenide (GaAs), the silicon handle layer does not have high resistivity values. The relatively low resistivity encountered in the silicon handle layer also limits the performance and quality factor of passive components, such as inductors, transmission lines, and couplers, by the generation of unwanted RF current loss in the silicon handle layer.
• Accordingly, there remains a need for improved substrate designs to benefit from high fabrication yields and low cost of silicon manufacturing without bearing deleterious harmonic generations. In addition, there is also a need to enhance the resistivity values of the substrates in final RF products.
SUMMARY
• The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer may be formed from silicon nitride, which provides selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.
• Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
• FIG. 1 shows an exemplary substrate structure with a buried dielectric layer according to one embodiment of the present disclosure.
• FIG. 2 provides a flow diagram that illustrates an exemplary process to fabricate the exemplary substrate structure shown inFIG. 1.
• FIGS. 3A-3E illustrate the steps associated with the exemplary process provided inFIG. 2.
• FIG. 4 provides a flow diagram that illustrates an exemplary process to fabricate a device using the substrate structure shown inFIG. 1.
• FIGS. 5A-5F illustrate the steps associated with the exemplary process provided inFIG. 4.
• It will be understood that for clear illustrations,FIGS. 1-5 may not be drawn to scale.
DETAILED DESCRIPTION
• The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
• It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
• It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
• Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
• The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
• Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
• FIG. 1 provides asubstrate structure10 according to one embodiment of the present disclosure. In this embodiment, thesubstrate structure10 includes asilicon handle layer12, a firstsilicon oxide layer14 over thesilicon handle layer12, a burieddielectric layer16 over the firstsilicon oxide layer14, a secondsilicon oxide layer18 over the burieddielectric layer16, and asilicon epitaxy layer20 over the secondsilicon oxide layer18. Thesilicon epitaxy layer20 has a ground surface that is opposite the secondsilicon oxide layer18.
• In detail, thesilicon handle layer12 is formed by a low cost silicon material, which has no requirement for high resistivity or low harmonic generation. A thickness of thesilicon handle layer12 is thicker than 100 μms, where 300 μms-700 μms is a typical range. Both the firstsilicon oxide layer14 and the secondsilicon oxide layer18 have a thickness between 200 Angstrom (Å) and 5000 Å. In some applications, the firstsilicon oxide layer14 may not exist in thesubstrate structure10. The burieddielectric layer16 is sandwiched between the firstsilicon oxide layer14 and the secondsilicon oxide layer18.
• The burieddielectric layer16 provides highly selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide. Also, the burieddielectric layer16 is smooth and thin enough so as to not create a significant increase in the thermal resistance of devices built with this technology. A thickness of the burieddielectric layer16 is between 300 Å and 2000 Å. One possible material used to form the burieddielectric layer16 is silicon nitride, which provides selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide. The silicon nitride used for the burieddielectric layer16 also provides a barrier to moisture and other possible chemical contaminants, such as sodium and potassium ions, which may cause significant device reliability issues. Other materials, such as Aluminum Nitride (both piezoelectric and non-piezoelectric options), alumina (Al₂O₃), Beryllium Oxide (BeO), and other suitable compounds may also be used to form the burieddielectric layer16.
• Thesilicon epitaxy layer20 is formed from a device grade silicon material, which has desired silicon epitaxy characteristics to form electronic components. Thesilicon epitaxy layer20 has higher resistivity than thesilicon handle layer12 and thesilicon epitaxy layer20 has lower harmonic generation than thesilicon handle layer12. In general, the resistivity of thesilicon epitaxy layer20 is between 1 ohm/cm and 50 ohm/cm depending on different fabrication processes. A thickness of thesilicon epitaxy layer20 is between 100 Å and 2 μms, where 500 Å-1 μm is a typical range for radio frequency power applications. Those skilled in the art will recognize that the present disclosure may be practiced in a number of different substrate diameters. Typical implementations in today's industry would yield final substrate structure in a 200 mm or 300 mm diameter.
• FIG. 2 provides a flow diagram that illustrates anexemplary process100 to fabricate the substrate structure shown inFIG. 1.FIGS. 3A-3E illustrate the steps associated with theexemplary process100 provided inFIG. 2. Although theexemplary process100 is illustrated as a series of sequential steps, theexemplary process100 is not necessarily order dependent. Some operations may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more operations than those illustrated inFIG. 2.
• Initially, thesilicon handle layer12 and a pre-grindsilicon epitaxy layer20′ are provided as depicted inFIG. 3A (Step102). Then, the firstsilicon oxide layer14 is formed over thesilicon handle layer12 and the secondsilicon oxide layer18 is formed over the pre-grindsilicon epitaxy layer20′ as depicted inFIG. 3B (Step104). The firstsilicon oxide layer14 and the secondsilicon oxide layer18 may be formed by thermally oxidizing thesilicon handle layer12 and the pre-grindsilicon epitaxy layer20′ in a conventional oxidation furnace, respectively. Herein, the formation of the firstsilicon oxide layer14 is optional.
• The burieddielectric layer16 is then deposited over the secondsilicon oxide layer18 as depicted inFIG. 3C (Step106). The depositing process may be implemented by a number of conventional dielectric deposition techniques such as plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition. In some applications, the burieddielectric layer16 may be deposited over the firstsilicon oxide layer14 instead.
• Next, the burieddielectric layer16 is bonded with the firstsilicon oxide layer14, such that the burieddielectric layer16 is sandwiched between the firstsilicon oxide layer14 and the secondsilicon oxide layer18 as depicted inFIG. 3D (Step108). The bonding process may be implemented by a number of different wafer bonding techniques such as anodic bonding, fusion bonding, low temperature glass assisted bonding, or ionic bonding. Some of these bonding techniques may require the deposition of a third silicon oxide layer (not shown) over the burieddielectric layer16 before bonding to the firstsilicon oxide layer14. This third oxide layer may facilitate the bonding process since it provides similar materials to both surfaces which are to be bonded. In another embodiment, if there is no firstsilicon oxide layer14 formed inStep104, the burieddielectric layer16 is directly bonded with thesilicon handle layer12. The parameters for the bonding process, such as temperature and pressure, have to be engineered to manage the mismatches in thermal expansion and stress levels of the different layers that are comprised in the substrate structure.
• Finally, the pre-grindsilicon epitaxy layer20′ is ground to form thesilicon epitaxy layer20 as depicted inFIG. 3E (Step110). A thickness of thesilicon epitaxy layer20 is between 100 Å and 2 μms depending on different applications. For example, if thesilicon epitaxy layer20 is used to form radio frequency power electronics components, the thickness of thesilicon epitaxy layer20 is between 500 Å and 1 μm. In another example, thesilicon epitaxy layer20 may be completely absent from applications such as integrated passive devices (IPD) or micro electro mechanical system (MEMS) technologies. The grinding process may be implemented by a number of conventional chemical/mechanical polishing steps.
• FIG. 4 provides a flow diagram that illustrates anexemplary process200 to fabricate a device using thesubstrate structure10 described above.FIGS. 5A-5F illustrate the steps associated with theexemplary process200 provided inFIG. 4. Although theexemplary process200 is illustrated as a series of sequential steps, theexemplary process200 is not necessarily order dependent. Some operations may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more operations than those illustrated inFIG. 4.
• After thesubstrate structure10 is formed, electronic components may be integrated in or on thesilicon epitaxy layer20 to form anelectronic layer22 as depicted inFIG. 5A (Step202). The formedelectronic layer22 may have a different thickness from thesilicon epitaxy layer20, between 2 μms and 10 μms. If thesubstrate structure10 does not include thesilicon epitaxy layer20 for some applications, such as IPD or MEMS, a conventional method including an oxidation/deposition process is used to form theelectronic layer22.
• Next, aprotective carrier layer24 is mounted to theelectronic layer22 as depicted inFIG. 5B (Step204). Normally, theprotective carrier layer24 has a thickness between 100 μms and 2000 μms. The mounting process may be implemented by simple conventional adhesive techniques or wafer bonding techniques.
• After theprotective carrier layer24 is mounted to theelectronic layer22, thesilicon handle layer12 and the firstsilicon oxide layer14 are removed as depicted inFIG. 5C (Step206). The removal process may be implemented by wet/dry chemical etching techniques.
• Well known etching chemistries used in wet/dry chemical etching techniques are potassium hydroxide/isopropyl alcohol (KOH/IPA), ethylenediamine pyrocatechol (EDP), and tetramethylammonium hydroxide (THAH). All of these etching chemistries etch silicon as well as silicon oxide, where the silicon is etched faster than the silicon oxide. However, none of these etching chemistries can etch silicon nitride at any appreciable rate. Notice that without the introduction of the burieddielectric layer16, it would be extremely difficult to completely etch the thicksilicon handle layer12 and completely stop the etching process in a much thinner silicon oxide layer (the firstsilicon oxide layer14 plus the second silicon oxide layer18). Although these etching chemistries etch silicon at a much faster rate than silicon oxide—for example, KOH etches silicon at a rate 30-50 times faster than silicon oxide—, the silicon oxide layer (the firstsilicon oxide layer14 plus the second silicon oxide layer18) alone cannot offer the control to completely eliminate thesilicon handle layer12 without the risk of puncturing theelectronic layer22. The reason is the silicon oxide layer (the firstsilicon oxide layer14 plus the second silicon oxide layer18) is thousands of times thinner than thesilicon handle layer12 and only has an Angstrom level thickness. During the removal process, thesilicon handle layer12 must be eliminated completely, while a portion of the firstburied oxide layer14 is allowed to remain.
• In the meantime, a new firstsilicon oxide layer14N is formed on a top of atransfer substrate layer26 as depicted inFIG. 5D (Step208). Thetransfer substrate layer26 does not include single crystal silicon and may be formed from polymer, ceramic, or gallium arsenide (GaAs) materials. A thickness of thetransfer substrate layer26 is between 50 μms and 2500 μms. A thickness of the new firstsilicon oxide layer14N is between 200 Å and 5000 Å.
• Next, the burieddielectric layer16 is bonded with the new firstsilicon oxide layer14N, such that the burieddielectric layer16 is sandwiched between the new firstsilicon oxide layer14N and the secondsilicon oxide layer18 as depicted inFIG. 5E (Step210). The bonding process may be implemented by anodic bonding, fusion bonding, low temperature glass assisted bonding, or ionic bonding. If there is a portion of the firstsilicon oxide layer14 remaining in Step206 (not shown inFIG. 5C), the bonding process is to bond the remaining portion of the firstsilicon oxide layer14 with the newsilicon oxide layer14N. The burieddielectric layer16 is still sandwiched between the two silicon oxide layers. In some applications, there is no silicon oxide layer required between the burieddielectric layer16 and thetransfer substrate layer26. Consequently,Step208 may be omitted. InStep210, thetransfer substrate layer26 is directly bonded with the burieddielectric layer16 or bonded with the remaining portion of the first silicon oxide layer14 (not shown). Lastly, theprotective carrier layer24 is removed to form adevice28 as depicted inFIG. 5F (Step212). In some applications, like wafer level fan out (WLFO), thetransfer substrate layer26 is not necessary. Thereby the process steps208 and210 shown inFIGS. 5D and 5E are optional.
• According to one embodiment of the present disclosure, thefinal device28 as shown inFIG. 5F includes thetransfer substrate layer26, which does not include silicon, the newsilicon oxide layer14N over thetransfer substrate layer26, the burieddielectric layer16 over the newsilicon oxide layer14N, where the burieddielectric layer16 is not formed from silicon oxide, the secondsilicon oxide layer18 over the burieddielectric layer16, and theelectronic components layer22 over the secondsilicon oxide layer18. This unique combination of layers yields a low cost fabrication technology suitable for use in RF applications, which benefit from the removal of the silicon handle layer.
• Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (20)

What is claimed is:

1. An apparatus comprising:

a silicon handle layer;

a buried dielectric layer over the silicon handle layer, wherein the buried dielectric layer is not formed from silicon oxide;

an upper silicon oxide layer over the buried dielectric layer; and

a silicon epitaxy layer over the upper silicon oxide layer.

2. The apparatus ofclaim 1 further comprising a lower silicon oxide layer residing between the silicon handle layer and the buried dielectric layer.

3. The apparatus ofclaim 1 wherein the buried dielectric layer is formed from silicon nitride.

4. The apparatus ofclaim 1 wherein the silicon epitaxy layer has a higher resistivity than the silicon handle layer and the silicon epitaxy layer has lower harmonic generation than the silicon handle layer.

5. The apparatus ofclaim 1 wherein:

the silicon epitaxy layer has a higher resistivity than the silicon handle layer;

the silicon epitaxy layer has lower harmonic generation than the silicon handle layer; and

the buried dielectric layer is formed from silicon nitride.

6. The apparatus ofclaim 1 wherein the resistivity of the silicon epitaxy layer is between 1 ohm/cm and 50 ohm/cm.

7. The apparatus ofclaim 1 wherein a thickness of the silicon epitaxy layer is between 100 Å and 2 μms.

8. The apparatus ofclaim 1 wherein a thickness of the silicon handle layer is thicker than 100 μms and a thickness of the silicon epitaxy layer is between 100 Å and 2 μms.

9. The apparatus ofclaim 2 wherein a thickness of the lower silicon oxide layer is between 200 Å and 5000 Å, a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å and a thickness of the buried dielectric layer is between 300 Å and 2000 Å.

10. The apparatus ofclaim 2 wherein a thickness of the silicon handle layer is thicker than 100 μms, a thickness of the silicon epitaxy layer is between 100 Å and 2 μms, a thickness of the lower silicon oxide layer is between 200 Å and 5000 Å, a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å, and a thickness of the buried dielectric layer is between 300 Å and 2000 Å.

11. The apparatus ofclaim 1 wherein the silicon epitaxy layer has a ground surface that is opposite the upper silicon oxide layer.

12. An apparatus comprising:

a buried dielectric layer over the transfer substrate layer, wherein the buried dielectric layer is not formed from silicon oxide;

an upper silicon oxide layer over the buried dielectric layer; and

an electronic layer over the second silicon oxide layer.

13. The apparatus ofclaim 12 further comprising a transfer substrate layer that does not comprise single crystal silicon.

14. The apparatus ofclaim 13 wherein the transfer substrate layer is formed from one of a group consisting of polymer, ceramic, and gallium arsenide.

15. The apparatus ofclaim 13 wherein a thickness of the transfer substrate layer is between 50 μms and 2500 μms.

16. The apparatus ofclaim 13 further comprising a lower silicon oxide layer residing between the transfer substrate layer and the buried dielectric layer.

17. The apparatus ofclaim 12 wherein the buried dielectric layer is formed from silicon nitride.

18. The apparatus ofclaim 12 wherein a thickness of the electronic layer is between 2 μms and 10 μms.

19. The apparatus ofclaim 12 wherein a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å, and a thickness of the buried dielectric layer is between 300 Å and 2000 Λ.

20. The apparatus ofclaim 16 wherein a thickness of the electronic layer is between 2 μms and 10 μms, a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å, a thickness of the buried dielectric layer is between 300 Å and 2000 Å, a thickness of the lower silicon oxide layer is between 200 Å and 5000 Å, and a thickness of the transfer substrate layer is between 50 μms and 2500 μms.

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