US20160342330A1 - Isolation switching for backup memory - Google Patents

Abstract

Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 14/173,219, titled “Isolation Switching For Backup Memory,” filed Feb. 5, 2014, which is a continuation of U.S. patent application Ser. No. 13/905,048, titled “Isolation Switching For Backup Memory,” filed May 29, 2013, now U.S. Pat. No. 8,671,243, issued Mar. 11, 2014, which is a continuation of U.S. patent application Ser. No. 13/536,173, titled “Data Transfer Scheme For Non-Volatile Memory Module,” filed Jun. 28, 2012, now U.S. Pat. No. 8,516,187, issued Aug. 20, 2013, which is a divisional of U.S. patent application Ser. No. 12/240,916, titled “Non-Volatile Memory Module,” filed Sep. 29, 2008, now U.S. Pat. No. 8,301,833, issued Oct. 30, 2012, which is a continuation of U.S. patent application Ser. No. 12/131,873, filed Jun. 2, 2008, which claims the benefit of U.S. Provisional Application No. 60/941,586, filed Jun. 1, 2007, the contents of which are incorporated by reference herein in their entirety.
• This application may be considered related to U.S. patent application Ser. No. 14/173,242, titled “Isolation Switching For Backup Of Registered Memory,” filed Feb. 5, 2014, which is a continuation of U.S. patent application Ser. No. 13/905,053, titled “Isolation Switching For Backup Of Registered Memory,” filed May 29, 2013, now U.S. Pat. No. 8,677,060, issued Mar. 18, 2014, which is a continuation of U.S. patent application Ser. No. 13/536,173, titled “Data Transfer Scheme For Non-Volatile Memory Module,” filed Jun. 28, 2012, now U.S. Pat. No. 8,516,187, issued Aug. 20, 2013, which is a divisional of U.S. patent application Ser. No. 12/240,916, titled “Non-Volatile Memory Module,” filed Sep. 29, 2008, now U.S. Pat. No. 8,301,833, issued Oct. 30, 2012, which is a continuation of U.S. patent application Ser. No. 12/131,873, filed Jun. 2, 2008, now abandoned, which claims the benefit of U.S. Provisional Application No. 60/941,586, filed Jun. 1, 2007, the contents of which are incorporated by reference herein in their entirety.
BACKGROUND
• Certain types of memory modules comprise a plurality of dynamic random-access memory (DRAM) devices mounted on a printed circuit board (PCB). These memory modules are typically mounted in a memory slot or socket of a computer system (e.g., a server system or a personal computer) and are accessed by the computer system to provide volatile memory to the computer system.
• Volatile memory generally maintains stored information only when it is powered. Batteries have been used to provide power to volatile memory during power failures or interruptions. However, batteries may require maintenance, may need to be replaced, are not environmentally friendly, and the status of batteries can be difficult to monitor.
• Non-volatile memory can generally maintain stored information while power is not applied to the non-volatile memory. In certain circumstances, it can therefore be useful to backup volatile memory using non-volatile memory.
SUMMARY
• Disclosed herein is a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.
• Also disclosed herein is a method for operating a memory system. The method includes coupling a circuit to a host system, a volatile memory subsystem, and a controller, wherein the controller is coupled to a non-volatile memory subsystem. In a first mode of operation that allows data to be communicated between the volatile memory subsystem and the host system, the circuit is used to (i) selectively isolate the controller from the volatile memory subsystem, and (ii) selectively couple the volatile memory subsystem to the host system. In a second mode of operation that allows data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem via the controller, the circuit is used to (i) selectively couple the controller to the volatile memory subsystem, and (ii) selectively isolate the volatile memory subsystem from the host system.
• Also disclosed herein is a nontransitory computer readable storage medium storing one or more programs configured to be executed by one or more computing devices. The programs, when executing on the one or more computing devices, cause a circuit that is coupled to a host system, to a volatile memory subsystem, and to a controller that is coupled to a non-volatile memory subsystem, to perform a method in which, in a first mode of operation that allows data to be communicated between the volatile memory subsystem and the host system, operating the circuit to (i) selectively isolate the controller from the volatile memory subsystem, and (ii) selectively couple the volatile memory subsystem to the host system. In a second mode of operation that allows data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem via the controller, operating the circuit to (i) selectively couple the controller to the volatile memory subsystem, and (ii) selectively isolate the volatile memory subsystem from the host system.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a block diagram of an example memory system compatible with certain embodiments described herein.
• FIG. 2 is a block diagram of an example memory module with ECC (error-correcting code) having a volatile memory subsystem with nine volatile memory elements and a non-volatile memory subsystem with five non-volatile memory elements in accordance with certain embodiments described herein.
• FIG. 3 is a block diagram of an example memory module having a microcontroller unit and logic element integrated into a single device in accordance with certain embodiments described herein.
• FIGS. 4A-4C schematically illustrate example embodiments of memory systems having volatile memory subsystems comprising registered dual in-line memory modules in accordance with certain embodiments described herein.
• FIG. 5 schematically illustrates an example power module of a memory system in accordance with certain embodiments described herein.
• FIG. 6 is a flowchart of an example method of providing a first voltage and a second voltage to a memory system including volatile and non-volatile memory subsystems.
• FIG. 7 is a flowchart of an example method of controlling a memory system operatively coupled to a host system and which includes at least 100 percent more storage capacity in non-volatile memory than in volatile memory.
• FIG. 8 schematically illustrates an example clock distribution topology of a memory system in accordance with certain embodiments described herein.
• FIG. 9 is a flowchart of an example method of controlling a memory system operatively coupled to a host system, the method including operating a volatile memory subsystem at a reduced rate in a back-up mode.
• FIG. 10 schematically illustrates an example topology of a connection to transfer data slices from two DRAM segments of a volatile memory subsystem of a memory system to a controller of the memory system.
• FIG. 11 is a flowchart of an example method of controlling a memory system operatively coupled to a host system, the method including backing up and/or restoring a volatile memory subsystem in slices.
DETAILED DESCRIPTION
• Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory, and a controller. The controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. Trigger conditions can include, for example, a power failure, power reduction, request by the host system, etc. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which does not comprise a battery and may include, for example, a capacitor or capacitor array.
• In certain embodiments, the memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or by the controller when the volatile memory is interacting with the host system. For example, one or more isolation devices may isolate the non-volatile memory and the controller from the volatile memory when the volatile memory is interacting with the host system and may allow communication between the volatile memory and the non-volatile memory when the data of the volatile memory is being restored or backed-up. This configuration generally protects the operation of the volatile memory when isolated while providing backup and restore capability in the event of a trigger condition, such as a power failure.
• In certain embodiments described herein, the memory system includes a power module which provides power to the various components of the memory system from different sources based on a state of the memory system in relation to a trigger condition (e.g., a power failure). The power module may switch the source of the power to the various components in order to efficiently provide power in the event of the power failure. For example, when no power failure is detected, the power module may provide power to certain components, such as the volatile memory, from system power while charging a secondary power source (e.g., a capacitor array). In the event of a power failure or other trigger condition, the power module may power the volatile memory elements using the previously charged secondary power source.
• In certain embodiments, the power module transitions relatively smoothly from powering the volatile memory with system power to powering it with the secondary power source. For example, the power system may power volatile memory with a third power source from the time the memory system detects that power failure is likely to occur until the time the memory system detects that the power failure has actually occurred.
• In certain embodiments, the volatile memory system can be operated at a reduced frequency during backup and/or restore operations which can improve the efficiency of the system and save power. In some embodiments, during backup and/or restore operations, the volatile memory communicates with the non-volatile memory by writing and/or, reading data words in bit-wise slices instead of by writing entire words at once. In certain embodiments, when each slice is being written to or read from the volatile memory the unused slice(s) of volatile memory is not active, which can reduce the power consumption of the system.
• In yet other embodiments, the non-volatile memory can include at least 100 percent more storage capacity than the volatile memory. This configuration can allow the memory system to efficiently handle subsequent trigger conditions.
• FIG. 1 is a block diagram of anexample memory system10 compatible with certain embodiments described herein. Thememory system10 can be coupled to a host computer system and can include avolatile memory subsystem30, anon-volatile memory subsystem40, and acontroller62 operatively coupled to thenon-volatile memory subsystem40. In certain embodiments, thememory system10 includes at least onecircuit52 configured to selectively operatively decouple thecontroller62 from thevolatile memory subsystem30.
• In certain embodiments, thememory system10 comprises a memory module. Thememory system10 may comprise a printed-circuit board (PCB)20. In certain embodiments, thememory system10 has a memory capacity of 512-MB, 1-GB, 2-GB, 4-GB, or 8-GB. Other volatile memory capacities are also compatible with certain embodiments described herein. In certain embodiments, thememory system10 has a non-volatile memory capacity of 512-MB, 1-GB, 2-GB, 4-GB, 8-GB, 16-GB, or 32-GB. Other non-volatile memory capacities are also compatible with certain embodiments described herein. In addition,memory systems10 having widths of 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits), are compatible with embodiments described herein. In certain embodiments, thePCB20 has an industry-standard form factor. For example, thePCB20 can have a low profile (LP) form factor with a height of 30 millimeters and a width of 133.35 millimeters. In certain other embodiments, thePCB20 has a very high profile (VHP) form factor with a height of 50 millimeters or more. In certain other embodiments, thePCB20 has a very low profile (VLP) form factor with a height of 18.3 millimeters. Other form factors including, but not limited to, small-outline (SO-DIMM), unbuffered (UDIMM), registered (RDIMM), fully-buffered (FBDIMM), miniDIMM, mini-RDIMM, VLP mini-DIMM, micro-DIMM, and SRAM DIMM are also compatible with certain embodiments described herein. For example, in other embodiments, certain non-DIMM form factors are possible such as, for example, single in-line memory module (SIMM), multi-media card (MMC), and small computer system interface (SCSI).
• In certain preferred embodiments, thememory system10 is in electrical communication with the host system. In other embodiments, thememory system10 may communicate with a host system using some other type of communication, such as, for example, optical communication. Examples of host systems include, but are not limited to, blade servers, 1U servers, personal computers (PCs), and other applications in which space is constrained or limited. Thememory system10 can be in communication with a disk controller of a computer system, for example. ThePCB20 can comprise aninterface22 that is configured to be in electrical communication with the host system (not shown). For example, theinterface22 can comprise a plurality of edge connections which fit into a corresponding slot connector of the host system. Theinterface22 of certain embodiments provides a conduit for power voltage as well as data, address, and control signals between thememory system10 and the host system. For example, theinterface22 can comprise a standard 240-pin DDR2 edge connector.
• Thevolatile memory subsystem30 comprises a plurality ofvolatile memory elements32 and thenon-volatile memory subsystem40 comprises a plurality ofnon-volatile memory elements42. Certain embodiments described herein advantageously provide non-volatile storage via thenon-volatile memory subsystem40 in addition to high-performance (e.g., high speed) storage via thevolatile memory subsystem30. In certain embodiments, the first plurality ofvolatile memory elements32 comprises two or more dynamic random-access memory (DRAM) elements. Types ofDRAM elements32 compatible with certain embodiments described herein include, but are not limited to, DDR, DDR2, DDR3, and synchronous DRAM (SDRAM). For example, in the block diagram ofFIG. 1, thefirst memory bank30 comprises eight 64 M×8DDR2 SDRAM elements32. Thevolatile memory elements32 may comprise other types of memory elements such as static random-access memory (SRAM). In addition,volatile memory elements32 having bit widths of 4, 8, 16, 32, as well as other bit widths, are compatible with certain embodiments described herein.Volatile memory elements32 compatible with certain embodiments described herein have packaging which include, but are not limited to, thin small-outline package (TSOP), ball-grid-array (BGA), fine-pitch BGA (FBGA), micro-BGA (1.1,BGA), mini-BGA (mBGA), and chip-scale packaging (CSP).
• In certain embodiments, the second plurality ofnon-volatile memory elements42 comprises one or more flash memory elements. Types offlash memory elements42 compatible with certain embodiments described herein include, but are not limited to, NOR flash, NAND flash, ONE-NAND flash, and multi-level cell (MLC). For example, in the block diagram ofFIG. 1, thesecond memory bank40 comprises 512 MB of flash memory organized as four 128 Mb×8 NANDflash memory elements42. In addition,nonvolatile memory elements42 having bit widths of 4, 8, 16, 32, as well as other bit widths, are compatible with certain embodiments described herein.Non-volatile memory elements42 compatible with certain embodiments described herein have packaging which include, but are not limited to, thin small-outline package (TSOP), ball-grid-array (BGA), fine-pitch BGA (FBGA), micro-BGA (PGA), mini-BGA (mBGA), and chip-scale packaging (CSP).
• FIG. 2 is a block diagram of anexample memory module10 with ECC (error-correcting code) having avolatile memory subsystem30 with ninevolatile memory elements32 and anon-volatile memory subsystem40 with fivenon-volatile memory elements42 in accordance with certain embodiments described herein. Theadditional memory element32 of thefirst memory bank30 and theadditional memory element42 of thesecond memory bank40 provide the ECC capability. In certain other embodiments, thevolatile memory subsystem30 comprises other numbers of volatile memory elements32 (e.g., 2, 3, 4, 5, 6, 7, more than 9). In certain embodiments, thenon-volatile memory subsystem40 comprises other numbers of non-volatile memory elements42 (e.g., 2, 3, more than 5).
• Referring toFIG. 1, in certain embodiments, thelogic element70 comprises a field-programmable gate array (FPGA). In certain embodiments, thelogic element70 comprises an FPGA available from Lattice Semiconductor Corporation which includes an internal flash. In certain other embodiments, thelogic element70 comprises an FPGA available from another vendor. The internal flash can improve the speed of thememory system10 and save physical space. Other types oflogic elements70 compatible with certain embodiments described herein include, but are not limited to, a programmable-logic device (PLD), an application-specific integrated circuit (ASIC), a custom-designed semiconductor device, a complex programmable logic device (CPLD). In certain embodiments, thelogic element70 is a custom device. In certain embodiments, thelogic element70 comprises various discrete electrical elements, while in certain other embodiments, thelogic element70 comprises one or more integrated circuits.FIG. 3 is a block diagram of anexample memory module10 having amicrocontroller unit60 andlogic element70 integrated into asingle controller62 in accordance with certain embodiments described herein. In certain embodiments, thecontroller62 includes one or more other components. For example, in one embodiment, an FPGA without an internal flash is used and thecontroller62 includes a separate flash memory component which stores configuration information to program the FPGA.
• In certain embodiments, the at least onecircuit52 comprises one or more switches coupled to thevolatile memory subsystem30, to thecontroller62, and to the host computer (e.g., via theinterface22, as schematically illustrated byFIGS. 1-3). The one or more switches are responsive to signals (e.g., from the controller62) to selectively operatively decouple thecontroller62 from thevolatile memory subsystem30 and to selectively operatively couple thecontroller62 to thevolatile memory subsystem30. In addition, in certain embodiments, the at least onecircuit52 selectively operatively couples and decouples thevolatile memory subsystem30 and the host system.
• In certain embodiments, thevolatile memory subsystem30 can comprise a registered DIMM subsystem comprising one ormore registers160 and a plurality ofDRAM elements180, as schematically illustrated byFIG. 4A. In certain such embodiments, the at least onecircuit52 can comprise one ormore switches172 coupled to the controller62 (e.g., logic element70) and to thevolatile memory subsystem30 which can be actuated to couple and decouple thecontroller62 to and from thevolatile memory subsystem30, respectively. Thememory system10 further comprises one ormore switches170 coupled to the one ormore registers160 and to the plurality ofDRAM elements180 as schematically illustrated byFIG. 4A. The one ormore switches170 can be selectively switched, thereby selectively operatively coupling thevolatile memory subsystem30 to thehost system150. In certain other embodiments, as schematically illustrated byFIG. 4B, the one ormore switches174 are also coupled to the one ormore registers160 and to apower source162 for the one ormore registers160. The one ormore switches174 can be selectively switched to turn power on or off to the one ormore registers160, thereby selectively operatively coupling thevolatile memory subsystem30 to thehost system150. As schematically illustrated byFIG. 4C, in certain embodiments the at least onecircuit52 comprises a dynamic on-die termination (ODT)176 circuit of thelogic element70. For example, thelogic element70 can comprise adynamic ODT circuit176 which selectively operatively couples and decouples thelogic element70 to and from thevolatile memory subsystem30, respectively. In addition, and similar to the example embodiment ofFIG. 4A described above, the one ormore switches170 can be selectively switched, thereby selectively operatively coupling thevolatile memory subsystem30 to thehost system150.
• Certain embodiments described herein utilize thenon-volatile memory subsystem40 as a flash “mirror” to provide backup of thevolatile memory subsystem30 in the event of certain system conditions. For example, thenon-volatile memory subsystem40 may backup thevolatile memory subsystem30 in the event of a trigger condition, such as, for example, a power failure or power reduction or a request from the host system. In one embodiment, thenon-volatile memory subsystem40 holds intermediate data results in a noisy system environment when the host computer system is engaged in a long computation. In certain embodiments, a backup may be performed on a regular basis. For example, in one embodiment, the backup may occur every millisecond in response to a trigger condition. In certain embodiments, the trigger condition occurs when thememory system10 detects that the system voltage is below a certain threshold voltage. For example, in one embodiment, the threshold voltage is 10 percent below a specified operating voltage. In certain embodiments, a trigger condition occurs when the voltage goes above a certain threshold value, such as, for example, 10 percent above a specified operating voltage. In some embodiments, a trigger condition occurs when the voltage goes below a threshold or above another threshold. In various embodiments, a backup and/or restore operation may occur in reboot and/or non-reboot trigger conditions.
• As schematically illustrated byFIGS. 1 and 2, in certain embodiments, thecontroller62 may comprise a microcontroller unit (MCU)60 and alogic element70. In certain embodiments, theMCU60 provides memory management for thenon-volatile memory subsystem40 and controls data transfer between thevolatile memory subsystem30 and thenon-volatile memory subsystem40. TheMCU60 of certain embodiments comprises a 16-bit microcontroller, although other types of microcontrollers are also compatible with certain embodiments described herein. As schematically illustrated byFIGS. 1 and 2, thelogic element70 of certain embodiments is in electrical communication with thenon-volatile memory subsystem40 and theMCU60. Thelogic element70 can provide signal level translation between the volatile memory elements32 (e.g., 1.8V SSTL-2 for DDR2 SDRAM elements) and the non-volatile memory elements42 (e.g., 3V TTL for NAND flash memory elements). In certain embodiments, thelogic element70 is also programmed to perform address/address translation between thevolatile memory subsystem30 and thenon-volatile memory subsystem40. In certain preferred embodiments, 1-NAND type flash are used for thenon-volatile memory elements42 because of their superior read speed and compact structure.
• Thememory system10 of certain embodiments is configured to be operated in at least two states. The at least two states can comprise a first state in which thecontroller62 and thenon-volatile memory subsystem40 are operatively decoupled (e.g., isolated) from thevolatile memory subsystem30 by the at least onecircuit52 and a second state in which thevolatile memory subsystem30 is operatively coupled to thecontroller62 to allow data to be communicated between thevolatile memory subsystem30 and thenonvolatile memory subsystem40 via thecontroller62. Thememory system10 may transition from the first state to the second state in response to a trigger condition, such as when thememory system10 detects that there is a power interruption (e.g., power failure or reduction) or a system hang-up.
• Thememory system10 may further comprise avoltage monitor50. Thevoltage monitor circuit50 monitors the voltage supplied by the host system via theinterface22. Upon detecting a low voltage condition (e.g., due to a power interruption to the host system), thevoltage monitor circuit50 may transmit a signal to thecontroller62 indicative of the detected condition. Thecontroller62 of certain embodiments responds to the signal from thevoltage monitor circuit50 by transmitting a signal to the at least onecircuit52 to operatively couple the controller to thevolatile memory system30, such that thememory system10 enters the second state. For example, the voltage monitor50 may send a signal to theMCU60 which responds by accessing the data on thevolatile memory system30 and by executing a write cycle on thenon-volatile memory subsystem40. During this write cycle, data is read from thevolatile memory subsystem30 and is transferred to thenon-volatile memory subsystem40 via theMCU60. In certain embodiments, thevoltage monitor circuit50 is part of the controller62 (e.g., part of the MCU60) and thevoltage monitor circuit50 transmits a signal to the other portions of thecontroller62 upon detecting a power threshold condition.
• The isolation or operational decoupling of thevolatile memory subsystem30 from the non-volatile memory subsystem in the first state can preserve the integrity of the operation of thememory system10 during periods of operation in which signals (e.g., data) are transmitted between the host system and thevolatile memory subsystem30. For example, in one embodiment during such periods of operation, thecontroller62 and thenonvolatile memory subsystem40 do not add a significant capacitive load to thevolatile memory system30 when thememory system10 is in the first state. In certain such embodiments, the capacitive load of thecontroller62 and thenon-volatile memory subsystem40 do not significantly affect the signals propagating between thevolatile memory subsystem30 and the host system. This can be particularly advantageous in relatively high-speed memory systems where loading effects can be significant. In one preferred embodiment, the at least onecircuit52 comprises an FSA1208 Low-Power, Eight-Port, Hi-Speed Isolation Switch from Fairchild Semiconductor. In other embodiments, the at least onecircuit52 comprises other types of isolation devices.
• Power may be supplied to thevolatile memory subsystem30 from a first power supply (e.g., a system power supply) when thememory system10 is in the first state and from asecond power supply80 when thememory system10 is in the second state. In certain embodiments, thememory system10 is in the first state when no trigger condition (e.g., a power failure) is present and thememory system10 enters the second state in response to a trigger condition. In certain embodiments, thememory system10 has a third state in which thecontroller62 is operatively decoupled from thevolatile memory subsystem30 and power is supplied to thevolatile memory subsystem30 from a third power supply (not shown). For example, in one embodiment the third power supply may provide power to thevolatile memory subsystem30 when thememory system10 detects that a trigger condition is likely to occur but has not yet occurred.
• In certain embodiments, thesecond power supply80 does not comprise a battery. Because a battery is not used, thesecond power supply80 of certain embodiments may be relatively easy to maintain, does not generally need to be replaced, and is relatively environmentally friendly. In certain embodiments, as schematically illustrated byFIG. 13, thesecond power supply80 comprises a step-uptransformer82, a step-downtransformer84, and acapacitor bank86 comprising one or more capacitors (e.g., double-layer capacitors). In one example embodiment, capacitors may take about three to four minutes to charge and about two minutes to discharge. In other embodiments, the one or more capacitors may take a longer time or a shorter time to charge and/or discharge. For example, in certain embodiments, thesecond power supply80 is configured to power thevolatile memory subsystem30 for less than thirty minutes. In certain embodiments, thesecond power supply80 may comprise a battery. For example, in certain embodiments, thesecond power supply80 comprises a battery and one or more capacitors and is configured to power thevolatile memory subsystem30 for no more than thirty minutes.
• In certain embodiments, thecapacitor bank86 of thesecond power supply80 is charged by the first power supply while thememory system10 is in the first state. As a result, thesecond power supply80 is fully charged when thememory system10 enters the second state. Thememory system10 and thesecond power supply80 may be located on the same printedcircuit board20. In other embodiments, thesecond power supply80 may not be on the same printedcircuit board20 and may be tethered to the printedcircuit board20, for example.
• When operating in the first state, in certain embodiments, the step-uptransformer82 keeps thecapacitor bank86 charged at a peak value. In certain embodiments, the step-downtransformer84 acts as a voltage regulator to ensure that regulated voltages are supplied to the memory elements (e.g., 1.8V to thevolatile DRAM elements32 and 3.0V to the non-volatile flash memory elements42) when operating in the second state (e.g., during power down). In certain embodiments, as schematically illustrated byFIGS. 1-3, thememory module10 further comprises a switch90 (e.g., FET switch) that switches power provided to thecontroller62, thevolatile memory subsystem30, and thenon-volatile memory subsystem40, between the power from thesecond power supply80 and the power from the first power supply (e.g., system power) received via theinterface22. For example, theswitch90 may switch from the first power supply to thesecond power supply80 when the voltage monitor50 detects a low voltage condition. Theswitch90 of certain embodiments advantageously ensures that thevolatile memory elements32 andnon-volatile memory elements42 are powered long enough for the data to be transferred from thevolatile memory elements32 and stored in thenon-volatile memory elements42. In certain embodiments, after the data transfer is complete, theswitch90 then switches back to the first power supply and thecontroller62 transmits a signal to the at least onecircuit52 to operatively decouple thecontroller62 from thevolatile memory subsystem30, such that thememory system10 reenters the first state.
• When thememory system10 re-enters the first state, data may be transferred back from thenon-volatile memory subsystem40 to thevolatile memory subsystem30 via thecontroller62. The host system can then resume accessing thevolatile memory subsystem30 of thememory module10. In certain embodiments, after thememory system10 enters or re-enters the first state (e.g., after power is restored), the host system accesses thevolatile memory subsystem30 rather than thenon-volatile memory subsystem40 because thevolatile memory elements32 have superior read/write characteristics. In certain embodiments, the transfer of data from thevolatile memory bank30 to thenonvolatile memory bank40, or from thenon-volatile memory bank40 to thevolatile memory bank30, takes less than one minute per GB.
• In certain embodiments, thememory system10 protects the operation of the volatile memory when communicating with the host-system and provides backup and restore capability in the event of a trigger condition such as a power failure. In certain embodiments, thememory system10 copies the entire contents of thevolatile memory subsystem30 into thenon-volatile memory subsystem40 on each backup operation. Moreover, in certain embodiments, the entire contents of thenon-volatile memory subsystem40 are copied back into thevolatile memory subsystem30 on each restore operation. In certain embodiments, the entire contents of thenon-volatile memory subsystem40 are accessed for each backup and/or restore operation, such that the non-volatile memory subsystem40 (e.g., flash memory subsystem) is used generally uniformly across its memory space and wear-leveling is not performed by thememory system10. In certain embodiments, avoiding wear-leveling can decrease cost and complexity of thememory system10 and can improve the performance of thememory system10. In certain other embodiments, the entire contents of thevolatile memory subsystem30 are not copied into thenon-volatile memory subsystem40 on each backup operation, but only a partial copy is performed. In certain embodiments, other management capabilities such as bad-block management and error management for the flash memory elements of thenon-volatile memory subsystem40 are performed in thecontroller62.
• Thememory system10 generally operates as a write-back cache in certain embodiments. For example, in one embodiment, the host system (e.g., a disk controller) writes data to thevolatile memory subsystem30 which then writes the data to non-volatile storage which is not part of thememory system10, such as, for example, a hard disk. The disk controller may wait for an acknowledgment signal from thememory system10 indicating that the data has been written to the hard disk or is otherwise secure. Thememory system10 of certain embodiments can decrease delays in the system operation by indicating that the data has been written to the hard disk before it has actually done so. In certain embodiments, thememory system10 will still be able to recover the data efficiently in the event of a power outage because of the backup and restore capabilities described herein. In certain other embodiments, thememory system10 may be operated as a write-through cache or as some other type of cache.
• FIG. 5 schematically illustrates anexample power module100 of thememory system10 in accordance with certain embodiments described herein. Thepower module100 provides power to the various components of thememory system10 using different elements based on a state of thememory system10 in relation to a trigger condition. In certain embodiments, thepower module100 comprises one or more of the components described above with respect toFIG. 1. For example, in certain embodiments, thepower module100 includes thesecond power supply80 and theswitch90.
• Thepower module100 provides a plurality of voltages to thememory system10 comprising non-volatile andvolatile memory subsystems30,40. The plurality of voltages comprises at least afirst voltage102 and asecond voltage104. Thepower module100 comprises aninput106 providing athird voltage108 to thepower module100 and avoltage conversion element120 configured to provide thesecond voltage104 to thememory system10. Thepower module100 further comprises afirst power element130 configured to selectively provide afourth voltage110 to theconversion element120. In certain embodiments, thefirst power element130 comprises a pulse-width modulation power controller. For example, in one example embodiment, thefirst power element130 is configured to receive a 1.8V input system voltage as thethird voltage108 and to output a modulated 5V output as thefourth voltage110.
• Thepower module100 further comprises asecond power element140 can be configured to selectively provide afifth voltage112 to theconversion element120. Thepower module100 can be configured to selectively provide thefirst voltage102 to thememory system10 either from theconversion element120 or from theinput106.
• Thepower module100 can be configured to be operated in at least three states in certain embodiments. In a first state, thefirst voltage102 is provided to thememory system10 from theinput106 and thefourth voltage110 is provided to theconversion element120 from thefirst power element130. In a second state, thefourth voltage110 is provided to theconversion element120 from thefirst power element130 and thefirst voltage102 is provided to thememory system10 from theconversion element120. In the third state, thefifth voltage112 is provided to theconversion element120 from thesecond power element140 and thefirst voltage104 is provided to thememory system10 from theconversion element120.
• In certain embodiments, thepower module100 transitions from the first state to the second state upon detecting that a trigger condition is likely to occur and transitions from the second state to the third state upon detecting that the trigger condition has occurred. For example, thepower module100 may transition to the second state when it detects that a power failure is about to occur and transitions to the third state when it detects that the power failure has occurred. In certain embodiments, providing thefirst voltage102 in the second state from thefirst power element130 rather than from theinput106 allows a smoother transition from the first state to the third state. For example, in certain embodiments, providing thefirst voltage102 from thefirst power element130 has capacitive and other smoothing effects. In addition, switching the point of power transition to be between theconversion element120 and the first andsecond power elements130,140 (e.g., the sources of the pre-regulatedfourth voltage110 in the second state and the pre-regulatedfifth voltage112 in the third state) can smooth out potential voltage spikes.
• In certain embodiments, thesecond power element140 does not comprise a battery and may comprise one or more capacitors. For example, as schematically illustrated inFIG. 4, thesecond power element140 comprises acapacitor array142, a buck-boost converter144 which adjusts the voltage for charging the capacitor array and a voltage/current limiter146 which limits the charge current to thecapacitor array142 and stops charging thecapacitor array142 when it has reached a certain charge voltage. In one example embodiment, thecapacitor array142 comprises two 50 farad capacitors capable of holding a total charge of 4.6V. For example, in one example embodiment, the buck-boost converter144 receives a 1.8V system voltage (first voltage108) and boosts the voltage to 4.3V which is outputted to the voltagecurrent limiter146. The voltage/current limiter146 limits the current going to thecapacitor array142 to1A and stops charging thearray142 when it is charged to 4.3V. Although described with respect to certain example embodiments, one of ordinary skill will recognize from the disclosure herein that thesecond power element140 may include alternative embodiments. For example, different components and/or different value components may be used. For example, in other embodiments, a pure boost converter may be used instead of a buck-boost converter. In another embodiment, only one capacitor may be used instead of acapacitor array142.
• Theconversion element120 can comprise one or more buck converters and/or one or more buck-boost converters. Theconversion element120 may comprise a plurality ofsub-blocks122,124,126 as schematically illustrated byFIG. 4, which can provide more voltages in addition to thesecond voltage104 to thememory system10. The sub-blocks may comprise various converter circuits such as buck-converters, boost converters, and buck-boost converter circuits for providing various voltage values to thememory system10. For example, in one embodiment, sub-block122 comprises a buck converter, sub-block124 comprises a dual buck converter, andsub-block126 comprises a buck-boost converter as schematically illustrated byFIG. 4. Various other components for the sub-blocks122,124,126 of theconversion element120 are also compatible with certain embodiments described herein. In certain embodiments, theconversion element120 receives as input either thefourth voltage110 from thefirst power element130 or thefifth voltage112 from thesecond power element140, depending on the state of thepower module100, and reduces the input to an appropriate amount for powering various components of the memory system. For example, the buck-converter of sub-block122 can provide 1.8V at2A for about 60 seconds to the volatile memory elements32 (e.g., DRAM), the non-volatile memory elements42 (e.g., flash), and the controller62 (e.g., an FPGA) in one embodiment. The sub-block124 can provide thesecond voltage104 as well as another reducedvoltage105 to thememory system10. In one example embodiment, thesecond voltage104 is 2.5V and is used to power the at least one circuit52 (e.g., isolation device) and the otherreduced voltage105 is 1.2V and is used to power the controller62 (e.g., FPGA). The sub-block126 can provide yet anothervoltage107 to thememory system10. For example, thevoltage107 may be 3.3V and may be used to power both thecontroller62 and the at least onecircuit52.
• Although described with respect to certain example embodiments, one of ordinary skill will recognize from the disclosure herein that theconversion element120 may include alternative embodiments. For example, there may be more or less sub-blocks which may comprise other types of converters (e.g., pure boost converters) or which may produce different voltage values. In one embodiment, thevolatile memory elements32 andnonvolatile memory elements42 are powered using independent voltages and are not both powered using thefirst voltage102.
• FIG. 6 is a flowchart of anexample method200 of providing afirst voltage102 and asecond voltage104 to amemory system10 including volatile andnonvolatile memory subsystems30,40. While themethod200 is described herein by reference to thememory system10 schematically illustrated byFIGS. 1-4, other memory systems are also compatible with embodiments of themethod200. During a first condition, themethod200 comprises providing thefirst voltage102 to thememory system10 from aninput power supply106 and providing thesecond voltage104 to thememory system10 from a first power subsystem inoperational block210. For example, in one embodiment, the first power subsystem comprises thefirst power element130 and thevoltage conversion element120 described above with respect toFIG. 4. In other embodiments, other first power subsystems are used.
• Themethod200 further comprises detecting a second condition inoperational block220. In certain embodiments, detecting the second condition comprises detecting that a trigger condition is likely to occur. During the second condition, themethod200 comprises providing thefirst voltage102 and thesecond voltage104 to thememory system10 from the first power subsystem in anoperational block230. For example, referring toFIG. 4, aswitch148 can be toggled to provide thefirst voltage102 from theconversion element120 rather than from the input power supply.
• Themethod200 further comprises charging a second power subsystem inoperational block240. In certain embodiments, the second power subsystem comprises thesecond power element140 or another power supply that does not comprise a battery. For example, in one embodiment, the second power subsystem comprises thesecond power element140 and thevoltage conversion element120 described above with respect toFIG. 4. In other embodiments, some other second power subsystem is used.
• Themethod200 further comprises detecting a third condition in anoperational block250 and during the third condition, providing thefirst voltage102 and thesecond voltage104 to thememory system10 from thesecond power subsystem140 in anoperational block250. In certain embodiments, detecting the third condition comprises detecting that the trigger condition has occurred. The trigger condition may comprise various conditions described herein. In various embodiments, for example, the trigger condition comprises a power reduction, power failure, or system hang-up. The operational blocks of themethod200 may be performed in different orders in various embodiments. For example, in certain embodiments, thesecond power subsystem140 is charged before detecting the second condition.
• In certain embodiments, thememory system10 comprises avolatile memory subsystem30 and anon-volatile memory subsystem40 comprising at least 100 percent more storage capacity than does the volatile memory subsystem. Thememory system10 also comprises acontroller62 operatively coupled to thevolatile memory subsystem30 and operatively coupled to thenon-volatile memory subsystem40. Thecontroller62 can be configured to allow data to be communicated between thevolatile memory subsystem30 and the host system when thememory system10 is operating in a first state and to allow data to be communicated between thevolatile memory subsystem30 and thenon-volatile memory subsystem40 when thememory system10 is operating in a second state.
• Although thememory system10 having extra storage capacity of thenon-volatile memory subsystem40 has been described with respect to certain embodiments, alternative configurations exist. For example, in certain embodiments, there may be more than 100 percent more storage capacity in thenon-volatile memory subsystem40 than in thevolatile memory subsystem30. In various embodiments, there may be at least 200, 300, or 400 percent more storage capacity in thenon-volatile memory subsystem40 than in thevolatile memory subsystem30. In other embodiments, thenon-volatile memory subsystem40 includes at least some other integer multiples of the storage capacity of thevolatile memory subsystem30. In some embodiments, thenon-volatile memory subsystem40 includes a non-integer multiple of the storage capacity of thevolatile memory subsystem30. In one embodiment, thenon-volatile memory subsystem40 includes less than 100 percent more storage capacity than does thevolatile memory subsystem30.
• The extra storage capacity of thenon-volatile memory subsystem40 can be used to improve the backup capability of thememory system10. In certain embodiments in which data can only be written to portions of thenon-volatile memory subsystem40 which do not contain data (e.g., portions which have been erased), the extra storage capacity of thenon-volatile memory subsystem40 allows thevolatile memory subsystem30 to be backed up in the event of a subsequent power failure or other trigger event. For example, the extra storage capacity of thenon-volatile memory subsystem40 may allow thememory system10 to backup thevolatile memory subsystem30 efficiently in the event of multiple trigger conditions (e.g., power failures). In the event of a first power failure, for example, the data in thevolatile memory system30 is copied to a first, previously erased portion of thenonvolatile memory subsystem40 via thecontroller62. Since thenon-volatile memory subsystem40 has more storage capacity than does thevolatile memory subsystem30, there is a second portion of thenon-volatile memory subsystem40 which does not have data from thevolatile memory subsystem30 copied to it and which remains free of data (e.g., erased). Once system power is restored, thecontroller62 of thememory system10 restores the data to thevolatile memory subsystem30 by copying the backed-up data from thenon-volatile memory subsystem40 back to thevolatile memory subsystem30. After the data is restored, thememory system10 erases thenon-volatile memory subsystem40. While the first portion of thenon-volatile memory subsystem40 is being erased, it may be temporarily unaccessible.
• If a subsequent power failure occurs before the first portion of thenon-volatile memory subsystem40 is completely erased, thevolatile memory subsystem30 can be backed-up or stored again in the second portion of thenon-volatile memory subsystem40 as described herein. In certain embodiments, the extra storage capacity of thenon-volatile memory subsystem40 may allow thememory system10 to operate more efficiently. For example, because of the extra storage capacity of thenon-volatile memory subsystem40, thememory system10 can handle a higher frequency of trigger events that is not limited by the erase time of thenon-volatile memory subsystem40.
• FIG. 7 is a flowchart of anexample method300 of controlling amemory system10 operatively coupled to a host system and which includes avolatile memory subsystem30 and anon-volatile memory subsystem40. In certain embodiments, thenon-volatile memory subsystem40 comprises at least 100 percent more storage capacity than does thevolatile memory subsystem30 as described herein. While themethod300 is described herein by reference to thememory system10 schematically illustrated byFIGS. 1-3, themethod300 can be practiced using other memory systems in accordance with certain embodiments described herein. In anoperational block310, themethod300 comprises communicating data between thevolatile memory subsystem30 and the host system when thememory system10 is in a first mode of operation. Themethod300 further comprises storing a first copy of data from thevolatile memory subsystem30 to thenon-volatile memory subsystem40 at a first time when thememory system10 is in a second mode of operation in anoperational block320.
• In anoperational block330, themethod300 comprises restoring the first copy of data from thenon-volatile memory subsystem40 to thevolatile memory subsystem30. Themethod300 further comprises erasing the first copy of data from thenon-volatile memory subsystem40 in anoperational block340. The method further comprises storing a second copy of data from thevolatile memory subsystem30 to thenon-volatile memory subsystem40 at a second time when thememory system10 is in the second mode of operation in anoperational block350. Storing the second copy begins before the first copy is completely erased from thenon-volatile memory subsystem40.
• In some embodiments, thememory system10 enters the second mode of operation in response to a trigger condition, such as a power failure. In certain embodiments, the first copy of data and the second copy of data are stored in separate portions of thenonvolatile memory subsystem40. Themethod300 can also include restoring the second copy of data from thenon-volatile memory subsystem40 to thevolatile memory subsystem30 in anoperational block360. The operational blocks ofmethod300 referred to herein may be performed in different orders in various embodiments. For example, in some embodiments, the second copy of data is restored to thevolatile memory subsystem30 atoperational block360 before the first copy of data is completely erased in theoperational block340.
• FIG. 8 schematically illustrates an exampleclock distribution topology400 of amemory system10 in accordance with certain embodiments described herein. Theclock distribution topology400 generally illustrates the creation and routing of the clock signals provided to the various components of thememory system10. Aclock source402 such as, for example, a 25 MHz oscillator, generates a clock signal. Theclock source402 may feed aclock generator404 which provides aclock signal406 to thecontroller62, which may be an FPGA. In one embodiment, theclock generator404 generates a 125MHz clock signal406. Thecontroller62 receives theclock signal406 and uses it to clock thecontroller62 master state control logic. For example, the master state control logic may control the general operation of anFPGA controller62.
• Theclock signal406 can also be input into aclock divider410 which produces a frequency-divided version of theclock signal406. In an example embodiment, theclock divider410 is a divide by two clock divider and produces a 62.5 MHz clock signal in response to the 125MHz clock signal406. A non-volatile memory phase-locked loop (PLL) block412 can be included (e.g., in the controller62) which distributes a series of clock signals to thenon-volatile memory subsystem40 and to associated control logic. For example, a series of clock signals414 can be sent from thecontroller62 to thenon-volatile memory subsystem40. Anotherclock signal416 can be used by the controller logic which is dedicated to controlling thenon-volatile memory subsystem40. For example, theclock signal416 may clock the portion of thecontroller62 which is dedicated to generating address and/or control lines for thenon-volatile memory subsystem40. Afeedback clock signal418 is fed back into the non-volatilememory PLL block412. In one embodiment, thePLL block412 compares thefeedback clock418 to thereference clock411 and varies the phase and frequency of its output until thereference411 andfeedback418 clocks are phase and frequency matched.
• A version of theclock signal406 such as thebackup clock signal408 may be sent from the controller to thevolatile memory subsystem30. Theclock signal408 may be, for example, a differential version of theclock signal406. As described herein, thebackup clock signal408 may be used to clock thevolatile memory subsystem30 when thememory system10 is backing up the data from thevolatile memory subsystem30 into thenon-volatile memory subsystem40. In certain embodiments, thebackup clock signal408 may also be used to clock thevolatile memory subsystem30 when thememory system10 is copying the backed-up data back into thevolatile memory subsystem30 from the nonvolatile memory subsystem40 (also referred to as restoring the volatile memory subsystem30). Thevolatile memory subsystem30 may normally be run at a higher frequency (e.g., DRAM running at 400 MHz) than the non-volatile memory subsystem40 (e.g., flash memory running at 62.5 MHz) when communicating with the host system (e.g., when no trigger condition is present). However, in certain embodiments thevolatile memory subsystem30 may be operated at a reduced frequency (e.g., at twice the frequency of the non-volatile memory subsystem40) without introducing significant delay into the system during backup operation and/or restore operations. Running thevolatile memory subsystem30 at the reduced frequency during a backup and/or restore operation may advantageously reduce overall power consumption of thememory system10.
• In one embodiment, thebackup clock408 and the volatile memorysystem clock signal420 are received by amultiplexer422, as schematically illustrated byFIG. 8. Themultiplexer422 can output either the volatile memorysystem clock signal420 or thebackup clock signal408 depending on the backup state of thememory system10. For example, when thememory system10 is not performing a backup or restore operation and is communicating with the host system (e.g., normal operation), the volatile memorysystem clock signal420 may be provided by themultiplexer422 to the volatilememory PLL block424. When thememory system10 is performing a backup (or restore) operation, thebackup clock signal408 may be provided.
• The volatilememory PLL block424 receives the volatile memoryreference clock signal423 from themultiplexer422 and can generate a series of clock signals which are distributed to thevolatile memory subsystem30 and associated control logic. For example, in one embodiment, thePLL block424 generates a series of clock signals426 which clock thevolatile memory elements32. Aclock signal428 may be used to clock control logic associated with the volatile memory elements, such as one or more registers (e.g., the one ore more registers of a registered DIMM). Anotherclock signal430 may be sent to thecontroller62. Afeedback clock signal432 is fed back into the volatilememory PLL block424. In one embodiment, thePLL block424 compares thefeedback clock signal432 to thereference clock signal423 and varies the phase and frequency of its output until thereference clock signal423 and thefeedback clock signal432 clocks are phase and frequency matched.
• Theclock signal430 may be used by thecontroller62 to generate and distribute clock signals which will be used by controller logic which is configured to control thevolatile memory subsystem30. For example, control logic in thecontroller62 may be used to control thevolatile memory subsystem30 during a backup or restore operation. Theclock signal430 may be used as a reference clock signal for the PLL block434 which can generate one or more clocks438 used by logic in thecontroller62. For example, the PLL block434 may generate one or more clock signals438 used to drive logic circuitry associated with controlling thevolatile memory subsystem30. In certain embodiments, thePLL block434 includes afeedback clock signal436 and operates in a similar manner to other PLL blocks described herein.
• Theclock signal430 may be used as a reference clock signal for the PLL block440 which may generate one or more clock signals used by a sub-block442 to generate one or more other clock signals444. In one embodiment, for example, thevolatile memory subsystem30 comprises DDR2 SDRAM elements and the sub-block442 generates one or more DDR2 compatible clock signals444. Afeedback clock signal446 is fed back into thePLL block440. In certain embodiments, thePLL block440 operates in a similar manner to other PLL blocks described herein.
• While described with respect to the example embodiment ofFIG. 8, various alternative clock distribution topologies are possible. For example, one or more of the clock signals have a different frequency in various other embodiments. In some embodiments, one or more of the clocks shown as differential signals are single ended signals. In one embodiment, thevolatile memory subsystem30 operates on the volatilememory clock signal420 and there is nobackup clock signal408. In some embodiments, thevolatile memory subsystem30 is operated at a reduced frequency during a backup operation and not during a restore operation. In other embodiments, thevolatile memory subsystem30 is operated at a reduced frequency during a restore operation and not during a backup operation.
• FIG. 9 is a flowchart of anexample method500 of controlling amemory system10 operatively coupled to a host system. Although described with respect to thememory system10 described herein, themethod500 is compatible with other memory systems. Thememory system10 may include aclock distribution topology400 similar to the one described above with respect toFIG. 8 or another clock distribution topology. Thememory system10 can include avolatile memory subsystem30 and anon-volatile memory subsystem40.
• In anoperational block510, themethod500 comprises operating thevolatile memory subsystem30 at a first frequency when thememory system10 is in a first mode of operation in which data is communicated between thevolatile memory subsystem30 and the host system. In anoperational block520, themethod500 comprises operating thenon-volatile memory subsystem40 at a second frequency when thememory system10 is in a second mode of operation in which data is communicated between thevolatile memory subsystem30 and thenon-volatile memory subsystem40. Themethod500 further comprises operating thevolatile memory subsystem30 at a third frequency in anoperational block530 when thememory system10 is in the second mode of operation. In certain embodiments, thememory system10 is not powered by a battery when it is in the second mode of operation. Thememory system10 may switch from the first mode of operation to the second mode of operation in response to a trigger condition. The trigger condition may be any trigger condition described herein such as, for example, a power failure condition. In certain embodiments, the second mode of operation includes both backup and restore operations as described herein. In other embodiments, the second mode of operation includes backup operations but not restore operations. In yet other embodiments, the second mode of operation includes restore operations but not backup operations.
• The third frequency can be less than the first frequency. For example, the third frequency can be approximately equal to the second frequency. In certain embodiments, the reduced frequency operation is an optional mode. In yet other embodiments, the first, second and/or third frequencies are configurable by a user or by thememory system10.
• FIG. 10 schematically illustrates an example topology of a connection to transfer data slices from twoDRAM segments630,640 of avolatile memory subsystem30 of amemory system10 to acontroller62 of thememory system10. While the example ofFIG. 10 shows a topology including twoDRAM segments630,640 for the purposes of illustration, each address location of thevolatile memory subsystem30 comprises more than the two segments in certain embodiments. The data lines632,642 from thefirst DRAM segment630 and thesecond DRAM segment640 of thevolatile memory subsystem30 are coupled toswitches650,652 which are coupled to the controller62 (e.g., logic element70) of thememory system10. The chipselect lines634,644 and the self-refresh lines636,646 (e.g., CKe signals) of the first andsecond DRAM segments630,640, respectively, are coupled to thecontroller62. In certain embodiments, thecontroller62 comprises a buffer (not shown) which is configured to store data from thevolatile memory subsystem30. In certain embodiments, the buffer is a first-in, first out buffer (FIFO). In certain embodiments, data slices from eachDRAM segment630,640 comprise a portion of the volatile memory subsystem data bus. In one embodiment, for example, thevolatile memory subsystem30 comprises a 72-bit data bus (e.g., each data word at each addressable location is 72 bits wide and includes, for example, 64 bits of accessible SDRAM and 8 bits of ECC), the first data slice from thefirst DRAM segment630 may comprise 40 bits of the data word, and the second data slice from thesecond DRAM segment640 may comprise the remaining 32 bits of the data word. Certain other embodiments comprise data buses and/or data slices of different sizes.
• In certain embodiments, theswitches650,652 can each be selectively switched to selectively operatively couple thedata lines632,642, respectively from the first andsecond DRAM segments630,640 to thecontroller62. The chipselect lines634,644 enable the first andsecond DRAM segments630,640, respectively, of thevolatile memory subsystem30, and the self-refresh lines636,646 toggle the first andsecond DRAM segments630,640, respectively, from self-refresh mode to active mode. In certain embodiments, the first andsecond DRAM segments630,640 maintain stored information but are not accessible when they are in self-refresh mode, and maintain stored information and are accessible when they are in active mode.
• In certain embodiments, when thememory system10 is backing up thevolatile memory system30, data slices from only one of the twoDRAM segments630,640 at a time are sent to thecontroller62. For example, when the first slice is being written to thecontroller62 during a back-up, thecontroller62 sends a signal via theCKe line636 to thefirst DRAM segment630 to put thefirst DRAM segment630 in active mode. In certain embodiments, the data slice from thefirst DRAM segment630 for multiple words (e.g., a block of words) is written to thecontroller62 before writing the second data slice from thesecond DRAM segment640 to thecontroller62. While the first data slice is being written to thecontroller62, thecontroller62 also sends a signal via theCKe line646 to put thesecond DRAM segment640 in self-refresh mode. Once the first data slice for one word or for a block of words is written to thecontroller62, thecontroller62 puts thefirst DRAM segment630 into self-refresh mode by sending a signal via theCKe line636 to thefirst DRAM segment640. Thecontroller62 also puts the second.DRAM segment640 into active mode by sending a signal via theCKe line646 to theDRAM segment640. The second slice for a word or for a block of words is written to thecontroller62. In certain embodiments, when the first and second data slices are written to the buffer in thecontroller62, thecontroller62 combines the first and second data slices630,640 into complete words or blocks of words and then writes each complete word or block of words to thenon-volatile memory subsystem40. In certain embodiments, this process is called “slicing” thevolatile memory subsystem30.
• In certain embodiments, the data may be sliced in a restore operation as well as, or instead of, during a backup operation. For example, in one embodiment, thenonvolatile memory elements42 write each backed-up data word to thecontroller62 which writes a first slice of the data word to thevolatile memory subsystem30 and then a second slice of the data word to thevolatile memory subsystem30. In certain embodiments, slicing thevolatile memory subsystem30 during a restore operation may be performed in a manner generally inverse to slicing thevolatile memory subsystem30 during a backup operation.
• FIG. 11 is a flowchart of anexample method600 of controlling amemory system10 operatively coupled to a host system and which includes avolatile memory subsystem30 and anon-volatile memory subsystem40. Although described with respect to thememory system10 described herein with respect toFIGS. 1-3 and 10, themethod600 is compatible with other memory systems. Themethod600 comprises communicating data words between thevolatile memory subsystem30 and the host system when thememory system10 is in a first mode of operation in anoperational block610. For example, thememory system10 may be in the first mode of operation when no trigger condition has occurred and the memory system is not performing a backup and/or restore operation or is not being powered by a secondary power supply.
• In anoperational block620, the method further comprises transferring data words from thevolatile memory subsystem30 to thenon-volatile memory subsystem40 when thememory system10 is in a second mode of operation. In certain embodiments, each data word comprises the data stored in a particular address of thememory system10. Thememory system10 may enter the second mode of operation, for example, when a trigger condition (e.g., a power failure) occurs. In certain embodiments, transferring each data word comprises storing a first portion (also referred to as a slice) of the data word in a buffer in anoperational block622, storing a second portion of the data word in the buffer in anoperational block624, and writing the entire data word from the buffer to thenon-volatile memory subsystem40 in an operational block626.
• In one example embodiment, the data word may be a 72 bit data word (e.g., 64 bits of accessible SDRAM and 8 bits of ECC), the first portion (or “slice”) may comprise 40 bits of the data word, and the second portion (or “slice”) may comprise the remaining 32 bits of the data word. In certain embodiments, the buffer is included in thecontroller62. For example, in one embodiment, the buffer is a first-in, first-out buffer implemented in thecontroller62 which comprises an FPGA. Themethod600 may generally be referred to as “slicing” the volatile memory during a backup operation. In the example embodiment, the process of “slicing” the volatile memory during a backup includes bringing the 32-bit slice out of self-refresh, reading a 32-bit block from the slice into the buffer, and putting the 32-bit slice back into self-refresh. The 40-bit slice is then brought out of self-refresh and a 40-bit block from the slice is read into a buffer. Each block may comprise a portion of multiple words. For example, each 32-bit block may comprise 32-bit portions of multiple 72-bit words. In other embodiments, each block comprises a portion of a single word. The 40-bit slice is then put back into self-refresh in the example embodiment. The 32-bit and 40-bit slices are then combined into a 72-bit block by thecontroller62 and ECC detection/correction is performed on each 72-bit word as it is read from the buffer and written into the non-volatile memory subsystem (e.g., flash).
• In some embodiments, the entire data word may comprise more than two portions. For example, the entire data word may comprise three portions instead of two and transferring each data word further comprises storing a third portion of each data word in the buffer. In certain other embodiments, the data word may comprise more than three portions.
• In certain embodiments, the data may be sliced in a restore operation as well as, or instead of, during a backup operation. For example, in one embodiment, thenonvolatile memory elements40 write each backed-up data word to thecontroller62 which writes a first portion of the data word to thevolatile memory subsystem30 and then a second portion of the data word to thevolatile memory30. In certain embodiments, slicing thevolatile memory subsystem30 during a restore operation may be performed in a manner generally inverse to slicing thevolatile memory subsystem30 during a backup operation.
• Themethod600 can advantageously provide significant power savings and can lead to other advantages. For example, in one embodiment where thevolatile memory subsystem30 comprises DRAM elements, only the slice of the DRAM which is currently being accessed (e.g., written to the buffer) during a backup is configured in full-operational mode. The slice or slices that are not being accessed may be put in self-refresh mode. Because DRAM in self-refresh mode uses significantly less power than DRAM in full-operational mode, themethod600 can allow significant power savings. In certain embodiments, each slice of the DRAM includes a separate self-refresh enable (e.g., CKe) signal which allows each slice to be accessed independently.
• In addition, the connection between the DRAM elements and thecontroller62 may be as large as the largest slice instead of as large as the data bus. In the example embodiment, the connection between thecontroller62 and the DRAM may be 40 bits instead of 72 bits. As a result, pins on thecontroller62 may be used for other purposes or a smaller controller may be used due to the relatively low number of pin-outs used to connect to thevolatile memory subsystem30. In certain other embodiments, the full width of the data bus is connected between thevolatile memory subsystem30 and thecontroller62 but only a portion of it is used during slicing operations. For example, in some embodiments, memory slicing is an optional mode.
• Various embodiments of the present invention have been described above. Although this invention has been described with reference to these specific embodiments, the descriptions are intended to be illustrative of the invention and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.

Claims (2)

1. A memory module comprising:

a volatile memory subsystem having a first storage capacity;

a nonvolatile memory subsystem having a second storage capacity, the second storage capacity being at least 400 percent more than the first storage capacity, wherein the memory module is configured to provide non-volatile storage via the non-volatile memory subsystem;

a standard DIMM interface configured to electrically couple the memory module to a host system, the standard DIMM interface including an edge connector which fits into a memory socket of the host system, the edge connector including a plurality of edge connections to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and the host system, the first plurality of DDR SDRAM signals including at least address/control and data signals, wherein data is communicated between the volatile memory subsystem and the host system using the first signals path; and

a controller in communication with the volatile memory subsystem via a second signals path for transmitting a second plurality of DDR SDRAM signals between the controller and the volatile memory subsystem, the second plurality of DDR SDRAM signals including at least address/control and data signals, the controller being coupled to the nonvolatile memory subsystem via a third signals path for transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem, wherein the controller includes:

a logic element operable to generate address and control signals for the nonvolatile memory subsystem, wherein the logic element performs address-to-address translation between the volatile memory subsystem and the nonvolatile memory subsystem, and

a microcontroller operable to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem,

wherein the controller is configured (i) to communicate data with the volatile memory subsystem using the second plurality of DDR SDRAM signals via the second signals path, and (ii) to communicate data with the nonvolatile memory subsystem using the at least data, address and control signals via the third signals path.

2.-20. (canceled)

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