US20160307925A1

Movatterモバイル変換

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Publication number: US20160307925A1
Application number: US15/191,644
Authority: US
Inventors: Shunpei Yamazaki; Hiroki Ohara; Junichiro Sakata; Toshinari Sasaki; Miyuki HOSOBA
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2009-07-10
Filing date: 2016-06-24
Publication date: 2016-10-20
Also published as: US8294147B2; JP6417440B2; TWI580054B; JP2019016810A; KR20120049873A; KR20140059306A; JP6695398B2; JP6731103B2; US9379141B2; US20130149813A1; JP2020017750A; JP2015133497A; JP2011035387A; JP7012787B2; JP2022068148A; JP7274618B2; KR101642620B1; JP2020178130A; KR20160087916A; JP7532591B2

Abstract

An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

Description

TECHNICAL FIELD

The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

In this specification, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

BACKGROUND ART

In recent years, a technique for forming a thin film transistor (TFT) by using a semiconductor thin film (having a thickness of approximately several nanometers to several hundred nanometers) formed over a substrate having an insulating surface has attracted attention. Thin film transistors are applied to a wide range of electronic devices such as ICs or electro-optical devices, and prompt development of thin film transistors that are to be used as switching elements in image display devices, in particular, is being pushed. Indium oxide is an example of metal oxides and is used as a light-transmitting electrode material which is necessary for liquid crystal displays and the like.

Some metal oxides have semiconductor characteristics. For example, metal oxides having semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like. Thin film transistors in which a channel formation region is formed using such a metal oxide having semiconductor characteristics are already known (Patent Documents 1 to 4 and Non-Patent Document 1).

Further, not only single-component oxides but also multi-component oxides are known as metal oxides. For example, a homologous compound, InGaO₃(ZnO)_m(m is natural number) is known as a multi-component oxide semiconductor containing In, Ga, and Zn (also referred to as an In—Ga—Zn—O-based oxide) (Non-Patent Documents 2 to 4).

Furthermore, it is confirmed that an oxide semiconductor containing such an In—Ga—Zn—O-based oxide is applicable to a channel layer of a thin film transistor (Patent Document 5 andNon-Patent Documents 5 and 6).

REFERENCES

[Patent Document 1] Japanese Published Patent Application No. S60-198861

[Patent Document 2] Japanese Published Patent Application No. H8-264794

[Patent Document 3] Japanese Translation of PCT International Application No. H11-505377

[Patent Document 4] Japanese Published Patent Application No. 2000-150900

[Patent Document 5] Japanese Published Patent Application No. 2004-103957

[Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, “A ferroelectric transparent thin-film transistor”,Appl. Phys. Lett.,17 Jun. 1996, Vol. 68 pp. 3650-3652
[Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In₂O₃—Ga₂ZnO₄—ZnO System at 1350° C.”,J. Solid State Chem.,1991, Vol. 93, pp. 298-315
[Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In₂O₃(ZnO)_m(m=3, 4, and 5), InGaO₃(ZnO)₃, and Ga₂O₃(ZnO)_m(m=7, 8, 9, and 16) in the In₂O₃—ZnGa₂O₄—ZnO System”,J. Solid State Chem.,1995, Vol. 116, pp. 170-178
[Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M. Isobe, “Homologous Series, Synthesis and Crystal Structure of InFeO₃(ZnO)m (m: natural number) and its Isostructural Compound”,KOTAI BUTSURI(SOLID STATE PHYSICS), 1993, Vol. 28, No. 5, pp. 317-327
[Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”,SCIENCE,2003, Vol. 300, pp. 1269-1272
[Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”,NATURE,2004, Vol. 432 pp. 488-492

DISCLOSURE OF INVENTION

An object is to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics.

In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for increasing purity of the oxide semiconductor film and reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed. Further, impurities such as moisture, which exist not only in the oxide semiconductor film but also in a source electrode layer, in a drain electrode layer, and in a gate insulating layer are reduced by performing heat treatment, and impurities such as moisture, which exist at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor film, are reduced by performing heat treatment.

An oxide semiconductor layer is formed and an oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer, and then heat treatment for dehydration or dehydrogenation is performed. Heat treatment is performed under a nitrogen atmosphere, an oxygen atmosphere, or an inert gas atmosphere of a rare gas (argon, helium, or the like), or under reduced pressure at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably higher than or equal to 350° C. and lower than a strain point of a substrate, whereby the moisture content in the source electrode layer, the drain electrode layer, the gate insulating layer, and the oxide semiconductor film, or the like is reduced. Further, the heat treatment can repair plasma damage which is caused to the oxide semiconductor layer when the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer. The heat treatment can reduce variation in electric characteristics of a thin film transistor.

When the oxide semiconductor layer in which the moisture content or the like is reduced by the heat treatment and whose plasma damage is repaired is used, electric characteristics of a thin film transistor are improved and a thin film transistor with mass productivity and high performance is realized.

In this specification, heat treatment under a nitrogen atmosphere, an oxygen atmosphere, or an inert gas atmosphere of a rare gas (argon, helium, or the like), or under reduced pressure is referred to as heat treatment for dehydration or dehydrogenation. In this specification, “dehydrogenation” does not indicate elimination of only H₂by the heat treatment. For convenience in this description, elimination of H, OH, and the like is referred to as “dehydrogenation or dehydration”.

Note that the oxide insulating film serving as a protective film which is in contact with the oxide semiconductor layer is formed using an inorganic insulating film which blocks impurities such as moisture, hydrogen ions, and OH⁻. Typically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. In addition, a silicon nitride film or an aluminum nitride film may be stacked over the oxide insulating film.

One embodiment of the present invention disclosed in this specification is a method for manufacturing a semiconductor device including the steps of: forming a gate electrode layer including a heat resistant conductive material; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer over the gate insulating layer; forming a connection electrode layer, a source electrode layer, and a drain electrode layer each including a heat resistant conductive material above the oxide semiconductor layer; forming, over the gate insulating layer, the oxide semiconductor layer, the connection electrode layer, the source electrode layer, and the drain electrode layer, an oxide insulating film which is in contact with part of the oxide semiconductor layer; and performing dehydration or dehydrogenation on the oxide semiconductor layer after the oxide insulating film is formed.

With the above structure, at least one of the above problems can be resolved.

Another embodiment of the present invention is a method for manufacturing a semiconductor device including the steps of: forming a gate electrode layer including a heat resistant conductive material over a substrate having an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer over the gate insulating layer; forming a connection electrode layer, a source electrode layer, and a drain electrode layer each including a heat resistant conductive material above the oxide semiconductor layer; forming, over the gate insulating layer, the oxide semiconductor layer, the connection electrode layer, the source electrode layer, and the drain electrode layer, an oxide insulating film which is in contact with part of the oxide semiconductor layer; performing dehydration or dehydrogenation on the oxide semiconductor layer after the oxide insulating film is formed; removing part of the oxide insulating film and forming a first contact hole which reaches the source electrode layer, and a third contact hole and a fourth contact hole which reach both end portions of the connection electrode layer; removing part of the oxide insulating film and part of the gate insulating layer and forming a second contact hole which reaches the gate electrode layer; and forming, over the oxide insulating film, a source wiring which is connected to the source electrode layer through the first contact hole, a first gate wiring which is connected to the gate electrode layer through the second contact hole and to the connection electrode layer through the third contact hole, and a second gate wiring which is connected to the connection electrode layer through the fourth contact hole.

Another embodiment of the present invention is a method for manufacturing a semiconductor device including the steps of: forming a gate electrode layer including a heat resistant conductive material over a substrate having an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer over the gate insulating layer; forming a connection electrode layer, a source electrode layer, and a drain electrode layer each including a heat resistant conductive material above the oxide semiconductor layer; forming, over the gate insulating layer, the oxide semiconductor layer, the connection electrode layer, the source electrode layer, and the drain electrode layer, an oxide insulating film which is in contact with part of the oxide semiconductor layer; performing dehydration or dehydrogenation on the oxide semiconductor layer after the oxide insulating film is formed; removing part of the oxide insulating film and forming a first contact hole which reaches the source electrode layer, and a third contact hole and a fourth contact hole which reach both end portions of the connection electrode layer; removing part of the oxide insulating film and part of the gate insulating layer and forming a second contact hole which reaches the gate electrode layer; and forming, over the oxide insulating film, a first source wiring which is connected to the source electrode layer through the first contact hole and to the connection electrode layer through the third contact hole, a second source wiring which is connected to the connection electrode layer through the fourth contact hole, and a gate wiring which is connected to the gate electrode layer through the second contact hole.

In any of the structures of the manufacturing methods, the dehydration or dehydrogenation is preferably heating under a nitrogen atmosphere, an oxygen atmosphere, or a rare gas atmosphere, or under reduced pressure, and the oxide semiconductor layer is more preferably heated at a temperature of higher than or equal to 350° C. and lower than a strain point of the substrate. Slow cooling is preferably performed after the heating.

As the heat resistant conductive material, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component is preferably used in a single layer or a stacked layer. The source wiring and the gate wiring are preferably formed using a low resistance conductive material which has lower resistivity than the source electrode layer and the drain electrode layer. Aluminum or copper is preferably used as the low resistance conductive material.

Another embodiment of the present invention is a semiconductor device including a gate electrode layer formed using a first mask over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer formed using a second mask over the gate insulating layer; a connection electrode layer, a source electrode layer, and a drain electrode layer which are formed using a third mask, wherein the source electrode layer and the drain electrode layer are above the oxide semiconductor layer; an oxide insulating film which covers the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein the oxide insulating film is in contact with part of the oxide semiconductor layer; and a gate wiring, a first source wiring, and a second source wiring which are formed using a fourth mask over the oxide insulating film. The first source wiring is electrically connected to the source electrode layer, the gate wiring is electrically connected to the gate electrode layer, the first source wiring and the second source wiring are electrically connected to the connection electrode layer, and the connection electrode layer overlaps the gate wiring with the oxide insulating film interposed therebetween. Here the first to fourth masks refer to photomasks.

Another embodiment of the present invention is a semiconductor device including: a gate electrode layer formed using a first mask over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer formed using a second mask over the gate insulating layer; a connection electrode layer, a source electrode layer, and a drain electrode layer which are formed using a third mask, wherein the source electrode layer and the drain electrode layer are above the oxide semiconductor layer; an oxide insulating film which covers the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein the oxide insulating film is in contact with part of the oxide semiconductor layer; and a gate wiring, a first source wiring, and a second source wiring which are formed using a fourth mask over the oxide insulating film. The first source wiring is electrically connected to the source electrode layer, the gate wiring is electrically connected to the gate electrode layer, the first source wiring and the second source wiring are electrically connected to the connection electrode layer; and the connection electrode layer overlaps the gate wiring with the oxide insulating film interposed therebetween. Here the first to fourth masks refer to photomasks.

In any of the structures of the semiconductor devices, a single layer or a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component is preferably used for the gate electrode layer, the connection electrode layer, the source electrode layer, and the drain electrode layer. The source wiring and the gate wiring are preferably formed using a low resistance conductive material which has lower resistivity than the source electrode layer and the drain electrode layer, and aluminum or copper is more preferably used.

An oxide semiconductor used in this specification is formed into a thin film represented by InMO₃(ZnO)_m(m>0), and a thin film transistor is manufactured using this thin film as an oxide semiconductor layer. However, m is not always an integer. Note that M represents one or more metal elements selected from Ga, Fe, Ni, Mn, or Co. As an example, M may be Ga or may include the above metal element in addition to Ga, for example, M may be Ga and Ni or Ga and Fe. Moreover, in the above oxide semiconductor, in some cases, a transition metal element such as Fe or Ni or an oxide of the transition metal is contained as an impurity element in addition to a metal element contained as M In this specification, among the oxide semiconductor layers whose composition formulae are represented by InMO₃(ZnO)_m(m>0), an oxide semiconductor whose composition formula includes at least Ga as M is referred to as an In—Ga—Zn—O-based oxide semiconductor, and a thin film of the In—Ga—Zn—O-based oxide semiconductor is referred to as an In—Ga—Zn—O-based non-single-crystal film.

The change of the oxide semiconductor layer in an amorphous state to a microcrystalline state or a polycrystalline state in some cases is determined by conditions of heat treatment or a material used to form the oxide semiconductor layer.

Since a thin film transistor is easily broken due to static electricity or the like, a protective circuit for protecting a driver circuit is preferably provided over the same substrate as a gate wiring or a source wiring. The protective circuit is preferably formed with a non-linear element including an oxide semiconductor.

The gate insulating layer and the oxide semiconductor film may be successively subjected to treatment (also referred to as successive treatment, an in-situ process, or successive film formation) without exposure to air. Successive treatment without exposure to air makes it possible to obtain an interface between the gate insulating layer and the oxide semiconductor film, which is not contaminated by atmospheric components or impurities floating in air, such as water, hydrocarbon, or the like. Therefore, variation in characteristics of the thin film transistor can be reduced.

Note that the term “successive treatment” in this specification means that during the process from a first treatment step by a PCVD method or a sputtering method to a second treatment step by a PCVD method or a sputtering method, an atmosphere in which a substrate to be processed is disposed is kept controlled to be vacuum or an inert gas atmosphere (a nitrogen atmosphere or a rare gas atmosphere) without exposure to a contaminant atmosphere such as air. By the successive treatment, treatment such as film formation can be performed while preventing moisture or the like from being attached again to the substrate to be processed which is cleaned.

Performing the process from the first treatment step to the second treatment step in the same chamber is within the scope of the successive treatment in this specification.

In addition, the following is also within the scope of the successive treatment in this specification: in the case of performing the process from the first treatment step to the second treatment step in different chambers, the substrate is transferred after the first treatment step to another chamber without exposure to air and subjected to the second treatment.

Note that the case where there is a substrate transfer step, an alignment step, a slow cooling step, a step of heating or cooling a substrate so that the temperature of the substrate is suitable to the second treatment step, or the like between the first treatment step and the second treatment step is also in the range of the successive treatment in this specification.

A step in which liquid is used, such as a cleaning step, wet etching, or formation of a resist may be provided between the first treatment step and the second treatment step. This case is not within the scope of the successive treatment in this specification.

A thin film transistor having stable electric characteristics can be provided. Further, a semiconductor device including a highly reliable thin film transistor having favorable electric characteristics can be provided.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1E are cross-sectional views illustrating a manufacturing process according to an embodiment of the present invention.

FIGS. 2A to 2D are plan views illustrating a manufacturing process according to an embodiment of the present invention.

FIGS. 3A to 3D are views illustrating semiconductor devices according to an embodiment of the present invention.

FIGS. 4A to 4E are cross-sectional views illustrating a manufacturing process according to an embodiment of the present invention.

FIGS. 5A to 5D are plan views illustrating a manufacturing process according to an embodiment of the present invention.

FIGS. 6A to 6D are views illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 7A to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 8A to 8C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 9A and 9B are cross-sectional views illustrating the method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 14A to 14D are views illustrating semiconductor devices according to an embodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating an electric furnace.

FIG. 16 is a cross-sectional view illustrating an electric furnace.

FIG. 17 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 18 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 19A to 19C are views illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 20A and 20B are cross-sectional views illustrating semiconductor devices according to an embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 22A and 22B are block diagrams of display devices.

FIGS. 23A and 23B are a view illustrating a structure of a signal line driver circuit and a timing chart thereof, respectively.

FIGS. 24A to 24C are circuit diagrams illustrating a structure of a shift register.

FIGS. 25A and 25B are a view illustrating an equivalent circuit of a shift register and a timing chart thereof showing operations of the shift register, respectively.

FIGS. 26A to 26C are views illustrating a semiconductor device.

FIG. 27 is a view illustrating a semiconductor device.

FIG. 28 is a view illustrating a semiconductor device.

FIG. 29 is a view illustrating a equivalent circuit of a pixel included in a semiconductor device.

FIGS. 30A to 30C are views illustrating semiconductor devices.

FIGS. 31A and 31B are views illustrating a semiconductor device.

FIG. 32 is an external view of an example of an e-book reader.

FIG. 33A is an external view of an example of a television device, andFIG. 33B is an external view of an example of a digital photo frame.

FIGS. 34A and 34B are external views of examples of an amusement machine.

FIG. 35A is an external view of an example of a portable computer, andFIG. 35B is an external view of an example of a cellular phone.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention is not construed as being limited to description of the embodiments.

Embodiment 1

FIG. 3A is a plan view of athin film transistor461 included in a semiconductor device, andFIG. 3B is a cross-sectional view taken along line C1-C2 ofFIG. 3A. Thethin film transistor461 is an inverted staggered thin film transistor. Agate electrode layer401 is provided over asubstrate400 having an insulating surface. Agate insulating layer402 is provided over thegate electrode layer401. Anoxide semiconductor layer403 is provided over thegate insulating layer402. Asource electrode layer405aand adrain electrode layer405bare provided over theoxide semiconductor layer403. In addition, anoxide insulating film407 which covers thegate insulating layer402, theoxide semiconductor layer403, thesource electrode layer405aand thedrain electrode layer405band which is in contact with part of theoxide semiconductor layer403 is provided.

Theoxide insulating film407 is provided with afirst contact hole421 which reaches thesource electrode layer405a, asecond contact hole422 which reaches thegate electrode layer401, and athird contact hole423 and afourth contact hole424 which reach both end portions of aconnection electrode layer420. Here, in this embodiment, since a source wiring and a gate wiring are formed from the same layer, afirst gate wiring426 and asecond gate wiring427 are formed so as to sandwich asource wiring425 therebetween. Thefirst gate wiring426 and thesecond gate wiring427 are electrically connected to each other through theconnection electrode layer420 which is formed so as to overlap thesource wiring425. Here, thesource wiring425 is electrically connected to thesource electrode layer405athrough thefirst contact hole421. Thefirst gate wiring426 is electrically connected to thegate electrode layer401 through thesecond contact hole422. Thefirst gate wiring426 and thesecond gate wiring427 are electrically connected to theconnection electrode layer420 through thethird contact hole423 and thefourth contact hole424. Thesource wiring425, thefirst gate wiring426, and thesecond gate wiring427 extend beyond the perimeter of theoxide semiconductor layer403.

After theoxide insulating film407 serving as a protective film is formed in contact with theoxide semiconductor layer403, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed on theoxide semiconductor layer403.

Impurities such as moisture, which exist not only in theoxide semiconductor layer403 but also in thegate insulating layer402, in thesource electrode layer405a, in thedrain electrode layer405b, and at interfaces between theoxide semiconductor layer403 and upper and lower films which are in contact with theoxide semiconductor layer403, specifically, at an interface between thegate insulating layer402 and theoxide semiconductor layer403 or at an interface between theoxide insulating film407 and theoxide semiconductor layer403, are reduced. When the moisture or the like content in theoxide semiconductor layer403 is reduced with the heat treatment, electric characteristics of the thin film transistor can be improved.

With this heat treatment, plasma damage which is caused to theoxide semiconductor layer403 is repaired when theoxide insulating film407 is formed.

Each of thegate electrode layer401, theconnection electrode layer420, thesource electrode layer405a, and thedrain electrode layer405bpreferably includes a heat resistant conductive material. As the heat resistant conductive material, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component can be used. Thegate electrode layer401, theconnection electrode layer420, thesource electrode layer405a, and thedrain electrode layer405bmay have a stacked structure of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component. For example, a combination of tungsten nitride for a first layer and tungsten for a second layer, a combination of molybdenum nitride for the first layer and tungsten for the second layer, or a combination of titanium nitride for the first layer and titanium for the second layer may be employed.

For the heat resistant conductive material used for theconnection electrode layer420, thesource electrode layer405a, and thedrain electrode layer405b, a transparent conductive oxide containing any of indium, tin, or zinc may be used. For example, indium oxide (In₂O₃) or an indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy is preferably used. Alternatively, a transparent conductive oxide to which an insulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in the transparent conductive oxide, crystallization of the transparent conductive oxide can be suppressed and the transparent conductive oxide can have an amorphous structure. Crystallization of the transparent conductive oxide is suppressed and an amorphous structure is formed, so that crystallization of the transparent conductive oxide or generation of microcrystalline grains can be prevented even when heat treatment is performed.

When such a heat resistant conductive material is included in thegate electrode layer401, theconnection electrode layer420, thesource electrode layer405a, and thedrain electrode layer405b, thegate electrode layer401, theconnection electrode layer420, thesource electrode layer405a, and thedrain electrode layer405bcan endure the heat treatment which is performed after theoxide insulating film407 is formed.

Thesource wiring425, thefirst gate wiring426, and thesecond gate wiring427 are preferably formed using a low resistance conductive material which has lower resistivity than thesource electrode layer405aand thedrain electrode layer405b, and aluminum or copper is particularly preferable. With the use of the low resistance conductive material for thesource wiring425, thefirst gate wiring426, and thesecond gate wiring427, wiring resistance or the like can be reduced.

The low resistance conductive material such as aluminum or copper has low heat resistance. However, the heat treatment is performed after forming the oxide insulating film, and then thesource wiring425, thefirst gate wiring426, and thesecond gate wiring427 are provided, whereby the above low resistance conductive material can be used as thesource wiring425, thefirst gate wiring426, and thesecond gate wiring427.

As theoxide semiconductor layer403 including a channel formation region, an oxide material having semiconductor characteristics may be used, and typically, In—Ga—Zn—O-based non-single-crystal is used.

As illustrated inFIG. 3C, afirst source wiring428 and a second source wiring429 may be formed so as to sandwich agate wiring430 therebetween and may be electrically connected to each other through theconnection electrode layer420 which is formed so as to overlap thegate wiring430. Here, thefirst source wiring428 is electrically connected to thesource electrode layer405athrough thefirst contact hole421. Thegate wiring430 is electrically connected to thegate electrode layer401 through thesecond contact hole422. Thefirst source wiring428 and the second source wiring429 are electrically connected to theconnection electrode layer420 through thethird contact hole423 and thefourth contact hole424 which reach both end portions of theconnection electrode layer420. The other portions are similar to those of the thin film transistor illustrated inFIGS. 3A and 3B.

As illustrated inFIG. 3D, thesource electrode layer405amay be formed so as to overlap thegate wiring430, and thefirst source wiring428 and the second source wiring429 may be electrically connected to each other through thesource electrode layer405a. Here, thefirst source wiring428 is electrically connected to thesource electrode layer405athrough thefirst contact hole421. The second source wiring429 is electrically connected to thesource electrode layer405athrough athird contact hole490 provided over thesource electrode layer405a. The other portions are similar to those of the thin film transistor illustrated inFIG. 3C.

FIGS. 1A to 1E are cross-sectional views of a manufacturing process of thethin film transistor461 illustrated inFIGS. 3A and 3B, andFIGS. 2A to 2D are plan views of the manufacturing process.

First, over thesubstrate400 having an insulating surface, thegate electrode layer401 is provided using a photolithography process with the use of a photomask.

Although there is no particular limitation on a glass substrate which can be used, it is necessary that the glass substrate have at least enough heat resistance to heat treatment to be performed later. As the light-transmittingsubstrate400, it is possible to use a glass substrate made of barium borosilicate glass, aluminoborosilicate glass, or the like.

As thesubstrate400, a substrate whose strain point is higher than or equal to 730° C. may be used when the temperature of later heat treatment is high. Further, as a material of thesubstrate400, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. Note that by containing a larger amount of barium oxide (BaO) than boric acid, a glass substrate is heat-resistant and of more practical use. Therefore, a glass substrate containing a larger amount of BaO than B₂O₃is preferably used.

Note that a substrate formed of an insulator such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used instead of theglass substrate400. Alternatively, crystallized glass or the like may be used.

An insulating film serving as a base film may be provided between thesubstrate400 and thegate electrode layer401. The base film has a function of preventing diffusion of an impurity element from thesubstrate400, and can be formed to have a single-layer or stacked structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.

Since heat treatment is performed in a later step, a material of thegate electrode layer401 preferably includes a heat resistant conductive material. As the heat resistant conductive material, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component can be used. Thegate electrode layer401 may have a single-layer or stacked structure of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component. For example, a combination of tungsten nitride for a first layer and tungsten for a second layer, a combination of molybdenum nitride for the first layer and tungsten for the second layer, or a combination of titanium nitride for the first layer and titanium for the second layer may be employed. However, a material of thegate electrode layer401 preferably has heat resistance that can withstand at least later heat treatment.

At this time, theconnection electrode layer420 which is formed at the same time as the formation of thesource electrode layer405aand thedrain electrode layer405bin a later step may be formed at the same time as the formation of thegate electrode layer401. In that case, theconnection electrode layer420 is not necessarily formed when thesource electrode layer405aand thedrain electrode layer405bare formed.

Next, thegate insulating layer402 is formed over thegate electrode layer401.

The gate insulating layer can be formed as a single layer or a stacked layer using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer by a plasma enhanced CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed using a deposition gas containing SiH₄, oxygen, and nitrogen by a plasma enhanced CVD method.

Next, an oxide semiconductor film is formed over thegate insulating layer402.

Note that before the oxide semiconductor film is formed by a sputtering method, powdery substances (also referred to as particles or dust) which are generated at the time of the film formation and attached on a surface of thegate insulating layer402 are preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which an RF power supply is used for application of voltage to a substrate side in an argon atmosphere and plasma is generated around the substrate to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used.

The oxide semiconductor film is formed by a sputtering method with the use of an In—Ga—Zn—O-based oxide semiconductor target. Alternatively, the oxide semiconductor film can be formed by a sputtering method under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically, argon) and oxygen.

Thegate insulating layer402 and the oxide semiconductor film may be formed successively without exposure to air. Successive film formation without exposure to air makes it possible to obtain each interface between stacked layers, which is not contaminated by atmospheric components or impurity elements floating in air, such as water, hydrocarbon, or the like. Therefore, variation in characteristics of the thin film transistor can be reduced.

The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer using a photolithography process with the use of a photomask.

Next, a first conductive film is formed over thegate insulating layer402 and the oxide semiconductor layer.

The material used for the first conductive film preferably includes a heat resistant conductive material in order to perform heat treatment in a later process. As the heat resistant conductive material, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component can be used. The first conductive film may have a single-layer or stacked structure of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component. For example, a combination of tungsten nitride for a first layer and tungsten for a second layer, a combination of molybdenum nitride for the first layer and tungsten for the second layer, or a combination of titanium nitride for the first layer and titanium for the second layer may be used. However, a material of the first conductive film preferably has heat resistance that can withstand at least later heat treatment.

For the heat resistant conductive material used for the first conductive film, a transparent conductive oxide containing any of indium, tin, or zinc may be used. For example, indium oxide (In₂O₃) or an indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy is preferably used. Alternatively, a transparent conductive oxide to which an insulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in the transparent conductive oxide, crystallization of the transparent conductive oxide can be suppressed and the transparent conductive oxide can have an amorphous structure. Crystallization of the transparent conductive oxide is suppressed and an amorphous structure is provided, so that crystallization of the transparent conductive oxide or generation of microcrystalline grains can be prevented even when heat treatment is performed.

The oxide semiconductor layer and the first conductive film are processed into anoxide semiconductor layer432, thesource electrode layer405a, thedrain electrode layer405b, and theconnection electrode layer420 using a photolithography with the use of a photomask (seeFIG. 1A andFIG. 2A). Note that only part of the oxide semiconductor layer is etched to be theoxide semiconductor layer432 having a groove (depression).

Theconnection electrode layer420 is not necessarily formed when theconnection electrode layer420 is formed at the same time as the formation of thegate electrode layer401. Also in the case of having the structure illustrated inFIG. 3D, theconnection electrode layer420 is not necessarily formed.

Theoxide insulating film407 which covers thegate insulating layer402, theoxide semiconductor layer432, thesource electrode layer405a, and thedrain electrode layer405band which is in contact with part of theoxide semiconductor layer432 is formed (seeFIG. 1B). Theoxide insulating film407 can be formed to a thickness of at least 1 nm or more using a method by which impurities such as water and hydrogen are prevented from being mixed to theoxide insulating film407, such as a CVD method or a sputtering method, as appropriate. Here, theoxide insulating film407 is formed using a sputtering method. Theoxide insulating film407 which is in contact with part of theoxide semiconductor layer432 does not include impurities such as moisture, hydrogen ions, and OH⁻ and is formed using an inorganic insulating film which prevents entry of these from the outside. Specifically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. Further, a silicon nitride film or an aluminum nitride film may be stacked so as to be formed over and in contact with theoxide insulating film407. The silicon nitride film does not include impurities such as moisture, hydrogen ions, and OW and prevents entry of these from the outside.

When slow cooling is performed under an oxygen atmosphere after heat treatment to be performed later, a region including oxygen at high concentration near a surface of the oxide semiconductor layer can be formed, and the oxide semiconductor layer can have sufficient high resistance, a silicon nitride film may be formed instead of theoxide insulating film407. For example, slow cooling may be performed so that the substrate temperature is lowered by at least approximately 50° C. to 100° C. from the highest heating temperature.

In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as theoxide insulating film407. The substrate temperature at the time of film formation may be higher than or equal to a room temperature and lower than or equal to 300° C., and the temperature is set at 100° C. in this embodiment. The silicon oxide film can be formed by a sputtering method under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically, argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as a target. For example, the silicon oxide film can be formed using a silicon target by a sputtering method under an atmosphere containing oxygen and nitrogen.

Next, heat treatment is performed on thesource electrode layer405a, thedrain electrode layer405b, thegate insulating layer402, theoxide insulating film407, and theoxide semiconductor layer432 under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or under reduced pressure, whereby theoxide semiconductor layer403 is formed (seeFIG. 1C andFIG. 2B). The heat treatment is performed at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate400. When the heat treatment is performed on thesource electrode layer405a, thedrain electrode layer405b, thegate insulating layer402, theoxide insulating film407, and theoxide semiconductor layer403 under the above atmosphere, impurities such as hydrogen and water included in thesource electrode layer405a, in thedrain electrode layer405b, in thegate insulating layer402, in theoxide insulating film407, and in theoxide semiconductor layer403, and at interfaces between theoxide semiconductor layer403 and upper and lower films which are in contact with theoxide semiconductor layer403 can be removed. In accordance with conditions of the heat treatment or a material of the oxide semiconductor layer, the oxide semiconductor layer is crystallized and changed to a microcrystalline film or a polycrystalline film in some cases.

When theoxide insulating film407 serving as a protective film is formed in contact with theoxide semiconductor layer432, there is a possibility that theoxide semiconductor layer432 might receive plasma damage. However, with the heat treatment, plasma damage which is caused to theoxide semiconductor layer432 can be repaired.

With this heat treatment, oxygen in theoxide insulating film407 is supplied to theoxide semiconductor layer403 using solid-phase diffusion. Accordingly, since the resistance of theoxide semiconductor layer403 increases, a highly reliable thin film transistor with favorable electric characteristics can be manufactured.

The heat treatment can reduce variation in electric characteristics of the thin film transistor.

Note that in heat treatment, it is preferable that water, hydrogen, and the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or a rare gas such as helium, neon, or argon introduced into an apparatus for heat treatment have purity of 6N (99.9999%) or more, preferably, 7N (99.99999%) or more, that is, an impurity concentration is set to 1 ppm or lower, preferably, 0.1 ppm or lower. After the heat treatment, slow cooling is preferably performed under an oxygen atmosphere. For example, slow cooling may be performed so that the substrate temperature is lowered by at least approximately 50° C. to 100° C. from the highest heating temperature.

As the heat treatment, an instantaneous heating method can be employed, such as a heating method using an electric furnace, a gas rapid thermal annealing (GRTA) method using a heated gas, or a lamp rapid thermal anneal (LRTA) method using lamp light.

Here, as an embodiment of heat treatment of thesource electrode layer405a, thedrain electrode layer405b, thegate insulating layer402, theoxide insulating film407, and theoxide semiconductor layer432, a heating method using anelectric furnace601 will be described with reference toFIG. 15.

FIG. 15 is a schematic view of theelectric furnace601.Heaters603 are provided outside achamber602, which heats thechamber602. Inside thechamber602, asusceptor605 in which asubstrate604 is mounted is provided. Thesubstrate604 is transferred into/from thechamber602. In addition, thechamber602 is provided with a gas supply means606 and an evacuation means607. With the gas supply means606, a gas is introduced into thechamber602. The evacuation means607 exhausts the inside of thechamber602 or reduces the pressure in thechamber602. Note that the temperature rise characteristics of theelectric furnace601 are preferably set to from 0.1° C./min to 20° C./min, inclusive. The temperature drop characteristics of theelectric furnace601 are preferably set to from 0.1° C./min to 15° C./min, inclusive.

The gas supply means606 includes agas supply source611a, agas supply source611b, apressure regulation valve612a, apressure regulation valve612b, arefiner613a, arefiner613b, amass flow controller614a, amass flow controller614b, astop valve615a, and astop valve615b. In this embodiment, therefiner613aand therefiner613bare preferably provided between thegas supply source611aand thechamber602 and between thegas supply source611band thechamber602, respectively. Therefiner613aand therefiner613bcan remove impurities such as water and hydrogen in a gas which is introduced into thechamber602 from thegas supply source611aand thegas supply source611b; thus, entry into thechamber602 of water, hydrogen, and the like, can be suppressed by provision of therefiner613aand therefiner613b.

In this embodiment, nitrogen or a rare gas is introduced into thechamber602 from thegas supply source611aor thegas supply source611b, respectively, so that the inside of the chamber is in an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere. In thechamber602 which is heated at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate400, theoxide semiconductor layer432 formed over thesubstrate400 is heated, whereby theoxide semiconductor layer432 can be subjected to dehydration or dehydrogenation.

Alternatively, thechamber602 in which the pressure is reduced by the evacuation means is heated at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate400. In such achamber602, theoxide semiconductor layer432 formed over thesubstrate400 is heated, whereby theoxide semiconductor layer432 can be subjected to dehydration or dehydrogenation.

Next, introduction of nitrogen or a rare gas from thegas supply source611ainto thechamber602 is stopped, and the heaters are turned off. Then, oxygen is introduced from thegas supply source611binto thechamber602, and thechamber602 of a heating apparatus is gradually cooled. That is, thechamber602 has an oxygen atmosphere, and thesubstrate604 is gradually cooled. Here, impurities such as water and hydrogen are preferably not included in oxygen which is introduced from thegas supply source611binto thechamber602. Alternatively, the purity of oxygen introduced from thegas supply source611binto thechamber602 is preferably 6N (99.9999%) or more, more preferably, 7N (99.99999%) or more, that is, an impurity concentration in oxygen is set to 1 ppm or lower, preferably, 0.1 ppm or lower.

As a result, reliability of the thin film transistor to be formed later can be improved.

Note that when heat treatment is performed under reduced pressure, oxygen may be introduced into thechamber602 after the heat treatment, pressure may be returned to atmospheric pressure, and then cooling may be performed.

Alternatively, oxygen is introduced from thegas supply source611binto thechamber602, and at the same time, one of or both nitrogen and a rare gas such as helium, neon, or argon may be introduced into thechamber602.

After thesubstrate604 in thechamber602 of the heating apparatus is cooled to 300° C., thesubstrate604 may be transferred into an atmosphere at room temperature. As a result, the cooling time of thesubstrate604 can be shortened.

When the heating apparatus has a multi-chamber structure, heat treatment and cooling treatment can be performed in chambers different from each other. Typically, an oxide semiconductor layer over a substrate is heated in a first chamber that is filled with oxygen, nitrogen, or a rare gas and heated at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate400. Next, the substrate which has been subjected to the heat treatment is transferred, through the transfer chamber in which nitrogen or a rare gas is introduced, into a second chamber that is filled with oxygen and heated at a temperature of lower than or equal to 100° C., preferably at room temperature, and then cooling treatment is performed therein. Through this process, throughput can be increased.

Although theoxide semiconductor layer432 which has been subjected to heat treatment under an inert gas atmosphere or reduced pressure is preferably an amorphous state, part of theoxide semiconductor layer432 may be crystallized.

As described above, when heat treatment is performed after the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer, impurities (H₂O, H, OH, or the like) included in the source electrode layer, the drain electrode layer, the gate insulating layer, the oxide insulating film, and the oxide semiconductor layer can be reduced. With the heat treatment, plasma damage which is caused to the oxide semiconductor layer when the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer can be repaired. The heat treatment can reduce variation in electric characteristics of the thin film transistor. As described above, electric characteristics and reliability of thethin film transistor461 can be improved.

Next, thefirst contact hole421, thesecond contact hole422, thethird contact hole423, and thefourth contact hole424 are formed in the oxide insulating film407 (seeFIG. 1D andFIG. 2C). First, when part of theoxide insulating film407 is removed by etching, thefirst contact hole421 which reaches thesource electrode layer405a, part of thesecond contact hole422 which reaches thegate electrode layer401, and thethird contact hole423 and thefourth contact hole424 which reach both end portions of theconnection electrode layer420 are formed. Further, part of thegate insulating layer402 is removed by etching, so that thesecond contact hole422 which reaches thegate electrode layer401 is formed.

Next, a second conductive film is formed over theoxide insulating film407. Here, the second conductive film is connected to thesource electrode layer405a, thegate electrode layer401, and theconnection electrode layer420 through thefirst contact hole421, thesecond contact hole422, thethird contact hole423, and thefourth contact hole424.

The second conductive film is preferably formed using a low resistance conductive material which has lower resistivity than thesource electrode layer405aand thedrain electrode layer405b, and aluminum or copper is particularly preferable. With the use of the low resistance conductive material for the second conductive film, wiring resistance or the like can be reduced.

Although the low resistance conductive material such as aluminum or copper has low heat resistivity, the second conductive film can be provided after the heat treatment; therefore, the low resistance conductive material such as aluminum or copper can be used.

Next, the second conductive film is processed using a photolithography process with the use of a photomask, so that thesource wiring425, thefirst gate wiring426, and thesecond gate wiring427 are formed over the oxide insulating film407 (seeFIG. 1E andFIG. 2D). Thesource wiring425 is formed so as to overlap theconnection electrode layer420 and so as to be connected to thesource electrode layer405athrough thefirst contact hole421. Thefirst gate wiring426 and thesecond gate wiring427 are formed so as to sandwich thesource wiring425 therebetween. Here, thefirst gate wiring426 is formed so as to be connected to thegate electrode layer401 through thesecond contact hole422 and so as to be connected to theconnection electrode layer420 through thethird contact hole423. Thesecond gate wiring427 is formed so as to be connected to theconnection electrode layer420 through thefourth contact hole424. Accordingly, thefirst gate wiring426 and thesecond gate wiring427 are electrically connected to each other through theconnection electrode layer420.

Through the above process, thethin film transistor461 can be formed. The structures illustrated inFIGS. 3C and 3D can be manufactured in a similar process.

As described above, when heat treatment is performed after the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer, impurities (H₂O, H, OH, or the like) included in the source electrode layer, the drain electrode layer, the gate insulating layer, and the oxide semiconductor layer can be reduced. With the heat treatment, plasma damage which is caused to the oxide semiconductor layer when the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer can be repaired. The heat treatment can reduce variation in electric characteristics of the thin film transistor. Therefore, reliability of thethin film transistor461 can be improved.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Embodiment 2

A semiconductor device and a method for manufacturing the semiconductor device will be described with reference toFIGS. 4A to 4E,FIGS. 5A to 5D, andFIGS. 6A to 6D. The same portion asEmbodiment 1 or a portion having similar function to that described inEmbodiment 1 can be formed in a manner similar to that described inEmbodiment 1; therefore, repetitive description is omitted.

FIG. 6A is a plan view of athin film transistor460 included in a semiconductor device, andFIG. 6B is a cross-sectional view taken along line D1-D2 ofFIG. 6A. Thethin film transistor460 is an inverted staggered thin film transistor. Agate electrode layer451 is provided over asubstrate450 having an insulating surface. Agate insulating layer452 is provided over thegate electrode layer451. Asource electrode layer455aand adrain electrode layer455bare provided over thegate insulating layer452. Anoxide semiconductor layer453 is provided over thesource electrode layer455a, thedrain electrode layer455b, and thegate insulating layer452. Anoxide insulating film457 which covers thegate insulating layer452, theoxide semiconductor layer453, thesource electrode layer455a, and thedrain electrode layer455band which is in contact with theoxide semiconductor layer453 is provided. An In—Ga—Zn—O-based non-single-crystal film is used for theoxide semiconductor layer453.

Theoxide insulating film457 is provided with afirst contact hole471 which reaches thesource electrode layer455a, asecond contact hole472 which reaches thegate electrode layer451, and athird contact hole473 and afourth contact hole474 which reach both end portions of aconnection electrode layer470. Here, in this embodiment, a source wiring and a drain wiring are formed from the same layer;

therefore, afirst gate wiring476 and asecond gate wiring477 are formed so as to sandwich asource wiring475 therebetween. Thefirst gate wiring476 and thesecond gate wiring477 are electrically connected to each other through theconnection electrode layer470 which is formed so as to overlap thesource wiring475. Here, thesource wiring475 is electrically connected to thesource electrode layer455athrough thefirst contact hole471. Thefirst gate wiring476 is electrically connected to thegate electrode layer451 through thesecond contact hole472. Thefirst gate wiring476 and thesecond gate wiring477 are electrically connected to theconnection electrode layer470 through thethird contact hole473 and thefourth contact hole474. Thesource wiring475, thefirst gate wiring476, and thesecond gate wiring477 extend beyond the perimeter of theoxide semiconductor layer453.

After theoxide insulating film457 serving as a protective film is formed in contact with theoxide semiconductor layer453, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed on theoxide semiconductor layer453.

Impurities such as moisture which exist not only in theoxide semiconductor layer453 but also in thegate insulating layer452, in thesource electrode layer455a, in thedrain electrode layer455b, or at interfaces between theoxide semiconductor layer453 and upper and lower films which are in contact with theoxide semiconductor layer453, specifically, at an interface between thegate insulating layer452 and theoxide semiconductor layer453 or at an interface between theoxide insulating film457 and theoxide semiconductor layer453 are reduced. When the moisture content or the like in theoxide semiconductor layer453 is reduced with the heat treatment, electric characteristics of the thin film transistor can be improved.

With the heat treatment, plasma damage which is caused to theoxide semiconductor layer453 when theoxide insulating film457 is formed is repaired.

Each of thegate electrode layer451, theconnection electrode layer470, thesource electrode layer455a, and thedrain electrode layer455bpreferably includes a heat resistant conductive material. As the heat resistant conductive material, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component can be used. Thegate electrode layer451, theconnection electrode layer470, thesource electrode layer455a, and thedrain electrode layer455bmay have a stacked structure of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium; an alloy including any of these elements as a component; or a nitride including any of these elements as a component. For example, a combination of tungsten nitride for a first layer and tungsten for a second layer, a combination of molybdenum nitride for the first layer and tungsten for the second layer, or a combination of titanium nitride for the first layer and titanium for the second layer may be employed.

For the heat resistant conductive material used for theconnection electrode layer470, thesource electrode layer455a, and thedrain electrode layer455b, a transparent conductive oxide containing any of indium, tin, or zinc may be used. For example, indium oxide (In₂O₃) or an indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy is preferably used. Alternatively, a transparent conductive oxide to which an insulating oxide such as silicon oxide is added may be used.

By inclusion of the insulating oxide such as silicon oxide in the transparent conductive oxide, crystallization of the transparent conductive oxide can be suppressed and the transparent conductive oxide can have an amorphous structure. Crystallization of the transparent conductive oxide is suppressed and the transparent conductive oxide has an amorphous structure, so that crystallization of the transparent conductive oxide or generation of microcrystalline grains can be prevented even when heat treatment is performed.

Such a heat resistant conductive material is included in thegate electrode layer451, theconnection electrode layer470, thesource electrode layer455a, and thedrain electrode layer455b, whereby thegate electrode layer451, theconnection electrode layer470, thesource electrode layer455a, and thedrain electrode layer455bcan endure heat treatment which is performed after theoxide insulating film457 is formed.

Thesource wiring475, thefirst gate wiring476, and thesecond gate wiring477 are preferably formed using a low resistance conductive material which has lower resistivity than thesource electrode layer455aand thedrain electrode layer455b, and aluminum or copper is particularly preferable. With the use of the low resistance conductive material for thesource wiring475, thefirst gate wiring476, and thesecond gate wiring477, wiring resistance or the like can be reduced.

The low resistance conductive material such as aluminum or copper has low heat resistance. However, when thesource wiring475, thefirst gate wiring476, and thesecond gate wiring477 are provided after performing heat treatment and forming the oxide insulating layer, and then the above low resistance conductive material can be used as thesource wiring475, thefirst gate wiring476, and thesecond gate wiring477.

As theoxide semiconductor layer453 including a channel formation region, an oxide material having semiconductor characteristics may be used, and typically, In—Ga—Zn—O-based non-single-crystal is used.

As illustrated inFIG. 6C, afirst source wiring478 and a second source wiring479 may be formed so as to sandwich agate wiring480 therebetween and may be electrically connected to each other through theconnection electrode layer470 which is formed so as to overlap thegate wiring480. Here, thefirst source wiring478 is electrically connected to thesource electrode layer455athrough thefirst contact hole471. Thegate wiring480 is electrically connected to thegate electrode layer451 through thesecond contact hole472. Thefirst source wiring478 and the second source wiring479 are electrically connected to theconnection electrode layer470 through thethird contact hole473 and thefourth contact hole474 which reach both end portions of theconnection electrode layer470. The other portions are similar to those of the thin film transistor illustrated inFIGS. 6A and 6B.

As illustrated inFIG. 6D, thesource electrode layer455amay be formed so as to overlap thegate wiring480, and thefirst source wiring478 and the second source wiring479 may be electrically connected to each other through thesource electrode layer455a. Here, thefirst source wiring478 is electrically connected to thesource electrode layer455athrough thefirst contact hole471. The second source wiring479 is electrically connected to thesource electrode layer455athrough athird contact hole491 provided over thesource electrode layer455a. The other portions are similar to those of the thin film transistor illustrated inFIG. 6C.

FIGS. 4A to 4E are cross-sectional views of a manufacturing process of thethin film transistor460 illustrated inFIGS. 6A and 6B, whileFIGS. 5A to 5D are plan views of the manufacturing process.

Thegate electrode layer451 is provided over thesubstrate450 which is a substrate having an insulating surface. An insulating film serving as a base film may be provided between thesubstrate450 and thegate electrode layer451. Thegate electrode layer451 can be formed using a material which is similar to that of thegate electrode layer401 described inEmbodiment 1.

Thegate insulating layer452 is formed over thegate electrode layer451. Thegate insulating layer452 can be formed in a manner similar to that of thegate insulating layer402 described inEmbodiment 1.

A first conductive film is formed over thegate insulating layer452 and patterned into the island-shapedsource electrode layer455a, the island-shapeddrain electrode layer455b, and theconnection electrode layer470 by a photolithography process. The first conductive film can be formed using a material which is similar to the material used for the first conductive film described inEmbodiment 1. Thesource electrode layer455aand thedrain electrode layer455bcan be formed in a manner similar to that of thesource electrode layer405aand thedrain electrode layer405bdescribed inEmbodiment 1.

When theconnection electrode layer470 is formed at the same time as the formation of thegate electrode layer451, theconnection electrode layer470 is not necessarily formed here. Also in the case of having such a structure as illustrated inFIG. 6D, theconnection electrode layer470 is not necessarily formed.

Then, an oxide semiconductor film is formed over thegate insulating layer452, thesource electrode layer455a, and thedrain electrode layer455band patterned into an island-shapedoxide semiconductor layer482 by a photolithography process (seeFIG. 4A andFIG. 5A).

Theoxide semiconductor layer482 serves as a channel formation region and is thus formed in a manner similar to theoxide semiconductor layer432 inEmbodiment 1.

Note that before theoxide semiconductor layer482 is formed by a sputtering method, powdery substances (also referred to as particles or dust) which are generated at the time of the film formation and attached on a surface of thegate insulating layer452 are preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated.

Next, theoxide insulating film457 which covers thegate insulating layer452, theoxide semiconductor layer482, thesource electrode layer455a, and thedrain electrode layer455band which is in contact with theoxide semiconductor layer482 is formed by a sputtering method or a PCVD method (seeFIG. 4B). Theoxide insulating film457 can also be formed in a manner similar to that of theoxide insulating film407 described inEmbodiment 1. In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as theoxide insulating film457. The substrate temperature at the time of film formation may be higher than or equal to a room temperature and lower than or equal to 300° C., and the temperature is set at 100° C. in this embodiment.

Next, heat treatment is performed on thesource electrode layer455a, thedrain electrode layer455b, thegate insulating layer452, theoxide insulating film457, and theoxide semiconductor layer482 under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or under reduced pressure, whereby theoxide semiconductor layer453 is formed (seeFIG. 4C andFIG. 5B). The heat treatment is performed at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate450. When the heat treatment is performed on thesource electrode layer455a, thedrain electrode layer455b, thegate insulating layer452, theoxide insulating film457, and theoxide semiconductor layer453 under the above atmosphere, impurities such as hydrogen and water included in thesource electrode layer455a, in thedrain electrode layer455b, in thegate insulating layer452, in theoxide insulating film457, and in theoxide semiconductor layer453, and at interfaces between theoxide semiconductor layer453 and upper and lower films which are in contact with theoxide semiconductor layer453 can be removed. In accordance with conditions of the heat treatment or a material of the oxide semiconductor layer, the oxide semiconductor layer is crystallized and changed to a microcrystalline film or a polycrystalline film in some cases.

When theoxide insulating film457 serving as a protective film is formed in contact with theoxide semiconductor layer482, there is a possibility that theoxide semiconductor layer482 might receive plasma damage. However, with the heat treatment, plasma damage which is caused to theoxide semiconductor layer482 can be repaired.

Note that in heat treatment for dehydration or dehydrogenation, it is preferable that water, hydrogen, and the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or a rare gas such as helium, neon, or argon introduced into an apparatus for heat treatment have purity of 6N (99.9999%) or more, preferably, 7N (99.99999%) or more, that is, an impurity concentration is set to 1 ppm or lower, preferably, 0.1 ppm or lower. After the heat treatment, slow cooling is preferably performed under an oxygen atmosphere. For example, slow cooling may be performed so that the substrate temperature is lowered by at least approximately 50° C. to 100° C. from the highest heating temperature.

Here, as an embodiment of heat treatment of theoxide semiconductor layer482, a heating method using anelectric furnace1601 will be described with reference toFIG. 16.

FIG. 16 is a schematic view of theelectric furnace1601.Heaters1603 are provided outside achamber1602, which heats thechamber1602. Inside thechamber1602, asusceptor1605 in which asubstrate1604 is mounted is provided. Thesubstrate1604 is transferred into/from thechamber1602. In addition, thechamber1602 is provided with a gas supply means1606 and an evacuation means1607. With the gas supply means1606, a gas is introduced into thechamber1602. The evacuation means1607 exhausts the inside of thechamber1602 or reduces the pressure in thechamber1602. Note that the temperature rise characteristics of theelectric furnace1601 are preferably set to from 0.1° C./min to 20° C./min, inclusive. The temperature drop characteristics of theelectric furnace1601 are preferably set to from 0.1° C./min to 15° C./min, inclusive.

The gas supply means1606 includes agas supply source1611, apressure regulation valve1612, arefiner1613, amass flow controller1614, and astop valve1615. In this embodiment, therefiner1613 is preferably provided between thegas supply source1611 and thechamber1602. Therefiner1613 can remove impurities such as water and hydrogen in a gas which is introduced into thechamber1602 from thegas supply source1611; thus, entry into thechamber1602 of water, hydrogen, and the like, can be suppressed by provision of therefiner1613.

In this embodiment, oxygen, nitrogen, or a rare gas is introduced into thechamber1602 from thegas supply source1611, so that the inside of the chamber is in a nitrogen atmosphere or a rare gas atmosphere. In thechamber1602 which is heated at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate450, the oxide semiconductor layer formed over thesubstrate450 is heated, whereby the oxide semiconductor layer can be subjected to dehydration or dehydrogenation.

Alternatively, thechamber1602 in which the pressure is reduced by the evacuation means is heated at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate450. In such achamber1602, the oxide semiconductor layer formed over thesubstrate450 is heated, whereby the oxide semiconductor layer can be subjected to dehydration or dehydrogenation.

Next, the heaters are turned off, and thechamber1602 of a heating apparatus is gradually cooled.

Note that when heat treatment is performed under reduced pressure, an inert gas may be introduced into thechamber1602 after the heat treatment, pressure may be returned to atmospheric pressure, and cooling may be performed.

After thesubstrate1604 in thechamber1602 of the heating apparatus is cooled to 300° C., thesubstrate1604 may be transferred into an atmosphere at room temperature. As a result, the cooling time of thesubstrate1604 can be shortened.

When the heating apparatus has a multi-chamber structure, heat treatment and cooling treatment can be performed in chambers different from each other. Typically, an oxide semiconductor layer over a substrate is heated in a first chamber that is filled with oxygen, nitrogen, or a rare gas and heated at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate450. Next, the substrate which has been subjected to the heat treatment is transferred, through the transfer chamber in which nitrogen or a rare gas is introduced, into a second chamber that is filled with nitrogen or a rare gas and heated at a temperature of lower than or equal to 100° C., preferably at room temperature, and then cooling treatment is performed therein. Through this process, throughput can be increased.

Although theoxide semiconductor layer482 which has been subjected to heat treatment under an inert gas atmosphere or reduced pressure is preferably an amorphous state, part of theoxide semiconductor layer482 may be crystallized.

As described above, when heat treatment is performed after the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer, impurities (H₂O, H, OH, or the like) included in the source electrode layer, the drain electrode layer, the gate insulating layer, the oxide insulating film, and the oxide semiconductor layer can be reduced. With the heat treatment, plasma damage which is caused to the oxide semiconductor layer when the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer can be repaired. The heat treatment can reduce variation in electric characteristics of the thin film transistor. Accordingly, electric characteristics and reliability of thethin film transistor460 can be improved.

Next, thefirst contact hole471, thesecond contact hole472, thethird contact hole473, and thefourth contact hole474 are formed in the oxide insulating film457 (seeFIG. 4D andFIG. 5C). First, when part of theoxide insulating film457 is removed by etching, thefirst contact hole471 which reaches thesource electrode layer455a, part of thesecond contact hole472 which reaches thegate electrode layer451, and thethird contact hole473 and thefourth contact hole474 which reach both end portions of theconnection electrode layer470 are formed. Further, part of thegate insulating layer452 is removed by etching, so that the second contact hole which reaches thegate electrode layer451 is formed.

Next, a second conductive film is formed over theoxide insulating film457. Here, the second conductive film is connected to thesource electrode layer455a, thegate electrode layer451, and theconnection electrode layer470 through thefirst contact hole471, thesecond contact hole472, thethird contact hole473, and thefourth contact hole474.

The second conductive film is preferably formed using a low resistance conductive material which has lower resistivity than thesource electrode layer455aand thedrain electrode layer455b, and aluminum or copper is particularly preferable. With the use of the low resistance conductive material for the second conductive film, wiring resistance or the like can be reduced.

Next, the second conductive film is etched through an etching process, so that thesource wiring475, thefirst gate wiring476, and thesecond gate wiring477 are formed over the oxide insulating film457 (seeFIG. 4E andFIG. 5D). Thesource wiring475 is formed so as to overlap theconnection electrode layer470 and so as to be connected to thesource electrode layer455athrough thefirst contact hole471. Thefirst gate wiring476 and thesecond gate wiring477 are formed so as to sandwich thesource wiring475 therebetween. Here, thefirst gate wiring476 is formed so as to be connected to thegate electrode layer451 through thesecond contact hole472 and so as to be connected to theconnection electrode layer470 through thethird contact hole473. Thesecond gate wiring477 is formed so as to be connected to theconnection electrode layer470 through thefourth contact hole474. Accordingly, thefirst gate wiring476 and thesecond gate wiring477 are electrically connected to each other through theconnection electrode layer470.

Through the above process, thethin film transistor460 can be formed. The structures illustrated inFIGS. 6C and 6D can be manufactured in a similar process.

As described above, when heat treatment is performed after the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer, impurities (H₂O, H, OH, or the like) included in the source electrode layer, the drain electrode layer, the gate insulating layer, and the oxide semiconductor layer can be reduced. With the heat treatment, plasma damage which is caused to the oxide semiconductor layer when the oxide insulating film serving as a protective film is formed in contact with the oxide semiconductor layer can be repaired. The heat treatment can reduce variation in electric characteristics of the thin film transistor. Therefore, reliability of thethin film transistor460 can be improved.

Embodiment 3

A manufacturing process of a semiconductor device including a thin film transistor will be described with reference toFIGS. 7A to 7D,FIGS. 8A to 8C,FIGS. 9A and 9B,FIG. 10,FIG. 11,FIG. 12, andFIG. 13.FIGS. 7A to 7D,FIGS. 8A to 8C, andFIGS. 9A and 9B are cross-sectional views of a manufacturing process, andFIG. 10,FIG. 11,FIG. 12, andFIG. 13 are plan views of the manufacturing process.

As for asubstrate100 having a light-transmitting property illustrated inFIG. 7A, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like can be used. Note that a substrate formed of an insulator such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used instead of theglass substrate100. Alternatively, crystallized glass or the like may be used.

Next, a conductive layer is formed over the entire surface of thesubstrate100, and then a first photolithography process is performed to form a resist mask. Then, an unnecessary portion is removed by etching, so that a wiring and an electrode (agate electrode layer101, acapacitor wiring108, and a first terminal121) are formed. At this time, the etching is performed so that at least end portions of thegate electrode layer101 have a tapered shape.

Thegate electrode layer101, thecapacitor wiring108, and thefirst terminal121 of a terminal portion can be formed using the material of thegate electrode layer401 described inEmbodiment 1, as appropriate. Each of thegate electrode layer101, thecapacitor wiring108, and thefirst terminal121 of the terminal portion is preferably formed using a heat-resistance conductive material in order to endure heat treatment in a later step, and is formed using an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), or scandium (Sc); an alloy including any of these elements as a component; an alloy film including any of these elements as a component in combination; or a nitride including any of these elements as a component, in a single layer or a stacked layer.

At this time, aconnection electrode layer220 which is formed at the same time as the formation of asource electrode layer105aand adrain electrode layer105bwhich are formed in a later step may be formed at the same time as the formation of thegate electrode layer101. In that case, theconnection electrode layer220 is not necessarily formed when thesource electrode layer105aand thedrain electrode layer105bare formed.

Next, agate insulating layer102 is formed over the entire surface of thegate electrode layer101. Thegate insulating layer102 is formed to a thickness of 50 to 250 nm by a sputtering method, a PCVD method, or the like.

For example, as thegate insulating layer102, a silicon oxide film is formed to a thickness of 100 nm by a sputtering method. Needless to say, thegate insulating layer102 is not limited to such as a silicon oxide film and may be formed to have a single-layer structure or a stacked structure using another insulating film such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, a tantalum oxide film, and the like.

Next, an oxide semiconductor film (In—Ga—Zn—O-based non-single-crystal film) is formed over thegate insulating layer102. It is effective to deposit the In—Ga—Zn—O-based non-single-crystal film without exposure to air after the plasma treatment because dust and moisture are not attached to the interface between the gate insulating layer and the semiconductor film. Here, the oxide semiconductor film is formed in an oxygen atmosphere, an argon atmosphere, or an atmosphere containing argon and oxygen under the condition where a target is an oxide semiconductor target containing In, Ga, and Zn (In—Ga—Zn—O-based oxide semiconductor target (In₂O₃:Ga₂O₃:ZnO=1:1:1)) with a diameter of 8 inches, the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, and the direct current (DC) power supply is 0.5 kW. Note that a pulse direct current (DC) power supply is preferable because dust can be reduced and the film thickness can be uniform. The In—Ga—Zn—O-based non-single-crystal film is formed to a thickness of 5 nm to 200 nm. As the oxide semiconductor film, an In—Ga—Zn—O-based non-single-crystal film with a thickness of 50 nm is formed using the In—Ga—Zn—O-based oxide semiconductor target by a sputtering method.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power supply is used for a sputtering power supply, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be deposited to be stacked in the same chamber, and a film of plural kinds of materials can be deposited by electric discharge at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, and a sputtering apparatus used for an ECR sputtering method in which plasma generated with the use of microwaves is used without using glow discharge.

In addition, as a film formation method using a sputtering method, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during film formation to form a thin film of a compound thereof, and a bias sputtering method in which voltage is also applied to a substrate during film formation.

Next, a second photolithography process is performed to form a resist mask, and then the oxide semiconductor film is etched. For example, unnecessary portions are removed by wet etching using a mixed solution of phosphoric acid, acetic acid, and nitric acid, so that anoxide semiconductor layer133 is formed (seeFIG. 7A andFIG. 10). Note that etching here is not limited to wet etching and dry etching may also be performed.

As the etching gas for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl₂), boron chloride (BCl₃), silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄)) is preferably used.

Alternatively, a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), nitrogen trifluoride (NF₃), or trifluoromethane (CHF₃)); oxygen (O₂); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like can be used as the etching gas used for dry etching.

As the dry etching method, a parallel plate reactive ion etching (RIE) method, an inductively coupled plasma (ICP) etching method, or the like can be used. In order to etch the films into desired shapes, the etching condition (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side, or the like) is adjusted as appropriate.

As an etchant used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid or the like can be used. In addition, ITO07N (produced by KANTO CHEMICAL CO., INC.) may also be used.

The etchant used in the wet etching is removed by cleaning together with the material which is etched off. The waste liquid including the etchant and the material etched off may be purified and the material may be reused. When a material such as indium included in the oxide semiconductor layer is collected from the waste liquid after the etching and reused, the resources can be efficiently used and the cost can be reduced.

Note that the etching condition (etching solution, etching time, temperature, or the like) are adjusted as appropriate, depending on a material, so that the films can be etched into the desired shapes.

Then, a firstconductive film132 made of a metal material is formed over theoxide semiconductor layer133 by a sputtering method or a vacuum evaporation method (seeFIG. 7B).

For a material of the firstconductive film132, a material which is similar to that of thesource electrode layer405aand thedrain electrode layer405bdescribed inEmbodiment 1 can be used as appropriate. The firstconductive film132 is preferably formed using a heat-resistance conductive material in order to endure heat treatment in a later step, and is formed using an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), or scandium (Sc); an alloy including any of these elements as a component; an alloy film including any of these elements as a component in combination; or a nitride including any of these elements as a component, in a single layer or a stacked layer.

For the heat resistant conductive material used for the firstconductive film132, a transparent conductive oxide containing any of indium, tin, or zinc may be used. For example, indium oxide (In₂O₃) or an indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated to ITO) alloy is preferably used. Alternatively, a transparent conductive oxide to which an insulating oxide such as silicon oxide is added may be used.

Next, a third photolithography process is performed. A resist mask is formed, and unnecessary portions are removed by etching, whereby thesource electrode layer105a, thedrain electrode layer105b, theconnection electrode layer220, and asecond terminal122 are formed (seeFIG. 7C andFIG. 11). Wet etching or dry etching is employed as an etching method at this time. For example, by wet etching using an ammonia hydrogen peroxide mixture (with the ratio of hydrogen peroxide:ammonia:water=5:2:2), the firstconductive film132 may be etched to form thesource electrode layer105aand thedrain electrode layer105b. In this etching step, an exposed region of theoxide semiconductor layer133 is partly etched to be anoxide semiconductor layer135. Therefore, a region of theoxide semiconductor layer135, which lies between thesource electrode layer105aand thedrain electrode layer105bhas a small thickness. The region with a small thickness has a thickness of approximately 30 nm which further hinders crystallization; therefore, the region with a small thickness is effective in the case where a portion serving as a channel is desired to be kept to be in an amorphous state. InFIG. 7C, the etching for forming thesource electrode layer105a, thedrain electrode layer105b, and theoxide semiconductor layer135 is performed at a time by dry etching. Accordingly, end portions of thesource electrode layer105aand thedrain electrode layer105bare aligned with end portions of theoxide semiconductor layer135; thus, continuous structures are formed.

In the third photolithography process, thesecond terminal122 which is formed using the same material as thesource electrode layer105aand thedrain electrode layer105bis left in a terminal portion. Note that thesecond terminal122 is electrically connected to a source wiring to be formed in a later step.

When theconnection electrode layer420 is formed at the same time as the formation of thegate electrode layer401, theconnection electrode layer420 is not necessarily formed here.

Further, by use of a resist mask having regions with plural thicknesses (typically, two different thicknesses) which is formed using a multi-tone mask, the number of resist masks can be reduced, resulting in simplified process and lower costs.

Then, the resist mask is removed, and a protectiveinsulating layer107 is formed to cover thegate insulating layer102, theoxide semiconductor layer135, thesource electrode layer105a, and thedrain electrode layer105b(seeFIG. 7D). The protectiveinsulating layer107 can be formed to a thickness of at least 1 nm or more using a method by which impurities such as water and hydrogen are prevented from being mixed to the protective insulatinglayer107, such as a CVD method or a sputtering method, as appropriate. Here, the protective insulatinglayer107 is formed using a sputtering method. The protectiveinsulating layer107 which is in contact with part of theoxide semiconductor layer135 does not include impurities such as moisture, hydrogen ions, and OH⁻, and is formed using an inorganic insulating film which prevents entry of these from the outside. Specifically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. Further, a silicon nitride film or an aluminum nitride film may be stacked so as to be formed over and in contact with the protective insulatinglayer107. The silicon nitride film does not include impurities such as moisture, hydrogen ions, and OW and prevents entry of these from the outside.

When the protective insulatinglayer107 is formed in contact with theoxide semiconductor layer135 by a sputtering method, a PCVD method, or the like, a region of theoxide semiconductor layer135, which is in contact with at least the protective insulatinglayer107 can be of high resistance (carrier concentration is decreased, preferably, the carrier concentration is less than 1×10¹⁸/cm³), and can serve as a high-resistance oxide semiconductor region.

Next, heat treatment is performed on thesource electrode layer105a, thedrain electrode layer105b, thegate insulating layer102, and theoxide semiconductor layer135 under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or under reduced pressure, whereby anoxide semiconductor layer103 is formed (seeFIG. 8A). The heat treatment is performed at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate100. When the heat treatment is performed on thesource electrode layer105a, thedrain electrode layer105b, thegate insulating layer102, and theoxide semiconductor layer103 under the above atmosphere, impurities such as hydrogen and water included in thesource electrode layer105a, in thedrain electrode layer105b, in thegate insulating layer102, and in theoxide semiconductor layer103, and at interfaces between theoxide semiconductor layer103 and upper and lower films which are in contact with theoxide semiconductor layer103 can be removed. In accordance with conditions of the heat treatment or a material of the oxide semiconductor layer, the oxide semiconductor layer is crystallized and changed to a microcrystalline film or a polycrystalline film in some cases.

When the protective insulatinglayer107 serving as a protective film is formed in contact with theoxide semiconductor layer133, there is a possibility that theoxide semiconductor layer133 might receive plasma damage. However, with the heat treatment, plasma damage which is caused to theoxide semiconductor layer133 can be repaired.

With this heat treatment, oxygen in the protective insulatinglayer107 is supplied to theoxide semiconductor layer103 using solid-phase diffusion. Accordingly, since the resistance of theoxide semiconductor layer103 increases, a highly reliable thin film transistor with favorable electric characteristics can be manufactured.

The heat treatment can reduce variation in electric characteristics of the thin film transistor. After the heat treatment, slow cooling is preferably performed under an oxygen atmosphere. For example, slow cooling may be performed so that the substrate temperature is lowered by at least approximately 50° C. to 100° C. from the highest heating temperature.

Next, a fourth photolithography process is performed. A resist mask is formed, and the protective insulatinglayer107 and thegate insulating layer102 are etched to form afirst contact hole221, asecond contact hole222, athird contact hole223, and a fourth contact hole224 (seeFIG. 8B andFIG. 12). First, when part of the protective insulatinglayer107 is removed by etching, thefirst contact hole221 which reaches thesource electrode layer105a, part of thesecond contact hole222 which reaches thegate electrode layer101, and thethird contact hole223 and thefourth contact hole224 which reach both end portions of theconnection electrode layer220 are formed. Further, part of thegate insulating layer102 is removed by etching, so that thesecond contact hole222 which reaches thegate electrode layer101 is formed.

When a reflective display device is manufactured, a contact hole which reaches thedrain electrode layer105bmay be formed here, and apixel electrode layer110 may be formed at the same time as the formation of a source wiring and a gate wiring.

Next, a second conductive film made of a metal material is formed over the protective insulatinglayer107 by a sputtering method or a vacuum evaporation method. Here, the second conductive film is connected to thesource electrode layer105a, thegate electrode layer101, and theconnection electrode layer220 through thefirst contact hole221, thesecond contact hole222, thethird contact hole223, and thefourth contact hole224.

As a material for the second conductive film, a material which is similar to that of the second conductive film described inEmbodiment 1 can be used as appropriate. The second conductive film is preferably formed using a low resistance conductive material which has lower resistivity than thesource electrode layer105aand thedrain electrode layer105b, and aluminum or copper is particularly preferable. With the use of the low resistance conductive material for the second conductive film, wiring resistance or the like can be reduced.

Next, a fifth photolithography process is performed. A resist mask is formed, and the second conductive film is etched to form asource wiring225, afirst gate wiring226, and a second gate wiring227 over the protective insulating layer107 (seeFIG. 8C andFIG. 12). Thesource wiring225 overlaps theconnection electrode layer220 and is formed so as to be connected to thesource electrode layer105athrough thefirst contact hole221. Thefirst gate wiring226 and thesecond gate wiring227 are formed so as to sandwich thesource wiring225. Here, thefirst gate wiring226 is formed so as to be connected to thegate electrode layer101 through thesecond contact hole222 and so as to be connected to theconnection electrode layer220 through thethird contact hole223. In addition, thesecond gate wiring227 is formed so as to be connected to theconnection electrode layer220 through thefourth contact hole224. Accordingly, thefirst gate wiring226 and thesecond gate wiring427 are electrically connected to each other through theconnection electrode layer220.

Through the above steps, athin film transistor170 can be manufactured.

Next, a sixth photolithography process is performed. A resist mask is formed, and the protective insulatinglayer107 is etched to form acontact hole125 which reaches thedrain electrode layer105b. In addition, acontact hole127 which reaches thesecond terminal122 and acontact hole126 which reaches thefirst terminal121 are also formed in the same etching step. A cross-sectional view at this stage is illustrated inFIG. 9A. Note that thecontact hole125, thecontact hole126, and thecontact hole127 can be formed at the same time in the fourth photolithography process.

Next, the resist mask is removed, and then a transparent conductive film is formed. The transparent conductive film is formed using indium oxide (In₂O₃), an indium oxide-tin oxide (In₂O₃—SnO₂, abbreviated as ITO) alloy, or the like by a sputtering method, a vacuum evaporation method, or the like. Such a material is etched with a hydrochloric acid-based solution. However, since a residue is easily generated particularly in etching ITO, indium oxide-zinc oxide alloy (In₂O₃—ZnO) may be used to improve etching processability. When heat treatment for reducing the resistance of the transparent conductive film is performed, an increase in the resistance of theoxide semiconductor layer103 and improvement and less variation in electric characteristics of the transistor can be achieved.

Next, a seventh photolithography process is performed. A resist mask is formed, and an unnecessary portion is removed by etching to form thepixel electrode layer110.

Further, in this seventh photolithography process, thecapacitor wiring108 and thepixel electrode layer110 together form a storage capacitor with the use of thegate insulating layer102 and the protective insulatinglayer107 in a capacitor portion as a dielectric.

In addition, in this seventh photolithography process, thefirst terminal121 and thesecond terminal122 are covered with the resist mask, and transparent

conductive films

128 and129 are left in the terminal portions. The transparent

conductive films

128 and129 function as electrodes or wirings connected to an FPC. The transparentconductive film128 formed over thefirst terminal121 is a connection terminal electrode which functions as an input terminal of the gate wiring. The transparentconductive film129 formed over thesecond terminal122 is a connection terminal electrode which functions as an input terminal of the source wiring.

Then, the resist mask is removed, and a cross-sectional view at this stage is illustrated inFIG. 9B. Note that a top view at this stage corresponds toFIG. 13.

Further,FIGS. 14A and 14B are a cross-sectional view of a gate wiring terminal portion at this stage and a plan view thereof, respectively.FIG. 14A corresponds to a cross-sectional view taken along E1-E2 ofFIG. 14B. InFIG. 14A, a transparentconductive film155 formed over a protectiveinsulating film154 is a connection terminal electrode which functions as an input terminal. In the terminal portion inFIG. 14A, afirst terminal151 formed using the same material as the material of the gate wiring and aconnection electrode layer153 formed using the same material as the material of the source wiring overlap each other with agate insulating layer152 interposed therebetween and are electrically connected through the transparentconductive film155. Note that a portion where the transparentconductive film128 and thefirst terminal121 are in contact with each other as illustrated inFIG. 9B corresponds to a portion where the transparentconductive film155 and thefirst terminal151 are in contact with each other inFIG. 14A.

FIGS. 14C and 14D are respectively a cross-sectional view and a top view of a source wiring terminal portion which is different from that illustrated inFIG. 9B.FIG. 14C is a cross-sectional view taken along line F1-F2 ofFIG. 14D. InFIG. 14C, the transparentconductive film155 formed over the protectiveinsulating film154 is a connection terminal electrode which functions as an input terminal. In the terminal portion inFIG. 14C, anelectrode layer156 formed using the same material as the gate wiring is located under asecond terminal150, which is electrically connected to the source wiring, with thegate insulating layer152 interposed therebetween. Theelectrode layer156 is not electrically connected to thesecond terminal150, and a capacitor for preventing noise or static electricity can be formed when the potential of theelectrode layer156 is set to a potential different from that of thesecond terminal150, such as floating, GND, or 0 V. Thesecond terminal150 is electrically connected to the transparentconductive film155 through the protectiveinsulating film154.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, the third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. The number of each of the terminals may be any number, and the number of the terminals may be determined by a practitioner, as appropriate.

Through these seven photolithography processes, the storage capacitor and a pixel thin film transistor portion including thethin film transistor170 of a bottom-gate staggered thin film transistor can be completed using the seven photomasks. By disposing the thin film transistor and the storage capacitor in each pixel of a pixel portion in which pixels are arranged in a matrix, one of substrates for manufacturing an active matrix display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the case of manufacturing an active matrix liquid crystal display device, an active matrix substrate and a counter substrate provided with a counter electrode are bonded to each other with a liquid crystal layer interposed therebetween. Note that a common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. The fourth terminal is provided so that the common electrode is set to a fixed potential such as GND or 0 V.

A capacitor wiring is not provided, and a pixel electrode overlaps a gate wiring of an adjacent pixel with a protective insulating film and a gate insulating layer interposed therebetween to form a storage capacitor.

In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix are driven to form a display pattern on a screen. Specifically, voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, so that a liquid crystal layer provided between the pixel electrode and the counter electrode is optically modulated and this optical modulation is recognized as a display pattern by an observer.

In displaying moving images, a liquid crystal display device has a problem that a long response time of liquid crystal molecules themselves causes afterimages or blurring of moving images. In order to improve the moving-image characteristics of a liquid crystal display device, a driving method called black insertion is employed in which black is displayed on the whole screen every other frame period.

Alternatively, a driving method called double-frame rate driving may be employed in which the vertical synchronizing frequency is 1.5 times or more, preferably twice or more as high as a usual vertical synchronizing frequency, whereby the moving-image characteristics are improved.

Further alternatively, in order to improve the moving-image characteristics of a liquid crystal display device, a driving method may be employed, in which a plurality of LED (light-emitting diode) light sources or a plurality of EL light sources are used to form a surface light source as a backlight, and each light source of the surface light source is independently driven in a pulsed manner in one frame period. As the surface light source, three or more kinds of LEDs may be used and an LED emitting white light may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of LEDs can be synchronized with the timing at which a liquid crystal layer is optically modulated. According to this driving method, LEDs can be partly turned off; therefore, an effect of reducing power consumption can be obtained particularly in the case of displaying an image having a large part on which black is displayed.

By combining these driving methods, the display characteristics of a liquid crystal display device, such as moving-image characteristics, can be improved as compared to those of conventional liquid crystal display devices.

The n-channel transistor disclosed in this specification includes an oxide semiconductor film which is used for a channel formation region and has excellent dynamic characteristics; thus, it can be combined with these driving techniques.

In manufacturing a light-emitting display device, one electrode (also referred to as a cathode) of an organic light-emitting element is set to a low power supply potential such as GND or 0 V; thus, a terminal portion is provided with a fourth terminal for setting the cathode to a low power supply potential such as GND or 0 V. Also in manufacturing a light-emitting display device, a power supply line is provided in addition to a source wiring and a gate wiring. Accordingly, the terminal portion is provided with a fifth terminal electrically connected to the power supply line.

When a light-emitting display device is manufactured, a partition formed using an organic resin layer is provided between organic light-emitting elements in some cases. In that case, heat treatment performed on the organic resin layer can also serve as the heat treatment which increases the resistance of theoxide semiconductor layer103 so that improvement and less variation in electric characteristics of the transistor are achieved.

By the heat treatment, impurities such as moisture are reduced and the purity of the oxide semiconductor film is increased. Therefore, a semiconductor device including a highly reliable thin film transistor having favorable electric characteristics can be manufactured without using a special sputtering apparatus in which dew point in a film formation chamber is lowered or an ultrapure oxide semiconductor target.

The channel formation region in the oxide semiconductor layer is a high-resistance region; thus, electric characteristics of the thin film transistor are stabilized and increase in off current can be prevented. Therefore, a semiconductor device including a highly reliable thin film transistor having favorable electric characteristics can be provided.

Embodiment 4

A semiconductor device and a method for manufacturing the semiconductor device will be described with reference toFIG. 17. The same portion asEmbodiment 1 or a portion having similar function to that described inEmbodiment 1 and a process can be formed in a manner similar to that described inEmbodiment 1; therefore, repetitive description is omitted.

In athin film transistor462 illustrated inFIG. 17, aconductive layer409 is provided from the same layer as thesource wiring425 over theoxide insulating film407 so that theconductive layer409 overlaps thegate electrode layer401 and a channel region of theoxide semiconductor layer403.

FIG. 17 is a cross-sectional view of thethin film transistor462 included in a semiconductor device. Thethin film transistor462 is a bottom-gate thin film transistor and includes thegate electrode layer401, thegate insulating layer402, theoxide semiconductor layer403, thesource electrode layer405a, thedrain electrode layer405b, theoxide insulating film407, thesource wiring425, and theconductive layer409, over thesubstrate400 having an insulating surface. Theconductive layer409 is provided over theoxide insulating film407 so that theconductive layer409 overlaps thegate electrode layer401. Although not illustrated inFIG. 17, a gate wiring and a connection electrode layer are also provided in a manner similar to that ofEmbodiment 1.

Theconductive layer409 can be formed using a material and a method which are similar to those of thesource wiring425 described inEmbodiment 1. When a pixel electrode layer is provided, the conductive layer may be formed using a material and a method which are similar to those of the pixel electrode layer. In this embodiment, a low resistance conductive material such as aluminum or copper is used for theconductive layer409.

The potential of theconductive layer409 may be the same as or different from the potential of thegate electrode layer401, and can function as a second gate electrode layer. Further, theconductive layer409 may be in a floating state.

Theconductive layer409 is provided in a position that overlaps theoxide semiconductor layer403, whereby in a bias-temperature stress test (hereinafter, referred to as a BT test) for examining reliability of the thin film transistor, the amount of change in threshold voltage of thethin film transistor462 between before and after the BT test can be reduced. In particular, in a −BT test in which voltage applied to a gate is set at −20 V after the substrate temperature is raised to 150° C., variations in threshold voltage can be suppressed.

This embodiment can be freely combined withEmbodiment 1.

Embodiment 5

A semiconductor device and a method for manufacturing the semiconductor device will be described with reference toFIG. 18. The same portion asEmbodiment 1 or a portion having similar function to that described inEmbodiment 1 and a process can be formed in a manner similar to that described inEmbodiment 1; therefore, repetitive description is omitted.

Athin film transistor463 illustrated inFIG. 18 includes aconductive layer419 with theoxide insulating film407 and an insulatinglayer410 interposed between theconductive layer419 and thegate electrode layer401 so that theconductive layer419 overlaps thegate electrode layer401 and the channel region of theoxide semiconductor layer403.

FIG. 18 is a cross-sectional view of thethin film transistor463 included in a semiconductor device. Thethin film transistor463 is a bottom-gate thin film transistor, and includes thegate electrode layer401, thegate insulating layer402, theoxide semiconductor layer403, asource region404a, adrain region404b, thesource electrode layer405a, thedrain electrode layer405b, theoxide insulating film407, the insulatinglayer410, thesource wiring425, and theconductive layer419, over thesubstrate400 having an insulating surface. Theconductive layer419 is provided over the insulatinglayer410 so that theconductive layer419 overlaps thegate electrode layer401. Although not illustrated inFIG. 18, a gate wiring and a connection electrode layer are also provided in a manner similar to that ofEmbodiment 1.

In this embodiment, after an oxide semiconductor layer is formed over thegate insulating layer402, thesource region404aand thedrain region404bare formed over the oxide semiconductor layer. Then, thesource electrode layer405aand thedrain electrode layer405bare formed, and theoxide insulating film407 is formed. In a manner similar to that ofEmbodiment 1, after theoxide insulating film407 is formed, heat treatment for dehydration or dehydrogenation is performed, and theoxide semiconductor layer403 is formed. The heat treatment is performed at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate400 under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or under reduced pressure. Slow cooling is preferably performed under an inert gas atmosphere or an oxygen atmosphere after the heat treatment. The heat treatment allows plasma damage caused when theoxide insulating film407 is formed to be repaired. Then, a contact hole is formed in theoxide insulating film407, and thesource wiring425 which is connected to thesource electrode layer405ais formed.

In this embodiment, thesource region404aand thedrain region404bare each formed using a Zn—O-based polycrystalline film or a Zn-based microcrystalline film and are formed under a film formation condition which is different from that of theoxide semiconductor layer403 and each have lower resistance thanoxide semiconductor layer403. In this embodiment, thesource region404aand thedrain region404bare in a polycrystalline state or a microcrystalline state, and theoxide semiconductor layer403 is also in a polycrystalline state or a microcrystalline state. Theoxide semiconductor layer403 is crystallized with the second heat treatment, so that theoxide semiconductor layer403 can be in a polycrystalline state or a microcrystalline state.

In the thin film transistor described in this embodiment, the insulatinglayer410 functioning as a planarization film is stacked over theoxide insulating film407, an opening which reaches thedrain electrode layer405bis formed in theoxide insulating film407 and the insulatinglayer410, and a conductive film is formed in the opening formed in theoxide insulating film407 and the insulatinglayer410, and the conductive film is etched to have a predetermined shape, whereby theconductive layer419 and apixel electrode layer411 are formed. In such a process in which thepixel electrode layer411 is formed, theconductive layer419 can be formed. In this embodiment, as thepixel electrode layer411 and theconductive layer419, an indium oxide-tin oxide alloy including silicon oxide (In—Sn—O-based oxide containing silicon oxide) is used.

Alternatively, theconductive layer419 may be formed using a material and a manufacturing method which are similar to that of thegate electrode layer401, thesource electrode layer405a, thedrain electrode layer405b, and thesource wiring425.

The potential of theconductive layer419 may be the same as or different from that of thegate electrode layer401. Theconductive layer419 can function as a second gate electrode layer. Further, theconductive layer419 may be in a floating state.

When theconductive layer419 is provided so as to overlap theoxide semiconductor layer403, the threshold voltage of thethin film transistor463 can be controlled.

This embodiment can be freely combined withEmbodiment 1.

Embodiment 6

In this embodiment, an example of a channel stop typethin film transistor1430 will be described with reference toFIGS. 19A, 19B, and 19C.FIG. 19C is an example of a top view of a thin film transistor, a cross-sectional view taken along dotted line Z1-Z2 of which corresponds toFIG. 19B. An example is described in which gallium is not contained in an oxide semiconductor layer of thethin film transistor1430.

InFIG. 19A, agate electrode layer1401 is formed over asubstrate1400. Here, the gate electrode layer is preferably formed using a heat resistant conductive material such as that described inEmbodiment 1 so that the gate electrode layer can endure heat treatment to be performed in a later step. Next, agate insulating layer1402 covering thegate electrode layer1401 is formed. Then, anoxide semiconductor layer1403 is formed over thegate insulating layer1402.

In this embodiment, as theoxide semiconductor layer1403, a Sn—Zn—O-based oxide semiconductor formed using a sputtering method is used. When gallium is not used for the oxide semiconductor layer, theoxide semiconductor layer1403 can be formed without expensive target, so that cost can be reduced.

Next, a channelprotective layer1418 is formed in contact with theoxide semiconductor layer1403. The formation of the channelprotective layer1418 over theoxide semiconductor layer1403 can prevent damage (reduction in thickness or the like due to plasma or an etchant in etching) in a later step of forming asource region1406aand adrain region1406b. Therefore, reliability of thethin film transistor1430 can be improved.

Alternatively, after theoxide semiconductor layer1403 is formed, the channelprotective layer1418 can be successively formed without exposure to air. Successive treatment without exposure to air makes it possible to obtain each interface of stacked layers, which are not contaminated by atmospheric components or impurity elements floating in air, such as water or hydrocarbon. Therefore, variation in characteristics of the thin film transistor can be reduced.

The channelprotective layer1418 can be formed using an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, or silicon nitride oxide). As a method for forming the channelprotective layer1418, a vapor deposition method such as a plasma enhanced CVD method or a thermal CVD method, or a sputtering method can be used. After the formation of the channelprotective layer1418, the shape thereof is processed by etching. Here, the channelprotective layer1418 is formed in such a manner that a silicon oxide film is formed by a sputtering method and processed by etching using a mask formed by photolithography.

Next, thesource region1406aand thedrain region1406bare formed over the channelprotective layer1418 and theoxide semiconductor layer1403. In this embodiment, thesource region1406aand thedrain region1406bare each formed using a Zn—O-based microcrystalline film or a Zn—O-based polycrystalline film and are formed under a film formation condition which is different from that of theoxide semiconductor layer1403 and each have lower resistance.

Next, asource electrode layer1405ais formed over thesource region1406aand adrain electrode layer1405bis formed over thedrain region1406b, so that thethin film transistor1430 is formed (seeFIG. 19B). Thesource electrode layer1405aand thedrain electrode layer1405bcan be formed in a manner similar to that of thesource electrode layer405aand thedrain electrode layer405bdescribed inEmbodiment 1, and preferably formed using a heat resistant conductive material. At this time, aconnection electrode layer1420 used for a gate wiring to be formed at the same time.

When thesource region1406ais provided between theoxide semiconductor layer1403 and thesource electrode layer1405aand thedrain region1406bis provided between theoxide semiconductor layer1403 and thedrain electrode layer1405b, thesource electrode layer1405aand thedrain electrode layer1405bwhich are metal layers each can be favorably bonded to theoxide semiconductor layer1403, which leads to a thermally stable operation as compared to a Schottky junction. Moreover, since resistance is reduced, good mobility can be ensured even with high drain voltage.

This embodiment is not limited to the structure including thesource region1406aand thedrain region1406b; for example, a structure in which source and drain regions are not provided may be used.

Next, anoxide insulating film1407 is formed so as to cover thesource electrode layer1405a, thedrain electrode layer1405b, and the channelprotective layer1418. Theoxide insulating film1407 can be formed to a thickness of at least 1 nm or more using a method by which impurities such as water and hydrogen are prevented from being mixed to theoxide insulating film1407, such as a CVD method or a sputtering method, as appropriate. Theoxide insulating film1407 does not include impurities such as moisture, hydrogen ions, and OW and is formed using an inorganic insulating film which prevents entry of these from the outside. Specifically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. Further, a silicon nitride film or an aluminum nitride film may be stacked so as to be formed over and in contact with theoxide insulating film1407.

Next, for dehydration or dehydrogenation, heat treatment is performed under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or under reduced pressure. The heat treatment is performed at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate1400. After the heat treatment, slow cooling is preferably performed under an oxygen atmosphere. For example, slow cooling may be performed so that the substrate temperature is lowered by at least approximately 50° C. to 100° C. from the highest heating temperature. In this embodiment, theoxide semiconductor layer1403 is in a microcrystalline state or in a polycrystalline state. The heat treatment can reduce variation in electric characteristics of the thin film transistor.

Next, a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed in theoxide insulating film1407. First, part of theoxide insulating film1407 is removed by etching, whereby the first contact hole which reaches thesource electrode layer1405a, part of the second contact hole which reaches thegate electrode layer1401, and the third contact hole and the fourth contact hole which reach both end portions of theconnection electrode layer1420 are formed. Further, part of thegate insulating layer1402 is removed by etching, whereby the second contact hole which reaches thegate electrode layer1401 is formed.

Next, a second conductive film is formed over theoxide insulating film1407, and then asource wiring1425, afirst gate wiring1426, and asecond gate wiring1427 are formed over the oxide insulating film1407 (seeFIG. 19C). The second conductive film is preferably formed using a material which is similar to that of the second conductive film described inEmbodiment 1, and a low resistance conductive material such as aluminum or copper is preferably used. Thesource wiring1425 overlaps theconnection electrode layer1420 and is formed so as to be connected to thesource electrode layer1405athrough the first contact hole. Thefirst gate wiring1426 and thesecond gate wiring1427 are formed so as to sandwich thesource wiring1425. Here, thefirst gate wiring1426 is formed so as to be connected to thegate electrode layer1401 through the second contact hole and so as to be connected to theconnection electrode layer1420 through the third contact hole. Thesecond gate wiring1427 is formed so as to be connected to theconnection electrode layer1420 through the fourth contact hole. Accordingly, thefirst gate wiring1426 and thesecond gate wiring1427 are electrically connected to each other through theconnection electrode layer1420.

Through the above-described steps, thethin film transistor1430 can be formed.

Embodiment 7

A semiconductor device and a method for manufacturing the semiconductor device will be described with reference toFIGS. 20A and 20B. The same portion as Embodiment 6 or a portion having similar function to that described in Embodiment 6 and a process can be formed in a manner similar to that described in Embodiment 6; therefore, repetitive description is omitted.

In athin film transistor1431 illustrated inFIG. 20A, aconductive layer1409 is provided so as to overlap thegate electrode layer1401 with the channelprotective layer1418 and theoxide insulating film1407 interposed therebetween, and so as to overlap theoxide semiconductor layer1403 with the channelprotective layer1418 and theoxide insulating film1407 interposed therebetween.

FIG. 20A is a cross-sectional view of thethin film transistor1431 included in a semiconductor device. Thethin film transistor1431 is a bottom gate thin film transistor and includes thegate electrode layer1401, thegate insulating layer1402, theoxide semiconductor layer1403, thesource region1406a, thedrain region1406b, thesource electrode layer1405a, thedrain electrode layer1405b, theoxide insulating film1407, thesource wiring1425, and theconductive layer1409 over thesubstrate1400 having an insulating surface. Theconductive layer1409 is provided over theoxide insulating film1407 so that theconductive layer1409 overlaps thegate electrode layer1401. Although not illustrated inFIG. 20A, a gate wiring and a connection electrode layer are also provided in a manner similar to that ofEmbodiment 1.

In this embodiment, thesource region1406aand thedrain region1406bformed over the oxide semiconductor layer are each formed using a Zn—O-based microcrystalline film or a Zn—O-based polycrystalline film and are formed under a film formation condition which is different from that of theoxide semiconductor layer1403 and each are a lower resistance oxide semiconductor layer than theoxide semiconductor layer1403. Further, theoxide semiconductor layer1403 is in an amorphous state.

Theconductive layer1409 can be formed using a material and a method which are similar to those of thesource wiring1425 described inEmbodiment 1. When a pixel electrode layer is provided, the conductive layer may be formed using a material and a method which are similar to those of the pixel electrode layer. In this embodiment, a low resistance conductive material such as aluminum or copper is used for theconductive layer1409.

The potential of theconductive layer1409 may be the same as or different from the potential of thegate electrode layer1401 and can function as a second gate electrode layer. Further, theconductive layer1409 may be in a floating state.

In addition, theconductive layer1409 is provided in a position that overlaps theoxide semiconductor layer1403, whereby in a bias-temperature stress test (hereinafter, referred to as a BT test) for examining reliability of the thin film transistor, the amount of change in threshold voltage of thethin film transistor1431 between before and after the BT test can be reduced.

FIG. 20B illustrates an example which is partly different from that inFIG. 20A. The same portion as that described inFIG. 20A or a portion having similar function to that illustrated inFIG. 20A and a process can be formed in a manner similar to that described inFIG. 20A; therefore, repetitive description is omitted.

For example, in athin film transistor1432 illustrated inFIG. 20B, theconductive layer1409 is provided so as to overlap thegate electrode layer1401 with the channelprotective layer1418, theoxide insulating film1407, and an insulatinglayer1408 interposed therebetween, and so as to overlap a channel region of theoxide semiconductor layer1403 with the channelprotective layer1418, theoxide insulating film1407, and the insulatinglayer1408 interposed therebetween.

As for thethin film transistor1432, in a manner similar to that ofEmbodiment 1, after theoxide insulating film1407 is formed, heat treatment for dehydration or dehydrogenation is performed, and theoxide semiconductor layer1403 is formed. The heat treatment is performed at a temperature of higher than or equal to 200° C. and lower than or equal to 700° C., preferably, higher than or equal to 350° C. and lower than the strain point of thesubstrate1400 under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or under reduced pressure. Slow cooling is preferably performed under an inert gas atmosphere or an oxygen atmosphere after the heat treatment. Then, a contact hole is formed in theoxide insulating film1407, and thesource wiring1425 which is connected to thesource electrode layer1405ais formed.

InFIG. 20B, the insulatinglayer1408 which functions as a planarization film is stacked over theoxide insulating film1407.

InFIG. 20B, theoxide semiconductor layer1403 is directly in contact with thesource electrode layer1405aand thedrain electrode layer1405bwithout any source and drain regions.

In the structure illustrated inFIG. 20B, when theconductive layer1409 is provided so as to overlap theoxide semiconductor layer1403, in a BT test for examining reliability of the thin film transistor, the amount of change in threshold voltage of thethin film transistor1432 between before and after the BT test can be reduced.

Embodiment 8

In this embodiment, an example of a structure which is partly different from that ofEmbodiment 1 will be described with reference toFIG. 21. The same portion asEmbodiment 1 or a portion having similar function to that described inEmbodiment 1 and a process can be formed in a manner similar to that described inEmbodiment 1; therefore, repetitive description is omitted.

In this embodiment, after a first oxide semiconductor layer is formed, a second oxide semiconductor film which is used for a source region and a drain region (also referred to as an n⁺ layer or a buffer layer) of a thin film transistor is formed over the first oxide semiconductor layer, and then a conductive film is formed.

Next, the first oxide semiconductor layer, the second oxide semiconductor film, and the conductive film are selectively etched by an etching process, so that theoxide semiconductor layer403, thesource region404a, thedrain region404b, thesource electrode layer405a, and thedrain electrode layer405bare formed. Note that part of theoxide semiconductor layer403 is etched and a groove (depression) is provided.

Then, a silicon oxide film is formed as theoxide insulating film407 to be in contact with theoxide semiconductor layer403 by a sputtering method or a PCVD method. Theoxide insulating film407 which is in contact with the oxide semiconductor layer with reduced resistivity does not include impurities such as moisture, hydrogen ions, and OW and is formed using an inorganic insulating film which prevents entry of these from the outside. Specifically, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. Further, a silicon nitride film or an aluminum nitride film may be stacked over theoxide insulating film407.

As thesource region404aand thedrain region404bin the structure illustrated inFIG. 21, In—Ga—Zn—O-based non-single-crystal is used. Alternatively, an Al—Zn—O-based amorphous film can be used for thesource region404aand thedrain region404b. Further alternatively, an Al—Zn—O-based amorphous film containing nitrogen, that is, an Al—Zn—O—N-based amorphous film (also referred to as an AZON film) may be used for thesource region404aand thedrain region404b.

In addition, a source region may be provided between the oxide semiconductor layer and the source electrode layer, and a drain region may be provided between theoxide semiconductor layer403 and the drain electrode layer.

The second oxide semiconductor layer used for thesource region404aand thedrain region404bof thethin film transistor464 is preferably thinner than the firstoxide semiconductor layer403 used for a channel formation region and preferably has higher conductivity (electrical conductivity) than the firstoxide semiconductor layer403.

Further, the firstoxide semiconductor layer403 used for the channel formation region has an amorphous structure and the second oxide semiconductor layer used for the source region and the drain region includes a crystal grain (nanocrystal) in an amorphous structure in some cases. The crystal grain (nanocrystal) in the second oxide semiconductor layer used for the source region and the drain region has a diameter of 1 nm to 10 nm, typically, approximately 2 nm to 4 nm.

Embodiment 9

In this embodiment, an example will be described below in which at least part of a driver circuit and a thin film transistor to be disposed in a pixel portion are formed over one substrate.

The thin film transistor provided in the pixel portion is formed according to any ofEmbodiments 1 to 8. Further, the thin film transistor described in any ofEmbodiments 1 to 8 is an n-channel TFT. Thus, part of a driver circuit that can be formed using n-channel TFTs among driver circuits is formed over the same substrate as that for the thin film transistor in the pixel portion.

FIG. 22A illustrates an example of a block diagram of an active matrix display device, which is one example of the display device. Apixel portion5301, a first scanline driver circuit5302, a second scanline driver circuit5303, and a signalline driver circuit5304 are provided over asubstrate5300 of a display device. In thepixel portion5301, a plurality of signal lines extending from the signalline driver circuit5304 are provided, and a plurality of scan lines extending from the first scanline driver circuit5302 and the second scanline driver circuit5303 are provided. Note that in cross regions of the scan lines and the signal lines, pixels each having a display element are arranged in a matrix. Further, thesubstrate5300 of the display device is connected to a timing control circuit5305 (also referred to as a controller or a control IC) through a connection portion of a flexible printed circuit (FPC) or the like.

InFIG. 22A, the first scanline driver circuit5302, the second scanline driver circuit5303, and the signalline driver circuit5304 are formed over thesame substrate5300 as thepixel portion5301. Accordingly, the number of parts such as driver circuits provided outside is reduced, so that cost can decrease. Further, a connection portion used for extending a wiring when a driver circuit is provided outside thesubstrate5300 has a smaller number of connections, so that reliability and yield can be improved.

Note that thetiming control circuit5305 supplies a start signal for the first scan line driver circuit (GSP1) and a clock signal for the scan line driver circuit (GCK1) to the first scanline driver circuit5302, as an example. In addition, thetiming control circuit5305 supplies, for example, a start signal for the second scan line driver circuit (GSP2) (also referred to as a start pulse) and a clock signal for the scan line driver circuit (GCK2) to the second scanline driver circuit5303. A start signal for the signal line driver circuit (SSP), a clock signal for the signal line driver circuit (SCK), data for a video signal (DATA) (also simply referred to as a video signal), and a latch signal (LAT) are supplied to the signalline driver circuit5304. Note that each clock signal may be a plurality of clock signals with different phases, or may be supplied with an inverted clock signal (CKB). Note that either the first scanline driver circuit5302 or the second scanline driver circuit5303 can be omitted.

InFIG. 22B, a circuit with a low drive frequency (e.g., the first scanline driver circuit5302 and the second scan line driver circuit5303) is formed over thesame substrate5300 as thepixel portion5301, and the signalline driver circuit5304 is formed over another substrate which is different from the substrate provided with thepixel portion5301. This structure enables a driver circuit formed over thesubstrate5300 using a thin film transistor having low field effect mobility, compared with a transistor formed using a single crystal semiconductor. Accordingly, increase in the size of the display device, reduction in the number of steps, reduction in cost, improvement in yield, or the like can be achieved.

The thin film transistors described inEmbodiments 1 to 8 are n-channel TFTs. InFIGS. 23A and 23B, an example of a structure and operation of a signal line driver circuit formed using an n-channel TFT is described.

The signal line driver circuit includes ashift register5601 and aswitching circuit5602. Theswitching circuit5602 includes a plurality of switching circuits5602_1 to5602_N (N is a natural number). The switching circuits5602_1 to5602_N each include a plurality of thin film transistors5603_1 to5603_k(k is a natural number). An example in which the thin film transistors5603_1 to5603_kare n-channel TFTs is described.

A connection relation of the signal line driver circuit will be described by using the switching circuit5602_1 as an example. First terminals of the thin film transistors5603_1 to5603_kare connected to wirings5604_1 to5604_k, respectively. Second terminals of the thin film transistors5603_1 to5603_kare connected to signal wirings S1 to Sk, respectively. Gates of the thin film transistors5603_1 to5603_kare connected to a wiring5605_1.

Theshift register5601 has a function of sequentially outputting H level signals (also referred to as an H signal or a high power supply potential level) to the wirings5605_1 to5605_N, and a function of sequentially selecting the switching circuits5602_1 to5602_N.

The switching circuit5602_1 has a function of controlling conduction states between the wirings5604_1 to5604_kand the signal lines S1 to Sk (conduction between the first terminal and the second terminal), that is, a function of controlling whether the potentials of the wirings5604_1 to5604_kare supplied or not to the signal lines S1 to Sk. In this manner, the switching circuit5602_1 has a function of a selector. The thin film transistors5603_1 to5603_khave functions of controlling conduction states between the wiring5604_1 to5604_kand the signal lines S1 to Sk, that is, functions of supplying potentials of the wirings5604_1 to5604_kto the signal lines S1 to Sk, respectively. In this manner, each of the thin film transistors5603_1 to5603_kfunctions as a switch.

Note that the data for a video signal (DATA) is input to the wirings5604_1 to5604_k. The data for a video signal (DATA) is an analog signal corresponding to image data or an image signal in many cases.

Next, operation of the signal line driver circuit illustrated inFIG. 23A is described with reference to a timing chart inFIG. 23B. InFIG. 23B, an example of signals Sout_1 to Sout_N and signals Vdata_1 to Vdata_k is illustrated. The signals Sout_1 to Sout_N are examples of output signals of theshift register5601, and the signals Vdata_1 to Vdata_k are examples of signals which are input to the wirings5604_1 to5604_k, respectively. Note that one operation period of the signal line driver circuit corresponds to one gate selection period in a display device. For example, one gate selection period is divided into periods T1 to TN. The periods T1 to TN are periods for writing the data for a video signal (DATA) to pixels in a selected TOW.

In the periods T1 to TN, theshift register5601 sequentially outputs H level signals to the wirings5605_1 to5605_N. For example, in the period T1, theshift register5601 outputs a high level signal to the wiring5605_1. Then, the thin film transistors5603_1 to5603_kare turned on, so that the wirings5604_1 to5604_kand the signal lines S1 to Sk are brought into conduction. In this case, Data (S1) to Data (Sk) are input to the wirings5604_1 to5604_k, respectively. The Data (S1) to Data (Sk) are input to pixels in a selected row in a first to k-th columns through the thin film transistors5603_1 to5603_k, respectively. Thus, in the periods T1 to TN, the data for a video signal (DATA) is sequentially written to the pixels in the selected row by k columns.

By writing the data for a video signal (DATA) to pixels by a plurality of columns, the number of the data for a video signal (DATA) or the number of wirings can be reduced. Accordingly, the number of connections to external circuits can be reduced. Further, by writing the data for a video signal (DATA) to pixels of a plurality of columns each time, write time can be extended, and shortage of writing of the data for a video signal (DATA) can be prevented.

Note that for theshift register5601 and theswitching circuit5602, a circuit formed using the thin film transistor described inEmbodiments 1 to 8 can be used. In that case, all the transistors included in theshift register5601 can be only n-channel transistors or only p-channel transistors.

One mode of a shift register which is used for part of a scan line driver circuit and/or a signal line driver circuit will be described with reference toFIGS. 24A to 24C andFIGS. 25A and 25B.

The scan line driver circuit includes a shift register. Additionally, the scan line driver circuit may include a level shifter, a buffer, or the like in some cases. In the scan line driver circuit, when the clock signal (CK) and the start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Since the transistors in the pixels of one line have to be turned on all at once, a buffer which can feed a large amount of current is used.

Note that a clock signal (CK) is a signal which alternates between an H level signal and an L level signal (also referred to as an L signal or a low power supply potential level) at a regular interval. Here, the first to fourth clock signals (CK1) to (CK4) are sequentially delayed by a quarter of a cycle. In this embodiment, by using the first to fourth clock signals (CK1) to (CK4), control or the like of driving of a pulse output circuit is performed. Although the clock signal is used as a GCK or an SCK in accordance with a driver circuit to which the clock signal is input, the clock signal is described as a CK here.

Afirst input terminal21, asecond input terminal22, and athird input terminal23 are electrically connected to any of the first tofourth wirings11 to14. For example, inFIG. 24A, thefirst input terminal21 of the first pulse output circuit10_1 is electrically connected to thefirst wiring11, thesecond input terminal22 of the first pulse output circuit10_1 is electrically connected to thesecond wiring12, and thethird input terminal23 of the first pulse output circuit10_1 is electrically connected to thethird wiring13. In addition, thefirst input terminal21 of the second pulse output circuit10_2 is electrically connected to thesecond wiring12, thesecond input terminal22 of the second pulse output circuit10_2 is electrically connected to thethird wiring13, and thethird input terminal23 of the secondpulse output circuit102 is electrically connected to thefourth wiring14.

Each of the first to N-th pulse output circuits10_1 to10_N includes thefirst input terminal21, thesecond input terminal22, thethird input terminal23, afourth input terminal24, afifth input terminal25, afirst output terminal26, and a second output terminal27 (seeFIG. 24B). In the first pulse output circuit10_1, the first clock signal CK1 is input to thefirst input terminal21, the second clock signal CK2 is input to thesecond input terminal22, the third clock signal CK3 is input to thethird input terminal23, the start pulse is input to thefourth input terminal24, a subsequent stage signal OUT (3) is input to thefifth input terminal25, a first output signal OUT (1) (SR) is output from thefirst output terminal26, and a second output signal OUT (1) is output from thesecond output terminal27.

Next, an example of a specific circuit structure of the pulse output circuit illustrated inFIG. 24B will be described with reference toFIG. 24C.

InFIG. 24C, a connection portion of the gate electrode of thethird transistor33, the gate electrode of thetenth transistor40, and the second terminal of theninth transistor39 is a node A. A connection portion of the gate electrode of thesecond transistor32, the gate electrode of thefourth transistor34, the second terminal of thefifth transistor35, the second terminal of thesixth transistor36, the first terminal of theeighth transistor38, and the gate electrode of theeleventh transistor41 is a node B.

InFIG. 25A, signals which are input or output to/from the first to thefifth input terminals21 to25, thefirst output terminal26, and thesecond output terminal27 when the pulse output circuit illustrated inFIG. 24C is applied to the first pulse output circuit10_1 are illustrated.

Specifically, the first clock signal CK1 is input to thefirst input terminal21, the second clock signal CK2 is input to thesecond input terminal22, the third clock signal CK3 is input to thethird input terminal23, the start pulse is input to thefourth input terminal24, the subsequent stage signal OUT (3) is input to thefifth input terminal25, the first output signal OUT (1) (SR) is output from thefirst output terminal26, and the second output signal OUT (1) is output from thesecond output terminal27.

Note that a thin film transistor is an element having at least three terminals of a gate, a drain, and a source. The thin film transistor includes a semiconductor whose channel region is formed at a region that overlaps the gate, and the potential of the gate is controlled, whereby current which flows between the drain and the source through the channel region can be controlled. Here, since the source and the drain of the thin film transistor may interchange depending on the structure, the operating condition, and the like of the thin film transistor, it is difficult to define which is a source or a drain. Therefore, a region functioning as a source and a drain is not called the source or the drain in some cases. In such a case, for example, one of the source and the drain may be referred to as a first terminal and the other thereof may be referred to as a second terminal.

Note that inFIGS. 24C and 25A, a capacitor may be provided in order to perform bootstrap operation effected by the node A in a floating state. A capacitor whose one electrode is electrically connected to the node B may be provided in order to hold the potential of the node B.

Here, a timing chart of a shift register in which a plurality of pulse output circuits illustrated inFIG. 25A are provided is illustrated inFIG. 25B. Note that inFIG. 25B, when the shift register is a scan line driver circuit, aperiod61 is a vertical retrace period and aperiod62 is a gate selection period.

Note that as illustrated inFIG. 25A, when theninth transistor39 having the gate to which the second power supply potential VCC is applied is provided, there are the following advantages before or after the bootstrap operation.

Without theninth transistor39 whose gate electrode is supplied with the second power supply potential VCC, when a potential of the node A is raised by bootstrap operation, a potential of a source which is the second terminal of thefirst transistor31 increases to a value higher than the first power supply potential VDD. Then, the source of thefirst transistor31 is switched to the first terminal side, that is, thepower supply line51 side. Therefore, in thefirst transistor31, a large amount of bias voltage is applied and thus great stress is applied between a gate and a source and between the gate and a drain, which can cause deterioration in the transistor. When theninth transistor39 is provided whose gate electrode is supplied with the second power supply potential VCC, a potential of the node A is raised by bootstrap operation, but at the same time, an increase in a potential of the second terminal of thefirst transistor31 can be prevented. In other words, with theninth transistor39, negative bias voltage applied between a gate and a source of thefirst transistor31 can be reduced. Accordingly, with a circuit structure in this embodiment, negative bias voltage applied between a gate and a source of thefirst transistor31 can be reduced, so that deterioration in thefirst transistor31, which is due to stress, can further be restrained.

Note that theninth transistor39 may be provided in any places where theninth transistor39 is connected between the second terminal of thefirst transistor31 and the gate of thethird transistor33 through the first terminal and the second terminal. When a shift register includes a plurality of pulse output circuits in this embodiment, theninth transistor39 may be omitted in a signal line driver circuit which has a larger number of stages than a scan line driver circuit, and there is an advantage of decreasing the number of transistors.

Note that when oxide semiconductors are used for semiconductor layers for the first to thethirteenth transistors31 to43, the off current of the thin film transistors can be reduced, the on current and the field effect mobility can be increased, and the degree of deterioration can be reduced, whereby malfunction in a circuit can decrease. Compared with a transistor formed using an oxide semiconductor and a transistor formed using amorphous silicon, the degree of deterioration of the transistor due to the application of a high potential to the gate electrode is low. Therefore, similar operation can be obtained even when the first power supply potential VDD is supplied to the power supply line which supplies the second power supply potential VCC, and the number of power supply lines which are led between circuits can decrease; therefore, the size of the circuit can be reduced

In this way, in a period during which the potential of thefirst output terminal26 and the potential of thesecond output terminal27 are each held at an L level, an H level signal is regularly supplied to the node B; therefore, malfunction of the pulse output circuit can be suppressed.

Embodiment 10

A thin film transistor is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor in a pixel portion and further in a driver circuit. Further, part or whole of the driver circuit can be formed over the same substrate as the pixel portion, using the thin film transistor, whereby a system-on-panel can be obtained.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. Furthermore, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

In addition, the display device includes a panel in which a display element is sealed, and a module in which an IC and the like including a controller are mounted on the panel. Furthermore, an element substrate, which corresponds to an embodiment before the display element is completed in a manufacturing process of the display device, is provided with a means for supplying current to the display element in each of a plurality of pixels. The element substrate may be specifically in a state where only a pixel electrode of a display element is formed or in a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form a pixel electrode, and can have any mode.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, the display device includes the following modules in its category: a module including a connector such as a flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP) attached; a module having a TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.

The appearance and a cross section of a liquid crystal display panel, which is an embodiment of a semiconductor device, will be described with reference toFIGS. 26A to 26C.FIGS. 26A and 26B are each a plan view of a panel in which highly reliable

thin film transistors

4010 and4011 each including the oxide semiconductor layer described in any ofEmbodiments 1 to 8, and aliquid crystal element4013 are sealed between afirst substrate4001 and asecond substrate4006 with asealant4005.FIG. 26C is a cross-sectional view taken along line M-N ofFIGS. 26A and 26B.

Thesealant4005 is provided so as to surround apixel portion4002 and a scanline driver circuit4004 which are provided over thefirst substrate4001. Thesecond substrate4006 is provided over thepixel portion4002 and the scanline driver circuit4004. Therefore, thepixel portion4002 and the scanline driver circuit4004 are sealed together with aliquid crystal layer4008, by thefirst substrate4001, thesealant4005, and thesecond substrate4006. A signalline driver circuit4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by thesealant4005 over thefirst substrate4001.

Note that there is no particular limitation on the connection method of a driver circuit which is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used.FIG. 26A illustrates an example in which the signalline driver circuit4003 is mounted by a COG method andFIG. 26B illustrates an example in which the signalline driver circuit4003 is mounted by a TAB method.

Each of thepixel portion4002 and the scanline driver circuit4004 which are provided over thefirst substrate4001 includes a plurality of thin film transistors.FIG. 26C illustrates thethin film transistor4010 included in thepixel portion4002 and thethin film transistor4011 included in the scanline driver circuit4004. Over the

thin film transistors

4010 and4011, insulating

layers

4020 and4021 are provided.

Any of the highly reliable thin film transistors including the oxide semiconductor layer which is described in any ofEmbodiments 1 to 8 can be used as the

thin film transistors

4010 and4011. In this embodiment, the

thin film transistors

4010 and4011 are n-channel thin film transistors.

Apixel electrode layer4030 included in theliquid crystal element4013 is electrically connected to thethin film transistor4010. Acounter electrode layer4031 of theliquid crystal element4013 is provided for thesecond substrate4006. A portion where thepixel electrode layer4030, thecounter electrode layer4031, and theliquid crystal layer4008 overlap one another corresponds to theliquid crystal element4013. Note that thepixel electrode layer4030 and thecounter electrode layer4031 are provided with an insulatinglayer4032 and an insulatinglayer4033 respectively which each function as an alignment film, and theliquid crystal layer4008 is sandwiched between thepixel electrode layer4030 and thecounter electrode layer4031 with the insulating

layers

4032 and4033 interposed therebetween.

Note that thefirst substrate4001 and thesecond substrate4006 can be formed using glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Aspacer4035 is a columnar spacer obtained by selective etching of an insulating film and is provided in order to control the distance (a cell gap) between thepixel electrode layer4030 and thecounter electrode layer4031. Alternatively, a spherical spacer may also be used. In addition, thecounter electrode layer4031 is electrically connected to a common potential line formed over the same substrate as thethin film transistor4010. With the use of a common connection portion, thecounter electrode layer4031 and the common potential line can be electrically connected to each other by conductive particles arranged between a pair of substrates. Note that the conductive particles are included in thesealant4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is generated within an only narrow range of temperature, a liquid crystal composition containing a chiral agent at 5 wt % or more so as to improve the temperature range is used for theliquid crystal layer4008. The liquid crystal composition which includes a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, has optical isotropy, which makes the alignment process unneeded, and has a small viewing angle dependence.

An embodiment of the present invention can also be applied to a reflective liquid crystal display device or a semi-transmissive liquid crystal display device, in addition to a transmissive liquid crystal display device.

An example of the liquid crystal display device is described in which a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer (color filter) and an electrode layer used for a display element are provided on the inner surface of the substrate; however, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing process. Further, a light-blocking film serving as a black matrix may be provided.

In order to reduce surface unevenness of the thin film transistor and to improve reliability of the thin film transistor, the thin film transistor obtained in any of the above embodiments is covered with the insulating layers (the insulatinglayer4020 and the insulating layer4021) serving as a protective film or a planarizing insulating film. Note that the protective film is provided to prevent entry of contaminant impurities such as organic substance, metal, or moisture existing in air and is preferably a dense film. The protective film may be formed with a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, and/or an aluminum nitride oxide film by a sputtering method. Although an example in which the protective film is formed by a sputtering method is described in this embodiment, an embodiment of the present invention is not limited to this method and a variety of methods may be employed.

In this embodiment, the insulatinglayer4020 having a stacked-layer structure is formed as a protective film. Here, as a first layer of the insulatinglayer4020, a silicon oxide film is formed by a sputtering method. The use of a silicon oxide film as a protective film has an effect of preventing hillock of an aluminum film used for the source and drain electrode layers.

As a second layer of the protective film, an insulating layer is formed. Here, as a second layer of the insulatinglayer4020, a silicon nitride film is formed by a sputtering method. The use of the silicon nitride film as the protective film can prevent mobile ions such as sodium ions from entering a semiconductor region, thereby suppressing variations in electric properties of the TFT.

Further, heat treatment (at 300° C. or lower) may be performed under a nitrogen atmosphere or an air atmosphere after the formation of the protective film.

The insulatinglayer4021 is formed as the planarizing insulating film. As the insulatinglayer4021, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. Note that the insulatinglayer4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include as a substituent an organic group (e.g., an alkyl group or an aryl group) or a fluoro group. In addition, the organic group may include a fluoro group.

There is no particular limitation on the formation method of the insulatinglayer4021, and the following method can be employed depending on the material: a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (e.g., an ink-jet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. The baking step of the insulatinglayer4021 also serves as annealing of the semiconductor layer, whereby a semiconductor device can be manufactured efficiently.

Thepixel electrode layer4030 and thecounter electrode layer4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

Conductive compositions including a conductive high molecule (also referred to as a conductive polymer) can be used for thepixel electrode layer4030 and thecounter electrode layer4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10000 ohms per square and a light transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given.

Further, a variety of signals and potentials are supplied to the signalline driver circuit4003 which is formed separately, the scanline driver circuit4004, or thepixel portion4002 from anFPC4018.

Aconnection terminal electrode4015 is formed using the same conductive film as thepixel electrode layer4030 included in theliquid crystal element4013. Aterminal electrode4016 is formed using the same conductive film as the source and drain electrode layers included in thethin film transistor4011.

Theconnection terminal electrode4015 is electrically connected to a terminal included in theFPC4018 via an anisotropicconductive film4019.

FIGS. 26A to 26C illustrate an example in which the signalline driver circuit4003 is formed separately and mounted on thefirst substrate4001; however, an embodiment of the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 27 illustrates an example in which a liquid crystal display module is formed as a semiconductor device using aTFT substrate2600 which is manufactured according to the manufacturing method disclosed in this specification.

FIG. 27 illustrates an example of a liquid crystal display module, in which theTFT substrate2600 and acounter substrate2601 are fixed to each other with asealant2602, and apixel portion2603 including a TFT or the like, adisplay element2604 including a liquid crystal layer, and acoloring layer2605, are provided between the substrates to form a display region. Thecoloring layer2605 is necessary to perform color display. In the RGB system, respective coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. Apolarizing plate2606 is provided on the outer side of thecounter substrate2601, while apolarizing plate2607 and adiffusion plate2613 are provided on the outer side of theTFT substrate2600. A light source includes acold cathode tube2610 and areflective plate2611, and acircuit substrate2612 is connected to awiring circuit portion2608 of theTFT substrate2600 by aflexible wiring board2609 and includes an external circuit such as a control circuit or a power supply circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

The liquid crystal display module can employ a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like.

Through this process, a highly reliable liquid crystal display panel as a semiconductor device can be manufactured.

Embodiment 11

An example of electronic paper will be described as a semiconductor device.

The semiconductor device can be used for electronic paper in which electronic ink is driven by an element electrically connected to a switching element. The electronic paper is also referred to as an electrophoretic display device (an electrophoretic display) and is advantageous in that it has the same level of readability as plain paper, it has lower power consumption than other display devices, and it can be made thin and lightweight.

Electrophoretic displays can have various modes. Electrophoretic displays contain a plurality of microcapsules dispersed in a solvent or a solute, each microcapsule containing first particles which are positively charged and second particles which are negatively charged. By applying an electric field to the microcapsules, the particles in the microcapsules move in opposite directions to each other and only the color of the particles gathering on one side is displayed. Note that the first particles and the second particles each contain dye and do not move without an electric field. Moreover, the first particles and the second particles have different colors (which may be colorless).

Thus, an electrophoretic display is a display that utilizes a so-called dielectrophoretic effect by which a substance having a high dielectric constant moves to a high-electric field region. An electrophoretic display device does not need to use a polarizing plate which is required in a liquid crystal display device.

A solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, by using a color filter or particles that have a pigment, color display can also be achieved.

In addition, when a plurality of the above microcapsules are arranged as appropriate over an active matrix substrate so as to be interposed between two electrodes, an active matrix display device can be completed, and display can be performed by application of an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistor described in any ofEmbodiments 1 to 8 can be used.

Note that the first particles and the second particles in the microcapsules may each be formed of a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophoretic material, or formed of a composite material of any of these.

FIG. 28 illustrates active matrix electronic paper as an example of a semiconductor device. Athin film transistor581 used for the semiconductor device can be formed in a manner similar to the thin film transistor described in any ofEmbodiments 1 to 8, which is a highly reliable thin film transistor including an oxide semiconductor layer.

The electronic paper inFIG. 28 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

Thethin film transistor581 formed over asubstrate580 is a bottom gate thin film transistor and is covered with an insulatingfilm583 which is in contact with a semiconductor layer. A source electrode layer or a drain electrode layer of thethin film transistor581 is in contact with afirst electrode layer587 in an opening formed in an insulatinglayer585, whereby thethin film transistor581 is electrically connected to thefirst electrode layer587. Between thefirst electrode layer587 and asecond electrode layer588 on asubstrate596,spherical particles589 are provided. Eachspherical particle589 includes ablack region590aand awhite region590b, and acavity594 filled with liquid around theblack region590aand thewhite region590b. The circumference of thespherical particle589 is filled with afiller595 such as a resin or the like. Thefirst electrode layer587 corresponds to a pixel electrode, and thesecond electrode layer588 corresponds to a common electrode. Thesecond electrode layer588 is electrically connected to a common potential line provided over thesame substrate580 as thethin film transistor581. With the use of a common connection portion, thesecond electrode layer588 can be electrically connected to the common potential line via conductive particles provided between thesubstrate580 and thesubstrate596.

Further, instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of approximately 10 μm to 200 μm in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is generally called electronic paper. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

Through this process, a highly reliable electronic paper as a semiconductor device can be manufactured.

Embodiment 12

An example of a light-emitting display device will be described as a semiconductor device. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Based on this mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that an example of an organic EL element as a light-emitting element is described here.

FIG. 29 illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device.

A structure and operation of a pixel to which digital time grayscale driving can be applied are described. Here, one pixel includes two n-channel transistors each of which includes an oxide semiconductor layer as a channel formation region.

The second electrode (common electrode6408) of the light-emittingelement6404 is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential<a high power supply potential with reference to the high power supply potential that is set to thepower supply line6407. As the low power supply potential, GND, 0 V, or the like may be employed, for example. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emittingelement6404 and current is supplied to the light-emittingelement6404, so that the light-emittingelement6404 emits light. Here, in order to make the light-emittingelement6404 emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is forward threshold voltage or higher of the light-emittingelement6404.

Gate capacitance of the driver transistor for a light-emittingelement6402 may be used as a substitute for thecapacitor6403, so that thecapacitor6403 can be omitted. The gate capacitance of the driver transistor for a light-emittingelement6402 may be formed between a channel region and a gate electrode.

In the case of a voltage-input voltage driving method, a video signal is input to the gate of the driver transistor for a light-emittingelement6402 so that the driver transistor for a light-emittingelement6402 is in either of two states of being sufficiently turned on and turned off. That is, the driver transistor for a light-emittingelement6402 operates in a linear region. Since the driver transistor for a light-emittingelement6402 operates in a linear region, voltage higher than the voltage of thepower supply line6407 is applied to the gate of the driver transistor for a light-emittingelement6402. Note that voltage higher than or equal to (voltage of the power supply line+Vth of the driver transistor for a light-emitting element6402) is applied to thesignal line6405.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel structure as that inFIG. 29 can be used by changing signal input.

Note that an embodiment of the present invention is not limited to the pixel structure illustrated inFIG. 29. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel illustrated inFIG. 29.

Next, structures of the light-emitting element will be described with reference toFIGS. 30A to 30C. A cross-sectional structure of a pixel is described by taking an n-channel driver TFT for a light-emitting element as an example. Driver TFTs for a light-emitting

element

7001,7011, and7021 used in semiconductor devices illustrated inFIGS. 30A, 30B, and 30C, respectively, can be formed in a manner similar to that of the thin film transistor which is described in any ofEmbodiments 1 to 8 and arranged in a pixel and are highly reliable thin film transistors each including an oxide semiconductor layer.

In order to extract light emitted from the light-emitting element, at least one of an anode and a cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure, in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure, in which light emission is extracted through the surface on the substrate side; or a dual emission structure, in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a top emission structure will be described with reference toFIG. 30A.

FIG. 30A is a cross-sectional view of a pixel in the case where the driver TFT for a light-emittingelement7001 is of an n type and light is emitted from a light-emittingelement7002 to ananode7005 side. InFIG. 30A, acathode7003 of the light-emittingelement7002 is electrically connected to the driver TFT for a light-emittingelement7001, and a light-emittinglayer7004 and theanode7005 are stacked in that order over thecathode7003. Thecathode7003 can be formed using a variety of conductive materials as long as they have a low work function and reflect light. For example, Ca, Al, MgAg, AlLi, or the like is desirably used. The light-emittinglayer7004 may be formed using a single layer or a plurality of layers stacked. When the light-emittinglayer7004 is formed using a plurality of layers, the light-emittinglayer7004 is formed by stacking an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer in that order over thecathode7003. It is not necessary to form all of these layers. Theanode7005 is made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

Apartition7009 is provided so as to cover part of thecathode7003. Thepartition7009 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that thepartition7009 be formed using a photosensitive resin material so that a side surface of thepartition7009 is formed as an inclined surface with continuous curvature. When thepartition7009 is formed using a photosensitive resin material, a step of forming a resist mask can be omitted.

The light-emittingelement7002 corresponds to a region where the light-emittinglayer7004 is sandwiched between thecathode7003 and theanode7005. In the case of the pixel illustrated inFIG. 30A, light is emitted from the light-emittingelement7002 to theanode7005 side as indicated by an arrow.

Next, a light-emitting element having a bottom emission structure will be described with reference toFIG. 30B.FIG. 30B is a cross-sectional view of a pixel in the case where the driver TFT for a light-emittingelement7011 is an n-channel transistor and light is emitted from a light-emittingelement7012 to acathode7013 side. InFIG. 30B, thecathode7013 of the light-emittingelement7012 is formed over a light-transmittingconductive film7017 that is electrically connected to the driver TFT for a light-emittingelement7011, and a light-emittinglayer7014 and ananode7015 are stacked in that order over thecathode7013. A light-blockingfilm7016 for reflecting or blocking light may be formed so as to cover theanode7015 when theanode7015 has a light-transmitting property. For thecathode7013, various materials can be used as in the case ofFIG. 30A as long as they are conductive materials having a low work function. Thecathode7013 is formed to a thickness that can transmit light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as thecathode7013. Similar to the case ofFIG. 30A, the light-emittinglayer7014 may be formed using either a single layer or a plurality of layers stacked. Theanode7015 is not required to transmit light, but can be formed using a conductive material having a light-transmitting property with respect to visible light as in the case ofFIG. 30A. As the light-blockingfilm7016, a metal or the like that reflects light can be used; however, it is not limited to a metal film. For example, a resin or the like to which black pigments are added can also be used.

Apartition7019 is provided so as to cover part of theconductive film7017. Thepartition7019 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that thepartition7019 be formed using a photosensitive resin material so that a side surface of thepartition7019 is formed as an inclined surface with continuous curvature. When thepartition7019 is formed using a photosensitive resin material, a step of forming a resist mask can be omitted.

The light-emittingelement7012 corresponds to a region where the light-emittinglayer7014 is sandwiched between thecathode7013 and theanode7015. In the case of the pixel illustrated inFIG. 30B, light is emitted from the light-emittingelement7012 to thecathode7013 side as indicated by an arrow.

Next, a light-emitting element having a dual emission structure will be described with reference toFIG. 30C. InFIG. 30C, acathode7023 of a light-emittingelement7022 is formed over a light-transmittingconductive film7027 which is electrically connected to the driver TFT for a light-emittingelement7021, and a light-emittinglayer7024 and ananode7025 are sequentially stacked over thecathode7023. For thecathode7023, various materials can be used as in the case ofFIG. 30A as long as they are conductive materials having a low work function. Thecathode7023 is formed to a thickness that can transmit light. For example, a film of Al having a thickness of 20 nm can be used as thecathode7023. As inFIG. 30A, the light-emittinglayer7024 may be formed using either a single layer or a plurality of layers stacked. In a manner similar toFIG. 30A, theanode7025 can be formed using a light-transmitting conductive material.

Apartition7029 is provided so as to cover part of theconductive film7027. Thepartition7029 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that thepartition7029 be formed using a photosensitive resin material so that a side surface of thepartition7029 is formed as an inclined surface with continuous curvature. When thepartition7029 is formed using a photosensitive resin material, a step of forming a resist mask can be omitted.

The light-emittingelement7022 corresponds to a region where thecathode7023, the light-emittinglayer7024, and theanode7025 overlap one another. In the case of the pixel illustrated inFIG. 30C, light is emitted from the light-emittingelement7022 to both theanode7025 side and thecathode7023 side as indicated by arrows.

Although the organic EL elements are described here as the light-emitting elements, an inorganic EL element can also be provided as a light-emitting element.

Note that the example is described in which a thin film transistor (a driver TFT for a light-emitting element) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driver TFT for a light-emitting element and the light-emitting element.

Note that the structure of the semiconductor device is not limited to those illustrated inFIGS. 30A to 30C and can be modified in various ways based on techniques disclosed in this specification.

Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) which corresponds to one mode of a semiconductor device will be described with reference toFIGS. 31A and 31B.FIG. 31A is a top view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed between the first substrate and a second substrate with a sealant.FIG. 31B is a cross-sectional view taken along line H-I ofFIG. 31A.

Asealant4505 is provided so as to surround apixel portion4502, signal

line driver circuits

4503aand4503b, and scan

line driver circuits

4504aand4504bwhich are provided over afirst substrate4501. In addition, asecond substrate4506 is provided over thepixel portion4502, the signal

line driver circuits

4503aand4503b, and the scan

line driver circuits

4504aand4504b. Accordingly, thepixel portion4502, the signal

line driver circuits

4503aand4503b, and the scan

line driver circuits

4504aand4504bare sealed together with afiller4507, by thefirst substrate4501, thesealant4505, and thesecond substrate4506. It is preferable that a panel be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air, in this manner.

Thepixel portion4502, the signal

line driver circuits

4503aand4503b, and the scan

line driver circuits

4504aand4504bformed over thefirst substrate4501 each include a plurality of thin film transistors, and athin film transistor4510 included in thepixel portion4502 and athin film transistor4509 included in the signalline driver circuit4503aare illustrated as an example inFIG. 31B.

For the

thin film transistors

4509 and4510, the highly reliable thin film transistor including the oxide semiconductor layer described in any ofEmbodiments 1 to 8 can be employed. The

thin film transistors

4509 and4510 are n-channel thin film transistors.

Moreover,reference numeral4511 denotes a light-emitting element. Afirst electrode layer4517 which is a pixel electrode included in the light-emittingelement4511 is electrically connected to a source electrode layer or a drain electrode layer of thethin film transistor4510. Note that the structure of the light-emittingelement4511 is, but not limited to, the stacked structure which includes thefirst electrode layer4517, anelectroluminescent layer4512, and asecond electrode layer4513. The structure of the light-emittingelement4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emittingelement4511, or the like.

Apartition4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that thepartition4520 be formed using a photosensitive material and an opening be formed over thefirst electrode layer4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

Theelectroluminescent layer4512 may be formed with a single layer or a plurality of layers stacked.

A protective film may be formed over thesecond electrode layer4513 and thepartition4520 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, and the like into the light-emittingelement4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal

line driver circuits

4503aand4503b, the scan

line driver circuits

4504aand4504b, or thepixel portion4502 from

FPCs

4518aand4518b.

Aconnection terminal electrode4515 is formed using the same conductive film as thefirst electrode layer4517 included in the light-emittingelement4511, and aterminal electrode4516 is formed using the same conductive film as the source and drain electrode layers included in thethin film transistor4509.

Theconnection terminal electrode4515 is electrically connected to a terminal included in theFPC4518avia an anisotropicconductive film4519.

As thesecond substrate4506 located in the direction in which light is extracted from the light-emittingelement4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used for thesecond substrate4506.

As thefiller4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, polyvinyl chloride (PVC), acrylic, polyimide, an epoxy resin, a silicone resin, polyvinyl butyral (PVB), or ethylene vinyl acetate (EVA) can be used. For example, nitrogen may be used for thefiller4507.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal

line driver circuits

4503aand4503band the scan

line driver circuits

4504aand4504bmay be mounted as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared. Alternatively, only the signal line driver circuits or part thereof, or only the scan line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated inFIGS. 31A and 31B.

Through this process, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

Embodiment 13

A semiconductor device disclosed in this specification can be applied to electronic paper. Electronic paper can be used for electronic devices of a variety of fields as long as they can display data. For example, electronic paper can be applied to an e-book reader (electronic book), a poster, an advertisement in a vehicle such as a train, or displays of various cards such as a credit card. An example of the electronic device is illustrated inFIG. 32.

FIG. 32 illustrates an example of ane-book reader2700. For example, thee-book reader2700 includes two housings, ahousing2701 and ahousing2703. Thehousing2701 and thehousing2703 are combined with ahinge2711 so that thee-book reader2700 can be opened and closed with thehinge2711 as an axis. With such a structure, thee-book reader2700 can operate like a paper book.

Adisplay portion2705 and adisplay portion2707 are incorporated in thehousing2701 and thehousing2703, respectively. Thedisplay portion2705 and thedisplay portion2707 may display one image or different images. In the case where thedisplay portion2705 and thedisplay portion2707 display different images, for example, a display portion on the right side (thedisplay portion2705 inFIG. 32) can display text and a display portion on the left side (thedisplay portion2707 inFIG. 32) can display graphics.

FIG. 32 illustrates an example in which thehousing2701 is provided with an operation portion and the like. For example, thehousing2701 is provided with apower switch2721, anoperation key2723, aspeaker2725, and the like. With theoperation key2723, pages can be turned. Note that a keyboard, a pointing device, and the like may be provided on the same surface as the display portion of the housing. Furthermore, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Moreover, thee-book reader2700 may have a function of an electronic dictionary.

Thee-book reader2700 may have a structure capable of wirelessly transmitting and receiving data. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.

Embodiment 14

A semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Examples of electronic devices are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a cellular phone handset (also referred to as a cellular phone or a cellular phone device), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.

FIG. 33A illustrates an example of atelevision set9600. In thetelevision set9600, adisplay portion9603 is incorporated in ahousing9601. Thedisplay portion9603 can display images. Here, thehousing9601 is supported by astand9605.

Thetelevision set9600 can be operated with an operation switch of thehousing9601 or a separateremote controller9610. Channels and volume can be controlled with anoperation key9609 of theremote controller9610 so that an image displayed on thedisplay portion9603 can be controlled. Furthermore, theremote controller9610 may be provided with adisplay portion9607 for displaying data output from theremote controller9610.

Note that thetelevision set9600 is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.

FIG. 33B illustrates an example of adigital photo frame9700. For example, in thedigital photo frame9700, adisplay portion9703 is incorporated in ahousing9701. Thedisplay portion9703 can display a variety of images. For example, thedisplay portion9703 can display data of an image taken with a digital camera or the like and function as a normal photo frame.

Note that thedigital photo frame9700 is provided with an operation portion, an external connection portion (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although these components may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of thedigital photo frame9700. For example, a memory storing data of an image taken with a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and then displayed on thedisplay portion9703.

Thedigital photo frame9700 may be configured to transmit and receive data wirelessly. The structure may be employed in which desired image data is transferred wirelessly to be displayed.

FIG. 34A is a portable amusement machine including two housings, ahousing9881 and ahousing9891. The

housings

9881 and9891 are connected with aconnection portion9893 so as to be opened and closed. Adisplay portion9882 and adisplay portion9883 are incorporated in thehousing9881 and thehousing9891, respectively. In addition, the portable amusement machine illustrated inFIG. 34A includes aspeaker portion9884, a recordingmedium insert portion9886, anLED lamp9890, an input means (anoperation key9885, aconnection terminal9887, a sensor9888 (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared rays), or a microphone9889), and the like. It is needless to say that the structure of the portable amusement machine is not limited to the above and other structures provided with at least a semiconductor device disclosed in this specification can be employed. The portable amusement machine may include other accessory equipment, as appropriate. The portable amusement machine illustrated inFIG. 34A has a function of reading a program or data stored in a recording medium to display it on the display portion, and a function of sharing information with another portable amusement machine by wireless communication. The portable amusement machine illustrated inFIG. 34A can have various functions without limitation to the above.

FIG. 34B illustrates an example of aslot machine9900 which is an amusement machine with a big size. In theslot machine9900, adisplay portion9903 is incorporated in ahousing9901. In addition, theslot machine9900 includes an operation means such as a start lever or a stop switch, a coin slot, a speaker, and the like. It is needless to say that the structure of theslot machine9900 is not limited to the above and other structures provided with at least a semiconductor device disclosed in this specification may be employed. Theslot machine9900 may include other accessory equipment, as appropriate.

FIG. 35A is a perspective view illustrating an example of a portable computer.

In the portable computer ofFIG. 35A, atop housing9301 having adisplay portion9303 and abottom housing9302 having akeyboard9304 can overlap each other by closing a hinge unit which connects thetop housing9301 and thebottom housing9302. The portable computer ofFIG. 35A can be convenient for carrying, and in the case of using the keyboard for input, the hinge unit is opened and the user can input looking at thedisplay portion9303.

Thebottom housing9302 includes apointing device9306 with which input can be performed, in addition to thekeyboard9304. Further, when thedisplay portion9303 is a touch input panel, input can be performed by touching part of the display portion. Thebottom housing9302 includes an arithmetic function portion such as a CPU or hard disk. In addition, thebottom housing9302 includes another device, for example, anexternal connection port9305 into which a communication cable conformable to communication standards of a USB is inserted.

Thetop housing9301, which includes adisplay portion9307 and can keep thedisplay portion9307 therein by sliding it toward the inside of thetop housing9301, can have a large display screen. In addition, the user can adjust the orientation of a screen of thedisplay portion9307 which can be kept in thetop housing9301. When thedisplay portion9307 which can be kept in thetop housing9301 is a touch input panel, input can be performed by touching part of thedisplay portion9307 which can be kept in thetop housing9301.

Thedisplay portion9303 or thedisplay portion9307 which can be kept in thetop housing9301 are formed using an image display device of a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element, or the like.

In addition, the portable computer inFIG. 35A can be provided with a receiver and the like and can receive a television broadcast to display an image on the display portion. The user can watch a television broadcast when the whole screen of thedisplay portion9307 is exposed by sliding thedisplay portion9307 while the hinge unit which connects thetop housing9301 and thebottom housing9302 is kept closed. In this case, the hinge unit is not opened and display is not performed on thedisplay portion9303. In addition, start up of only a circuit for displaying a television broadcast is performed. Therefore, power can be consumed to the minimum, which is useful for the portable computer whose battery capacity is limited.

FIG. 35B is a perspective view illustrating an example of a cellular phone that the user can wear on the wrist like a wristwatch.

This cellular phone is formed including a main body which includes a communication device having at least a telephone function, and a battery; aband portion9204 which enables the main body to be worn on the wrist; an adjustingportion9205 for adjusting the band portion to fit the wrist; adisplay portion9201; aspeaker9207; and amicrophone9208.

In addition, the main body includes operation switches9203. The operation switches9203 can serve, for example, as a switch for starting a program for the Internet when pushed, in addition to serving as a power switch, a switch for shifting the display, a switch for instruction to start taking images, or the like, and can be configured to have respective functions.

Input to this cellular phone is operated by touching thedisplay portion9201 with a finger or an input pen, operating the operation switches9203, or inputting voice into themicrophone9208. InFIG. 35B,display buttons9202 are displayed on thedisplay portion9201. Input can be performed by touching thedisplay buttons9202 with a finger or the like.

Further, the main body includes acamera portion9206 including an image pick-up means having a function of converting an image of an object, which is formed through a camera lens, to an electronic image signal. Note that the camera portion is not necessarily provided.

The cellular phone illustrated inFIG. 35B is provided with a receiver of a television broadcast and the like, and can display an image on thedisplay portion9201 by receiving a television broadcast. In addition, the cellular phone illustrated inFIG. 35B is provided with a memory device and the like such as a memory, and can record a television broadcast in the memory. The cellular phone illustrated inFIG. 35B may have a function of collecting location information such as GPS.

An image display device of a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element, or the like is used as thedisplay portion9201. The cellular phone illustrated inFIG. 35B is compact and lightweight and thus has limited battery capacity. Therefore, a panel which can be driven with low power consumption is preferably used as a display device for thedisplay portion9201.

Note thatFIG. 35B illustrates the electronic device which is worn on the wrist; however, this embodiment is not limited thereto as long as a portable shape is employed.

This application is based on Japanese Patent Application serial No. 2009-164197 filed with Japan Patent Office on Jul. 10, 2009, the entire contents of which are hereby incorporated by reference.