US20160269031A1 - COMPACT ReRAM BASED FPGA - Google Patents
COMPACT ReRAM BASED FPGADownload PDFInfo
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- US20160269031A1 US20160269031A1US15/010,222US201615010222AUS2016269031A1US 20160269031 A1US20160269031 A1US 20160269031A1US 201615010222 AUS201615010222 AUS 201615010222AUS 2016269031 A1US2016269031 A1US 2016269031A1
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- 239000002184metalSubstances0.000description15
- 229910021420polycrystalline siliconInorganic materials0.000description4
- 229920005591polysiliconPolymers0.000description4
- 230000007704transitionEffects0.000description4
- 230000008901benefitEffects0.000description2
- 238000010586diagramMethods0.000description2
- 238000003491arrayMethods0.000description1
- 230000006870functionEffects0.000description1
- 238000004519manufacturing processMethods0.000description1
- 238000000206photolithographyMethods0.000description1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/74—Array wherein each memory cell has more than one access device
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/78—Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
Definitions
- Push-pull resistive random access memory (ReRAM) cellssuch as the ones disclosed in U.S. Pat. No. 8,415,650, are attractive for use in configuration memory for configurable logic integrated circuits such as field programmable gate arrays (FPGAs).
- FPGAsfield programmable gate arrays
- any change in transistor pitchforces designers to use a large transition region to allow photolithographic production of the pattern.
- This transition regioncan range from 0.2 um to 1 um or more and can be a significant disadvantage in designing a configurable logic integrated circuit employing ReRAM push-pull configuration memory cell circuits that has a compact efficient layout.
- An FPGArequires logic, routing switches, and programming transistors to be intermingled. To eliminate the transition region which is required by photolithography processing requirements, all the above listed devices must have the same pitch, including channel length pitch. Normally this requirement is not compatible with devices that are operated at different voltages.
- the transistor devices used to program themwill be subjected to higher drain and gate biases, and will switch at a higher gate bias during programming and operation as compared to other transistors employed in the integrated circuit.
- An objective of the present inventionis to provide ReRAM push-pull configuration memory cell circuits that eliminate this transition region.
- a push-pull ReRAM cell circuitemploys two programming transistors that are cascaded in series and have the same pitch and channel length.
- a switch transistor used in the push-pull ReRAM cell circuithas the same pitch and channel length as the two programming transistors in order to maintain the same pitch and channel length for both the programming devices and the switch transistors that are used to configure and/or interconnect the logic cells.
- the switch transistor whose state is configured by the ReRAMwill use the same thick dielectric that is used in the programming transistors to mitigate elevated gate stress during programming.
- Use of a thicker dielectricalso allows the gate of the configuration switch to be overdriven at higher V CC during operation, thus allowing the passage of the full V CC logic signal.
- a push-pull resistive random access memory cell circuitincludes an output node, a word line, a first bit line, and a second bit line.
- a first resistive random access memory deviceis connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line.
- a first programming transistorhas a gate connected to the word line, a drain connected to the output node, and a source.
- a second programming transistorhas a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source.
- the first and second programming transistorshave the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
- At least one switch transistorhas a gate connected to the output node, a drain connected to a first logic net node and a source connected to a second logic net node.
- the switch transistorhas the same pitch, channel length, and gate dielectric thickness as the first and second programming transistors.
- FIG. 1is a schematic diagram of a push-pull ReRAM cell in accordance with one aspect of the present invention
- FIG. 2is a cross-sectional view of an exemplary layout of the push-pull ReRAM cell of the present invention
- FIG. 3is a top view of an exemplary layout of the push-pull ReRAM cell of the present invention.
- FIG. 1a schematic diagram shows an illustrative push-pull ReRAM cell circuit 10 in accordance with one aspect of the present invention.
- a first ReRAM device 12is coupled in series with a second ReRAM device 14 to form a ReRAM cell 16 .
- a first end of the series connected ReRAM devices 12 , 14at one terminal of ReRAM device 12 , is coupled to a first bit line (BL) 18 and a second end of the series connected ReRAM devices 12 , 14 , at one terminal of ReRAM device 14 , is coupled to a second bit line (B1_bar) 20 .
- the ReRAM cell 16 depicted in FIG. 1is a front-to-back ReRAM cell, particularly useful for biasing a switch as shown, but persons of ordinary skill in the art will appreciate that back-to-back ReRAM cells could also be employed in the present invention.
- ReRAM devices 12 and 14together comprise a push-pull ReRAM cell 16 .
- the common output node 22 between ReRAM devices 12 and 14is connected to the gate of one or more switch transistors.
- FIG. 1shows the common output node 22 connected to the gates of two switch transistors 24 a and 24 b.
- Switch transistor 24 ais shown connected between two logic net nodes 26 a and 28 a.
- switch transistor 24 bis shown connected between two logic net nodes 26 b and 28 b.
- logic net nodes 26 a, 26 b, 28 a, and 28 bcan represent logic gates or other devices in a programmable integrated circuit that are connected together by the switch transistors 24 a and 24 b, respectively, and can also represent circuit nets in a single logic device in such an integrated circuit that define the function of the logic device, or can represent a wiring interconnection in a programmable integrated circuit.
- FIG. 1shows multiple switch transistors 24 a and 24 b so that more than one logic circuit net can be activated by a single push-pull ReRAM cell 16 , persons of ordinary skill in the art will appreciate that a single switch transistor could be connected to the common output node 22 .
- push-pull ReRAM cell 16is programmed using a pair of n-channel programming transistors 30 and 32 cascaded in series.
- N-channel programming transistor 30has its drain connected to the common output node 22 of the push-pull ReRAM cell 16 , and its source connected to the drain of the n-channel programming transistor 32 .
- a single n+ regionserves as the source of n-channel programming transistor 30 and the drain of n-channel programming transistor 32 .
- the source of n-channel programming transistor 32is connected to a word line WLS.
- both n-channel programming transistors 30 and 32can be designed having the same pitch and channel length as the n-channel switch transistors 24 a and 24 b.
- the same pitch and channel length used for switch transistors 24 a and 24 bare used for the logic devices in the integrated circuit.
- n-channel programming transistors 30 and 32 and n-channel switch transistors 24 a and 24 bare fabricated having the same gate dielectric thicknesses.
- N-channel programming transistors 30 and 32have gate dielectric thicknesses selected to withstand the programming and erase potentials that the ReRAM push-pull memory cell will be subjected to during its operation.
- Most integrated circuitsinclude input/output (I/O) transistors used to interface the integrated circuit with external components. Because these transistors interface with components that often operate at voltages higher than the voltages normally found internally in the integrated circuit, the I/O transistors are usually fabricated having gate dielectric thicknesses larger than other transistors used internally in the integrated circuit. It may therefore be convenient to employ n-channel programming transistors 30 and 32 having the same gate dielectric thicknesses as the I/O transistors.
- switch transistors 24 a and 24 bUsing the same larger gate dielectric thickness for the transistors 24 a and 24 b will mitigate elevated gate stress that switch transistors 24 a and 24 b would otherwise be subjected to during programming, because its gates are connected to the common node 22 of the push-pull ReRAM memory cell 16 , and that node will experience programming voltages during erase and programming of the memory cell 16 .
- Use of a thicker dielectric for switch transistors 24 a and 24 balso allows the gates of the switch transistors 24 a and 24 b to be overdriven at higher values of V CC during operation, thus allowing the switch transistors 24 a and 24 b to pass the full V CC logic signal.
- thin gate oxidescan be used for the switch transistors 24 a and 24 b, but care should be taken to avoid stress during programming and erase operations. This may be done by raising the source/drain bias to V CC logic during programming.
- bit line BL 18is connected to a voltage source V CC and BL_bar 20 is connected to a potential such as ground.
- the WLS linecan be connected to ground or to a slightly positive potential such as 0.9V to limit leakage in the n-channel programming transistors 30 and 32 .
- Push-pull ReRAM cell 16is programmed so that only one of the ReRAM devices 12 and 14 is on at any one time, thus either pulling common node 22 up to the voltage on bitline BL 18 or pulling common node 22 down to the voltage on bitline BL_bar 20 (usually ground).
- Push-pull ReRAM cell 16is shown in FIG. 1 with ReRAM device 12 turned on and ReRAM device 14 turned off. The common node 22 is thus pulled up to the voltage on bit line BL 18 (V CC ), thus turning on switch transistors 24 a and 24 b (shown in FIG. 1 as n-channel transistors).
- FIG. 2is a cross-sectional view of an exemplary layout 40 of the push-pull ReRAM cell circuit 10 of the present invention.
- FIG. 3is a top view of an exemplary layout 40 of the push-pull ReRAM cell circuit 10 of the present invention.
- Persons of ordinary skill in the artwill observe that the layouts shown in FIGS. 2 and 3 are illustrative only and non-limiting.
- Push-pull ReRAM cell circuit 10( FIG. 1 ) is formed in a p-type substrate or well 42 in an integrated circuit.
- N+ region 44forms the drain of n-channel programming transistor 30 and n+ region 46 forms its source, as well as acting as the drain of n-channel programming transistor 32 .
- Polysilicon or metal line 48forms the gate of n-channel programming transistor 30 .
- N+ region 50forms the source of n-channel programming transistor 32 and polysilicon or metal line 52 forms its gate.
- Contacts 54connect the polysilicon gates 48 and 52 of n-channel programming transistors 30 and 32 to word line 34 , shown as being formed from a first metal interconnect layer (M1).
- M1first metal interconnect layer
- the switch transistor shown in FIG. 3includes source region 56 and drain region 58 , separated by gate 60 . It is noted that the cross sectional view of FIG. 2 is partially taken through the source region of one of switch transistors 24 a and 24 b.
- the switch transistorsmay be n-channel or p-channel devices.
- ReRAM device 12is formed between metal interconnect layers on the integrated circuit (for example between first and second metal layers M1 and M2). In FIGS. 2 and 3 , ReRAM device 12 is shown formed between M1 metal segment 62 and M2 metal segment 64 . ReRAM device 12 is formed over metal segment 62 and is connected to M2 metal segment 64 through contact 66 . ReRAM device 12 is connected to bitline BL 18 through contact 68 .
- M2 segment 64Contact to common node 22 is made from M2 segment 64 to an M1 metal segment 70 through contact 72 .
- a contact 74connects M1 metal segment 70 to polysilicon gate 60 of the switch transistor.
- ReRAM device 14is shown formed between M1 metal segment 70 and the M2 metal segment forming second bitline B1_bar 20 .
- a contact 76connects M1 ReRAM device 14 to second bitline B1_bar 20 .
- a contact 78connects M1 metal segment 70 to the n+ region 44 forming the drain of n-channel programming transistor 30 .
- a metal segment 80forms the word line WLS and is connected to n+ region 50 forming the source of programming transistor 32 through contact 82 .
- Push-pull ReRAM cell 16is programmed by turning on the desired one of ReRAM devices 12 and 14 so as to either turn off, or turn on, switch transistors 24 a and 24 b. First, both ReRAM devices 12 and 14 are erased. To erase a ReRAM device means to turn it off so that it does not pass current. To erase ReRAM device 12 , bitline BL 18 is brought to a high voltage (e.g., 1.8V) and common node 22 is brought to ground. To avoid stressing ReRAM device 14 , second bit line B1_bar 20 is also brought to ground so that there is no potential impressed across ReRAM device 14 .
- a high voltagee.g., 1.8V
- common node 22is brought to a high voltage (e.g., 1.8V) and second bit line B1_bar 20 is brought to ground.
- bitline BL 18is also brought to the high voltage so that there is no potential impressed across ReRAM device 12 .
- bitline BL 18is brought to ground and common node 22 is brought to a high voltage (e.g., 1.8V).
- second bit line B1_bar 20is also brought to the high voltage so that there is no potential impressed across ReRAM device 14 .
- common node 22is brought to ground and second bit line B1_bar 20 is brought to the high voltage.
- bitline BL 18is also brought to ground so that there is no potential impressed across ReRAM device 12 .
- two series connected n-channel programming transistors 30 and 32are coupled between common node 22 and word line WLS.
- the gates of n-channel transistors 30 and 32are connected together to word line WL 34 .
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Abstract
Description
- This application claims the benefit of U.S. Provisional Patent Application No. 62/132,333 filed Mar. 12, 2015, the contents of which are incorporated in this disclosure by reference in its entirety.
- Push-pull resistive random access memory (ReRAM) cells, such as the ones disclosed in U.S. Pat. No. 8,415,650, are attractive for use in configuration memory for configurable logic integrated circuits such as field programmable gate arrays (FPGAs).
- When designing circuits using deep sub-micron (14 nM and beyond) transistors, any change in transistor pitch forces designers to use a large transition region to allow photolithographic production of the pattern. This transition region can range from 0.2 um to 1 um or more and can be a significant disadvantage in designing a configurable logic integrated circuit employing ReRAM push-pull configuration memory cell circuits that has a compact efficient layout.
- An FPGA requires logic, routing switches, and programming transistors to be intermingled. To eliminate the transition region which is required by photolithography processing requirements, all the above listed devices must have the same pitch, including channel length pitch. Normally this requirement is not compatible with devices that are operated at different voltages.
- For ReRAM memory cells, the transistor devices used to program them will be subjected to higher drain and gate biases, and will switch at a higher gate bias during programming and operation as compared to other transistors employed in the integrated circuit.
- Therefore, there is a need for a design for ReRAM configuration memory cells which is not associated with these disadvantages. An objective of the present invention is to provide ReRAM push-pull configuration memory cell circuits that eliminate this transition region.
- According to the present invention, a push-pull ReRAM cell circuit employs two programming transistors that are cascaded in series and have the same pitch and channel length. A switch transistor used in the push-pull ReRAM cell circuit has the same pitch and channel length as the two programming transistors in order to maintain the same pitch and channel length for both the programming devices and the switch transistors that are used to configure and/or interconnect the logic cells.
- According to the present invention, the switch transistor whose state is configured by the ReRAM will use the same thick dielectric that is used in the programming transistors to mitigate elevated gate stress during programming. Use of a thicker dielectric also allows the gate of the configuration switch to be overdriven at higher VCCduring operation, thus allowing the passage of the full VCClogic signal.
- According to one aspect of the present invention, a push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
- According to another aspect of the present invention, at least one switch transistor has a gate connected to the output node, a drain connected to a first logic net node and a source connected to a second logic net node. The switch transistor has the same pitch, channel length, and gate dielectric thickness as the first and second programming transistors.
- These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
FIG. 1 is a schematic diagram of a push-pull ReRAM cell in accordance with one aspect of the present invention;FIG. 2 is a cross-sectional view of an exemplary layout of the push-pull ReRAM cell of the present invention;FIG. 3 is a top view of an exemplary layout of the push-pull ReRAM cell of the present invention.- Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.
- Referring first to
FIG. 1 , a schematic diagram shows an illustrative push-pullReRAM cell circuit 10 in accordance with one aspect of the present invention. Afirst ReRAM device 12 is coupled in series with asecond ReRAM device 14 to form aReRAM cell 16. A first end of the series connected ReRAMdevices device 12, is coupled to a first bit line (BL)18 and a second end of the series connectedReRAM devices device 14, is coupled to a second bit line (B1_bar)20. TheReRAM cell 16 depicted inFIG. 1 is a front-to-back ReRAM cell, particularly useful for biasing a switch as shown, but persons of ordinary skill in the art will appreciate that back-to-back ReRAM cells could also be employed in the present invention. - As described above,
ReRAM devices pull ReRAM cell 16. Thecommon output node 22 betweenReRAM devices FIG. 1 shows thecommon output node 22 connected to the gates of twoswitch transistors transistor 24ais shown connected between twologic net nodes switch transistor 24bis shown connected between twologic net nodes logic net nodes switch transistors - While
FIG. 1 showsmultiple switch transistors pull ReRAM cell 16, persons of ordinary skill in the art will appreciate that a single switch transistor could be connected to thecommon output node 22. - According to one aspect of the present invention, push-pull ReRAM
cell 16 is programmed using a pair of n-channel programming transistors channel programming transistor 30 has its drain connected to thecommon output node 22 of the push-pull ReRAMcell 16, and its source connected to the drain of the n-channel programming transistor 32. In an actual embodiment, a single n+ region serves as the source of n-channel programming transistor 30 and the drain of n-channel programming transistor 32. The source of n-channel programming transistor 32 is connected to a word line WLS. By connecting two n-channel programming transistors channel programming transistors channel switch transistors switch transistors - According to another aspect of the present invention, n-
channel programming transistors channel switch transistors channel programming transistors channel programming transistors - Using the same larger gate dielectric thickness for the
transistors switch transistors common node 22 of the push-pullReRAM memory cell 16, and that node will experience programming voltages during erase and programming of thememory cell 16. Use of a thicker dielectric forswitch transistors switch transistors switch transistors switch transistors - In normal operation of the programmable integrated circuit,
bit line BL 18 is connected to a voltage source VCCandBL_bar 20 is connected to a potential such as ground. The WLS line can be connected to ground or to a slightly positive potential such as 0.9V to limit leakage in the n-channel programming transistors pull ReRAM cell 16 is programmed so that only one of theReRAM devices common node 22 up to the voltage onbitline BL 18 or pullingcommon node 22 down to the voltage on bitline BL_bar20 (usually ground). Push-pull ReRAM cell 16 is shown inFIG. 1 withReRAM device 12 turned on andReRAM device 14 turned off. Thecommon node 22 is thus pulled up to the voltage on bit line BL18 (VCC), thus turning onswitch transistors FIG. 1 as n-channel transistors). - Referring now to both
FIG. 2 andFIG. 3 , an exemplary layout of the push-pull ReRAM cell of the present invention is shown.FIG. 2 is a cross-sectional view of anexemplary layout 40 of the push-pullReRAM cell circuit 10 of the present invention.FIG. 3 is a top view of anexemplary layout 40 of the push-pullReRAM cell circuit 10 of the present invention. Persons of ordinary skill in the art will observe that the layouts shown inFIGS. 2 and 3 are illustrative only and non-limiting. - Push-pull ReRAM cell circuit10 (
FIG. 1 ) is formed in a p-type substrate or well42 in an integrated circuit.N+ region 44 forms the drain of n-channel programming transistor 30 andn+ region 46 forms its source, as well as acting as the drain of n-channel programming transistor 32. Polysilicon ormetal line 48 forms the gate of n-channel programming transistor 30.N+ region 50 forms the source of n-channel programming transistor 32 and polysilicon ormetal line 52 forms its gate.Contacts 54 connect thepolysilicon gates channel programming transistors word line 34, shown as being formed from a first metal interconnect layer (M1). Persons of ordinary skill in the art will appreciate that p-channel transistors may also be used in other embodiments of the invention. - The switch transistor shown in
FIG. 3 includessource region 56 and drainregion 58, separated bygate 60. It is noted that the cross sectional view ofFIG. 2 is partially taken through the source region of one ofswitch transistors ReRAM device 12 is formed between metal interconnect layers on the integrated circuit (for example between first and second metal layers M1 and M2). InFIGS. 2 and 3 ,ReRAM device 12 is shown formed betweenM1 metal segment 62 andM2 metal segment 64.ReRAM device 12 is formed overmetal segment 62 and is connected toM2 metal segment 64 throughcontact 66.ReRAM device 12 is connected to bitlineBL 18 throughcontact 68.- Contact to
common node 22 is made fromM2 segment 64 to anM1 metal segment 70 throughcontact 72. Acontact 74 connectsM1 metal segment 70 topolysilicon gate 60 of the switch transistor.ReRAM device 14 is shown formed betweenM1 metal segment 70 and the M2 metal segment formingsecond bitline B1_bar 20. Acontact 76 connectsM1 ReRAM device 14 tosecond bitline B1_bar 20. Acontact 78 connectsM1 metal segment 70 to then+ region 44 forming the drain of n-channel programming transistor 30. Ametal segment 80 forms the word line WLS and is connected to n+region 50 forming the source ofprogramming transistor 32 throughcontact 82. - Push-pull
ReRAM cell 16 is programmed by turning on the desired one ofReRAM devices switch transistors ReRAM devices ReRAM device 12,bitline BL 18 is brought to a high voltage (e.g., 1.8V) andcommon node 22 is brought to ground. To avoid stressingReRAM device 14, secondbit line B1_bar 20 is also brought to ground so that there is no potential impressed acrossReRAM device 14. To eraseReRAM device 14,common node 22 is brought to a high voltage (e.g., 1.8V) and secondbit line B1_bar 20 is brought to ground. To avoid stressingReRAM device 12,bitline BL 18 is also brought to the high voltage so that there is no potential impressed acrossReRAM device 12. - After both
ReRAM cells ReRAM devices program ReRAM device 12,bitline BL 18 is brought to ground andcommon node 22 is brought to a high voltage (e.g., 1.8V). To avoid stressingReRAM device 14 while programmingReRAM device 12, secondbit line B1_bar 20 is also brought to the high voltage so that there is no potential impressed acrossReRAM device 14. Toprogram ReRAM device 14,common node 22 is brought to ground and secondbit line B1_bar 20 is brought to the high voltage. To avoid stressingReRAM device 12,bitline BL 18 is also brought to ground so that there is no potential impressed acrossReRAM device 12. - According to another aspect of the present invention, two series connected n-
channel programming transistors common node 22 and word line WLS. The gates of n-channel transistors word line WL 34. - While the present disclosure is directed to the application of a ReRAM memory device where the logic is switching at a first voltage and the programming and erasing of the ReRAM cell is performed at a second voltage, persons of ordinary skill in the art will appreciate that it is also applicable to other devices where it is desirable to switch two different voltages in different operating modes.
- Although the present invention has been discussed in considerable detail with reference to certain preferred embodiments, other embodiments are possible. Therefore, the scope of the appended claims should not be limited to the description of preferred embodiments contained in this disclosure.
Claims (5)
1. A push-pull resistive random access memory cell circuit comprising:
an output node;
a word line;
a first bit line;
a second bit line;
a first resistive random access memory device connected between the first bit line and the output node;
a second resistive random access memory device connected between the output node and the second bit line;
a first programming transistor having a gate connected to the word line, a drain connected to the output node, and a source; and
a second programming transistor having a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source,
wherein the first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness of the first and second programming transistors chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
2. The push-pull resistive random access memory cell circuit ofclaim 1 wherein:
the push-pull resistive random access memory cell circuit is fabricated on an integrated circuit having input/output transistors; and
the thickness of the gate dielectric of the first and second programming transistors is the same as the thickness of the gate dielectric of the input/output transistors.
3. The push-pull resistive random access memory cell circuit ofclaim 2 , further comprising:
at least one switch transistor having a gate connected to the output node, a drain connected to a first logic net node and a source connected to a second logic net node; and
wherein the switch transistor has the same pitch, channel length, and gate dielectric thickness as the first and second programming transistors.
4. The push-pull resistive random access memory cell circuit ofclaim 1 wherein:
the push-pull resistive random access memory cell circuit is fabricated on an integrated circuit having logic transistors; and
the thickness of the gate dielectric of the first and second programming transistors is larger than the thickness of the gate dielectric of the logic transistors.
5. The push-pull resistive random access memory cell circuit ofclaim 4 , further comprising:
at least one switch transistor having a gate connected to the output node, a drain connected to a first logic net node and a source connected to a second logic net node; and
wherein the switch transistor has the same pitch, channel length, and gate dielectric thickness as the first and second programming transistors.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017566605AJP2018513569A (en) | 2015-03-12 | 2016-01-29 | Compact ReRAM-based FPGA |
| PCT/US2016/015756WO2016144434A1 (en) | 2015-03-12 | 2016-01-29 | COMPACT ReRAM BASED FPGA |
| US15/010,222US9444464B1 (en) | 2015-03-12 | 2016-01-29 | Compact ReRAM based FPGA |
| DE112016001160.1TDE112016001160B4 (en) | 2015-03-12 | 2016-01-29 | Compact ReRAM-based FPGA |
| US15/233,054US9520448B1 (en) | 2015-03-12 | 2016-08-10 | Compact ReRAM based PFGA |
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|---|---|---|---|
| US201562132333P | 2015-03-12 | 2015-03-12 | |
| US15/010,222US9444464B1 (en) | 2015-03-12 | 2016-01-29 | Compact ReRAM based FPGA |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US15/233,054DivisionUS9520448B1 (en) | 2015-03-12 | 2016-08-10 | Compact ReRAM based PFGA |
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| Publication Number | Publication Date |
|---|---|
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| US20160269031A1true US20160269031A1 (en) | 2016-09-15 |
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US15/010,222ActiveUS9444464B1 (en) | 2015-03-12 | 2016-01-29 | Compact ReRAM based FPGA |
| US15/233,054ActiveUS9520448B1 (en) | 2015-03-12 | 2016-08-10 | Compact ReRAM based PFGA |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US15/233,054ActiveUS9520448B1 (en) | 2015-03-12 | 2016-08-10 | Compact ReRAM based PFGA |
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| Country | Link |
|---|---|
| US (2) | US9444464B1 (en) |
| JP (1) | JP2018513569A (en) |
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| WO (1) | WO2016144434A1 (en) |
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| US9990993B2 (en) | 2016-09-29 | 2018-06-05 | Microsemi SoC Corporation | Three-transistor resistive random access memory cells |
| CN108288616B (en) | 2016-12-14 | 2023-04-07 | 成真股份有限公司 | Chip package |
| US11625523B2 (en) | 2016-12-14 | 2023-04-11 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
| US10348306B2 (en) | 2017-03-09 | 2019-07-09 | University Of Utah Research Foundation | Resistive random access memory based multiplexers and field programmable gate arrays |
| US10447274B2 (en) | 2017-07-11 | 2019-10-15 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells |
| US10957679B2 (en) | 2017-08-08 | 2021-03-23 | iCometrue Company Ltd. | Logic drive based on standardized commodity programmable logic semiconductor IC chips |
| US10630296B2 (en) | 2017-09-12 | 2020-04-21 | iCometrue Company Ltd. | Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells |
| US10608642B2 (en) | 2018-02-01 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells |
| US10623000B2 (en) | 2018-02-14 | 2020-04-14 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
| US10608638B2 (en) | 2018-05-24 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
| US11309334B2 (en) | 2018-09-11 | 2022-04-19 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
| US10892011B2 (en) | 2018-09-11 | 2021-01-12 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
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| US11211334B2 (en) | 2018-11-18 | 2021-12-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
| US11227838B2 (en) | 2019-07-02 | 2022-01-18 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits |
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| US11637056B2 (en) | 2019-09-20 | 2023-04-25 | iCometrue Company Ltd. | 3D chip package based on through-silicon-via interconnection elevator |
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- 2016
- 2016-01-29USUS15/010,222patent/US9444464B1/enactiveActive
- 2016-01-29DEDE112016001160.1Tpatent/DE112016001160B4/enactiveActive
- 2016-01-29WOPCT/US2016/015756patent/WO2016144434A1/ennot_activeCeased
- 2016-01-29JPJP2017566605Apatent/JP2018513569A/ennot_activeWithdrawn
- 2016-08-10USUS15/233,054patent/US9520448B1/enactiveActive
Also Published As
| Publication number | Publication date |
|---|---|
| US20160351626A1 (en) | 2016-12-01 |
| DE112016001160B4 (en) | 2023-12-28 |
| US9444464B1 (en) | 2016-09-13 |
| DE112016001160T5 (en) | 2017-11-30 |
| US9520448B1 (en) | 2016-12-13 |
| JP2018513569A (en) | 2018-05-24 |
| WO2016144434A1 (en) | 2016-09-15 |
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