TABLE 1

	Field	Purpose

	Busy	Indicates that hardware is actively
		in an access. Microcode is not
		allowed to change the value of the
		register.
	TID	Final Thread ID
	R/W#	If R/W# = 1, the register is to be
		rad, if R/W# = 0, the FIL register
		is to be written.
	PMA/FIL#	If PMA/FIL# = 1, access CAB
		unit, if 0, access FIL

In one embodiment, information of mailbox address/command and data registers may be communicated over particular bits of an address field. For example, data information of a data register of a given mailbox storage1612 may be communicated over address bits[31:0] and command information of a command/address register of the mailbox storage, e.g., TID is sent over address bit[32], and the corresponding register address is sent over address bits[36:33]. Note in this embodiment, there is no need to send the trust indicator, as the trust check is done inmailbox control logic1615 prior to sending the information. Further, there is no need to send a PMA/FIL# indication, as dedicated hardware (e.g., the two different converters) is used for each of those routes.

In an example, IDI request fields may be used to communicate data information from mailbox storages1612 to corresponding FIL registers1622. To realize this, uncore1690 may be configured to ignore the information (not related to an IDI request) via the NOP command.

Via the mailbox interface, a variety of autonomous intellectual property (IP) logic blocks may communicate firmware with other domains inside and coupled to a given IP logic block. Embodiments may be used to reduce power management flow latencies, while at the same time simplifying communication between microcode and ring/mesh and infrastructure domains.

The following examples pertain to further embodiments.

In one example, a processor comprises: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages, each of the plurality of mailbox storages to be associated with a thread; a first core perimeter logic coupled to the core, the first core perimeter logic including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state.

In an example, each of the plurality of mailbox storages comprises: a data storage; and a command/address storage.

In an example, the core is to check a busy indicator of the command/address storage of a first mailbox storage and if the busy indicator is inactive, the core is to write data information to the data storage of the first mailbox storage and second information to the command/address storage of the first mailbox storage and activate the busy indicator.

In an example, the core is to write the data information and the second information responsive to a microcode write command.

In an example, the core is to access a trust indicator associated with the first mailbox storage and if the trust indicator is set, enable communication of the data information in the data storage of the first mailbox storage to one of the first core perimeter logic and the second core perimeter logic, if microcode that issued the microcode write command is trusted.

In an example, the core is to raise a machine check exception if the microcode is not trusted.

In an example, the microcode write command comprises an intra-die interconnect no operation command.

In an example, the core includes a first converter to convert information stored in a first mailbox storage to a format for communication on an intra-die interconnect coupled between the core and the first core perimeter logic.

In an example, the core includes a second converter to convert information stored in a second mailbox storage to a format for communication on a parallel interconnect coupled between the core and the second core perimeter logic.

Note that the above processor can be implemented using various means.

In an example, the processor comprises a SoC incorporated in a user equipment touch-enabled device.

In another example, a system comprises a display and a memory, and includes the processor of one or more of the above examples.

In another example, a method comprises: determining, via a mailbox control logic of a core of a processor, a state of a busy indicator of a first mailbox storage of the core; if the busy indicator state is inactive writing, via the mailbox control logic, data information and control information into the first mailbox storage and setting the busy indicator to an active state; and determining whether a trust indicator associated with the first mailbox storage is active, and if so, sending at least a portion of the data information and the control information to one of a first core perimeter logic coupled to the core or a second core perimeter logic coupled to the core based on a value of a destination indicator of the control information.

In an example, the method further comprises causing the core to enter into a low power state, while the selected first core perimeter logic or the second core perimeter logic is to remain powered on.

In an example, the method further comprises: sending at least the portion of the data information and the control information to the first core perimeter logic, if selected, via a first interconnect coupled between the core and the first core perimeter logic and sending at least the portion of the data information and the control information to the second core perimeter logic, if selected, via a second interconnect coupled between the core and the second core perimeter logic.

In an example, the method further comprises converting the data information and the control information from a first format to a second format and thereafter sending the converted data information and the converted control information to the first core perimeter logic.

In an example, the method further comprises sending a no operation command with the data information and the control information to the first core perimeter logic, where the first core perimeter logic is to store the data information and the control information in a storage of the first core perimeter logic responsive to the no operation command, and an uncore coupled to the first interconnect is to report a global observation to the core responsive to the no operation command.

In an example, the first core perimeter logic is to store the data information and the control information in the storage responsive to the no operation command including an active prefetch indicator.

In an example, the method further comprises: storing the data information from the storage of the first core perimeter logic to a second storage of the second core perimeter logic before entry of the first core perimeter logic into a low power state; and storing the data information to a memory coupled to the processor before entry of the second core perimeter logic into a low power state.

In an example, the method further comprises: restoring the data information from the memory to the second storage of the second core perimeter logic after the second core perimeter logic exits the low power state; and restoring the data information from the second storage of the second core perimeter logic to the storage of the first core perimeter logic after the first core perimeter logic exits the low power state.

In another example, a computer readable medium including instructions is to perform the method of any of the above examples.

In another example, a computer readable medium including data is to be used by at least one machine to fabricate at least one integrated circuit to perform the method of any one of the above examples.

In another example, an apparatus comprises means for performing the method of any one of the above examples.

In another example, a system comprises: a processor having a core to execute instructions, the core including a mailbox interface having a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages, each of the plurality of mailbox storages to be associated with a thread, a core perimeter logic coupled to the core and including a first domain having a first storage to store state information of the core when the core is in a low power state and a second domain having a second storage to store the state information of the core when the first domain is in a low power state, a first interconnect to communicate between the mailbox interface and the first domain, and a second interconnect to communicate between the mailbox interface and the second domain; and a DRAM coupled to the processor.

In an example, the core, if a busy indicator of a first mailbox storage is inactive, is to write information to the first mailbox storage and activate the busy indicator, responsive to a microcode write command.

In an example, the core is to determine whether a trust indicator associated with the first mailbox storage is active, and if so, send at least a portion of the information from the first mailbox storage to one of the first domain or the second domain, based on a value of a destination indicator of the information.

Understand that various combinations of the above examples are possible.

Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.