US20160211394A1 - Nano wire array based solar energy harvesting device - Google Patents

Abstract

A photovoltaic device operable to convert light to electricity, comprising a substrate, a plurality of structures essentially perpendicular to the substrate, one or more recesses between the structures, each recess having a planar mirror on a bottom wall thereof and each recess filled with a transparent material. The structures have p-n or p-i-n junctions for converting light into electricity. The planar mirrors function as an electrode and can reflect light incident thereon back to the structures to be converted into electricity.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 12/982,269 filed Dec. 30, 2010, the entire contents of which are incorporated herein by reference.
• This application is related to the disclosures of U.S. Patent application Ser. No. 12/270,233, filed Nov. 13, 2008 (now U.S. Pat. No. 8,274,039, issued Sep. 25, 2012), Ser. No. 13/925,429, filed Jun. 24, 2013, Ser. No. 13/570,027, filed Aug. 8, 2012 (now U.S. Pat. No. 8,471,190, issued Jun. 25, 2013), Ser. No. 12/472,264, filed May 26, 2009 (now U.S. Pat. No. 8,269,985, issued Sep. 18, 2012), Ser. No. 13/621,607, filed Sep. 17, 2012 (now U.S. Pat. No. 8,514,411, issued Aug. 20, 2013), Ser. No. 13/971,523, filed Aug. 20, 2013 (now U.S. Pat. No. 8,810,808, issued Aug. 19, 2014), Ser. No. 14/459,398, filed Aug. 14, 2014, Ser. No. 12/472,271, filed May 26, 2009 (now abandoned), Ser. No. 12/478,598, filed Jun. 4, 2009 (now U.S. Pat. No. 8,546,742, issued Oct. 1, 2013), Ser. No. 14/021,672, filed Sep. 9, 2013 (now U.S. Pat. No. 9,177,985, issued Nov. 3, 2015), Ser. No. 12/573,582, filed Oct. 5, 2009 (now U.S. Pat. No. 8,791,470, issued Jul. 29, 2014), Ser. No. 14/274,448, filed May 9, 2014, Ser. No. 12/575,221, filed Oct. 7, 2009 (now U.S. Pat. No. 8,384,007, issued Feb. 26, 2013), Ser. No. 12/633,323, filed Dec. 8, 2009 (now U.S. Pat. No. 8,735,797, issued May 27, 2014), Ser. No. 14/068,864, filed Oct. 31, 2013 (now U.S. Pat. No. 9,263,613, issued Feb. 16, 2016), Ser. No. 14/281,108, filed May 19, 2014 (now U.S. Pat. No. 9,123,841, issued Sep. 1, 2015), Ser. No. 13/494,661, filed Jun. 12, 2012 (now U.S. Pat. No. 8,754,359, issued Jun. 17, 2014), Ser. No. 12/633,318, filed Dec. 8, 2009 (now U.S. Pat. No. 8,519,379, issued Aug. 27, 2013), Ser. No. 13/975,553, filed Aug. 26, 2013 (now U.S. Pat. No. 8,710,488, issued Apr. 29, 2014), Ser. No. 12/633,313, filed Dec. 8, 2009, Ser. No. 12/633,305, filed Dec. 8, 2009 (now U.S. Pat. No. 8,299,472, issued Oct. 30, 2012), Ser. No. 13/543,556, filed Jul. 6, 2012 (now U.S. Pat. No. 8,766,272, issued Jul. 1, 2014), Ser. No. 14/293,164, filed Jun. 2, 2014, Ser. No. 12/621,497, filed Nov. 19, 2009 (now abandoned), Ser. No. 12/633,297, filed Dec. 8, 2009 (now U.S. Pat. No. 8,889,455, issued Nov. 18, 2014), Ser. No. 14/501,983 filed Sep. 30, 2014, Ser. No. 12/982,269, filed Dec. 29, 2010, Ser. No. 12/966,573, filed Dec. 13, 2010 (now U.S. Pat. No. 8,866,065, issued Oct. 21, 2014), Ser. No. 14/503,598, filed Oct. 1, 2014, Ser. No. 12/967,880, filed Dec. 14, 2010 (now U.S. Pat. No. 8,748,799, issued Jun. 10, 2014), Ser. No. 14/291,888, filed May 30, 2014, Ser. No. 12/966,514, filed Dec. 13, 2010, Ser. No. 12/974,499, filed Dec. 21, 2010 (now U.S. Pat. No. 8,507,840, issued Aug. 13, 2013), Ser. No. 12/966,535, filed Dec. 13, 2010 (now U.S. Pat. No. 8,890,271, issued Nov. 18, 2014), Ser. No. 12/910,664, filed Oct. 22, 2010 (now U.S. Pat. No. 9,000,353 issued Apr. 7, 2015), Ser. No. 14/632,739, filed Feb. 26, 2015, Ser. No. 12/945,492, filed Nov. 12, 2010, Ser. No. 13/047,392, filed Mar. 14, 2011 (now U.S. Pat. No. 8,835,831, issued Sep. 16, 2014), Ser. No. 14/450,812, filed Aug. 4, 2014, Ser. No. 13/048,635, filed Mar. 15, 2011 (now U.S. Pat. No. 8,835,905, issued Sep. 16, 2014), Ser. No. 13/106,851, filed May 12, 2011, Ser. No. 13/288,131, filed Nov. 3, 2011, Ser. No. 14/334,848, filed Jul. 18, 2014, Ser. No. 14/032,166, filed Sep. 19, 2013, Ser. No. 13/543,307, filed Jul. 6, 2012, Ser. No. 13/963,847, filed Aug. 9, 2013, Ser. No. 13/693,207, filed Dec. 4, 2012, 61/869,727, filed Aug. 25, 2013, Ser. No. 14/322,503, filed Jul. 2, 2014, and Ser. No. 14/311,954, filed Jun. 23, 2014, Ser. No. 14/563,781, filed Dec. 8, 2014, 61/968,816, filed Mar. 21, 2014, Ser. No. 14/516,402, filed Oct. 16, 2014, Ser. No. 14/516,162, filed Oct. 16, 2014, and 62/161,485, filed May 14, 2015 are each hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
• A photovoltaic device, also called a solar cell is a solid state device that converts the energy of sunlight directly into electricity by the photovoltaic effect. Assemblies of cells are used to make solar modules, also known as solar panels. The energy generated from these solar modules, referred to as solar power, is an example of solar energy.
• The photovoltaic effect is the creation of a voltage (or a corresponding electric current) in a material upon exposure to light. Though the photovoltaic effect is directly related to the photoelectric effect, the two processes are different and should be distinguished. In the photoelectric effect, electrons are ejected from a material's surface upon exposure to radiation of sufficient energy. The photovoltaic effect is different in that the generated electrons are transferred between different bands (i.e. from the valence to conduction bands) within the material, resulting in the buildup of a voltage between two electrodes.
• Photovoltaics is a method for generating electric power by using solar cells to convert energy from the sun into electricity. The photovoltaic effect refers to photons of light-packets of solar energy-knocking electrons into a higher state of energy to create electricity. At higher state of energy, the electron is able to escape from its normal position associated with a single atom in the semiconductor to become part of the current in an electrical circuit. These photons contain different amounts of energy that correspond to the different wavelengths of the solar spectrum. When photons strike a PV cell, they may be reflected or absorbed, or they may pass right through. The absorbed photons can generate electricity. The term photovoltaic denotes the unbiased operating mode of a photodiode in which current through the device is entirely due to the light energy. Virtually all photovoltaic devices are some type of photodiode.
• A conventional solar cell often has opaque electrodes on a surface that receives light. Any light incident on such opaque electrodes is either reflected away from the solar cell or absorbed by the opaque electrodes, and thus does not contribute to generation of electricity. Therefore, a photovoltaic device that does not have this drawback is desired.
BRIEF SUMMARY OF THE INVENTION
• Described herein is a photovoltaic device operable to convert light to electricity, comprising a substrate, a plurality of structures essentially perpendicular to the substrate, one or more recesses between the structures, each recess having a sidewall and a bottom wall, and a planar reflective layer disposed on the bottom wall of each recess, wherein the structures comprise a single semiconductor material; the sidewall of each recess is free of the planar reflective layer; and each recess is filled with a transparent material. Unlike a conventional solar cell, light incident on the planar reflective layer is not wasted but reflected to the structures to be absorbed and converted to electricity. This photovoltaic device can also be used as a photo detector.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1A is a schematic cross sectional view of a photovoltaic device according to an embodiment.
• FIG. 1B is a process of manufacturing the photovoltaic device ofFIG. 1A, according to an embodiment.
• FIG. 2A is a schematic cross sectional view of a photovoltaic device according to an embodiment.
• FIG. 2B is a process of manufacturing the photovoltaic device ofFIG. 2A, according to an embodiment.
• FIG. 3A is a schematic cross sectional view of a photovoltaic device according to an embodiment.
• FIG. 3B is a process of manufacturing the photovoltaic device ofFIG. 3A, according to an embodiment.
• FIG. 4A shows a method of print coating a resist layer, according to an embodiment.
• FIG. 4B shows a method of print coating a resist layer, according to another embodiment.
• FIG. 5 shows a schematic of light concentration in the structures of the photovoltaic device.
• FIG. 6 shows an exemplary top cross sectional view of the photovoltaic device.
• FIG. 7 shows an exemplary perspective view of the photovoltaic device.
• FIGS. 8A-8C shows schematics of drawing electrical current from the photovoltaic devices ofFIG. 1A,FIG. 2A andFIG. 3A, respectively.
• FIG. 9 shows a top view of an alternative stripe-shaped structures of the photovoltaic device.
• FIG. 10 shows a top view of an alternative mesh-shaped structures of the photovoltaic device.
• FIG. 11A andFIG. 11B show a process of making vias.
• FIG. 12A andFIG. 12B show top views of exemplary vias.
DETAILED DESCRIPTION OF THE INVENTION
• Described herein is a photovoltaic device operable to convert light to electricity, comprising a substrate, a plurality of structures essentially perpendicular to the substrate, one or more recesses between the structures, each recess having a sidewall and a bottom wall, and a planar reflective layer disposed on the bottom wall of each recess, wherein the structures comprise a single semiconductor material; the sidewall of each recess is free of the planar reflective layer; and each recess is filled with a transparent material. The term “photovoltaic device” as used herein means a device that can generate electrical power by converting light such as solar radiation into electricity. That the structures are single crystalline as used herein means that the crystal lattice of the entire structures is continuous and unbroken throughout the entire structures, with no grain boundaries therein. An electrically conductive material can be a material with essentially zero band gap. The electrical conductivity of an electrically conductive material is generally above 10³S/cm. A semiconductor can be a material with a finite band gap upto about 3 eV and general has an electrical conductivity in the range of 10³to 10⁻⁸S/cm. An electrically insulating material can be a material with a band gap greater than about 3 eV and generally has an electrical conductivity below 10⁻⁸S/cm. The term “structures essentially perpendicular to the substrate” as used herein means that angles between the structures and the substrate are from 85° to 90°. The term “recess” as used herein means a hollow space in the substrate and is open to a space outside the substrate.
• According to an embodiment, the single semiconductor material is selected from a group consisting of silicon, germanium, group III-V compound materials, group II-VI compound materials, and quaternary materials. A group III-V compound material as used herein means a compound consisting of a group III element and a group V element. A group III element can be B, Al, Ga, In, Tl, Sc, Y, the lanthanide series of elements and the actinide series of elements. A group V element can be V, Nb, Ta, Db, N, P, As, Sb and Bi. A group II-VI compound material as used herein means a compound consisting of a group II element and a group VI element. A group II element can be Be, Mg, Ca, Sr, Ba and Ra. A group VI element can be Cr, Mo, W, Sg, O, S, Se, Te, and Po. A quaternary material is a compound consisting of four elements.
• According to an embodiment, the structures are cylinders or prisms with a cross-section selected from a group consisting of elliptical, circular, rectangular, and polygonal cross-sections, strips, or a mesh. The term “mesh” as used herein means a web-like pattern or construction.
• According to an embodiment, the structures are pillars with diameters from 50 nm to 5000 nm, heights from 1000 nm to 20000 nm, a center-to-center distance between two closest pillars of 300 nm to 15000 nm.
• According to an embodiment, the structures have an overhanging portion along an entire contour of a top surface of the structures. The term “overhanging portion” as used herein means a portion of the structures that project over the sidewall of the recesses. The term “contour of a top surface of the structures” as used herein means the edge of the top surface of the structures. The top surface of the structures can be broken by the recesses. An edge of the top surface is the boundary on the top surface between the structures and the recesses.
• According to an embodiment, each recess has a rounded or beveled inner edge between the sidewall and the bottom wall thereof.
• According to an embodiment, the planar reflective layer is a material selected from a group consisting of ZnO, Al, Au, Ag, Pd, Cr, Cu, Ti, Ni and a combination thereof the planar reflective layer is an electrically conductive material; the planar reflective layer is a metal; the planar reflective layer has a reflectance (i.e., the fraction of incident electromagnetic power that is reflected) of at least 50% for visible light (i.e., light have a wavelength from 390 to 750 nm) of any wavelength; the planar reflective layer has a thickness of at least 5 nm; the planar reflective layers in all the recesses are connected; the planar reflective layer is functional to reflect light incident thereon to the structures so that the light is absorbed by the structures; and/or the planar reflective layer is functional as an electrode of the photovoltaic device. The term “electrode” as used herein means a conductor used to establish electrical contact with the photovoltaic device.
• According to an embodiment, the substrate has a flat surface opposite the structures.
• According to an embodiment, the flat surface has a doped layer and optionally a metal layer metal layer disposed on and forming an Ohmic contact with the doped layer. An Ohmic contact is a region a current-voltage (I-V) curve across which is linear and symmetric.
• According to an embodiment, total area of the planar reflective layer is at least 40% of a surface area of the flat surface.
• According to an embodiment, the substrate has a thickness of at least 50 microns.
• According to an embodiment, the structures are pillars arranged in an array; each structure is about 5 microns in height; a pitch of the structures is from 300 nm to 15 microns.
• According to an embodiment, the transparent material has a surface coextensive with a top surface of the structures; the transparent material is substantially transparent to visible light with a transmittance of at least 50%; the transparent material is an electrically conductive material; the transparent material is a transparent conductive oxide; the transparent material forms an Ohmic contact with the planar reflective layer; and/or the transparent material is functional as an electrode of the photovoltaic device.
• According to an embodiment, the photovoltaic device further comprises an electrode layer and optionally a coupling layer, wherein: the electrode layer is disposed on the transparent material and the structures; the electrode layer is the same material as the transparent material or different material from the transparent material; the electrode layer is substantially transparent to visible light with a transmittance of at least 50%; the electrode layer is an electrically conductive material; the electrode layer is a transparent conductive oxide; the electrode layer is functional as an electrode of the photovoltaic device; and/or the coupling layer is disposed on the electrode layer and only above a top surface of the structures. The term “coupling layer” as used herein means a layer effective to guide light into the structures.
• According to an embodiment, the photovoltaic device further comprises a passivation layer and optionally a coupling layer, wherein: the passivation layer is disposed on the sidewall, and on the bottom wall under the planar reflective layer; a top surface of the structures is free of the passivation layer; and the passivation layer is effective to passivate the sidewall and the bottom wall; and/or each of the structures has a top portion and a bottom portion having dissimilar conduction types. The terms “passivation” and “passivate” as used herein means a process of eliminating dangling bonds (i.e., unsatisfied valence on immobilized atoms).
• According to an embodiment further of the embodiment, the structures have one of the following doping profiles: (i) the bottom portion is intrinsic and the top portion is p type; (ii) the bottom portion is n type and the top portion is p type; (iii) the bottom portion is intrinsic and the top portion is n type; (iv) the bottom portion is p type and the top portion is n type.
• According to an embodiment further of the embodiment, the top portion has a height of 1 micron to 20 micron; the passivation layer has a thickness from 1 nm to 100 nm; the passivation layer is an electrically insulating material selected from a group consisting of HfO₂, SiO₂, Si₃N₄, Al₂O₃, an organic molecule monolayer; the doped layer has an opposite conduction type from the top portion; the doped layer is electrically connected to the bottom portion; the doped layer, the bottom portion and the top portion form a p-n or p-i-n junction; the coupling layer is the same material as the cladding layer or different material from the cladding layer; and/or a refractive index of the structures n₁, a refractive index of the transparent material n₂, a refractive index of the coupling layer n₃, satisfy relations of n₁>n₂and n₁>n₃.
• According to an embodiment, the photovoltaic device further comprises a junction layer wherein: the junction layer is a doped semiconductor; the junction layer is disposed on the sidewall, on the bottom wall under the planar reflective layer, and on a top surface of the structures; and the junction layer is effective to passivate the sidewall and the bottom wall.
• According to an embodiment further of the embodiment, the structures are a doped semiconductor and the structures and the junction layer have opposite conduction types; or the structures are an intrinsic semiconductor. An intrinsic semiconductor, also called an undoped semiconductor or i-type semiconductor, is a substantially pure semiconductor without any significant dopant species present. The number of charge carriers is therefore determined by the properties of the material itself instead of the amount of impurities. External electric field is not substantially screened in an intrinsic semiconductor because the intrinsic semiconductor does not have mobile electrons or holes supplied by dopants. It is thus more efficient to remove and/or collect electrons and/or holes generated in an intrinsic semiconductor by photons, using an external electric field.
• According to an embodiment further of the embodiment, the junction layer has a thickness from 5 nm to 100 nm; the doped layer has an opposite conduction type from the junction layer; the doped layer is electrically connected to each of the structures; the doped layer, the structures and the junction layer form a p-n or p-i-n junction; the cladding layer has a thickness of about 175 nm; the coupling layer is the same material as the cladding layer or different material from the cladding layer; and/or a refractive index of the structures n₁, a refractive index of the transparent material n₂, a refractive index of the coupling layer n₃, satisfy relations of n₁>n₂and n₁>n₃.
• According to an embodiment, each of the structures has a top portion and a bottom portion having dissimilar conduction types.
• According to an embodiment further of the embodiment, the top portion and the junction layer have the same conduction type; and the structures have one of the following doping profiles: (i) the bottom portion is intrinsic and the top portion is p type; (ii) the bottom portion is n type and the top portion is p type; (iii) the bottom portion is intrinsic and the top portion is n type; (iv) the bottom portion is p type and the top portion is n type.
• According to an embodiment further of the embodiment, the junction layer has a thickness from 5 nm to 100 nm; the doped layer has an opposite conduction type from the junction layer; the doped layer is electrically connected to the bottom portion of each of the structures; the doped layer, the bottom portion, the top portion and the junction layer form a p-n or p-i-n junction; the coupling layer is the same material as the cladding layer or different material from the cladding layer; and/or a refractive index of the structures n₁, a refractive index of the transparent material n₂, a refractive index of the coupling layer n₃, satisfy relations of n₁>n₂and n₁>n₃.
• According to an embodiment, a method of making the photovoltaic device comprises: generating a pattern of openings in a resist layer using a lithography technique; forming the structures and recesses by etching the substrate; depositing the planar reflective layer such that the sidewall of each recess is free of the planar reflective layer; depositing the transparent material such that each recess is completely filled by the transparent material. A resist layer as used herein means a thin layer used to transfer a pattern to the substrate which the resist layer is deposited upon. A resist layer can be patterned via lithography to form a (sub)micrometer-scale, temporary mask that protects selected areas of the underlying substrate during subsequent processing steps. The resist is generally proprietary mixtures of a polymer or its precursor and other small molecules (e.g. photoacid generators) that have been specially formulated for a given lithography technology. Resists used during photolithography are called photoresists. Resists used during e-beam lithography are called e-beam resists. A lithography technique can be photolithography, e-beam lithography, holographic lithography. Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photo mask to a light-sensitive chemical photo resist, or simply “resist,” on the substrate. A series of chemical treatments then engraves the exposure pattern into the material underneath the photo resist. In complex integrated circuits, for example a modern CMOS, a wafer will go through the photolithographic cycle up to 50 times. E-beam lithography is the practice of scanning a beam of electrons in a patterned fashion across a surface covered with a film (called the resist), (“exposing” the resist) and of selectively removing either exposed or non-exposed regions of the resist (“developing”). The purpose, as with photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate material, often by etching. It was developed for manufacturing integrated circuits, and is also used for creating nanotechnology artifacts.
• According to an embodiment, the method of making the photovoltaic device further comprises: planarizing the transparent material; coating the substrate with the resist layer; developing (i.e., selectively removing either exposed or non-exposed regions of the resist) the pattern in the resist layer; depositing a mask layer; and lifting off the resist layer. A mask layer as used herein means a layer that protects an underlying portion of the substrate from being etched.
• According to an embodiment, the method of making the photovoltaic device further comprises ion implantation or depositing a dopant layer. A dopant, also called a doping agent, is a trace impurity element that is inserted into a substance (in very low concentrations) in order to alter the electrical properties or the optical properties of the substance. Ion implantation is process by which ions of a material can be implanted into another solid, thereby changing the physical properties of the solid. Ion implantation is used in semiconductor device fabrication and in metal finishing, as well as various applications in materials science research. The ions introduce both a chemical change in the target, in that they can be a different element than the target or induce a nuclear transmutation, and a structural change, in that the crystal structure of the target can be damaged or even destroyed by the energetic collision cascades.
• According to an embodiment, the structures and recesses are formed by deep etch followed by isotropic etch. A deep etch is a highly anisotropic etch process used to create deep, steep-sided holes and trenches in wafers, with aspect ratios of often 20:1 or more. An exemplary deep etch is the Bosch process. The Bosch process, also known as pulsed or time-multiplexed etching, alternates repeatedly between two modes to achieve nearly vertical structures: 1. a standard, nearly isotropic plasma etch, wherein the plasma contains some ions, which attack the wafer from a nearly vertical direction (For silicon, this often uses sulfur hexafluoride (SF₆)); 2. deposition of a chemically inert passivation layer (for instance, C₄F₈source gas yields a substance similar to Teflon). Each phase lasts for several seconds. The passivation layer protects the entire substrate from further chemical attack and prevents further etching. However, during the etching phase, the directional ions that bombard the substrate attack the passivation layer at the bottom of the trench (but not along the sides). They collide with it and sputter it off, exposing the substrate to the chemical etchant. These etch/deposit steps are repeated many times over resulting in a large number of very small isotropic etch steps taking place only at the bottom of the etched pits. To etch through a 0.5 mm silicon wafer, for example, 100-1000 etch/deposit steps are needed. The two-phase process causes the sidewalls to undulate with an amplitude of about 100-500 nm. The cycle time can be adjusted: short cycles yield smoother walls, and long cycles yield a higher etch rate. Isotropic etch is non-directional removal of material from a substrate via a chemical process using an etchant substance. The etchant may be a corrosive liquid or a chemically active ionized gas, known as a plasma.
• According to an embodiment, the method of making the photovoltaic device further comprises applying a resist layer by a print coating method, the print coating method comprising: coating a roller of a flexible material with a resist layer; transferring the resist layer to a surface of a substrate by rolling the roller on the surface, wherein the surface is flat or textured. According to an embodiment, the roller is polydimethylsiloxane.
• According to an embodiment, the method of making the photovoltaic device further comprises applying a resist layer by a print coating method, the print coating method comprising: coating a stamp of a flexible material with a resist layer; transferring the resist layer to a surface of a substrate by pressing the stamp on the surface, wherein the surface is flat or textured. According to an embodiment, the stamp is polydimethylsiloxane.
• According to an embodiment, a method of converting light to electricity comprises: exposing the photovoltaic device to light; drawing an electrical current from the photovoltaic device. The electrical current can be drawn from the planar reflective layer.
• According to an embodiment, a photo detector comprises the photovoltaic device, wherein the photo detector is functional to output an electrical signal when exposed to light.
• According to an embodiment, a method of detecting light comprises exposing the photovoltaic device to light; measuring an electrical signal from the photovoltaic device. The electrical signal can be an electrical current, an electrical voltage, an electrical conductance and/or an electrical resistance.
• According to an embodiment, photovoltaic devices produce direct current electricity from sun light, which can be used to power equipment or to recharge a battery. A practical application of photovoltaics was to power orbiting satellites and other spacecraft, but today the majority of photovoltaic modules are used for grid connected power generation. In this case an inverter is required to convert the DC to AC. There is a smaller market for off-grid power for remote dwellings, boats, recreational vehicles, electric cars, roadside emergency telephones, remote sensing, and cathodic protection of pipelines. In most photovoltaic applications the radiation is sunlight and for this reason the devices are known as solar cells. In the case of a p-n junction solar cell, illumination of the material results in the creation of an electric current as excited electrons and the remaining holes are swept in different directions by the built-in electric field of the depletion region. Solar cells are often electrically connected and encapsulated as a module. Photovoltaic modules often have a sheet of glass on the front (sun up) side, allowing light to pass while protecting the semiconductor wafers from the elements (rain, hail, etc.). Solar cells are also usually connected in series in modules, creating an additive voltage. Connecting cells in parallel will yield a higher current. Modules are then interconnected, in series or parallel, or both, to create an array with the desired peak DC voltage and current.
• According to an embodiment, the photovoltaic device can also be associated with buildings: either integrated into them, mounted on them or mounted nearby on the ground. The photovoltaic device can be retrofitted into existing buildings, usually mounted on top of the existing roof structure or on the existing walls. Alternatively, the photovoltaic device can be located separately from the building but connected by cable to supply power for the building. The photovoltaic device can be used as as a principal or ancillary source of electrical power. The photovoltaic device can be incorporated into the roof or walls of a building.
• According to an embodiment, the photovoltaic device can also be used for space applications such as in satellites, spacecrafts, space stations, etc. The photovoltaic device can be used as main or auxiliary power sources for land vehicles, marine vehicles (boats) and trains. Other applications include road signs, surveillance cameras, parking meters, personal mobile electronics (e.g., cell phones, smart phones, laptop computers, personal media players).
Examples
• FIG. 1A shows a schematic cross-section of aphotovoltaic device100, according to an embodiment. Thephotovoltaic device100 comprises asubstrate105, a plurality ofstructures120 essentially perpendicular to thesubstrate105, one ormore recesses130 between thestructures120, and anelectrode layer180. Eachrecess130 is filled with atransparent material140. Eachrecess130 has asidewall130aand abottom wall130b. Thesidewall130aand thebottom wall130bboth have apassivation layer131. Atop surface120aof thestructures120 is free of thepassivation layer131. Thebottom wall130bhas a planarreflective layer132 disposed on thepassivation layer131. Thesidewall130adoes not have any planar reflective layer. Eachstructure120 has atop portion121 and abottom portion122, thetop portion121 and thebottom portion122 having dissimilar conduction types. Thetransparent material140 preferably has a surface coextensive with thetop surface120aof thestructures120. Thephotovoltaic device100 further comprises anelectrode layer180 disposed on thetransparent material140 and thestructures120. The term “dissimilar conduction types” as used herein means that thetop portion121 and thebottom portion122 cannot be both p type, or both n type. Thestructures120 can have one of the following four doping profiles (i.e., doping level distribution): (i) thebottom portion122 is intrinsic and thetop portion121 is p type; (ii) thebottom portion122 is n type and thetop portion121 is p type; (iii) thebottom portion122 is intrinsic and thetop portion121 is n type; (iv) thebottom portion122 is p type and thetop portion121 is n type. Thetop portion121 can have a doping profile with decreasing doping levels in a direction from thetop surface120ato thebottom portion122. Thestructures120 are a single semiconductor material. Thephotovoltaic device100 can further comprise acoupling layer160 disposed on theelectrode layer180 and only directly above thetop surface120a.
• Thestructures120 can comprise any suitable single semiconductor material, such as silicon, germanium, group III-V compound materials (e.g., gallium arsenide, gallium nitride, etc.), group II-VI compound materials (e.g., cadmium selenide, cadmium sulfide, cadmium telluride, zinc oxide, zinc selenide, etc.), quaternary materials (e.g., copper indium gallium selenide).
• Thestructures120 can have any cross-sectional shape. For example, thestructures120 can be cylinders or prisms with elliptical, circular, rectangular, polygonal cross-sections. Thestructures120 can also be strips, or a mesh as shown inFIG. 10. According to one embodiment, thestructures120 are pillars with diameters from 50 nm to 5000 nm, heights from 1000 nm to 20000 nm, a center-to-center distance between two closest pillars of 300 nm to 15000 nm. Thetop portion121 preferably has a height of 1 micron to 20 micron. Thetop portion121 preferably has a gradient of doping levels, with a highest doping level at thetop surface120a. Preferably, thestructures120 have an overhangingportion124 along an entire contour of thetop surface120aof thestructures120.
• Eachrecess130 preferably has a rounded or beveled inner edge between thesidewall130aand thebottom wall130b.
• Thepassivation layer131 can be any suitable electrically insulating material, such as HfO₂, SiO₂, Si₃N₄, Al₂O₃, an organic molecule monolayer, etc. Thepassivation layer131 can have any suitable thickness, such as from 1 nm to 100 nm. Thepassivation layer131 is effective to passivate thesidewall130aand thebottom wall130b.
• The planarreflective layer132 can be any suitable material, such as ZnO, Al, Au, Ag, Pd, Cr, Cu, Ti, Ni, a combination thereof, etc. The planarreflective layer132 preferably is an electrically conductive material, more preferably a metal. The planarreflective layer132 preferably has a reflectance of at least 50%, more preferably has a reflectance of at least 70%, most preferably has a reflectance of at least 90%, for visible light of any wavelength. The planarreflective layer132 has a thickness of preferably at least 5 nm, more preferably at least 20 nm. The planarreflective layer132 in all therecesses130 is preferably connected. The planarreflective layer132 is functional to reflect light incident thereon to thestructures120 so the light is absorbed by thestructures120. A photovoltaic device often has opaque electrodes on a surface that receives light. Any light incident on such opaque electrodes is either reflected away from the photovoltaic device or absorbed by the opaque electrodes, and thus does not contribute to generation of electricity. The planarreflective layer132 preferably is functional as an electrode of thephotovoltaic device100.
• Thetransparent material140 is substantially transparent to visible light, preferably with a transmittance of at least 50%, more preferably at least 70%, most preferably at least 90%. Thetransparent material140 can be an electrically conductive material. Thetransparent material140 preferably is a transparent conductive oxide, such as ITO (indium tin oxide), AZO (aluminum doped zinc oxide), ZIO (zinc indium oxide), ZTO (zinc tin oxide), etc. Thetransparent material140 preferably forms an Ohmic contact with the planarreflective layer132. Thetransparent material140 preferably is functional as an electrode of thephotovoltaic device100. Thetransparent material140 can also be a suitable electrically insulating material such as SiO₂or a polymer.
• Thesubstrate105 preferably has aflat surface150 opposite thestructures120. Theflat surface150 can have a dopedlayer151 of the opposite conduction type from thetop portions121, i.e. if thetop portion121 is n type, the dopedlayer151 is p type; if thetop portion121 is p type, the dopedlayer151 is n type. The dopedlayer151 is electrically connected to thebottom portion122 of each of thestructures120. If thebottom portion122 is intrinsic, thetop portion121, thebottom portion122 and the dopedlayer151 form a p-i-n junction. If thebottom portion122 is n type or p type, thetop portion121 and thebottom portion122 form a p-n junction. Theflat surface150 can also have ametal layer152 disposed on the dopedlayer151. Themetal layer152 forms an Ohmic contact with the dopedlayer151. Thesubstrate105 preferably has a thickness of at least 50 microns. Total area of the planarreflective layer132 is preferable at least 40% of a surface area of theflat surface150.
• Theelectrode layer180 can be the same material as thetransparent material140 or different material from thetransparent material140. Theelectrode layer180 is substantially transparent to visible light, preferably with a transmittance of at least 50%, more preferably at least 70%, most preferably at least 90%. Theelectrode layer180 is an electrically conductive material. Theelectrode layer180 preferably is a transparent conductive oxide, such as ITO (indium tin oxide), AZO (aluminum doped zinc oxide), ZIO (zinc indium oxide), ZTO (zinc tin oxide), etc. Theelectrode layer180 preferably forms an Ohmic contact with thetop portions121 of thestructures120. Theelectrode layer180 preferably is functional as an electrode of thephotovoltaic device100.
• Thecoupling layer160 can be the same material as thetransparent material140 or different material from thetransparent material140. As shown inFIG. 5, refractive index of the structure120 n₁, refractive index of the transparent material140 n₂, refractive index of the coupling layer160 n₃, preferably satisfy relations of n₁>n₂and n₁>n₃, which lead to enhanced light concentration in thestructures120.
• In one embodiment, thestructures120 are pillars arranged in an array, such as a rectangular array, a hexagonal array, a square array, concentric ring. Eachstructure120 is about 5 microns in height. A pitch of thestructures120 is from 300 nm to 15 microns. The term “pitch” is defined as a distance of astructure120 to a nearest neighbor of thestructure120 along a direction parallel to thesubstrate105. The term “array” as used herein means a spatial arrangement having a particular order.
• A method of making thephotovoltaic device100 as shown inFIG. 1B, according to an embodiment, comprises the following steps:
• Instep1000, providing thesubstrate105 having the dopedlayer151 and anepi layer11 disposed on the dopedlayer151. Epitaxy is a process of growing a crystal of a particular orientation on top of another crystal, where the orientation is determined by the underlying crystal. The term “epi layer” as used herein means a layer grown by epitaxy.
• Instep1001, anupper layer12 of theepi layer11 is doped by ion implantation.
• Instep1002, a resistlayer14 is applied on the dopedupper layer12. The resistlayer14 can be applied by spin coating. The resistlayer14 can be a photo resist or an e-beam resist.
• Instep1003, lithography is performed. The resistlayer14 now has a pattern of openings in which the dopedupper layer12 is exposed. Shapes and locations of the openings correspond to the shapes and locations of therecesses130. The resolution of the lithography is limited by the wavelength of the radiation used. Photolithography tools using deep ultraviolet (DUV) light with wavelengths of approximately 248 and 193 nm, allows minimum feature sizes down to about 50 nm. E-beam lithography tools using electron energy of 1 keV to 50 keV allows minimum feature sizes down to a few nanometers.
• Instep1004, amask layer15 is deposited. The deposition can be done using a technique such as thermal evaporation, e-beam evaporation, sputtering. Themask layer15 can be a metal such as Cr or Al, or a dielectric such as SiO₂or Si₃N₄. The thickness of themask layer15 can be determined by a depth of therecesses130 and etching selectivity (i.e., ratio of etching rates of themask layer15 and the substrate105).
• Instep1005, remainder of the resistlayer14 is lift off by a suitable solvent or ashed in a resist asher to remove anymask layer15 support thereon. A portion of themask layer15 in the openings of the resistlayer14 is retained. A portion of the dopedupper layer12 is now exposed through the retainedmask layer15.
• Instep1006, the exposed portion of the dopedupper layer12 and the portion of theepi layer11 directly therebelow are deep etched to a desired depth (e.g., 1 to 20 microns) followed by an isotropic etch, until theepi layer11 is partially exposed, to form thestructures120 with the overhangingportion124 and therecesses130 with the beveled inner edge. Each of thestructures120 now has thetop portion121 which is part of the upper dopedlayer12 and abottom portion122 which is part of theepi layer11. Deep etching includes alternating deposition and etch steps and can lead to “scalloping” on thesidewall130aof therecesses130, i.e. thesidewall130ais not smooth. Thesidewall130acan be smoothed by thermal annealing or dipping into an etchant such as potassium hydroxide (KOH) followed by rinsing. The deep etching can use gases such as C₄F₈and SF₆.
• Instep1007, thepassivation layer131 is conformally (i.e., isotropically) deposited on surfaces of therecesses130 and atop surface15aof the retainedmask layer15. A conformal layer, such as thepassivation131, is a layer that covers a morphologically uneven surface and has an essentially uniform thickness. Thepassivation layer131 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition.
• Instep1008, a resistlayer16 is selectively applied such that thesidewall130aandbottom wall130bof the recesses are free of the resistlayer16 and atop surface131aof thepassivation layer131 is completely covered by the resistlayer16. The resistlayer16 can be selectively applied by a suitable method such as a print coating method detailed hereinbelow according an embodiment.
• Instep1009, ametal layer17 is anisotropically deposited (i.e., non-conformally) such that the resistlayer16 and thebottom wall130bare covered by themetal layer17 while thesidewall130ais free of themetal layer17. Themetal layer17 can be deposited by a suitable technique such as thermal evaporation, e-beam evaporation. Themetal17 can be any suitable metal such as aluminum.
• Instep1010, the resistlayer16 is lift off by a suitable solvent or ashed in a resist asher to remove anymetal layer17 support thereon. Thetop surface131aof thepassivation layer131 is now exposed.
• Instep1011, thetop surface131aof thepassivation layer131 is selected removed by a suitable technique such as ion milling, dry etching, sputtering, while leaving thepassivation layer131 on thesidewall130aandbottom wall130bof therecesses130 intact. Thetop surface15aof the retainedmask layer15 is now exposed. Themetal layer17 on thebottom wall130bprotects thepassivation layer131 underneath from being removed.
• Instep1012, the retainedmask layer15 and themetal layer17 are removed by a suitable technique such as wet etch in a suitable etchant. Now thetop surface120aof thestructures120 is exposed.
• Instep1013, a resistlayer18 is selectively applied such that thesidewall130aandbottom wall130bof the recesses are free of the resistlayer18 and thetop surface120aof thestructures120 is completely covered by the resistlayer18. The resistlayer18 can be selectively applied by a suitable method such as the print coating method detailed hereinbelow according an embodiment.
• Instep1014, the planarreflective layer132 is anisotropically deposited (i.e., non-conformally) such that the resistlayer18 and thebottom wall130bare covered by the planarreflective layer132 while thesidewall130ais free of the planarreflective layer132. The planarreflective layer132 can be deposited by a suitable technique such as thermal evaporation, e-beam evaporation. The planarreflective layer132 can be any suitable material such as silver.
• Instep1015, the resistlayer18 is lift off by a suitable solvent or ashed in a resist asher to remove any portion of the planarreflective layer132 support thereon. Thetop surface120aof thestructures120 is now exposed.
• Instep1016, thetransparent material140 is deposited such that the planarreflective layer132, thepassivation layer131 and thetop surface120aare completely covered and therecesses130 are completely filled. Thetransparent material140 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition.
• Instep1017, thetransparent material140 is planarized using a suitable technique such as chemical mechanical polishing/planarization (CMP) such that thetransparent material140 has a surface coextensive with thetop surface120aof thestructures120 and thetop surface120ais exposed.
• Instep1018, theelectrode layer180 is deposited using a suitable technique such as thermal evaporation, e-beam evaporation, sputtering, onto thetransparent material140 and thetop surfaces120a. Thecoupling layer160 can be then deposited using a suitable technique such as sputtering, thermal evaporation or e-beam evaporation onto theelectrode layer180.
• Instep1019, themetal layer152 is deposited on the dopedlayer151.
• The method can further comprise one or more steps of thermal annealing.
• FIG. 2A shows a schematic cross-section of aphotovoltaic device200, according to another embodiment. Thephotovoltaic device200 comprises asubstrate205, a plurality ofstructures220 essentially perpendicular to thesubstrate205, one ormore recesses230 between thestructures220 and anelectrode layer280. Eachrecess230 is filled with atransparent material240. Eachrecess230 has asidewall230aand abottom wall230b. Thesidewall230a, thebottom wall230bof eachrecess230 and atop surface220aof thestructures220 have ajunction layer231 disposed thereon. Thejunction layer231 is a doped semiconductor. Thebottom wall230bhas a planarreflective layer232 disposed on thejunction layer231. Thesidewall230adoes not have any planar reflective layer. Thestructures220 are a single semiconductor material. Thestructure220 can be an intrinsic semiconductor or a doped semiconductor. If thestructure220 is a doped semiconductor, thestructures220 and thejunction layer231 have opposite conduction types, i.e., if thestructures220 are p type, thejunction layer231 is n type; if thestructures220 are n type, thejunction layer231 is p type. Thetransparent material240 preferably has a surface coextensive with thetop surface220aof thestructures220. Thephotovoltaic device200 further comprises anelectrode layer280 disposed on thetransparent material240 and thestructures220. Thephotovoltaic device200 can further comprise acoupling layer260 disposed on theelectrode layer280 and only directly above thetop surface220a.
• Thestructures220 can comprise any suitable single semiconductor material, such as silicon, germanium, group III-V compound materials (e.g., gallium arsenide, gallium nitride, etc.), group II-VI compound materials (e.g., cadmium selenide, cadmium sulfide, cadmium telluride, zinc oxide, zinc selenide, etc.), quaternary materials (e.g., copper indium gallium selenide).
• Thestructures220 can have any cross-sectional shape. For example, thestructures220 can be cylinders or prisms with elliptical, circular, rectangular, polygonal cross-sections. Thestructures220 can also be strips as shown inFIG. 9, or a mesh as shown inFIG. 10. According to one embodiment, thestructures220 are pillars with diameters from 50 nm to 5000 nm, heights from 1000 nm to 20000 nm, a center-to-center distance between two closest pillars of 300 nm to 15000 nm. Preferably, thestructures220 have an overhangingportion224 along an entire contour of thetop surface220aof thestructures220.
• Eachrecess230 preferably has a rounded or beveled inner edge between thesidewall230aand thebottom wall230b.
• Thejunction layer231 preferably has a thickness from 5 nm to 100 nm. Thejunction layer231 is effective to passivate surfaces of thestructures220.
• The planarreflective layer232 can be any suitable material, such as ZnO, Al, Au, Ag, Pd, Cr, Cu, Ti, Ni, a combination thereof, etc. The planarreflective layer232 preferably is an electrically conductive material, more preferably a metal. The planarreflective layer232 preferably has a reflectance of at least 50%, more preferably has a reflectance of at least 70%, most preferably has a reflectance of at least 90%, for visible light of any wavelength. The planarreflective layer232 has a thickness of preferably at least 5 nm, more preferably at least 20 nm. The planarreflective layer232 in all therecesses230 is preferably connected. The planarreflective layer232 is functional to reflect light incident thereon to thestructures220 so the light is absorbed by thestructures220. The planarreflective layer232 preferably is functional as an electrode of thephotovoltaic device200.
• Thetransparent material240 is substantially transparent to visible light, preferably with a transmittance of at least 50%, more preferably at least 70%, most preferably at least 90%. Thetransparent material240 can be an electrically conductive material. Thetransparent material240 preferably is made of a transparent conductive oxide, such as ITO (indium tin oxide), AZO (aluminum doped zinc oxide), ZIO (zinc indium oxide), ZTO (zinc tin oxide), etc. Thetransparent material240 preferably forms an Ohmic contact with thejunction layer231. Thetransparent material240 preferably forms an Ohmic contact with the planarreflective layer232. Thetransparent material240 preferably is functional as an electrode of thephotovoltaic device200. Thetransparent material140 can also be a suitable electrically insulating material such as SiO₂or a polymer.
• Thesubstrate205 preferably has aflat surface250 opposite thestructures220. Theflat surface250 can have a dopedlayer251 of the opposite conduction type from thejunction layer231, i.e. if thejunction layer231 is n type, the dopedlayer251 is p type; if thejunction layer231 is p type, the dopedlayer251 is n type. The dopedlayer251 is electrically connected to each of thestructures220. If thestructures220 are intrinsic, thejunction layer231, thestructures220 and the dopedlayer251 form a p-i-n junction. If thestructures220 are is n-type or p-type, thejunction layer231 and thestructures220 form a p-n junction. Theflat surface250 can also have ametal layer252 disposed on the dopedlayer251. Themetal layer252 forms an Ohmic contact with the dopedlayer251. Thesubstrate205 preferably has a thickness of at least 50 microns. Total area of the planarreflective layer232 is preferable at least 40% of a surface area of theflat surface250.
• Theelectrode layer280 can be the same material as thetransparent material240 or different material from thetransparent material240. Theelectrode layer280 is substantially transparent to visible light, preferably with a transmittance of at least 50%, more preferably at least 70%, most preferably at least 90%. Theelectrode layer280 is an electrically conductive material. Theelectrode layer280 preferably is a transparent conductive oxide, such as ITO (indium tin oxide), AZO (aluminum doped zinc oxide), ZIO (zinc indium oxide), ZTO (zinc tin oxide), etc. Theelectrode layer280 preferably forms an Ohmic contact with thejunction layer231. Theelectrode layer280 preferably is functional as an electrode of thephotovoltaic device200.
• Thecoupling layer260 can be the same material as thetransparent material240 or different material from thetransparent material240. As shown inFIG. 5, refractive index of the structure220 n₁, refractive index of the transparent material240 n₂, refractive index of the coupling layer260 n₃, preferably satisfy relations of n₁>n₂and n₁>n₃, which lead to enhanced light concentration in thestructures220.
• In one embodiment, thestructures220 are pillars arranged in an array, such as a rectangular array, a hexagonal array, a square array, concentric ring. Each pillar is about 5 microns in height. A pitch of thestructures220 is from 300 nm to 15 microns.
• A method of making thephotovoltaic device200 as shown inFIG. 2B, according to an embodiment, comprises the following steps:
• Instep2000, providing thesubstrate205 having the dopedlayer251 and anepi layer21 disposed on the dopedlayer251.
• Instep2001, a resistlayer24 is applied on theepi layer21. The resistlayer24 can be applied by spin coating. The resistlayer24 can be a photo resist or an e-beam resist.
• Instep2002, lithography is performed. The resistlayer24 now has a pattern of openings in which theepi layer21 is exposed. Shapes and locations of the openings correspond to the shapes and locations of therecesses230. The resolution of the lithography is limited by the wavelength of the radiation used. Photolithography tools using deep ultraviolet (DUV) light with wavelengths of approximately 248 and 193 nm, allows minimum feature sizes down to about 50 nm. E-beam lithography tools using electron energy of 1 keV to 50 keV allows minimum feature sizes down to a few nanometers.
• Instep2003, amask layer25 is deposited. The deposition can be done using a technique such as thermal evaporation, e-beam evaporation, sputtering. Themask layer25 can be a metal such as Cr or Al, or a dielectric such as SiO₂or Si₃N₄. The thickness of themask layer25 can be determined by a depth of therecesses230 and etching selectivity (i.e., ratio of etching rates of themask layer25 and the substrate205).
• Instep2004, remainder of the resistlayer24 is lift off by a suitable solvent or ashed in a resist asher to remove anymask layer25 support thereon. A portion of themask layer25 in the openings of the resistlayer24 is retained. A portion of theepi layer21 is now exposed through the retainedmask layer25.
• Instep2005, the exposed portion of theepi layer21 is deep etched to a desired depth (e.g., 1 to 20 microns) followed by an isotropic etch, to form thestructures220 with the overhangingportion224 and therecesses230 with the beveled inner edge. Deep etching includes alternating deposition and etch steps and can lead to “scalloping” on thesidewall230bof therecesses230, i.e. thesidewall230bis not smooth. Thesidewall230bcan be smoothed by thermal annealing or dipping into an etchant such as potassium hydroxide (KOH) followed by rinsing. The deep etching can use gases such as C₄F₈and SF₆.
• Instep2006, themask layer25 is removed by a suitable such as wet etching with suitable etchant, ion milling, sputtering. Thetop surface220aof thestructures220 is exposed.
• Instep2007, adopant layer22 is conformally (i.e., isotropically) deposited on surfaces of therecesses230 and atop surface220aof thestructures220. Thedopant layer22 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition. Thedopant layer22 can comprise any suitable material such as trimethylboron, triisopropylborane ((C₃H₇)₃B), triethoxyborane ((C₂H₅O)₃B, and/or triisopropoxyborane ((C₃H₇O)₃B. More details can be found in an abstract of a presentation titled “Atomic layer deposition of boron oxide as dopant source for shallow doping of silicon” by Bodo Kalkofen and Edmund P. Burte in the 218th Electrochemical Society Meeting, Oct. 10, 2010-Oct. 15, 2010, which is hereby incorporated by reference in its entirety.
• Instep2008, ashield layer23 is conformally (i.e., isotropically) deposited on surfaces of thedopant layer22. Theshield layer23 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition. Theshield layer23 has a suitable material (such as silicon oxide, silicon nitride) and a suitable thickness (e.g., at least 10 nm, at least 100 nm or at least 1 micron) effective to prevent thedopant layer22 from evaporation instep2009.
• Instep2009, thedopant layer22 is diffused into thesidewall230b, thebottom wall230aand thetop surface220aby thermal annealing, which forms thejunction layer231 thereon. Thermal annealing can be conducted, for example, at about 850° C. for 10 to 30 minutes under a suitable atmosphere (e.g., argon).
• Instep2010, theshield layer23 is removed by a suitable technique such as wet etch using a suitable etchant such as HF. Thejunction layer231 is now exposed.
• Instep2011, a resistlayer26 is selectively applied such that thesidewall230aandbottom wall230bof therecesses230 are free of the resistlayer26 and atop surface231aof thejunction layer231 is completely covered by the resistlayer26. The resistlayer26 can be selectively applied by a suitable method such as the print coating method detailed hereinbelow according an embodiment.
• Instep2012, the planarreflective layer232 is anisotropically deposited (i.e., non-conformally) such that the resistlayer26 and thebottom wall230bare covered by the planarreflective layer232 while thesidewall230ais free of the planarreflective layer232. The planarreflective layer232 can be deposited by a suitable technique such as thermal evaporation, e-beam evaporation. The planarreflective layer232 can be any suitable material such as silver.
• Instep2013, the resistlayer26 is lift off by a suitable solvent or ashed in a resist asher to remove any portion of the planarreflective layer232 support thereon. Thetop surface231aof thejunction layer220 is now exposed.
• Instep2014, thetransparent material240 is deposited such that the planarreflective layer232, thejunction layer231 and thetop surface231aare completely covered and therecesses230 are completely filled. Thetransparent material240 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition.
• Instep2015, thetransparent material240 is planarized using a suitable technique such as CMP such that thetransparent material240 has a surface coextensive with thetop surface220aof thestructures220 and thetop surface231aof thejunction layer231 is exposed.
• Instep2016, theelectrode layer280 is deposited using a suitable technique such as thermal evaporation, e-beam evaporation, sputtering, onto thetransparent material240 and thetop surfaces231a. Thecoupling layer260 can be then deposited using a suitable technique such as sputtering, thermal evaporation or e-beam evaporation onto theelectrode layer280.
• Instep2017, themetal layer252 is deposited on the dopedlayer251.
• The method can further comprise one or more steps of thermal annealing.
• FIG. 3A shows a schematic cross-section of aphotovoltaic device300, according to an embodiment. Thephotovoltaic device300 comprises asubstrate305, a plurality ofstructures320 essentially perpendicular to thesubstrate305, one ormore recesses330 between thestructures320 and anelectrode layer380. Eachrecess330 is filled with atransparent material340. Eachrecess330 has asidewall330aand abottom wall330b. Thesidewall330a, thebottom wall330bof eachrecess330 and atop surfaces320aof thestructures320 have ajunction layer331 disposed thereon. Thejunction layer331 is a doped semiconductor. Thebottom wall330bhas a planarreflective layer332 disposed on thejunction layer331. Thesidewall330adoes not have any planar reflective layer. Eachstructure320 has atop portion321 and abottom portion322. Thestructures320 can have one of the following four doping profiles (i.e., doping level distribution): (i) thebottom portion322 is intrinsic and thetop portion321 is p type; (ii) thebottom portion322 is n type and thetop portion321 is p type; (iii) thebottom portion322 is intrinsic and thetop portion321 is n type; (iv) thebottom portion322 is p type and thetop portion321 is n type. Thetop portion321 can have a doping profile with decreasing doping levels in a direction from thetop surface320ato thebottom portion322. Thestructures320 are a single semiconductor material. Thetop portion321 of thestructures320 and thejunction layer331 are semiconductor materials of the same conduction types, i.e., if thetop portion321 is p type, thejunction layer331 is p type; if thetop portion321 is n type, thejunction layer331 is n type. Thetransparent material340 preferably has a surface coextensive with thetop surface320aof thestructures320. Thephotovoltaic device300 further comprises anelectrode layer380 disposed on thetransparent material340 and thestructures320. Thephotovoltaic device300 can further comprise acoupling layer360 disposed on theelectrode layer280 and only directly above thetop surface320a.
• Thestructures320 can comprise any suitable single semiconductor material, such as silicon, germanium, group III-V compound materials (e.g., gallium arsenide, gallium nitride, etc.), group II-VI compound materials (e.g., cadmium selenide, cadmium sulfide, cadmium telluride, zinc oxide, zinc selenide, etc.), quaternary materials (e.g., copper indium gallium selenide).
• Thestructures320 can have any cross-sectional shape. For example, thestructures320 can be cylinders or prisms with elliptical, circular, rectangular, polygonal cross-sections. Thestructures320 can also be strips as shown inFIG. 9, or a mesh as shown inFIG. 10. According to one embodiment, thestructures320 are pillars with diameters from 50 nm to 5000 nm, heights from 1000 nm to 20000 nm, a center-to-center distance between two closest pillars of 300 nm to 15000 nm. Thetop portion321 preferably has a height of 1 micron to 20 micron. Thetop portion321 preferably has a gradient of doping levels, with a highest doping level at thetop surface320a. Preferably, thestructures320 have an overhangingportion324 along an entire contour of thetop surface320aof thestructures320.
• Eachrecess330 preferably has a rounded or beveled inner edge between thesidewall130aand thebottom wall330b.
• Thejunction layer331 preferably has a thickness from 5 nm to 100 nm. Thejunction layer331 is effective to passivate surfaces of thestructures320.
• The planarreflective layer332 can be any suitable material, such as ZnO, Al, Au, Ag, Pd, Cr, Cu, Ti, Ni, a combination thereof, etc. The planarreflective layer332 preferably is an electrically conductive material, more preferably a metal. The planarreflective layer332 preferably has a reflectance of at least 50%, more preferably has a reflectance of at least 70%, most preferably has a reflectance of at least 90%, for visible light of any wavelength. The planarreflective layer332 has a thickness of preferably at least 5 nm, more preferably at least 20 nm. The planarreflective layer332 in all therecesses330 is preferably connected. The planarreflective layer332 is functional to reflect light incident thereon to thestructures320 so the light is absorbed by thestructures320. The planarreflective layer332 preferably is functional as an electrode of thephotovoltaic device300.
• Thetransparent material340 is substantially transparent to visible light, preferably with a transmittance of at least 50%, more preferably at least 70%, most preferably at least 90%. Thetransparent material340 can be an electrically conductive material. Thetransparent material340 preferably is made of a transparent conductive oxide, such as ITO (indium tin oxide), AZO (aluminum doped zinc oxide), ZIO (zinc indium oxide), ZTO (zinc tin oxide), etc. Thetransparent material340 preferably forms an Ohmic contact with thejunction layer331. Thetransparent material340 preferably forms an Ohmic contact with the planarreflective layer332. Thetransparent material340 preferably is functional as an electrode of thephotovoltaic device300. Thetransparent material340 can also be a suitable electrically insulating material such as SiO₂or a polymer.
• Thesubstrate305 preferable has aflat surface350 opposite thestructures320. Theflat surface350 can have a dopedlayer351 of the opposite conduction type from thejunction layer331, i.e. if thejunction layer331 is n type, the dopedlayer351 is also p type; if thejunction layer331 is p type, the dopedlayer351 is also n type. The dopedlayer351 is electrically connected to thebottom portion322 of each of thestructures320. If thebottom portion322 is intrinsic, thejunction layer331 and thetop portion321 form a p-i-n junction with thebottom portion322 and the dopedlayer351. If thebottom portion322 is n type or p type, thejunction layer331 and thetop portion321 form a p-n junction with thebottom portion322. Theflat surface350 can also have ametal layer352 disposed on the dopedlayer351. Themetal layer352 forms an Ohmic contact with the dopedlayer351. Thesubstrate305 preferably has a thickness of at least 50 microns. Total area of the planarreflective layer332 is preferable at least 40% of a surface area of theflat surface350.
• Theelectrode layer380 can be the same material as thetransparent material340 or different material from thetransparent material340. Theelectrode layer380 is substantially transparent to visible light, preferably with a transmittance of at least 50%, more preferably at least 70%, most preferably at least 90%. Theelectrode layer380 is an electrically conductive material. Theelectrode layer380 preferably is a transparent conductive oxide, such as ITO (indium tin oxide), AZO (aluminum doped zinc oxide), ZIO (zinc indium oxide), ZTO (zinc tin oxide), etc. Theelectrode layer380 preferably forms an Ohmic contact with thejunction layer331. Theelectrode layer380 preferably is functional as an electrode of thephotovoltaic device300.
• Thecoupling layer360 can be the same material as thetransparent material340 or different material from thetransparent material340. As shown inFIG. 5, refractive index of the structure320 n₁, refractive index of the transparent material340 n₂, refractive index of the coupling layer360 n₃, preferably satisfy relations of m>n₂and m>n₃, which lead to enhanced light concentration in thestructures320.
• In one embodiment, thestructures320 are pillars arranged in an array, such as a rectangular array, a hexagonal array, a square array, concentric ring. Each pillar is about 5 microns in height. A pitch of thestructures320 is from 300 nm to 15 microns. The “pitch” is defined as a distance of astructure320 to a nearest neighbor of thestructure320 along a direction parallel to thesubstrate305.
• A method of making thephotovoltaic device300 as shown inFIG. 3B, according to an embodiment, comprises the following steps:
• Instep3000, providing thesubstrate305 having the dopedlayer351 and anepi layer31 disposed on the dopedlayer351.
• Instep3001, anupper layer32 of theepi layer31 is doped by ion implantation.
• Instep3002, a resistlayer34 is applied on the dopedupper layer32. The resistlayer34 can be applied by spin coating. The resistlayer34 can be a photo resist or an e-beam resist.
• Instep3003, lithography is performed. The resistlayer34 now has a pattern of openings in which the dopedupper layer32 is exposed. Shapes and locations of the openings correspond to the shapes and locations of therecesses330. The resolution of the lithography is limited by the wavelength of the radiation used. Photolithography tools using deep ultraviolet (DUV) light with wavelengths of approximately 248 and 193 nm, allows minimum feature sizes down to about 50 nm. E-beam lithography tools using electron energy of 1 keV to 50 keV allows minimum feature sizes down to a few nanometers.
• Instep3004, amask layer35 is deposited. The deposition can be done using a technique such as thermal evaporation, e-beam evaporation, sputtering. Themask layer35 can be a metal such as Cr or Al, or a dielectric such as SiO₂or Si₃N₄. The thickness of themask layer35 can be determined by a depth of therecesses330 and etching selectivity (i.e., ratio of etching rates of themask layer35 and the substrate305).
• Instep3005, remainder of the resistlayer34 is lift off by a suitable solvent or ashed in a resist asher to remove anymask layer35 support thereon. A portion of themask layer35 in the openings of the resistlayer34 is retained. A portion of the dopedupper layer32 is now exposed through the retainedmask layer35.
• Instep3006, the exposed portion of the dopedupper layer32 and the portion of theepi layer31 directly therebelow are deep etched to a desired depth (e.g., 1 to 20 microns) followed by an isotropic etch, until theepi layer31 is partially exposed, to form thestructures320 with the overhangingportion324 and therecesses330 with the beveled inner edge. Each of thestructures320 now has thetop portion321 which is part of the upper dopedlayer32 and abottom portion322 which is part of theepi layer31. Deep etching includes alternating deposition and etch steps and can lead to “scalloping” on thesidewall330bof therecesses330, i.e. thesidewall330bis not smooth. Thesidewall330bcan be smoothed by thermal annealing or dipping into an etchant such as potassium hydroxide (KOH) followed by rinsing. The deep etching can use gases such as C₄F₈and SF₆.
• Instep3007, themask layer35 is removed by a suitable such as wet etching with suitable etchant, ion milling, sputtering. Thetop surface320aof thestructures320 is exposed.
• Instep3008, adopant layer39 is conformally (i.e., isotropically) deposited on surfaces of therecesses330 and atop surface320aof thestructures320. Thedopant layer39 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition. Thedopant layer39 can comprise any suitable material such as trimethylboron, triisopropylborane ((C₃H₇)₃B), triethoxyborane ((C₂H₅O)₃B, and/or triisopropoxyborane ((C₃H₇O)₃B. More details can be found in an abstract of a presentation titled “Atomic layer deposition of boron oxide as dopant source for shallow doping of silicon” by Bodo Kalkofen and Edmund P. Burte in the 218th Electrochemical Society Meeting, Oct. 10, 2010-Oct. 15, 2010, which is hereby incorporated by reference in its entirety.
• Instep3009, ashield layer33 is conformally (i.e., isotropically) deposited on surfaces of thedopant layer39. Theshield layer33 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition. Theshield layer33 has a suitable material (such as silicon oxide, silicon nitride) and a suitable thickness (e.g., at least 10 nm, at least 100 nm or at least 1 micron) effective to prevent thedopant layer39 from evaporation instep3010.
• Instep3010, thedopant layer39 is diffused into thesidewall330b, thebottom wall330aand thetop surface320aby thermal annealing, which forms thejunction layer331 thereon. Thermal annealing can be conducted, for example, at about 850° C. for 10 to 30 minutes under a suitable atmosphere (e.g., argon).
• Instep3011, theshield layer33 is removed by a suitable technique such as wet etch using a suitable etchant such as HF. Thejunction layer331 is now exposed.
• Instep3012, a resistlayer36 is selectively applied such that thesidewall330aandbottom wall330bof therecesses330 are free of the resistlayer36 and atop surface331aof thejunction layer331 is completely covered by the resistlayer36. The resistlayer36 can be selectively applied by a suitable method such as the print coating method detailed hereinbelow according an embodiment.
• Instep3013, the planarreflective layer332 is anisotropically deposited (i.e., non-conformally) such that the resistlayer36 and thebottom wall330bare covered by the planarreflective layer332 while thesidewall330ais free of the planarreflective layer332. The planarreflective layer332 can be deposited by a suitable technique such as thermal evaporation, e-beam evaporation. The planarreflective layer332 can be any suitable material such as silver.
• Instep3014, the resistlayer36 is lift off by a suitable solvent or ashed in a resist asher to remove any portion of the planarreflective layer332 support thereon. Thetop surface331aof thejunction layer320 is now exposed.
• Instep3015, thetransparent material340 is deposited such that the planarreflective layer332, thejunction layer331 and thetop surface331aare completely covered and therecesses330 are completely filled. Thetransparent material340 can be deposited by a suitable technique such as plating, chemical vapor deposition or atomic layer deposition.
• Instep3016, thetransparent material340 is planarized using a suitable technique such as CMP such that thetransparent material340 has a surface coextensive with thetop surface320aof thestructures320 and thetop surface331aof thejunction layer331 is exposed.
• Instep3017, theelectrode layer380 is deposited using a suitable technique such as thermal evaporation, e-beam evaporation, sputtering, onto thetransparent material340 and thetop surfaces331a. Thecoupling layer360 can be then deposited using a suitable technique such as sputtering, thermal evaporation or e-beam evaporation onto theelectrode layer380.
• Instep3018, themetal layer352 is deposited on the dopedlayer351.
• The method can further comprise one or more steps of thermal annealing.
• FIG. 6 shows an exemplary top cross sectional view of thephotovoltaic device100,200 or300, with thetransparent material140/240/340, theelectrode layer180/280/380 and thecoupling layer160/260/360 not shown for clarity.FIG. 7 shows an exemplary perspective view of thephotovoltaic device100,200 or300, with thetransparent material140/240/340, theelectrode layer180/280/380 and thecoupling layer160/260/360 not shown for clarity.
• An embodiment of the print method used insteps1008,1013,2011 and3012 comprises: coating aroller410 of a flexible material such as polydimethylsiloxane (PDMS) with a resistlayer420; transferring the resistlayer420 to asurface405aof asubstrate405 by rolling theroller410 on thesurface405a. Thesurface405acan be flat or textured. During rolling theroller410, thesurface405acan face upward or downward.
• Another embodiment of the print method used insteps1008,1013,2011 and3012 comprises: coating astamp430 of a flexible material such as polydimethylsiloxane (PDMS) with a resistlayer420; transferring the resistlayer420 to asurface405aof asubstrate405 by pressing thestamp430 on thesurface405a. Thesurface405acan be flat or textured. During rolling theroller410, thesurface405acan face upward or downward.
• As shown inFIG. 11B, thephotovoltaic device100,200 or300 can further comprise at least one via599 in thetransparent material140,240 or340 and between theelectrode layer180,280 or380 and the planarreflective layer132,232 or332, wherein the at least one via599 is an electrically conductive material, preferably an electrically conductive transparent material (e.g. ITO, AZO, etc.) and the at least one via electrically connects theelectrode layer180,280 or380 and the planarreflective layer132,232 or332. As shown inFIG. 11A, the via599 can be made by etching arecess598 through theelectrode layer180,280 or380 and thetransparent material140,240 or340 until the planarreflective layer132,232 or332 is exposed and then filling therecess598 to form the via599. As shown inFIGS. 12A and 12B, thevias599 can be any suitable shape such as rod-shaped or bar-shaped.
• A method of converting light to electricity comprises: exposing thephotovoltaic device100,200 or300 to light; reflecting light to thestructures120,220 or320 using the planarreflective layer132,232 or332; absorbing the light and converting the light to electricity using thestructures120,220 or320; drawing an electrical current from thephotovoltaic device100,200 or300. As shown inFIGS. 8A-8C, the electrical current can be drawn from themetal layer152 and the planarreflective layer132 or themetal layer152 and theelectrode layer180, themetal layer252 and the planarreflective layer232, themetal layer352 and the planarreflective layer332, respectively, in thephotovoltaic device100,200 or300.
• A photo detector according to an embodiment comprises thephotovoltaic device100,200 or300, wherein the photo detector is functional to output an electrical signal when exposed to light.
• A method of detecting light comprises: exposing thephotovoltaic device100,200 or300 to light; measuring an electrical signal from thephotovoltaic device100,200 or300. The electrical signal can be an electrical current, an electrical voltage, an electrical conductance and/or an electrical resistance. A bias voltage can be applied to thestructures120,220 and320 respectively in thephotovoltaic device100,200 or300 when measuring the electrical signal.
• While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims (22)

What is claimed:

1. A photovoltaic device operable to convert light to electricity, comprising a substrate, a plurality of structures essentially perpendicular to the substrate, one or more recesses between the structures, each recess having a sidewall and a bottom wall, and a planar reflective layer disposed on the bottom wall of each recess, wherein the structures comprise a semiconductor material; the sidewall of each recess is free of the planar reflective layer; and each recess is filled with a material, wherein the structures have an overhanging portion along an entire contour of a top surface of the structures.

2. The photovoltaic device ofclaim 1, wherein the semiconductor material is selected from a group consisting of silicon, germanium, group III-V compound materials, group II-VI compound materials, and quaternary materials.

3. The photovoltaic device ofclaim 1, wherein the structures are cylinders or prisms with a cross-section selected from a group consisting of elliptical, circular, rectangular, and polygonal cross-sections, strips, or a mesh.

4. The photovoltaic device ofclaim 1, wherein the structures are pillars with diameters from 50 nm to 5000 nm, heights from 1000 nm to 20000 nm, a center-to-center distance between two closest pillars of 300 nm to 15000 nm.

5. The photovoltaic device ofclaim 1, wherein the planar reflective layer has a thickness of at least 5 nm.

6. The photovoltaic device ofclaim 1, wherein each recess has a rounded or beveled inner edge between the sidewall and the bottom wall thereof.

7. The photovoltaic device ofclaim 1, wherein the planar reflective layer comprises ZnO, Al, Au, Ag, Pd, Cr, Cu, Ti, Ni, or a combination thereof.

8. The photovoltaic device ofclaim 1, wherein the planar reflective layer is an electrically conductive material.

9. The photovoltaic device ofclaim 1, wherein the planar reflective layer is a metal.

10. The photovoltaic device ofclaim 1, wherein the planar reflective layer has a reflectance of at least 50% for visible light of any wavelength.

11. A method of making a photovoltaic device comprising a substrate, a plurality of structures essentially perpendicular to the substrate, one or more recesses between the structures, each recess having a sidewall and a bottom wall, a planar reflective layer disposed on the bottom wall of each recess and each recess filled with a material, the method comprising:

forming the structures and recesses by etching the substrate;

depositing the planar reflective layer to the bottom wall, such that the sidewall of each recess is free of the planar reflective layer;

depositing the material such that each recess is completely filled by the material;

wherein the structures comprise a semiconductor material, wherein the structures have an overhanging portion along an entire contour of a top surface of the structures.

12. The method ofclaim 11, further comprising:

planarizing the material; coating the substrate with the resist layer;

developing the pattern in the resist layer;

depositing a mask layer; and

lifting off the resist layer.

12. The method ofclaim 11, further comprising ion implantation or depositing a dopant layer.

13. The method ofclaim 11, wherein the structures and recesses are formed by deep etch followed by isotropic etch.

14. The method ofclaim 11, further comprising applying a resist layer by a print coating method, the print coating method comprising:

coating a roller of a flexible material with a resist layer; transferring the resist layer to a surface of a substrate by rolling the roller on the surface, wherein the surface is flat or textured.

15. The method ofclaim 11, further comprising applying a resist layer by a print coating method, the print coating method comprising:

coating a stamp of a flexible material with a resist layer; transferring the resist layer to a surface of a substrate by pressing the stamp on the surface, wherein the surface is flat or textured.

16. A method of converting light to electricity comprising:

exposing a photovoltaic device to light, wherein the photovoltaic device comprises a substrate, a plurality of structures essentially perpendicular to the substrate, one or more recesses between the structures, each recess having a sidewall and a bottom wall, a planar reflective layer disposed on the bottom wall of each recess, the sidewall of each recess being free of the planar reflective layer, and each recess filled with a material;

reflecting light to the structures using the planar reflective layer;

absorbing the light and converting the light to electricity using the structures;

drawing an electrical current from the photovoltaic device;

wherein the structures comprise a semiconductor material, wherein the structures have an overhanging portion along an entire contour of a top surface of the structures.

16. The method ofclaim 15, wherein the electrical current is drawn from the planar reflective layer.

17. The method ofclaim 16, wherein the electrical signal is an electrical current, an electrical voltage, an electrical conductance and/or an electrical resistance.

18. The method ofclaim 16, wherein a bias voltage is applied to the structures in the photovoltaic device.

19. A photo detector comprising the photovoltaic device ofclaim 1, wherein the photo detector is functional to output an electrical signal when exposed to light.

20. A method of detecting light comprises: exposing the photovoltaic device ofclaim 1 to light; measuring an electrical signal from the photovoltaic device.

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