US20160086954A1 - Memory Device Having Electrically Floating Body Transistor - Google Patents

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Description

CROSS-REFERENCE
• This application claims the benefit of co-pending U.S. Provisional Application No. 61/621,546 filed Apr. 8, 2012, which application is incorporated herein by reference.
FIELD OF THE INVENTION
• The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device having an electrically floating body transistor.
BACKGROUND OF THE INVENTION
• Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.
• A DRAM cell without a capacitor has been investigated previously. Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Chatterjee et al. have proposed a Taper Isolated DRAM cell concept in “Taper Isolated Dynamic Gain RAM Cell”, P. K. Chatterjee et al., pp. 698-699, International Electron Devices Meeting, 1978 (“Chatterjee-1”), “Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories”, P. K. Chatterjee et al., pp. 22-23, IEEE International Solid-State Circuits Conference, February 1979 (“Chatterjee-2”), and “dRAM Design Using the Taper-Isolated Dynamic RAM Cell”, J. E. Leiss et al., pp. 337-344, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 2, April 1982 (“Leiss”), which are hereby incorporated herein, in their entireties, by reference thereto. The holes are stored in a local potential minimum, which looks like a bowling alley, where a potential barrier for stored holes is provided. The channel region of the Taper Isolated DRAM cell contains a deep n-type implant and a shallow p-type implant. As shown in “A Survey of High-Density Dynamic RAM Cell Concepts”, P. K. Chatterjee et al., pp. 827-839, IEEE Transactions on Electron Devices, vol. ED-26, no. 6, June 1979 (“Chatterjee-3”), which is hereby incorporated herein, in its entirety, by reference thereto, the deep n-type implant isolates the shallow p-type implant and connects the n-type source and drain regions.
• Terada et al. have proposed a Capacitance Coupling (CC) cell in “A New VLSI Memory Cell Using Capacitance Coupling (CC) Cell”, K. Terada et al., pp. 1319-1324, IEEE Transactions on Electron Devices, vol. ED-31, no. 9, September 1984 (“Terada”), while Erb has proposed Stratified Charge Memory in “Stratified Charge Memory”, D. M. Erb, pp. 24-25, IEEE International Solid-State Circuits Conference, February 1978 (“Erb”), both of which are hereby incorporated herein, in their entireties, by reference thereto.
• DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate (see for example “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”), “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002, all of which are hereby incorporated herein, in their entireties, by reference thereto) and in bulk silicon (see for example “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM”, R. Ranica et al., pp. 128-129, Digest of Technical Papers, 2004 Symposium on VLSI Technology, June 2004 (“Ranica-1”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-Cost eDRAM Applications”, R. Ranica et al., 2005 Symposium on VLSI Technology, Digest of Technical Papers (“Ranica-2”), “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al, pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17^thIEEE International Conference on Electronics, Circuits, and Systems (ICECS) (“Pulicani”), all of which are hereby incorporated herein, in their entireties, by reference thereto).
• Widjaja and Or-Bach describes a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto). This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination.
• As memory cells are being scaled to smaller feature size, the variability in memory cells characteristics also increase, for example due to the Random Dopant Fluctuation (RDF). A purpose of this invention is to provide an improvement of the variability of memory cells characteristics.
SUMMARY OF THE INVENTION
• In one aspect of the present invention, a semiconductor memory cell comprises: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; and a back-bias region configured to generate impact ionization when the memory cell is in one of the first and second states, and wherein the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
• In at least one embodiment, the memory cell further comprises a substrate region, wherein the back-bias region is positioned between the substrate region and the floating body region.
• In at least one embodiment, the floating body region comprises first and second subregions, wherein the first subregion has a first doping concentration level and the second region has a second doping concentration level, and wherein the first doping concentration is different from the second doping concentration level.
• In at least one embodiment, the first and second subregions have the same conductivity type.
• In at least one embodiment, the first subregion is further from the back-bias region than a distance from the second subregion to the back bias region, and wherein the second doping concentration level is greater than the first doping concentration level.
• In at least one embodiment, the floating body region further comprises a third subregion, the third subregion having a third doping concentration level, wherein the third doping concentration level is different from at least one of the first and second doping concentration levels.
• In at least one embodiment, the first subregion is furthest from the back-bias region, relative to the second and third subregions, and the first doping concentration level is lowest relative to the second and third doping concentration levels.
• In at least one embodiment, the memory cell the first and second subregions are localized so that they do not underlie the first and second regions.
• In at least one embodiment, the memory cell further comprises at least one halo region adjacent to at least one of the first and second regions, wherein each halo region comprises a first conductivity type selected from p-type conductivity type and n-type conductivity type; and wherein the first and second regions each comprise a second conductivity type selected from the p-type conductivity type and the n-type conductivity type, wherein the second conductivity type is different from the first conductivity type.
• In at least one embodiment, the first and second states are stable states.
• In another aspect of the present invention, a semiconductor memory cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; and a back-bias region configured to maintain a charge in the floating body region; wherein the first region, the floating body region, and the back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of the bipolar transistor approaches unity.
• In at least one embodiment, the back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and wherein the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
• In at least one embodiment, the memory cell further comprises a second region in electrical contact with the floating body region and spaced apart from the first region.
• In at least one embodiment, the memory cell further comprises a gate region positioned above the floating body region.
• In at least one embodiment, the memory cell further comprises a substrate region, wherein the back-bias region is positioned between the substrate region and the floating body region.
• In at least one embodiment, the first and second states are stable states.
• In at least one embodiment, the memory cell the floating body region comprises first and second subregions, wherein the first subregion has a first doping concentration level and the second region has a second doping concentration level, and wherein the first doping concentration is different from the second doping concentration level.
• In another aspect of the present invention, a semiconductor memory cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; wherein the floating body region acts as a base region of a first bipolar transistor that maintains the state of the memory cell; and wherein the floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of the memory cell.
• In at least one embodiment, the memory cell further comprises a back-bias region configured to maintain a charge in the floating body region.
• In at least one embodiment, the first and second states are stable states.
• In at least one embodiment, the product of forward emitter gain and impact ionization efficiency of the first bipolar transistor approaches unity when the memory cell is in one of the first and second states, and wherein impact ionization, when the memory cell is in the other of the first and second states is less than the impact ionization when the memory cell is in the one of the first and second states.
• In at least one embodiment, current flow through the first bipolar transistor is larger when the memory cell is in one of the first and second states than when the memory cell is in the other of the first and second states.
• In at least one embodiment, the memory cell states are maintained through impact ionization.
• In another aspect of the present invention, a semiconductor memory cell comprises: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back-bias region located below the floating body region; wherein the back-bias region acts as a collector region of a bipolar transistor that maintains the state of the memory cell.
• In at least one embodiment, the first and second states are stable.
• In at least one embodiment, the product of forward emitter gain and impact ionization efficiency of the bipolar transistor that maintains the state of the memory cell approaches unity when the memory cell is in one of the first and second states, and wherein impact ionization, when the memory cell is in the other of the first and second states is less than the impact ionization when the memory cell is in the one of the first and second states.
• In at least one embodiment, current flow through the bipolar transistor is larger when the memory cell is in one of the first and second states than when the memory cell is in the other of the first and second states.
• In at least one embodiment, the memory cell states are maintained through impact ionization.
• In at least one embodiment, the back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
• These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the memory cells, arrays and methods as more fully described below.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic, cross-sectional illustration of a memory cell according to the present invention.
• FIG. 2 is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 3A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 3B is a schematic, top-view illustration of the memory cell shown inFIG. 3A.
• FIG. 4 schematically illustrates an equivalent circuit representation of the memory cells shown inFIGS. 1-3.
• FIG. 5 schematically illustrates a bipolar device inherent in memory devices ofFIGS. 1-3.
• FIG. 6 schematically illustrates multiple cells of the type shown inFIGS. 1-3 joined to make a memory array.
• FIG. 7 schematically illustrates a holding operation performed on a memory array according to an embodiment of the present invention.
• FIG. 8 illustrates exemplary bias conditions applied on the terminals of a memory cell of the array ofFIG. 7.
• FIG. 9A shows an energy band diagram characterizing an intrinsic bipolar device when a floating body region is positively charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.
• FIG. 9B shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.
• FIG. 10 shows a graph of the net current I flowing into or out of a floating body region as a function of the potential V of the floating body, according to an embodiment of the present invention.
• FIG. 11 shows a schematic curve of a potential energy surface (PES) of a memory cell according to an embodiment of the present invention.
• FIG. 12 illustrates a charge stored in a floating body region of a memory cell as a function of a potential applied to a buried well region, connected to a BW terminal, according to an embodiment of the present invention.
• FIG. 13 schematically illustrates a read operation performed on a memory array according to an embodiment of the present invention.
• FIG. 14 illustrates bias conditions applied on the terminals of a memory cell to perform a read operation.
• FIG. 15 schematically illustrates a write logic-0 operation performed on a memory array according to an embodiment of the present invention.
• FIG. 16 illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-0 operation.
• FIG. 17 schematically illustrates a write logic-1 operation performed on a memory array according to an embodiment of the present invention.
• FIG. 18 illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation.
• FIG. 19 is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 20A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 20B is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 21A schematically illustrates an equivalent circuit representation of the memory cells shown inFIGS. 20A-20B.
• FIG. 21B schematically illustrates a bipolar device inherent in memory devices ofFIGS. 20A-20B.
• FIG. 22 shows an energy band diagram characterizing an intrinsic bipolar device of a memory cell according to an embodiment of the present invention under equilibrium condition.
• FIG. 23 illustrates exemplary bias conditions applied on the terminals of a memory cell shown inFIGS. 20A-20B to perform a holding operation.
• FIG. 24 shows an energy band diagram characterizing an intrinsic bipolar device when a floating body region is positively charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.
• FIG. 25 shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.
• FIG. 26 schematically illustrates bias conditions applied on the terminals of a memory cell to perform an alternative holding operation on a memory cell employing intrinsic silicon controlled rectifier principle according to an embodiment of the present invention.
• FIG. 27 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a read operation on a memory cell according to an embodiment of the present invention.
• FIG. 28 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation with impact ionization mechanism on a memory cell according to an embodiment of the present invention.
• FIG. 29 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation with band-to-band tunneling or gate induced drain leakage (GIDL) mechanism on a memory cell according to an embodiment of the present invention.
• FIG. 30 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-0 operation on a memory cell according to an embodiment of the present invention.
• FIG. 31 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a bit-selective write logic-0 operation on a memory cell according to another embodiment of the present invention.
• FIG. 32A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 32B is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
• FIG. 33 shows an energy band diagram characterizing an intrinsic bipolar device of a memory cell according to an embodiment of the present invention under equilibrium condition.
• FIG. 34 is a schematic, cross-sectional illustration of an asymmetric memory cell according to another embodiment of the present invention.
• FIG. 35 schematically illustrates an equivalent circuit representation of the memory cells shown inFIG. 34.
• FIG. 36 schematically illustrates a bipolar device inherent in memory devices ofFIG. 34.
• FIG. 37 schematically illustrates a write logic-1 operation performed on a memory array according to an embodiment of the present invention.
• FIG. 38 illustrates exemplary bias conditions applied on the terminals of a selected memory cell of the array ofFIG. 37.
• FIG. 39 illustrates exemplary bias conditions applied on the terminals of an unselected memory cell, sharing the same row as the selected cell, of the array ofFIG. 37.
• FIG. 40 illustrates exemplary bias conditions applied on the terminals of an unselected memory cell, sharing the same column as the selected cell, of the array ofFIG. 37.
• FIG. 41 illustrates exemplary bias conditions applied on the terminals of an unselected memory cell, not sharing the same row nor the same column as the selected cell, of the array ofFIG. 37.
• FIG. 42 schematically illustrates a write logic-0 operation performed on a memory array according to an embodiment of the present invention.
• FIG. 43 illustrates exemplary bias conditions applied on the terminals of a selected memory cell of the array ofFIG. 42.
• FIG. 44A is a schematic, cross-sectional illustration of a memory cell which can be used as a reference cell in sensing the state of a floating body memory cell according to an embodiment of the present invention.
• FIG. 44B is a schematic, cross-sectional illustration of a memory cell which can be used as a reference cell in sensing the state of a floating body memory cell according to another embodiment of the present invention.
• FIG. 45A is a schematic illustration of a top view of a memory cell according to another embodiment of the present invention.
• FIGS. 45B and 45C are schematic, cross-sectional illustrations of the cell ofFIG. 45A taken along the I-I′ and II-II′ cut lines ofFIG. 30A, respectively.
• FIG. 46 schematically illustrates a memory array comprising multiple cells of the type shown inFIGS. 1-3 and a reference cell of the type shown inFIGS. 44A and 44B.
• FIG. 47 schematically illustrates a memory array comprising multiple cells of the type shown inFIGS. 1-3 and a reference cell of the type shown inFIGS. 45A-45C.
DETAILED DESCRIPTION OF THE INVENTION
• Before the present memory cells, arrays and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.
• Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.
• Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.
• It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a substrate terminal” includes a plurality of such substrate terminals and reference to “the region” includes reference to one or more regions and equivalents thereof known to those skilled in the art, and so forth.
• The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.
• Referring toFIG. 1, amemory cell50 according to an embodiment of the present invention is shown.Memory cell50 includes asubstrate12 of a first conductivity type such as p-type, for example.Substrate12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention,substrate12 can be the bulk material of the semiconductor wafer. In another embodiment shown inFIG. 2,substrate12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well29 of the second conductivity type, such as n-type. The well29 in turn can be another well insidesubstrate12B of the first conductivity type (for example, p-type). In another embodiment, well12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected toregion12A. To simplify the description, thesubstrate12 will usually be drawn as the semiconductor bulk material as it is inFIG. 1.
• Memory cell50 also includes a buriedlayer region22 of a second conductivity type, such as n-type, for example; a floatingbody region24 of the first conductivity type, such as p-type, for example; and source/drain regions16 and18 of the second conductivity type, such as n-type, for example.
• Buried layer22 may be formed by an ion implantation process on the material ofsubstrate12. Alternatively, buriedlayer22 can be grown epitaxially on top ofsubstrate12 or formed through a solid state diffusion process.
• The floatingbody region24 of the first conductivity type is bounded on top bysource line region16,drain region18, and insulating layer62 (or bysurface14 in general), on the sides by insulatinglayer26, and on the bottom by buriedlayer22. Floatingbody24 may be the portion of theoriginal substrate12 above buriedlayer22 if buriedlayer22 is implanted. Alternatively, floatingbody24 may be epitaxially grown. Depending on how buriedlayer22 and floatingbody24 are formed, floatingbody24 may have the same doping assubstrate12 in some embodiments or a different doping, if desired in other embodiments.
• Asource line region16 having a second conductivity type, such as n-type, for example, is provided in floatingbody region24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed atsurface14.Source line region16 may be formed by an implantation process on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to formsource line region16.
• Abit line region18, also referred to asdrain region18, having a second conductivity type, such as n-type, for example, is also provided in floatingbody region24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed atcell surface14.Bit line region18 may be formed by an implantation process on the material making upsubstrate12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to formbit line region18.
• Agate60 is positioned in between thesource line region16 and thedrain region18, above the floatingbody region24. Thegate60 is insulated from the floatingbody region24 by an insulatinglayer62. Insulatinglayer62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Thegate60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
• Insulating layers26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulatinglayers26 insulatememory cell50 fromadjacent memory cell50. The bottom of insulatinglayer26 may reside inside the buriedregion22 allowing buriedregion22 to be continuous as shown inFIGS. 1 and 2. Alternatively, the bottom of insulatinglayer26 may reside below the buriedregion22 as inFIGS. 3A and 3B (shown better inFIG. 3A). This requires a shallower insulatinglayer28, which insulates the floatingbody region24, but allows the buriedlayer22 to be continuous in the perpendicular direction of the cross-sectional view shown inFIG. 3A. For simplicity, onlymemory cell50 with continuous buriedregion22 in all directions will be shown from hereon.
• Cell50 includes several terminals: word line (WL) terminal70 electrically connected togate60, bit line (BL) terminal74 electrically connected to bitline region18, source line (SL) terminal72 electrically connected to sourceline region16, buried well (BW) terminal76 electrically connected to buriedlayer22, andsubstrate terminal78 electrically connected to thesubstrate12. Alternatively, theSL terminal72 may be electrically connected toregion18 andBL terminal74 may be electrically connected toregion16.
• FIG. 4 illustrates an equivalent circuit representation ofmemory cell50. Inherent inmemory cell50 are metal-oxide-semiconductor (MOS)transistor20, formed bysource line region16,gate60,bit line region18, and floatingbody region24, andbipolar devices30aand30b, formed by buriedwell region22, floatingbody region24, andsource line region16 orbit line region18, respectively.
• Also inherent inmemory device50 isbipolar device30c, formed bysource line region16, floatingbody24, and bitline region18. For drawings clarity,bipolar device30cis shown separately inFIG. 5.
• FIG. 6 schematically illustrates an exemplary embodiment of amemory array80 of memory cells50 (four exemplary instances ofmemory cell50 being labeled as50a,50b,50cand50d) arranged in rows and columns. In many, but not all, of the figures wherearray80 appears,representative memory cell50awill be representative of a “selected”memory cell50 when the operation being described has one (or more in some embodiments) selected memory cell(s)50. In such figures,representative memory cell50bwill be representative of anunselected memory cell50 sharing the same row as selectedrepresentative memory cell50a,representative memory cell50cwill be representative of anunselected memory cell50 sharing the same column as selectedrepresentative memory cell50a, andrepresentative memory cell50dwill be representative of anunselected memory cell50 sharing neither a row or a column with selectedrepresentative memory cell50a.
• Present inFIG. 6 areword lines70athrough70n, source lines72athrough72n,bit lines74athrough74p, buried wellterminals76athrough76n, andsubstrate terminal78. Representation of the lines/terminal with letters a-n or a through p, includes not only embodiments which include literally twelve lines/terminals (i.e., a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p) or fourteen lines/terminals (i.e., a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p), but is meant to more generically represent a plurality of such line terminals, which can be less than twelve (i.e., as low as one given that there is a plurality of cells and at least one row and at least one column) or greater than twelve, thirteen or fourteen (much greater than fourteen up to any positive integer practical)).
• Each of the source lines72athrough72nis associated with a single row ofmemory cells50 and is coupled to thesource line region18 of eachmemory cell50 in that row. Each of the bit lines74athrough74pis associated with a single column ofmemory cells50 and is coupled to thebit line region16 of eachmemory cell50 in that column.
• Substrate12 is present at all locations underarray80. Persons of ordinary skill in the art will appreciate that one ormore substrate terminals78 may be present in one or more locations. Such skilled persons will also appreciate that althougharray80 is shown inFIG. 6 as a single continuous array, many other organizations and layouts are possible. For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, thearray80 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed aroundarray80 or inserted between sub-arrays ofarray80. Thus the present invention is not limited to the exemplary embodiments, features, design options, etc., shown and described.
• Several operations can be performed bymemory cell50 such as holding, read, write logic-1 and write logic-0 operations, and have been described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.
• FIG. 7 schematically illustrates performance of a holding operation onmemory array80, whileFIG. 8 shows the bias applied on the terminals of amemory cell50 during the holding operation, according to an exemplary, non-limiting embodiment. The holding operation is performed by applying a positive back bias to theBW terminal76, zero or negative bias on theWL terminal70, zero bias on theBL terminal74,SL terminal72, andsubstrate terminal78. Alternatively, thesubstrate terminal78 may be left floating. In another embodiment, one of theSL terminal72 orBL terminal74 may be left floating. The positive back bias applied to the buriedlayer region22 connected to theBW terminal76 will maintain the state of thememory cell50 that it is connected to. The positive bias applied to theBW terminal76 needs to generate an electric field sufficient to trigger an impact ionization mechanism when the floatingbody region24 is positively charged, as will be described through the band diagram shown inFIGS. 9A and 9B. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.
• In one embodiment the bias conditions for the holding operation onmemory cell50 are: 0 volts is applied toWL terminal70, 0 volts is applied toBL terminal74, 0 volts is applied toSL terminal72, a positive voltage, for example, +1.2 volts is applied toBW terminal76, and 0 volts is applied to thesubstrate terminal78. In other embodiments, different voltages may be applied to the various terminals ofmemory cell50 and the exemplary voltages described are not limiting.
• FIG. 9A shows an energy band diagram characterizing the intrinsic n-p-nbipolar device30bwhen the floatingbody region24 is positively charged and a positive bias voltage is applied to the buriedwell region22. The vertical dashed lines mark the different regions of thebipolar device30b. The energy band diagram of the intrinsic n-p-nbipolar device30acan be constructed in a similar manner, with the source line region16 (connected to the SL terminal72) in place of the bit line region18 (connected to the BL terminal74). The horizontal dashed lines indicate the Fermi levels in the various regions of then-p-n transistor30b. The Fermi level is located in the band gap between thesolid line27 indicating the top of the valence band (the bottom of the band gap) and thesolid line29 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. If floatingbody24 is positively charged, a state corresponding to logic “1”, thebipolar transistors30aand30bwill be turned on as the positive charge in the floating body region lowers the energy bather of electron flow (from thesource line region16 or bit line region18) into the base region (floating body region24). Once injected into the floatingbody region24, the electrons will be swept into the buried well region22 (connected to BW terminal76) due to the positive bias applied to the buriedwell region22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theBW terminal76 while the resulting hot holes will subsequently flow into the floatingbody region24. When the following condition is met: β×(M−1)≈1—where β is the forward common-emitter current gain of thebipolar transistors30aor30band M is the impact ionization coefficient—the amount of holes injected into the floatingbody region24 compensates for the charge lost due to p-n junction forward bias current between the floatingbody region24 and thesource line region16 orbit line region18 and due to holes recombination. This process maintains the charge (i.e. holes) stored in the floatingbody region24 which will keep the n-p-nbipolar transistors30aand30bon for as long as a positive bias is applied to the buriedwell region22 throughBW terminal76.
• The region where the product β×(M−1) approaches 1 and is characterized by hole current moving into the base region of a bipolar transistor is sometimes referred to as the reverse base current region and has been described for example in “A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistor”, K. Sakui et al., pp. 44-47, International Electron Devices Meeting, 1988 (“Sakui-1”), “A New Static Memory Cell Based on the Reverse Base Current Effect of Bipolar Transistors”, K. Sakui et al., pp. 1215-1217, IEEE Transactions on Electron Devices, vol. 36, no. 6, June 1989 (“Sakui-2”), “On Bistable Behavior and Open-Base Breakdown of Bipolar Transistors in the Avalanche Regime—Modeling and Applications”, M. Reisch, pp. 1398-1409, IEEE Transactions on Electron Devices, vol. 39, no. 6, June 1992 (“Reisch”), which are hereby incorporated herein, in their entireties, by reference thereto.
• The latching behavior based on the reverse base current region has also been described in a biristor (i.e. bi-stable resistor) for example in “Bistable resistor (Biristor)—Gateless Silicon Nanowire Memory”, J.-W. Han and Y.-K. Choi, pp. 171-172, 2010 Symposium on VLSI Technology, Digest of Technical Papers, 2010 “(“J.-W. Han”), which is hereby incorporated herein, in its entirety, by reference thereto. In a two-terminal biristor device, a refresh operation is still required. J.-W. Han describes a 200 ms data retention for the silicon nanowire biristor memory. Inmemory cell50, the state of the memory cell is maintained due to the verticalbipolar transistors30aand30b, while the remaining cell operations (i.e. read and write operations) are governed by the lateralbipolar transistor30candMOS transistor20. Hence, the holding operation does not require any interruptions to thememory cell50 access.
• If floatingbody24 is neutrally charged (the voltage on floatingbody24 being equal to the voltage on grounded bit line region18), a state corresponding to logic-0, no (or low) current will flow through the n-p-nbipolar devices30aand30b. Thebipolar devices30aand30bwill remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
• FIG. 9B shows an energy band diagram of the intrinsicbipolar device30awhen the floatingbody region24 is neutrally charged and a bias voltage is applied to the buriedwell region22. In this state the energy level of the band gap bounded bysolid lines27A and29A is different in the various regions of n-p-nbipolar device30a. Because the potential of the floatingbody region24 and thebit line region18 is equal, the Fermi levels are constant, resulting in an energy barrier between thebit line region18 and the floatingbody region24.Solid line23 indicates, for reference purposes, the energy barrier between thebit line region18 and the floatingbody region24. The energy barrier prevents electron flow from the bit line region18 (connected to BL terminal74) to the floatingbody region24. Thus the n-p-nbipolar device30aand30bwill remain off.
• Sakui-1 and Sakui-2 describe a memory cell based on the reverse base current effect, where the base of a n-p-n bipolar transistor is connected to a p-type MOS transistor. Reisch describes the challenges with the memory cell described in Sakui-1 and Sakui-2, which includes the requirement for the current of the p-type MOS transistor. Because the collector terminal of the bipolar transistor also serves as the channel of the p-type MOS transistor, any changes in operating conditions or process conditions will affect both the bipolar transistor and the p-type MOS transistor. For example, increasing the doping level of the collector region will improve the impact ionization efficiency. However, it will also increase the doping level of the p-type MOS transistor channel region, and reduces the drive current of the p-type MOS transistor.
• An autonomous refresh for a floating body memory, without requiring to first read the memory cell state, has been described for example in “Autonomous Refresh of Floating Body Cell (FBC)”, Ohsawa et al., pp. 801-804, International Electron Device Meeting, 2008 (“Ohsawa”), U.S. Pat. No. 7,170,807 “Data Storage Device and Refreshing Method for Use with Such Device”, Fazan et al. (“Fazan”), which are hereby incorporated herein, in their entireties, by reference thereto. Ohsawa and Fazan teach an autonomous refresh method by applying a periodic gate and drain voltage pulses, which interrupts access to the memory cells being refreshed. Inmemory cell50, more than one stable state is achieved because of the verticalbipolar transistors30aand30b. The read and write operations of thememory cell50 are governed by the lateralbipolar transistor30candMOS transistor20. Hence, the holding operation does not require any interruptions to thememory cell50 access.
• In the holding operation described with regard toFIG. 7, there is no individually selected memory cell. Rather the holding operation will be performed at all cells connected to the same buried well terminal76. In addition, the holding operation does not interrupt read or write access to thememory cell50.
• FIG. 10 shows a graph of the net current I flowing into or out of the floatingbody region24 as a function of the potential V of the floating body24 (not drawn to scale). A negative current indicates a net current flowing into the floatingbody region24, while a positive current indicates a net current flowing out of the floatingbody region24. At low floatingbody24 potential, between 0V and V_FB0indicated inFIG. 10, the net current is flowing into the floatingbody region24 as a result of the p-n diode formed by the floatingbody region24 and the buriedwell region22 being reverse biased. If the value of the floatingbody24 potential is between V_FB0and V_TS, the current will switch direction, resulting in a net current flowing out of the floatingbody region24. This is because of the p-n diode, formed by the floatingbody region24 and the buriedwell region22, being forward biased as the floatingbody region24 becomes increasingly more positive. As a result, if the potential of the floatingbody region24 is less than V_TS, then at steady state the floatingbody region24 will reach V_FB0. If the potential of the floatingbody region24 is higher than V_TS, the current will switch direction, resulting in a net current flowing into the floatingbody region24. This is as a result of the base current flowing into the floatingbody region24 being greater than the p-n diode leakage current. When the floatingbody24 potential is higher than V_FB1, the net current will be out of the floatingbody region24. This is because the p-n diode leakage current is once again greater than the base current of thebipolar devices30aand30b.
• The holding operation results in the floating body memory cell having two stable states: the logic-0 state and the logic-1 state separated by an energy barrier, which are represented by V_FB0, V_FB1, and V_TS, respectively.FIG. 11 shows a schematic curve of a potential energy surface (PES) of thememory cell50, which shows another representation of the two stable states resulting from applying a back bias to the BW terminal76 (connected to the buried well region22).
• The values of the floatingbody24 potential where the current changes direction, i.e. V_FB0, V_FB1, and V_TS, can be modulated by the potential applied to theBW terminal76. These values are also temperature dependent.
• The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floatingbody24. Without the holding/standby operation, the maximum potential that can be stored in the floatingbody24 is limited to the flat band voltage V_FBas the junction leakage current toregions16 and18 increases exponentially at floating body potential greater than V_FB. However, by applying a positive voltage tosubstrate terminal78, the bipolar action results in a hole current flowing into the floatingbody24, compensating for the junction leakage current between floatingbody24 andregions16 and18. As a result, the maximum charge V_MCstored in floatingbody24 can be increased by applying a positive bias to thesubstrate terminal78 as shown inFIG. 12. The increase in the maximum charge stored in the floatingbody24 results in a larger memory window.
• Floating body DRAM cells described in Ranica-1, Ranica-2, Villaret, and Pulicani only exhibit one stable state, which is often assigned as logic-0 state. Villaret describes the intrinsic bipolar transistors enhance the data retention of logic-1 state, by drawing the electrons which otherwise would recombine with the holes stored in the floating body region. However, only one stable state is observed because there is no hole injection into the floating body region to compensate for the charge leakage and recombination.
• The operation range to satisfy the holding operation condition β×(M−1)≈1 is low β and high M to high β and low M. The low β, high M condition is preferred as it results in a lower power for the holding operation since the current flow (from the collector (BW terminal76) to the emitter (source line region16 or bit line region18) is proportional to β. Therefore, the lower the common-emitter gain β (i.e. the closer β is to 1), the lower the current consumed during the holding operation is (a common value of β would be between 20 and 500). Process conditions that result in low β, high M will be described below, following discussion on the read and write operations.
• The read and write operations of the memory cell have been described, for example, in Widjaja-1 and Widjaja-2. An active low read scheme—where the selectedBL terminal74 is biased at low voltage, for example, at zero voltage—will be described inFIGS. 13 and 14, where the following bias conditions are applied: a positive voltage is applied to theBW terminal76a, a positive voltage is applied to the selected SL terminal72a, zero voltage is applied to the selected BL terminal74a, a positive voltage applied to the selected WL terminal70a, while zero voltage is applied to the substrate terminal78a. The positive voltage applied toSL terminal72 may be less than the positive voltage applied toWL terminal70, in which the difference in the threshold voltage of thememory cell50 is employed to represent the state of thememory cell50. The positive voltage applied toSL terminal72 may also be greater than or equal to the positive voltage applied toWL terminal70 and may generate sufficiently high electric field to trigger the bipolar read mechanism. Whencell50 is in anarray80 ofcells50, the unselected BL terminals74 (e.g.,74b, . . . ,74n) will be biased at the same voltage applied to the selected SL terminal, theunselected SL terminals72 will be at zero voltage, and the unselected WL terminals70 (e.g.,70nand anyother WL terminals70 not connected to selectedcell50a) will remain at zero or negative voltage.
• In one particular non-limiting embodiment, about 0.0 volts is applied to the selected BL terminal74a, about +0.4 volts is applied to the selected SL terminal72a, about +1.2 volts is applied to the selected WL terminal70a, about +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied toterminal78, as illustrated inFIG. 13. Theunselected SL terminals72 remain at 0.0 volts, theunselected BL terminals74 are biased at +0.4 volts, and theunselected WL terminals70 remain at 0.0 volts as illustrated inFIG. 13. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
• A row write logic-0 operation is described inFIGS. 15 and 16, where the following bias conditions are applied: a negative voltage is applied to the selected SL terminal72a, zero or positive voltage is applied to theBW terminal76, zero voltage or negative voltage is applied to theWL terminal70, and zero voltage is applied toBL terminal74 andsubstrate terminal78; while zero voltage is applied to theunselected SL terminals72. Under these conditions, the p-n junction between floatingbody24 andsource line region16 of the selectedcell50 is forward-biased, evacuating holes from the floatingbody24. Allmemory cells50 sharing thesame SL terminal72awill be written to simultaneously. To write arbitrary binary data todifferent memory cells50, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.
• In one particular non-limiting embodiment, about −1.2 volts is applied to selected SL terminal72a, about 0.0 volts is applied toWL terminal70a, about 0.0 volts or +1.2 volts is applied toBW terminal76a, and about 0.0 volts is applied to substrate terminal78a. These voltage levels are exemplary only may vary from embodiment to embodiment.
• A write logic-0 operation may also be performed by applying the following bias conditions: a negative voltage to the selectedBW terminal76, zero voltage is applied to theWL terminal70,SL terminal72,BL terminal74, andsubstrate terminal78. Under these conditions, the p-n junction between floatingbody24 and buried well22 of the selectedcell50 is forward-biased, evacuating any holes from the floatingbody24. In one particular non-limiting embodiment, about −0.5 volts is applied toBW terminal76, about 0.0 volts is applied toWL terminal70,SL terminal72,BL terminal76, andsubstrate terminal78. A lower negative voltage may also be applied to thesubstrate terminal78 to prevent the p-n diode formed between thesubstrate terminal78 and theBW terminal76 to be forward biased.
• An active low write logic-1 operation is shown inFIGS. 17 and 18, where the following bias conditions are applied: a positive voltage is applied to theBW terminal76a, a positive voltage is applied to the selected SL terminal72a, zero voltage is applied to the selected BL terminal74a, a positive voltage applied to the selected WL terminal70a, while zero voltage is applied to the substrate terminal78a. The positive voltage applied to the selected SL terminal72ais greater than or equal to the positive voltage applied to the selected WL terminal70aand may generate sufficiently high enough electric field to trigger impact ionization mechanism. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.
• Whencell50 is in anarray80 ofcells50, the unselected BL terminals74 (e.g.,74b, . . . ,74n) will be biased at the same voltage applied to the selected SL terminal, theunselected SL terminals72 will be at zero voltage, and the unselected WL terminals70 (e.g.,70nand anyother WL terminals70 not connected to selectedcell50a) will remain at zero or negative voltage. A negative voltage can be applied on theunselected WL terminals70 to suppress the electron flow from thebit line region18 to sourceline region16, thus reducing the probability that unselected cells in logic-0 state will be accidentally written to logic-1. (The negative voltage will also reduce the probability of undesired write, often referred to as write disturb, in active high write logic-1 scheme).
• In one particular non-limiting embodiment, about 0.0 volts is applied to the selected BL terminal74a, about +1.2 volts is applied to the selected SL terminal72a, about +1.2 volts is applied to the selected WL terminal70a, about +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied to terminal78a, as illustrated inFIG. 17. Theunselected SL terminals72 remain at 0.0 volts, theunselected BL terminals74 are biased at +1.2 volts, and theunselected WL terminals70 remain at 0.0 volts as illustrated inFIG. 17. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
• Low β and high impact ionization efficiency M will result in a more efficient holding operation. In an embodiment of thememory cell50G shown inFIG. 19, the buriedwell region22G comprises a material with a low band gap (relative to the band gap of silicon, which is about 1.12 eV), examples of which include germanium (band gap is ˜0.7 eV) and silicon germanium (band gap depends on the ratio of silicon and germanium), which band gap is lower than that of silicon (band gap is ˜1.12 eV). The lower band gap results in a lower energy necessary to create an electron-hole pair, thus increases the impact ionization efficiency M. The lower band gap also results in a lower voltage that can be applied to theBW terminal76 during the operation of thememory cell50G. For example, using germanium as the buriedwell region22G may result in a holding voltage as low as 0.7V to be applied to theBW terminal76. A lower band gap can also be obtained by having the buriedwell region22G heavily doped. For example, H. P. D Lanyon and R. A. Tuft describe the band gap narrowing in silicon in “Bandgap Narrowing in Moderately to Heavily Doped Silicon”, pp. 1014-1018, IEEE Transactions on Electron Devices, vol. ED-26, no. 7, July 1979. The lowerband gap region22G can be formed through ion implantation process, solid state diffusion, and/or through epitaxial growth process.
• In another embodiment of thememory cell150 shown inFIG. 20A, the floatingbody region24 may comprise regions having different doping concentrations having the same conductivity type.FIG. 20A illustrates an example of floatingbody region24 comprising threedifferent regions24a,24b, and24c.Region24a, which is the closest one to thesurface region14, may have the lowest doping concentration to reduce the random dopant fluctuation (RDF) and hence improve the variability of the memory cell performance, for example its threshold voltage. The doping concentration ofregion24bmay be, but not necessarily, lower than the doping concentration ofregion24c, but higher than that ofregion24a.Region24bmay also function as a barrier layer to suppress dopant diffusion, for example but not limited to Si:C layer. This prevents dopant diffusion from the heavier dopedregion24cto the lowest dopedregion24a. The different floatingbody regions24a,24b, and24c, may be formed through ion implantation process, solid-state diffusion, and/or epitaxial growth.
• FIG. 20B illustrates another example of another embodiment ofmemory cell150 according to the present invention, whereregions24band24care localized, for example between theregions16 and18, meaning thatregions24band24cdo not underlie all portions ofregions16 and18. The remainder ofregion24 outside ofregions24band24cunderlies all portions ofregions16 and18 and is considered to beregion24ain this embodiment.
• FIG. 21A illustrates an equivalent circuit representation ofmemory cell150. Inherent inmemory cell150 are metal-oxide-semiconductor (MOS)transistor120, formed bysource line region16,gate60,bit line region18, and floatingbody region24, andbipolar devices130aand130b, formed by buriedwell region22, floatingbody region24, andsource line region16 orbit line region18, respectively.
• Also inherent inmemory device150 isbipolar device130c, formed bysource line region16, floatingbody24, and bitline region18. For drawings clarity,bipolar device30cis shown separately inFIG. 21B.
• FIG. 22 illustrates an energy band diagram characterizing the intrinsic n-p-nbipolar device130aformed by thesource line region16, floatingbody region24, and the buriedwell region22 when the n-p-n bipolar device is in equilibrium for thememory cell150 comprising of regions withdifferent doping concentrations24a,24b, and24c. The vertical dashed lines mark the regions with different doping concentrations of thebipolar device130b. The energy band diagram of the intrinsic n-p-nbipolar device130bcan be constructed in a similar manner, with the bit line region18 (connected to the BL terminal74) in place of the source line region16 (connected to the SL terminal72). The dashed horizontal lines indicate the Fermi levels in the various regions of the n-p-nbipolar device130a. The Fermi level is located in the band gap between thesolid line27 indicating the top of the valence band (the bottom of the band gap) and thesolid line29 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. The different regions of the floatingbody24 are indicated inFIG. 22. Because of the different doping concentration in different regions of floatingbody24, the Fermi level is also different across different regions. In the band diagram illustrated inFIG. 22,region24cwith the highest doping concentration has the lowest energy for holes storage. As a result, whenmemory cell150 stores holes in the floatingbody region24, holes storage will be concentrated inregion24c.
• FIG. 23 schematically illustrates performance of a holding operation onmemory cell150 comprising different regions of floatingbody24. The holding operation is similar to that ofmemory cell50 shown inFIGS. 7 and 8 and is performed by applying a positive back bias to theBW terminal76, zero bias on theWL terminal70,BL terminal74,SL terminal72, andsubstrate terminal78. The positive back bias applied to the buriedlayer region22 connected to theBW terminal76 will maintain the state of thememory cell50 that it is connected to. The positive bias applied to theBW terminal76 needs to generate sufficient electric field to trigger impact ionization mechanism as will be described through the band diagram shown inFIGS. 24 and 25. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.
• In one embodiment the bias conditions for the holding operation onmemory cell150 is: 0 volts is applied toWL terminal70, 0 volts is applied toBL terminal74, 0 volts is applied toSL terminal72, a positive voltage, for example, +1.2 volts is applied toBW terminal76, and 0 volts is applied to thesubstrate terminal78. In other embodiments, different voltages may be applied to the various terminals ofmemory cell150 and the exemplary voltages described are not limiting.
• FIG. 24 shows an energy band diagram characterizing the intrinsic n-p-nbipolar device130awhen the floatingbody region24 is positively charged and a positive bias voltage is applied to the buriedwell region22. The energy band diagram of the intrinsic n-p-nbipolar device130bcan be constructed in a similar manner, with the bit line region18 (connected to the BL terminal74) in place of the bit line region16 (connected to the SL terminal72). If floatingbody24 is positively charged, a state corresponding to logic-1, thebipolar transistors130aand130bwill be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floatingbody region24, the electrons will be swept into the buried well region22 (connected to BW terminal76) due to the positive bias applied to the buriedwell region22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into theBW terminal76 while the resulting hot holes will subsequently flow into the floatingbody region24. This process restores the charge on floatingbody24 and will maintain the charge stored in the floatingbody region24 which will keep the n-p-nbipolar transistors130aand130bon for as long as a positive bias is applied to the buriedwell region22 throughBW terminal76.
• The higher doping concentration ofregion24crelative to the remaining floatingbody regions24aand24bresult in a higher electric field between the floatingbody region24cand the buriedwell region22. This results in a more efficient impact ionization mechanism, which in turn results in a lower voltage applied to the buried well region needed for the holding operation.
• If floatingbody24 is neutrally charged (the voltage on floatingbody24 being equal to the voltage on grounded source line region16), a state corresponding to logic-0, no current will flow through the n-p-nbipolar devices130aand130b. Thebipolar devices130aand130bwill remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.
• FIG. 25 shows an energy band diagram of the intrinsicbipolar device130awhen the floatingbody region24 is neutrally charged and a bias voltage is applied to the buriedwell region22. In this state the energy level of the band gap bounded bysolid lines27A and29A is different in the various regions of n-p-nbipolar device130a. Because the potential of the floatingbody region24 and thesource line region16 is equal, the Fermi levels are constant, resulting in an energy barrier between thesource line region16 and the floatingbody region24.Solid line23 indicates, for reference purposes, the energy bather between thesource line region16 and the floatingbody region24. The energy bather prevents electron flow from the source line region16 (connected to BL terminal72) to the floatingbody region24. Thus the n-p-nbipolar devices130aand130bwill remain off.
• In the holding operation described with regard toFIG. 23, there is no individually selected memory cell. Rather the holding operation will be performed at all cells connected to the same buried well terminal76.
• An alternative holding operation employing the intrinsic silicon controlled rectifier (SCR) device of memory cell, as described for example in Widjaja-2, may also be performed onmemory cell150.FIG. 26 illustrates bias conditions for an alternative holding operation applied onmemory cell150, as described for example in U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle”, which is incorporated by reference herein in its entirety. The holding operation may also be performed by applying the following bias conditions: zero voltage is applied toWL terminal70,SL terminal72, andBL terminal74, a positive voltage is applied to thesubstrate terminal78, while theBW terminal76 is left floating. Under these conditions, ifmemory cell150 is in memory/data state “1” with positive voltage in floatingbody24, the intrinsic silicon controlled rectifier (SCR) device ofmemory cell150, formed by thesubstrate12, the buriedwell region22, the floatingbody region24, and thebit line region16 or thesource line region18, is turned on, thereby maintaining the state “1” data. Memory cells in state “0” will remain in blocking mode, since the voltage in floatingbody24 is not substantially positive and therefore floatingbody24 does not turn on the SCR device. Accordingly, current does not flow through the SCR device and these cells maintain the state “0” data. In this way, an array ofmemory cells150 may be refreshed by periodically applying a positive voltage pulse throughsubstrate terminal78. Thosememory cells150 that are commonly connected tosubstrate terminal78 and which have a positive voltage inbody region24 will be refreshed with a “1” data state, while thosememory cells150 that are commonly connected to thesubstrate terminal78 and which do not have a positive voltage inbody region24 will remain in blocking mode, since their SCR device will not be turned on, and therefore memory state “0” will be maintained in those cells. In this way, allmemory cells150 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This process occurs automatically, upon application of voltage to thesubstrate terminal78, in a parallel, non-algorithmic, efficient process. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied toBL terminal74, a voltage of about 0.0 volts is applied toWL terminal70, about 0.0 volts is applied toSL terminal72, and about +1.2 volts is applied toterminal78, while theBW terminal76 is left floating. However, these voltage levels may vary, while maintaining the relative relationships therebetween.
• The amount of charge stored in the floatingbody24 can be sensed by monitoring the cell current of thememory cell150. If the memory cell is in a logic-1 state having holes in the floatingbody region24, then thememory cell150 will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current, compared to when the floatingbody memory cell150 is in logic-0 state having no holes in the floatingbody region24. The higher doping concentration ofregion24cwill also result in a larger difference between the logic-0 and logic-1 states.
• FIG. 27 illustrates an exemplary bias condition applied to thememory cell150 for performing a read operation. The read operation is performed by applying the following bias conditions: a positive bias to theWL terminal70, a positive bias to theBL terminal74, zero bias to theSL terminal72, zero or positive bias to theBW terminal76, and zero bias to thesubstrate terminal78.
• In one embodiment the bias conditions for the read operation formemory cell150 are: +1.2 volts is applied toWL terminal70, +0.4 volts is applied toBL terminal74, 0.0 volts is applied toSL terminal72, +1.2 volts is applied toBW terminal76, and 0.0 volts is applied to thesubstrate terminal78. In other embodiments, different voltages may be applied to the various terminals ofmemory cell150 and the exemplary voltages described are not limiting. The positive voltage applied toBL terminal74 may be less than the positive voltage applied toWL terminal70, in which the difference in the threshold voltage of thememory cell150 is employed to represent the state of thememory cell150. The positive voltage applied toBL terminal74 may also be greater than or equal to the positive voltage applied toWL terminal70 and may generate sufficiently high electric field to trigger the bipolar read mechanism.
• A sensing circuit typically connected toBL terminal74 can be used to determine the data state of thememory cell150. Any sensing scheme known in the art can be used in conjunction withmemory cell150.
• A higher doping concentration ofregion24calso results in a higher body effect, which in turn results in a greater difference between the characteristics of memory cells in logic-0 and logic-1 states.
• FIG. 28 illustrates exemplary bias conditions for an active high write logic-1 operation on thememory cell150, where the following bias conditions are applied: a positive voltage is applied to the selectedWL terminal70, a positive voltage is applied to the selectedBL terminal74, zero voltage is applied to the selectedSL terminal72, zero or positive voltage is applied to the selectedBW terminal76, and zero voltage is applied to thesubstrate terminal78. This positive voltage applied to the selectedBL terminal74 is greater than or equal to the positive voltage applied to the selectedWL terminal70 and may generate sufficiently high enough electric field to trigger impact ionization mechanism.
• In one particular non-limiting embodiment, about +1.2 volts is applied to the selectedWL terminal70, about +1.2 volts is applied to the selectedBL terminal74, about 0.0 volts is applied toSL terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied to theunselected WL terminals70, unselectedBL terminals74, unselected SL terminals, andsubstrate terminal78, and 0.0 volts or +1.2 volts is applied toBW terminal76. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• In another example, the positive voltage applied to the selectedWL terminal70 is about one-half of the positive voltage applied to the selectedBL terminal74. These bias conditions result in a high impact ionization efficiency, which will shorten the excess hole charging time to the floatingbody region24 and consequently increase the speed for the write logic-1. In addition, the power required for the write logic-1 operation can be reduced since a lower gate voltage results in a lower current flow (from theBL terminal74 to the SL terminal72) compared to the current flow when the voltage applied to the selectedWL terminal70 is equal to the positive voltage applied to the selectedBL terminal74.
• In another particular non-limiting embodiment, about +0.6 volts is applied to the selectedWL terminal70, about +1.2 volts is applied to the selectedBL terminal74, about 0.0 volts is applied toSL terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied to theunselected WL terminals70, unselectedBL terminals74, unselected SL terminals, andsubstrate terminal78, and 0.0 volts or +1.2 volts is applied toBW terminal76. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• In another embodiment of thememory cell150, the doping concentration ofregion24bmay be lower than the doping concentration ofregion24aand lower than the doping concentration ofregion24c(while the doping concentration ofregion24cis higher than that ofregion24a). This results in a current flow in theregion24b, away from thesurface14 of thememory cell150. This will be advantageous for logic-1 write operation using impact ionization mechanism, as the hot electron will be generated away from thesurface14, hence reduces the damage ofgate oxide62 due to hot electron effect and improves the reliability of thememory cell150.
• FIG. 29 is a schematic illustration showing bias conditions for a write logic-1 operation using band-to-band tunneling mechanism performed onmemory cell150, where the following bias conditions are applied: a negative voltage is applied to the selectedWL terminal70, a positive voltage is applied to the selectedBL terminal74, zero voltage is applied to the selectedSL terminal72, zero or positive voltage is applied to the selectedBW terminal76, and zero voltage is applied to thesubstrate terminal78.
• In one particular non-limiting embodiment, about −1.2 volts is applied to the selectedWL terminal70, about +1.2 volts is applied to the selectedBL terminal74, about 0.0 volts is applied toSL terminal72, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78; while about 0.0 volts is applied to theunselected WL terminals70, unselectedBL terminals74, unselected SL terminals, andsubstrate terminal78, and 0.0 volts or +1.2 volts is applied toBW terminal76. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• The negative charge on the gate60 (connected to WL terminal70) and the positive voltage on bit line region18 (connected to BL terminal74) create a strong electric field (for example, about 10⁶V/cm in silicon, as described in Sze, p. 104) between thebit line region18 and the floatingbody region24 in the proximity ofgate60. This bends the energy band sharply upward near the gate and bit line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floatingbody region24 and become the hole charge that creates the logic-1 state.
• FIG. 30 is a schematic illustration showing bias conditions for a write logic-0 operation which can be performed by applying a negative voltage bias to the selectedSL terminal72, zero bias to the selectedWL terminal70, zero bias to theBL terminal74, zero or positive bias to theBW terminal76, and zero bias to thesubstrate terminal78; while zero voltage is applied to theunselected SL terminals72, zero voltage bias applied to theunselected WL terminals70, zero or positive bias applied to theBW terminal76, and zero voltage bias applied to thesubstrate78. Under these conditions, the p-n junction between floatingbody24 andsource line region16 of the selectedcell150 is forward-biased, evacuating holes from the floatingbody24. Allmemory cells150 sharing the same selected SL terminal72awill be written to simultaneously. To write arbitrary binary data todifferent memory cells150, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.
• In one particular non-limiting embodiment, about −1.2 volts is applied to selectedSL terminal72, about 0.0 volts is applied toWL terminal70, about 0.0 volts is applied toBL terminal74, about 0.0 volts or +1.2 volts is applied toBW terminal76, and about 0.0 volts is applied tosubstrate terminal78, while zero voltage is applied to theunselected SL terminals72, zero voltage bias applied to theunselected WL terminals70, zero or positive bias applied to theBW terminal76, and zero voltage bias applied to thesubstrate78. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• FIG. 31 illustrates a bit-selective write logic-0 operation performed on a selectedmemory cell150, where the following bias conditions are applied: a positive voltage to the selectedWL terminal70, a negative voltage to the selectedBL terminal74, zero voltage bias to the selectedSL terminal72, zero or positive voltage bias to theBW terminal76, and zero voltage to thesubstrate terminal78; while zero voltage is applied to theunselected WL terminals70, zero voltage is applied to theunselected BL terminals74, zero voltage bias is applied to theunselected SL terminals72, zero or positive voltage is applied to theBW terminal76, and zero voltage is applied to thesubstrate terminal78. Under these conditions, the floatingbody24 potential will increase through capacitive coupling from the positive voltage applied to theWL terminal70. As a result of the floatingbody24 potential increase and the negative voltage applied to theBL terminal74, the p-n junction between floatingbody region24 andbit line region18 is forward-biased, evacuating holes from the floatingbody24.
• To reduce undesired write logic-0 disturb toother memory cells150 in a memory array, the applied potential can be optimized as follows: if the floatingbody24 potential of state logic-1 is referred to as V_FB1, then the voltage applied to theWL terminal70 is configured to increase the floatingbody24 potential by V_FB1/2 while −V_FB1/2 is applied toBL terminal74. Additionally, either ground or a slightly positive voltage may also be applied to theBL terminals74 ofunselected memory cells150 that do not share thesame BL terminal74 as the selectedmemory cell150, while a negative voltage may also be applied to theWL terminals70 ofunselected memory cells150 that do not share thesame WL terminal70aas the selectedmemory cell150.
• As illustrated inFIG. 31, the following exemplary bias conditions may be applied to the selectedmemory cell50 to perform a bit-selective write logic-0 operation: a potential of about −0.2 volts to the selectedBL terminal74, a potential of about +1.2 volts to the selectedWL terminal70, about 0.0 volts is applied to the selectedSL terminal72, a potential of about 0.0 volts or +1.2 volts to theBW terminal76, about 0.0 volts to thesubstrate terminal78.
• FIG. 32A illustratesmemory cell250 according to another embodiment of the present invention, which compriseshalo regions17 and19 of the first conductivity type respectively adjacent to thesource line region16 andbit line region18 of the second conductivity type.Memory cell250 may comprise bothhalo regions17 and19, ormemory cell250 may comprise only onehalo region17 or19, as shown in anasymmetric cell250 inFIG. 32B.FIG. 32A also shows floatingbody region24 comprises, although not necessarily,different doping concentrations24a,24b, and24c. Thehalo regions17 or19 can be located at an angle with respect to thesurface14, such as shown inFIG. 32A or could be located below thesource line region16 orbit line region18, such as shown inFIG. 32B.
• FIG. 33 illustrates the band diagram ofmemory cell250 under equilibrium condition. Because of the different doping concentrations, multiple regions with lower energy for holes exist inmemory cell250. For example, regions of low energy for holes storage are available in halo region17 (and19) andregion24c. Multiple storage locations can be used to construct a multi-level cell with amemory cell250 storing holes in different regions of thememory cell250.
• FIG. 34 illustrates a cross-sectional view of another embodiment of thememory cell350.Memory cell350 is asymmetric in that thesource line region16 and thebit line region18 have different physical properties, for example the junction depth, and electrical properties, for example the breakdown voltage. As will be described,asymmetric memory cell350 has some advantages, for example, allowing for a write logic-1 operation through impact ionization mechanism away from thesurface region14. This results in less degradation of thegate oxide62. The source line region16 (connected to the SL terminal72) is shown to have a deeper junction depth inFIG. 34 than that ofbit line region18. In another embodiment of thememory cell350, thebit line region18 may have a deeper junction depth than thesource line region16.
• An equivalent circuit representation ofmemory cell350 is shown inFIG. 35. The verticalbipolar device330a—formed by thesource line region16, floatingbody region24, and buried wellregion22—is schematically shown to be larger in size compared to the verticalbipolar device330b, formed by thebit line region18, floatingbody region24, and buried wellregion22. For the same bias conditions (for example the same voltage difference across the emitter and collector terminals, i.e. the buriedwell region22 and thesource line region16 or the bit line region18), the verticalbipolar device330awill conduct a higher current because of the narrower base region of thebipolar device330a. Similarly, the emitter-collector breakdown voltage, which results in impact ionization at the collector region (buried well region22) and subsequently injects holes into the floatingbody region24, is lower forbipolar device330acompared to that ofbipolar device330b.
• Also inherent inmemory device350 isbipolar device330c, formed bysource line region16, floatingbody24, and bitline region18. For drawings clarity,bipolar device330cis shown separately inFIG. 36.
• The operations performed on thememory cell350 are similar to those ofmemory cell50. Due to the asymmetric nature of thememory cell350, further optimizations can be performed to the write operations.
• FIG. 37 schematically illustrates a write logic-1 operation performed onmemory array380, where the following bias conditions are applied to the selectedmemory cell350a: a positive voltage is applied to the selectedWL terminal70, zero voltage is applied to the selectedBL terminal74, a positive voltage is applied to theBW terminal76, zero voltage is applied to thesubstrate terminal78, and selectedSL terminal72 is left floating; while the following bias conditions are applied to the unselected terminals: zero voltage is applied to theunselected WL terminal70, a positive voltage is applied to theunselected BL terminal74, a positive voltage is applied to theunselected SL terminal72, a positive voltage is applied to the unselected BW terminal, and zero voltage is applied to the unselected substrate terminal78 (in the case ofmemory array380 where theBW terminals76 andsubstrate terminals78 are segmented).
• In one particular non-limiting embodiment, about +0.6 volts is applied to selectedWL terminal70, about 0.0 volts is applied to the selectedBL terminal74, about +1.2 volts is applied to the selectedBW terminal76, about 0.0 volts is applied to thesubstrate terminal78, while selectedSL terminal72 is left floating; while about 0.0 volts is applied to theunselected WL terminal70, about +0.6 volts is applied to theunselected BL terminal74, and about +0.6 volts is applied to theunselected SL terminal72. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.
• The bias conditions on the selectedmemory cell350aare shown inFIG. 38. The positive voltage applied to the selected WL terminal70awill turn on theMOS transistor320 and pull the source line region16 (which is floating) to about zero voltage (the potential applied to theBL terminal74a). Because thebipolar transistor330ahas a lower emitter-collector breakdown voltage, this will result in electron flow from thesource line region16 to the buriedwell region22. The electron flow will result in impact ionization at the interface of the buriedwell region22 and the floatingbody region24, and hot holes will be injected to the floatingbody region24. No (or significantly lower) electron flow will occur through thebipolar transistor330bas it has a higher emitter-collector breakdown voltage.
• FIG. 39 shows the bias conditions on theunselected memory cell350b, which is a representative of an unselected memory cell in the same row as the selectedmemory cell350a. The potential of the floatingsource line region16 for thememory cell350bwill be about the voltage difference between the gate voltage and the threshold voltage of theMOS transistor320. The emitter-collector voltage (the difference between the potential of the buriedwell region22 and thesource line region16 or the bit line region18) is lower than the emitter-collector breakdown voltage of bothbipolar transistors330aand330band thus no (or significantly lower) impact ionization occurs on theunselected memory cell350b.
• FIG. 40 shows the bias conditions on theunselected memory cell350c, which is a representative of an unselected memory cell sharing the same column as the selectedmemory cell350a. The emitter-collector voltages of thebipolar transistor330aand330bare both lower than the emitter-collector breakdown voltages of bothbipolar transistor330aand330band thus no (or significantly lower) impact ionization occurs on theunselected memory cell350c.
• FIG. 41 shows the bias conditions on theunselected memory cell350d, which is a representative of an unselected memory cell sharing neither row nor column with the selectedmemory cell350a. The emitter-collector voltages of thebipolar transistor330aand330bare both lower than the emitter-collector breakdown voltages of bothbipolar transistor330aand330band thus no (or significantly lower) impact ionization occurs on theunselected memory cell350d.
• A write logic-0 is performed on thememory cell350 as shown inFIGS. 42 and 43 through the application of the following bias conditions: a negative voltage is applied to the selectedSL terminal72, zero or negative voltage is applied to the selectedWL terminal70, zero voltage is applied to theBL terminal74, zero or positive voltage is applied to the selectedBW terminal76, and zero voltage is applied to the selectedsubstrate terminal78; while zero voltage is applied to theunselected SL terminal72,BL terminal74, andsubstrate terminal78, zero or negative voltage is applied to theunselected WL terminal70, and zero or positive voltage is applied to the selectedBW terminal76.
• Under these conditions, the p-n junction between floatingbody24 andsource line region16 of the selectedcell350 is forward-biased, evacuating holes from the floatingbody24. Allmemory cells350 sharing the same selected SL terminal72awill be written to simultaneously. To write arbitrary binary data todifferent memory cells350, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.
• In the write logic-0 operation shown inFIGS. 42 and 43, hole injection into the floatingbody region24 may occur if the emitter-collector voltage of thebipolar transistor330ais larger than its emitter-collector breakdown voltage and reduces the efficiency of the write logic-0 operation. In another embodiment of the write logic-0 operation, the following bias conditions are applied: a negative voltage is applied to the selectedBL terminal74, zero or negative voltage is applied to the selectedWL terminal70, zero voltage is applied to theSL terminal72, zero or positive voltage is applied to the selectedBW terminal76, and zero voltage is applied to the selectedsubstrate terminal78; while zero voltage is applied to theunselected SL terminal72,BL terminal74, andsubstrate terminal78, zero or negative voltage is applied to theunselected WL terminal70, and zero or positive voltage is applied to the selectedBW terminal76. Because the emitter-collector breakdown voltage of thebipolar transistor330bis higher than that ofbipolar transistor330a, no (or significantly lower) impact ionization and hole injection into the floatingbody region24 occur.
• Memory cells50,50G,150,250, and350 can also be constructed in a three-dimensional structure for example having FinFET structures.
• FIGS. 44A-44B andFIGS. 45A-45C illustrate reference memory cells450R1 and450R2, respectively, which have been described by Widjaja in U.S. application Ser. No. 13/244,899, “Asymmetric Semiconductor Memory Device Having Electrically Floating Body”, which is hereby incorporated herein, in its entirety, by reference thereto. Reference memory cells450R1 and450R2 comprisesense line region20 having the same conductivity type as that of floatingbody region24. Thesense line region20 allows for an Ohmic connection to the floatingbody region24. Reference memory cells450R1 and450R2 may also comprise buried wellregions22G having a lower band gap materials (such as illustrated in memory cell500 shown inFIG. 19), or having different regions comprising the floating body region24 (such asregions24a,24b, and24cofmemory cell150 shown inFIG. 20A),halo regions17 and19 (such asmemory cell250 shown inFIG. 32A orFIG. 32B), or having asymmetric source and drain regions (such asmemory cell350 shown inFIG. 34).
• FIG. 46 shows anexemplary memory array80 comprising a plurality ofmemory cells50 along with a row of reference cells450R1. Although only one row of reference cells450R1 is shown, it is understood thatmemory array80 may comprise multiple rows of reference cells450R1, which may be located adjacent to each other or located separate from each other. Similarly, rows of reference cells450R1 may be located at the edge of thearray80, or in the middle of thememory array80, or otherwise intermediate of rows ofmemory cells50.
• FIG. 47 shows anexemplary memory array80 comprising a plurality ofmemory cells50 along with a column of reference cells450R2. Although only one column of reference cells450R2 is shown, it is understood thatmemory array80 may comprise multiple columns of reference cells450R2, which may be located adjacent to each other or located separate from each other. Similarly, columns of reference cells450R2 may be located at the edge of thearray80, or in the middle of thememory array80, or otherwise intermediate of columns ofmemory cells50.
• From the foregoing it can be seen that a memory cell comprising a floating body transistor has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.
• While the present invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, process, process step or steps, to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto.

Claims (20)

1-29. (canceled)

30. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region; and

a back-bias region configured to maintain a charge in said floating body region;

wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity, and

wherein said back bias region has a lower band gap than said floating body region.

31. The semiconductor memory cell ofclaim 30, wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.

32. The semiconductor memory cell ofclaim 30, further comprising a second region in electrical contact with said floating body region and spaced apart from said first region.

33. The semiconductor memory cell ofclaim 30, further comprising a gate region positioned above said floating body region.

34. The semiconductor memory cell ofclaim 30, further comprising a substrate region, wherein said back-bias region is positioned between said substrate region and said floating body region.

35. The semiconductor memory cell ofclaim 30 wherein said first and second states are stable states.

36. The semiconductor memory cell ofclaim 30, wherein said floating body region comprises first and second subregions, wherein said first subregion has a first doping concentration level and said second region has a second doping concentration level, and wherein said first doping concentration is different from said second doping concentration level.

37. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a back bias region;

wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;

wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region; and

wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell.

38. The semiconductor memory cell ofclaim 37, wherein said back-bias region is configured to maintain a charge in said floating body region.

39. The semiconductor memory cell ofclaim 37, wherein said first and second states are stable states.

40. The semiconductor memory cell ofclaim 37, wherein a product of forward emitter gain and impact ionization efficiency of said first bipolar transistor approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

41. The semiconductor memory cell ofclaim 37, wherein current flow through said first bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states.

42. The semiconductor memory cell ofclaim 37, wherein said memory cell states are maintained through impact ionization.

43. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and

a back-bias region located below said floating body region;

wherein said back-bias region acts as a collector region of a bipolar transistor that maintains the state of said memory cell and has a lower band gap than said floating body region.

44. The semiconductor memory cell ofclaim 43, wherein said first and second states are stable.

45. The semiconductor memory cell ofclaim 43, wherein a product of forward emitter gain and impact ionization efficiency of said bipolar transistor that maintains the state of said memory cell approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

46. The semiconductor memory cell ofclaim 43, wherein current flow through said bipolar transistor is larger when said memory cell is in one said first and second states than when said memory cell is in the other of said first and second states.

47. The semiconductor memory cell ofclaim 43, wherein said memory cell states are maintained through impact ionization.

48. The semiconductor memory cell ofclaim 43, wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.

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