US20160054834A1 - Slew rate and shunting control separation - Google Patents

Abstract

Setting a slew rate, e.g., a rising time or a falling time, of a scanning signal can be performed with a first operation, and a shunting resistance of the scanning line can be set with a second operation. A scanning system that scans a display screen, a touch screen, etc., can set a desired slew rate during a first period of time and can set a desired shunting resistance during a second period of time. A gate line system can sequentially scan gate lines to display an image during a display phase of a touch screen. The gate line system can, for example, increase the falling times of gate line signals. After the falling gate line signal has stabilized, for example, the gate line system can decrease the shunting resistance of the gate line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 12/976,909, filed Dec. 22, 2010, and published as 2012-0162121 on Jun. 28, 2012, the disclosure of which is herein incorporated by reference in its entirety for all purposes.
FIELD OF THE DISCLOSURE
• This relates generally to touch screens, and more particularly to systems and methods of separately controlling a slew rate of a scanning signal and a shunting capability of the scanning line.
BACKGROUND OF THE DISCLOSURE
• Many types of input devices are presently available for performing operations in a computing system, such as buttons or keys, mice, trackballs, joysticks, touch sensor panels, touch screens and the like. Touch screens, in particular, are becoming increasingly popular because of their ease and versatility of operation as well as their declining price. Touch screens can include a touch sensor panel, which can be a clear panel with a touch-sensitive surface, and a display device such as a liquid crystal display (LCD) that can be positioned partially or fully behind the panel so that the touch-sensitive surface can cover at least a portion of the viewable area of the display device. Touch screens can allow a user to perform various functions by touching the touch sensor panel using a finger, stylus or other object at a location often dictated by a user interface (UI) being displayed by the display device. In general, touch screens can recognize a touch and the position of the touch on the touch sensor panel, and the computing system can then interpret the touch in accordance with the display appearing at the time of the touch, and thereafter can perform one or more actions based on the touch. In the case of some touch sensing systems, a physical touch on the display is not needed to detect a touch. For example, in some capacitive-type touch sensing systems, fringing fields used to detect touch can extend beyond the surface of the display, and objects approaching near the surface may be detected near the surface without actually touching the surface.
• Capacitive touch sensor panels can be formed from a matrix of drive and sense lines of a substantially transparent conductive material, such as Indium Tin Oxide (ITO), often arranged in rows and columns in horizontal and vertical directions on a substantially transparent substrate. It is due in part to their substantial transparency that capacitive touch sensor panels can be overlaid on a display to form a touch screen, as described above. Some touch screens can be formed by integrating touch sensing circuitry into a display pixel stackup (i.e., the stacked material layers forming the display pixels).
SUMMARY
• The following description includes examples of systems and methods in which a slew rate, e.g., a rising time or a falling time, of a scanning signal can be set with a first operation, and a shunting resistance of the scanning line can be set with a second operation. In some embodiments, a scanning system that scans a display screen, a touch screen, etc., can set a desired slew rate during a first period of time and can set a desired shunting resistance during a second period of time. In some embodiments, a gate line system can sequentially scan gate lines to display an image during a display phase of a touch screen. The gate line system can, for example, increase the falling times of gate line signals to reduce or eliminate certain visual artifacts that can be caused by short falling times. After the falling gate line signal has stabilized, for example, the gate line system can decrease the shunting resistance of the gate line to reduce or eliminate other visual artifacts that can be caused by high shunting resistance of the gate line.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1A-1C illustrate an example mobile telephone, an example media player, and an example personal computer that each include an example touch screen according to embodiments of the disclosure.
• FIG. 2 is a block diagram of an example computing system that illustrates one implementation of an example touch screen according to embodiments of the disclosure.
• FIG. 3 is a more detailed view of the touch screen ofFIG. 2 showing an example configuration of drive lines and sense lines according to embodiments of the disclosure.
• FIG. 4 illustrates an example configuration in which touch sensing circuitry includes common electrodes (Vcom) according to embodiments of the disclosure.
• FIG. 5 illustrates an exploded view of display pixel stackups according to embodiments of the disclosure.
• FIG. 6 illustrates an example touch sensing operation according to embodiments of the disclosure.
• FIG. 7 illustrates a partial circuit diagram of an example display pixel according to embodiments of the disclosure.
• FIG. 8 illustrates an example configuration of horizontal and vertical Vcom lines according to embodiments of the disclosure.
• FIG. 9 illustrates a partial circuit diagram of example display pixels according to embodiments of the disclosure.
• FIG. 10 illustrates an example double-sided gate driver configuration according to embodiments of the disclosure.
• FIG. 11 illustrates example gate drivers according to embodiments of the disclosure.
• FIG. 12 illustrates example gate clock signals according to embodiments of the disclosure.
• FIG. 13 illustrates an example method performing separate control of a falling time operation and a shunting operation according to embodiments of the disclosure.
• FIG. 14 illustrates example signals of an example gate line system according to embodiments of the disclosure.
• FIG. 15 illustrates an example Vcom driver system according to embodiments of the disclosure.
• FIG. 16 illustrates an example timing of signals of a Vcom driver system ofFIG. 15 according to embodiments of the disclosure.
DETAILED DESCRIPTION
• In the following description of example embodiments, reference is made to the accompanying drawings which form a part hereof, and in which it is shown by way of illustration specific embodiments in which embodiments of the disclosure can be practiced. It is to be understood that other embodiments can be used and structural changes can be made without departing from the scope of the embodiments of this disclosure.
• The following description includes examples of systems and methods in which a slew rate, e.g., a rising time or a falling time, of a scanning signal can be set with a first operation, and a shunting resistance of the scanning line can be set with a second operation. In some embodiments, a scanning system that scans a display screen, a touch screen, etc., can set a desired slew rate during a first period of time and can set a desired shunting resistance during a second period of time. In some embodiments, a gate line system can sequentially scan gate lines to display an image during a display phase of a touch screen. The gate line system can, for example, increase the falling times of gate line signals to reduce or eliminate certain visual artifacts that can be caused by short falling times. After the falling gate line signal has stabilized, for example, the gate line system can decrease the shunting resistance of the gate line to reduce or eliminate other visual artifacts that can be caused by high shunting resistance of the gate line.
• Example systems and methods can be utilized in many types of scanning systems, and can be particularly useful in systems that implement CMOS transistors to control the application of the scanning signals to scan lines. Separate control of scanning signal slew rate and scan line shunting resistance can be useful in some integrated touch screen systems.FIGS. 1A-1C and2 illustrate some example systems in which touch screens, including integrated touch screens, can be implemented.FIGS. 3-6 illustrate some example structures and operations of example integrated touch screens.FIGS. 7-9 illustrate some potential errors, such as visual artifacts, that can occur in some integrated touch screens.FIGS. 10-15 illustrate example embodiments of systems and methods that can set a slew rate of a scanning signal with a first operation, and can set a shunting resistance of the scanning line with a second operation. In this way, for example, some visual artifacts can be reduced or eliminated by adjusting the slew rate of a scanning signal, and other visual artifacts can be reduced or eliminated by adjusting the shunting resistances of the scan lines.
• FIGS. 1A-1C show example systems in which a touch screen according to embodiments of the disclosure may be implemented.FIG. 1A illustrates an examplemobile telephone136 that includes atouch screen124.FIG. 1B illustrates an exampledigital media player140 that includes atouch screen126.FIG. 1C illustrates an examplepersonal computer144 that includes atouch screen128.Touch screens124,126, and128 may be based on, for example, self capacitance or mutual capacitance, or another touch sensing technology in which effects of parasitic capacitances can be equalized. For example, in a self capacitance based touch system, an individual electrode with a self-capacitance to ground can be used to form a touch pixel for detecting touch. As an object approaches the touch pixel, an additional capacitance to ground can be formed between the object and the touch pixel. The additional capacitance to ground can result in a net increase in the self-capacitance seen by the touch pixel. This increase in self-capacitance can be detected and measured by a touch sensing system to determine the positions of multiple objects when they touch the touch screen. A mutual capacitance based touch system can include, for example, drive regions and sense regions, such as drive lines and sense lines. For example, drive lines can be formed in rows while sense lines can be formed in columns (e.g., orthogonal). Touch pixels can be formed at the intersections of the rows and columns. During operation, the rows can be stimulated with an AC waveform and a mutual capacitance can be formed between the row and the column of the touch pixel. As an object approaches the touch pixel, some of the charge being coupled between the row and column of the touch pixel can instead be coupled onto the object. This reduction in charge coupling across the touch pixel can result in a net decrease in the mutual capacitance between the row and the column and a reduction in the AC waveform being coupled across the touch pixel. This reduction in the charge-coupled AC waveform can be detected and measured by the touch sensing system to determine the positions of multiple objects when they touch the touch screen. In some embodiments, a touch screen can be multi-touch, single touch, projection scan, full-imaging multi-touch, or any capacitive touch.
• FIG. 2 is a block diagram of anexample computing system200 that illustrates one implementation of anexample touch screen220 according to embodiments of the disclosure.Computing system200 could be included in, for example,mobile telephone136,digital media player140,personal computer144, or any mobile or non-mobile computing device that includes a touch screen.Computing system200 can include a touch sensing system including one ormore touch processors202,peripherals204, atouch controller206, and touch sensing circuitry (described in more detail below).Peripherals204 can include, but are not limited to, random access memory (RAM) or other types of memory or storage, watchdog timers and the like.Touch controller206 can include, but is not limited to, one ormore sense channels208,channel scan logic210 anddriver logic214.Channel scan logic210 can accessRAM212, autonomously read data from the sense channels and provide control for the sense channels. In addition,channel scan logic210 can controldriver logic214 to generatestimulation signals216 at various frequencies and phases that can be selectively applied to drive regions of the touch sensing circuitry oftouch screen220, as described in more detail below. In some embodiments,touch controller206,touch processor202 andperipherals204 can be integrated into a single application specific integrated circuit (ASIC).
• Computing system200 can also include ahost processor228 for receiving outputs fromtouch processor202 and performing actions based on the outputs. For example,host processor228 can be connected toprogram storage232 and a display controller, such as anLCD driver234.Host processor228 can useLCD driver234 to generate an image ontouch screen220, such as an image of a user interface (UI), and can usetouch processor202 andtouch controller206 to detect a touch on or neartouch screen220, such a touch input to the displayed UI. The touch input can be used by computer programs stored inprogram storage232 to perform actions that can include, but are not limited to, moving an object such as a cursor or pointer, scrolling or panning, adjusting control settings, opening a file or document, viewing a menu, making a selection, executing instructions, operating a peripheral device connected to the host device, answering a telephone call, placing a telephone call, terminating a telephone call, changing the volume or audio settings, storing information related to telephone communications such as addresses, frequently dialed numbers, received calls, missed calls, logging onto a computer or a computer network, permitting authorized individuals access to restricted areas of the computer or computer network, loading a user profile associated with a user's preferred arrangement of the computer desktop, permitting access to web content, launching a particular program, encrypting or decoding a message, and/or the like.Host processor228 can also perform additional functions that may not be related to touch processing.
• Touch screen220 can include touch sensing circuitry that can include a capacitive sensing medium having a plurality ofdrive lines222 and a plurality of sense lines223. It should be noted that the term “lines” is sometimes used herein to mean simply conductive pathways, as one skilled in the art will readily understand, and is not limited to elements that are strictly linear, but includes pathways that change direction, and includes pathways of different size, shape, materials, etc. Drivelines222 can be driven bystimulation signals216 fromdriver logic214 through adrive interface224, and resulting sense signals217 generated insense lines223 can be transmitted through asense interface225 to sense channels208 (also referred to as an event detection and demodulation circuit) intouch controller206. In this way, drive lines and sense lines can be part of the touch sensing circuitry that can interact to form capacitive sensing nodes, which can be thought of as touch picture elements (touch pixels), such astouch pixels226 and227. This way of understanding can be particularly useful whentouch screen220 is viewed as capturing an “image” of touch. In other words, aftertouch controller206 has determined whether a touch has been detected at each touch pixel in the touch screen, the pattern of touch pixels in the touch screen at which a touch occurred can be thought of as an “image” of touch (e.g. a pattern of fingers touching the touch screen).
• In some example embodiments,touch screen220 can be an integrated touch screen in which touch sensing circuit elements of the touch sensing system can be integrated into the display pixels stackups of a display. An example integrated touch screen in which embodiments of the disclosure can be implemented with now be described with reference toFIGS. 3-6.FIG. 3 is a more detailed view oftouch screen220 showing an example configuration ofdrive lines222 andsense lines223 according to embodiments of the disclosure. As shown inFIG. 3, eachdrive line222 can be formed of one or moredrive line segments301 that can be electrically connected by drive line links303 atconnections305. Drive line links303 are not electrically connected to senselines223, rather, the drive line links can bypass the sense lines throughbypasses307. Drivelines222 andsense lines223 can interact capacitively to form touch pixels such astouch pixels226 and227. Drive lines222 (i.e., driveline segments301 and corresponding drive line links303) andsense lines223 can be formed of electrical circuit elements intouch screen220. In the example configuration ofFIG. 3, each oftouch pixels226 and227 can include a portion of onedrive line segment301, a portion of asense line223, and a portion of anotherdrive line segment301. For example,touch pixel226 can include a right-half portion309 of a drive line segment on one side of aportion311 of a sense line, and a left-half portion313 of a drive line segment on the opposite side ofportion311 of the sense line.
• The circuit elements can include, for example, elements that can exist in conventional LCD displays, as described above. It is noted that circuit elements are not limited to whole circuit components, such a whole capacitor, a whole transistor, etc., but can include portions of circuitry, such as only one of the two plates of a parallel plate capacitor.FIG. 4 illustrates an example configuration in which common electrodes (Vcom) can form portions of the touch sensing circuitry of a touch sensing system. Each display pixel includes a common electrode401, which is a circuit element of the display system circuitry in the pixel stackup (i.e., the stacked material layers forming the display pixels) of the display pixels of some types of conventional LCD displays, e.g., fringe field switching (FFS) displays, that can operate as part of the display system to display an image.
• In the example shown inFIG. 4, each common electrode (Vcom)401 can serve as a multi-function circuit element that can operate as display circuitry of the display system oftouch screen220 and can also operate as touch sensing circuitry of the touch sensing system. In this example, each common electrode401 can operate as a common electrode of the display circuitry of the touch screen, and can also operate together when grouped with other common electrodes as touch sensing circuitry of the touch screen. For example, a group of common electrodes401 can operate together as a capacitive part of a drive line or a sense line of the touch sensing circuitry during the touch sensing phase. Other circuit elements oftouch screen220 can form part of the touch sensing circuitry by, for example, electrically connecting together common electrodes401 of a region, switching electrical connections, etc. In general, each of the touch sensing circuit elements may be either a multi-function circuit element that can form part of the touch sensing circuitry and can perform one or more other functions, such as forming part of the display circuitry, or may be a single-function circuit element that can operate as touch sensing circuitry only. Similarly, each of the display circuit elements may be either a multi-function circuit element that can operate as display circuitry and perform one or more other functions, such as operating as touch sensing circuitry, or may be a single-function circuit element that can operate as display circuitry only. Therefore, in some embodiments, some of the circuit elements in the display pixel stackups can be multi-function circuit elements and other circuit elements may be single-function circuit elements. In other embodiments, all of the circuit elements of the display pixel stackups may be single-function circuit elements.
• In addition, although example embodiments herein may describe the display circuitry as operating during a display phase, and describe the touch sensing circuitry as operating during a touch sensing phase, it should be understood that a display phase and a touch sensing phase may be operated at the same time, e.g., partially or completely overlap, or the display phase and touch phase may operate at different times. Also, although example embodiments herein describe certain circuit elements as being multi-function and other circuit elements as being single-function, it should be understood that the circuit elements are not limited to the particular functionality in other embodiments. In other words, a circuit element that is described in one example embodiment herein as a single-function circuit element may be configured as a multi-function circuit element in other embodiments, and vice versa.
• For example,FIG. 4 shows common electrodes401 grouped together to form drive region segments403 and sense regions405 that generally correspond to driveline segments301 andsense lines223, respectively. Grouping multi-function circuit elements of display pixels into a region can mean operating the multi-function circuit elements of the display pixels together to perform a common function of the region. Grouping into functional regions may be accomplished through one or a combination of approaches, for example, the structural configuration of the system (e.g., physical breaks and bypasses, voltage line configurations), the operational configuration of the system (e.g., switching circuit elements on/off, changing voltage levels and/or signals on voltage lines), etc.
• Multi-function circuit elements of display pixels of the touch screen can operate in both the display phase and the touch phase. For example, during a touch phase, common electrodes401 can be grouped together to form touch signal lines, such as drive regions and sense regions. In some embodiments circuit elements can be grouped to form a continuous touch signal line of one type and a segmented touch signal line of another type. For example,FIG. 4 shows one example embodiment in which drive region segments403 and sense regions405 correspond to driveline segments301 andsense lines223 oftouch screen220. Other configurations are possible in other embodiments, for example, common electrodes401 could be grouped together such that drive lines are each formed of a continuous drive region and sense lines are each formed of a plurality of sense region segments linked together through connections that bypass a drive region.
• The drive regions in the example ofFIG. 3 are shown inFIG. 4 as rectangular regions including a plurality of common electrodes of display pixels, and the sense regions ofFIG. 3 are shown inFIG. 4 as rectangular regions including a plurality of common electrodes of display pixels extending the vertical length of the LCD. In some embodiments, a touch pixel of the configuration ofFIG. 4 can include, for example, a 64×64 area of display pixels. However, the drive and sense regions are not limited to the shapes, orientations, and positions shown, but can include any suitable configurations according to embodiments of the disclosure. It is to be understood that the display pixels used to form the touch pixels are not limited to those described above, but can be any suitable size or shape to permit touch capabilities according to embodiments of the disclosure.
• FIG. 5 is a three-dimensional illustration of an exploded view (expanded in the z-direction) of exampledisplay pixel stackups500 showing some of the elements within the pixel stackups of an exampleintegrated touch screen550.Stackups500 can include a configuration of conductive lines that can be used to group common electrodes, such as common electrodes401, into drive region segments and sense regions, such as shown inFIG. 4, and to link drive region segments to form drive lines.
• Stackups500 can include elements in a first metal (M1) layer501, a second metal (M2)layer503, a common electrode (Vcom)layer505, and a third metal (M3)layer507. Each display pixel can include acommon electrode509, such as common electrodes401 inFIG. 4, that is formed inVcom layer505.M3 layer507 can includeconnection element511 that can electrically connect togethercommon electrodes509. In some display pixels, breaks513 can be included inconnection element511 to separate different groups ofcommon electrodes509 to formdrive region segments515 and asense region517, such as drive region segments403 and sense region405, respectively.Breaks513 can include breaks in the x-direction that can separate driveregion segments515 fromsense region517, and breaks in the y-direction that can separate onedrive region segment515 from another drive region segment. M1 layer501 can include gate lines518. M1 layer501 can includetunnel lines519 that can electrically connect together driveregion segments515 through connections, such asconductive vias521, which can electrically connecttunnel line519 to the grouped common electrodes in drive region segment display pixels.Tunnel line519 can run through the display pixels insense region517 with no connections to the grouped common electrodes in the sense region, e.g., novias521 in the sense region.M2 layer503 can include data lines523. Only onedata line523 is shown for the sake of clarity; however, a touch screen can include multiple data lines running through each vertical row of pixels, for example, one data line for each red, green, blue (RGB) color sub-pixel in each pixel in a vertical row of an RGB display integrated touch screen.
• Structures such asconnection elements511,tunnel lines519, andconductive vias521 can operate as a touch sensing circuitry of a touch sensing system to detect touch during a touch sensing phase of the touch screen. Structures such asdata lines523, along with other pixel stackup elements such as transistors, pixel electrodes, common voltage lines, data lines, etc. (not shown), can operate as display circuitry of a display system to display an image on the touch screen during a display phase. Structures such ascommon electrodes509 can operate as multifunction circuit elements that can operate as part of both the touch sensing system and the display system.
• For example, in operation during a touch sensing phase, stimulation signals can be transmitted through a row ofdrive region segments515 connected bytunnel lines519 andconductive vias521 to form electric fields between the stimulated drive region segments andsense region517 to create touch pixels, such astouch pixel226 inFIG. 2. In this way, the row of connected together driveregion segments515 can operate as a drive line, such asdrive line222, andsense region517 can operate as a sense line, such assense line223. When an object such as a finger approaches or touches a touch pixel, the object can affect the electric fields extending between thedrive region segments515 and thesense region517, thereby reducing the amount of charge capacitively coupled to the sense region. This reduction in charge can be sensed by a sense channel of a touch sensing controller connected to the touch screen, such astouch controller206 shown inFIG. 2, and stored in a memory along with similar information of other touch pixels to create an “image” of touch.
• A touch sensing operation according to embodiments of the disclosure will be described with reference toFIG. 6.FIG. 6 shows partial circuit diagrams of some of the touch sensing circuitry within display pixels in adrive region segment601 and asense region603 of an example touch screen according to embodiments of the disclosure. For the sake of clarity, only one drive region segment is shown. Also for the sake of clarity,FIG. 6 includes circuit elements illustrated with dashed lines to signify some circuit elements operate primarily as part of the display circuitry and not the touch sensing circuitry. In addition, a touch sensing operation is described primarily in terms of a single display pixel601aofdrive region segment601 and asingle display pixel603aofsense region603. However, it is understood that other display pixels indrive region segment601 can include the same touch sensing circuitry as described below for display pixel601a, and the other display pixels insense region603 can include the same touch sensing circuitry as described below fordisplay pixel603a. Thus, the description of the operation of display pixel601aanddisplay pixel603acan be considered as a description of the operation ofdrive region segment601 andsense region603, respectively.
• Referring toFIG. 6, driveregion segment601 includes a plurality of display pixels including display pixel601a. Display pixel601acan include aTFT607, agate line611, adata line613, apixel electrode615, and acommon electrode617.FIG. 6 showscommon electrode617 connected to the common electrodes in other display pixels indrive region segment601 through aconnection element619 within the display pixels ofdrive region segment601 that is used for touch sensing as described in more detail below.Sense region603 includes a plurality of display pixels includingdisplay pixel603a.Display pixel603aincludes aTFT609, agate line612, adata line614, apixel electrode616, and acommon electrode618.FIG. 6 showscommon electrode618 connected to the common electrodes in other display pixels insense region603 through aconnection element620 that can be connected, for example, in a border region of the touch screen to form an element within the display pixels ofsense region603 that is used for touch sensing as described in more detail below.
• During a touch sensing phase, drive signals can be applied tocommon electrodes617 through atunnel line621 that is electrically connected to a portion ofconnection element619 within adisplay pixel601bofdrive region segment601. The drive signals, which are transmitted to allcommon electrodes617 of the display pixels indrive region segment601 throughconnection element619, can generate anelectrical field623 between the common electrodes of the drive region segment andcommon electrodes618 ofsense region603, which can be connected to a sense amplifier, such as a charge amplifier626. Electrical charge can be injected into the structure of connected common electrodes ofsense region603, and charge amplifier626 converts the injected charge into a voltage that can be measured. The amount of charge injected, and consequently the measured voltage, can depend on the proximity of a touch object, such as afinger627, to the drive and sense regions. In this way, the measured voltage can provide an indication of touch on or near the touch screen.
• FIG. 7 illustrates an example partial circuit diagram of onedisplay pixel700 according to various embodiments. Some of the circuit elements ofdisplay pixel700 can include a transistor (TFT)701, agate line703, adata line705, apixel electrode707, and aVcom709.Vcom709 can be electrically connected to anamplifier711 through aresistance713. Whengate line703 is opened, for example, during a scan of the touch screen display, a high voltage of the gate signal can be applied toTFT701, turning the gate of the TFT to the on state. A data signal ondata line705 can apply a voltage topixel electrode707, which can correspond to an amount of luminance required of the pixel to display the current frame of an image. The voltage applied by the data signal can be applied across a pixel electrode-to-Vcom capacitance715 to create an electric field through liquid crystal (not shown). The electric field can cause the liquid crystal of the pixel to allow a controlled amount of backlight to pass through, thereby generating the desired amount of luminance for the pixel. However, when the gate signal transitions from the high voltage to the low voltage, a kickback voltage can result acrosselectrode715. The kickback voltage can affect the luminance of the pixel, for example, by causing a decrease in the luminance from the desired luminance of the pixel. In some designs, aparasitic capacitance717 can exist betweengate line703 andVcom709. For example,parasitic capacitance717 can depend on the orientation and the amount of overlap betweengate line703 andVcom709 within the stack up of the display pixel. In some designs, the amount of kickback voltage, and therefore the effect on luminance, of each display pixel may be the same or similar. However, in some embodiments the kickback voltage may vary depending on the position of the display pixel in the touch screen layout.
• FIG. 8 illustrates another view ofexample touch screen550 according to various embodiments. InFIG. 5 thecommon electrodes509 ofsense region517 can be connected together withconnection element511. Therefore, the Vcoms in eachsense region517 form an electrically connected together structure that is represented inFIG. 8 as verticalVcom line801 and verticalVcom line803. VerticalVcom lines801 and803 can be electrically separated from each other.Vcoms509 ofdrive region segments515 can be connected together withconnection elements511. In addition, the connected together Vcoms in each drive region segment can be further connected together throughtunnel lines519 to form an electrically connected together structure represented inFIG. 8 ashorizontal Vcom line805. While verticalVcom lines801 and1003 can be electrically separated from each other, the segments that make uphorizontal Vcom line1005 can be electrically connected together via tunnel lines519.
• Referring again toFIG. 7,parasitic capacitance717 can depend on, for example, an amount of overlap ofgate line703 withVcom709. In the example in embodiment illustrated inFIG. 8, it can be seen that the amount of overlap between agate line518 andhorizontal Vcom line805 can be much greater than an amount of overlap between the gate line and verticalVcom line801, for example. In other words, the parasitic capacitance between a gate line and the Vcom in a pixel indrive region segment515 can be much greater than the parasitic capacitance in a display pixel in asense region517 oftouch screen550. The difference in the parasitic capacitances of display pixels in the drive regions and in the sense regions can cause a difference in the effective kickback voltages in each of the regions. The difference in kickback voltages can result in, for example, a difference in the luminance of pixels in the drive regions and of pixels in the sense regions oftouch screen550.
• FIG. 9 illustrates an example partial circuit diagram of two display pixels in anexample touch screen900 according to various embodiments. The two display pixels can be, for example, two display pixels in adjacent rows ofdrive region segment515, two display pixels in adjacent rows ofsense region517, etc. Adisplay pixel901acan include aTFT903a, agate line905a, adata line907, a pixel electrode909a, aVcom911a, a pixel electrode-to-Vcom capacitance913a, a parasitic capacitance915a, a resistance917a, and anamplifier919a. Likewise,display pixel901bcan include aTFT903b, agate line905b, adata line907, apixel electrode909b, aVcom911b, a pixel electrode-to-Vcom capacitance913b, aparasitic capacitance915b, aresistance917b, and anamplifier919b. For example,touch screen900 can correspond totouch screen550 ofFIG. 5, and the various elements inFIG. 9, such as gate lines, data lines, pixel electrodes, etc., can correspond to the same elements intouch screen550. Likewise, aconnection element921 ofFIG. 9 can correspond toconnection element511 ofFIG. 5.Connection element921 can electrically connect togetherVcom911aandVcom911boftouch screen900, such thatVcoms911aand911bcan form a single conductive circuit element. In other words,display pixel901aanddisplay pixel901bcan be display pixels in adjacent rows of display pixels of an integrated touch screen that includes connected together Vcoms of display pixels to form drive region segments and sense regions such as those shown inFIG. 5.
• FIG. 10 illustrates an example configuration of gate drivers according to various embodiments in which a double-sided gate driver configuration can be used.FIG. 10 shows atouch screen1000 including two sets of gate drivers,gate drivers1001 and1003, on either side of the active area oftouch screen1000.Gate drivers1001 can receive gate clock signals GCK1 and GCK2 fromgate clock lines1005, andgate drivers1003 can receive gate clock signals GCK3 and GCK4 from gate clock lines1007.Gate drivers1001 can apply GCK1 to afirst gate line1009 and can apply GCK2 to athird gate line1013.Gate drivers1003 can apply GCK3 to asecond gate line1011 and can apply GCK4 to afourth gate line1015.
• Example systems and operations of separate controlling of slew rate and shunting capability in scanning systems will now be described in reference toFIGS. 11-15.
• FIG. 11 illustrates an example configuration ofgate drivers1001 according to various embodiments.Gate drivers1001 can include a firstgate line driver1101 and a thirdgate line driver1103, as well as additional gate line drivers for the other gate lines (not shown) driven from the left side of the touch screen. Each ofgate line drivers1101 and1103 can include alatch1105, aNAND gate1107, aPFET1109, asmall NFET1111, and alarge NFET1113. During operation,PFET1109 can connect a high gate voltage (VGH)line1119 to the gate line, such that the PFET can control a rising time of the gate line signal.Small NFET1111 andlarge NFET1113 can each connect the gate line to a low gate voltage (VGL)line1117. Therefore, each ofsmall NFET1111 andlarge NFET1113 can provide a separate shunting resistance between the gate line andVGL line1117.Small NFET1111 can be designed to provide a shunting resistance greater than a predetermined amount that results in a sufficiently long falling time of the gate line signal. In some embodiments, for example,small NFET1111 can be 10 micrometers in size.Large NFET1113 can be designed to provide a shunting resistance less than a predetermined amount that results in a sufficiently low shunting resistance between the gate line andVGL line1117. In some embodiments, for example,large NFET1113 can be 50 micrometers in size. A startingvoltage line1115 can carry a starting voltage STV1 that can provide an initial input forlatch1105 of firstgate line driver1101, as described in more detail below. It should be understood that the memory elements, gates, transistor switches, and switches configured to provide shunting resistances shown inFIG. 11 are only examples, and that other circuit elements and configurations capable of performing similar functions can also be employed.
• FIG. 12 illustrates an example set of gate clock signals including first, second, third and fourth gate clock signals, GCK1, GCK2, GCK3, GCK4, respectively. As shown inFIG. 10, gate signals based on gate clock signals GCK1 and GCK2 can be applied bygate drivers1001 tofirst gate line1009 andthird gate line1013 from the left side of thetouch screen1000, and gate signals based on GCK3 and GCK4 can be applied bygate drivers1003 tosecond gate line1011 andfourth gate line1015 from the right side of the touch screen. As the gate lines are scanned sequentially from top to bottom, the order of the gate clock signals can be, for example, GCK1 fromgate driver1001, GCK3 fromgate driver1003, GCK2 fromgate driver1001, GCK4 fromgate driver1003, etc. This pattern can repeat for the remainder of the gate lines in the touch screen.
• Table 1 illustrates an example state table ofNAND gates1107, as well as corresponding transistor states and gate line operations of firstgate line driver1101 and thirdgate line driver1103 according to various embodiments.

• 	TABLE 1
  	Transistor State

  NAND Gate Logic

  Small

  Large

  Gate Line Driver

  Q	DriveClk	Y	PFET	NFET	NFET	Operation
  1	1	0	ON	OFF	OFF	Rising
  1	0	1	OFF	ON	OFF	High R Falling/
  						High R Shunting
  0	1	1	OFF	ON	ON	Low R Shunting
  0	0	1	OFF	ON	ON	Low R Shunting

• Referring to Table 1 together withFIGS. 11-14, an example method of scanning the gate lines withgate drivers1001 will now be described. One skilled in the art would understand that a corresponding method can be used to scan the gate lines driven bygate drivers1003.
• Table 1 illustrates example gate line driver operations that can be performed when the transistors, PFET, small NFET, and large NFET are placed into particular combinations of states through the operation of the NAND gate logic.FIG. 13 illustrates an example timing of gate line driver operations according to the timing of various signals applied tolatches1105 andNAND gates1107 according to various embodiments.
• FIG. 13 shows example signals STV1, GCK2, GCK1, a first gate line signal (Gate1), and a third gate line signal (Gate3).FIG. 13 also showslatch1105 values D (previous gate line), CLK (LatchClk), Q, and Qbar, and corresponding DriveClk values, corresponding to the values of the signals for the firstgate line driver1101 and the thirdgate line driver1103 during multiple time periods, T1-T11.
• Referring to Table 1 andFIG. 13, the example operation of firstgate line driver1101 will now be described. In time periods T1-T2, firstgate line driver1101 can perform a high resistance (R) shunting operation in which a high level signal of STV1 is latched to set the value of Q to equal 1, and DriveClk (which is GCK1 for the first gate line driver) remains at a low level signal. In other words, during the high R shunting operation, the first gate line signal can be low,small NFET1111 be on and can connectfirst gate line1009 toVGL line1117, andPFET1109 andlarge NFET1113 can be in the off state. In T3, GCK1 can go to a high level, which switches on thePFET1109 of firstgate line driver1101 and connectsVGH line1119 to thefirst gate line1009. Thus,PFET1109 can control the rising time of the first gate line signal in T3. In T4, GCK1 can go to a low level, which switch offPFET1109 and switches onsmall NFET1111, resulting in a high R falling operation. In other words, during the high R fallingoperation PFET1109 andlarge NFET1113 can be off, andsmall NFET1111 can connect first gate line1009 (which is at a high level) toVGL line1117, thus providing a high resistance shunt to allow a sufficiently long falling time.
• In T5, GCK2 can go to high level while STV1 can be at a low level. Thus, GCK2 can latch the low level of STV1, which can set the value of Q to zero and turn on large NFET1113 (which is controlled by Qbar). Therefore, for the remaining time periods, T5-T11 (and subsequent time periods remaining in the current scan of the display, which are not shown), bothsmall NFET1111 andlarge NFET1113 can connect, in parallel,first gate line1009 toVGL1117.Large NFET1113 can provide a low resistance and, in parallel with the resistance ofsmall NFET1111, can provide a low resistance shunting operation to shunt the first gate line to the VGL line.
• The example operation of thirdgate line driver1103 will now be described. In time periods T1-T2, the value of Q can be zero, and Qbar can have a value of 1. Therefore,third gate driver1103 can perform a low R shunting operation during T1-T2. In T3-T4, thirdgate line driver1103 can perform a high R shunting operation in which a high level signal of the first gate line signal during T3 is latched to set the value of Q to equal 1, and DriveClk (which is GCK2 for the third gate line driver) remains at a low level signal. In T5, GCK2 can go to a high level, which switches on thePFET1109 of thirdgate line driver1103 and connectsVGH line1119 to thethird gate line1013. Thus,PFET1109 can control the rising time of the third gate line signal in T5. In T6, GCK2 can go to a low level, which can switch offPFET1109 and can switch onsmall NFET1111, resulting in a high R falling operation. In T7, GCK1 can go to high level while the first gate line signal can be at a low level. Thus, GCK1 can latch the low level of the first gate line signal, which can set the value of Q to zero and turn onlarge NFET1113. Therefore, for the remaining time periods, T7-T11 (and subsequent time periods remaining in the current scan of the display, which are not shown), bothsmall NFET1111 andlarge NFET1113 can connect, in parallel,third gate line1013 toVGL1117.Large NFET1113 can provide a low resistance and, in parallel with the resistance ofsmall NFET1111, can provide a low resistance shunting operation to shunt the third gate line to the VGL line.
• The structures and operations of gate drivers1003 (on the right side oftouch screen1000 as shown inFIG. 10) can be similar to those described for firstgate line driver1101 and thirdgate line driver1103, as one skilled in the art would understand.FIG. 14 illustrates an example set of start signals (STV1 and STV2), gate clock signals (GCK1, GCK2, GCK3, and GCK4), and corresponding gate line signals (Gate1-Gate6) for the first six gate lines of an example touch screen such astouch screen1000. In this example embodiment, scanning the gate lines from two sides of the touch screen can conveniently allow the low R shunting operation of a gate line driver to begin a period of time after the high R falling operation begins. In the example shown inFIG. 13, for example, the low R shunting operation can begin one time period after the high R falling operation begins. This can conveniently provide a time period during which a slow falling time can occur. In this way, for example, the control of the shunting operation can begin after the gate line signal has reached a steady state.
• FIG. 15 illustrates a portion of anexample Vcom driver1500 according to various embodiments. The portion ofVcom driver1500 includesNAND gates1501, ANDgates1502, latches1503,small NFETs1505,large NFETs1507, high level Vcom voltage lines (VcomH)1509, low level Vcom voltage lines (VcomL)1511, afirst Vcom line1513, and a second Vcom line1515.Vcom driver1500 can includepolarity signal lines1521, N-1lines1523, and N-2lines1525.
• Vcom driver1500 also includessmall PFETs1517 andlarge PFETs1519.Small PFETs1517,large PFETs1519,small NFETs1509, andlarge NFETs1507 can be controlled bylatches1503 and the NAND and AND gates as shown in the example timing diagram shown inFIG. 16. For example,FIG. 16 illustrates that a high value of Q can switch the small NFET on, and a low value of Q can switch the small PFETs on. A low value of Qbar can switch on large NFET, and a high value of Qbar can switch on large PFET. It should be understood that the memory elements, gates, transistor switches, and switches configured to provide shunting resistances shown inFIG. 15 are only examples, and that other circuit elements and configurations capable of performing similar functions can also be employed.
• As one skilled in the art would understand, other types of transistors and/or other configurations can be used to provide separate slew rate and shunting operations. For example, some embodiments can provide separate control of rising times and shunting capability. In some embodiments, a slew rate can be controlled by a low resistance transistor, such that the slew rate is high, and the shunting operation can be controlled by switching on a high resistance transistor and switching off the low R transistor to provide a high shunting capability.
• Although embodiments of this disclosure have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications including, but not limited to, combining features of different embodiments, omitting a feature or features, etc., as will be apparent to those skilled in the art in light of the present description and figures.
• For example, one or more of the functions ofcomputing system200 described above can be performed by firmware stored in memory (e.g. one of theperipherals204 inFIG. 2) and executed bytouch processor202, or stored inprogram storage232 and executed byhost processor228. The firmware can also be stored and/or transported within any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” can be any medium that can contain or store the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, a portable computer diskette (magnetic), a random access memory (RAM) (magnetic), a read-only memory (ROM) (magnetic), an erasable programmable read-only memory (EPROM) (magnetic), a portable optical disc such a CD, CD-R, CD-RW, DVD, DVD-R, or DVD-RW, or flash memory such as compact flash cards, secured digital cards, USB memory devices, memory sticks, and the like.
• The firmware can also be propagated within any transport medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “transport medium” can be any medium that can communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The transport readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic or infrared wired or wireless propagation medium.
• Example embodiments may be described herein with reference to a Cartesian coordinate system in which the x-direction and the y-direction can be equated to the horizontal direction and the vertical direction, respectively. However, one skilled in the art will understand that reference to a particular coordinate system is simply for the purpose of clarity, and does not limit the direction of the elements to a particular direction or a particular coordinate system. Furthermore, although specific materials and types of materials may be included in the descriptions of example embodiments, one skilled in the art will understand that other materials that achieve the same function can be used. For example, it should be understood that a “metal layer” as described in the examples below can be a layer of any electrically conductive material.
• In some embodiments, the drive lines and/or sense lines can be formed of other elements including, for example other elements already existing in typical LCD displays (e.g., other electrodes, conductive and/or semiconductive layers, metal lines that would also function as circuit elements in a typical LCD display, for example, carry signals, store voltages, etc.), other elements formed in an LCD stackup that are not typical LCD stackup elements (e.g., other metal lines, plates, whose function would be substantially for the touch sensing system of the touch screen), and elements formed outside of the LCD stackup (e.g., such as external substantially transparent conductive plates, wires, and other elements). For example, part of the touch sensing system can include elements similar to known touch panel overlays.
• In this example embodiment, each sub-pixels can be a red (R), green (G) or blue (B) sub-pixel, with the combination of all three R, G and B sub-pixels forming one color display pixel. Although this example embodiment includes red, green, and blue sub-pixels, a sub-pixel may be based on other colors of light or other wavelengths of electromagnetic radiation (e.g., infrared) or may be based on a monochromatic configuration.
• A scanning system is disclosed. In some examples, the scanning system can comprise: a first gate line driver including: a first scan line, a first voltage line and a second voltage line, a first p-type transistor coupled to the first voltage line and the first scan line, the p-type transistor configured to control a rise time of the first scan line, a first n-type transistor coupled to the second voltage line and the first scan line, the first n-type transistor configured to control a fall time of the first scan line by providing a first shunting resistance greater than a predetermined amount, and a second n-type transistor coupled to the second voltage line and the first scan line, the second n-type transistor configured to provide a second shunting resistance less than the predetermined amount, wherein the first and second n-type transistors are both configured to be on when the second n-type transistor provides the second shunting resistance.
• Additionally or alternatively, in some examples, a gate of the p-type transistor is directly coupled to the gate of the first n-type transistor. Additionally or alternatively, in some examples, each scan line includes a first time period, a second time period, and a third time period, the first time period configured for activating the p-type transistor, the second time period configured for activating the first n-type transistor, and the third time period configured for activating both the first n-type transistor and the second n-type transistor. Additionally or alternatively, in some examples, the third time period begins one clock period after the second time period begins. Additionally or alternatively, in some examples, the first n-type transistor is configured with a size of 10 um. Additionally or alternatively, in some examples, the second n-type transistor is configured with a size of 50 um. Additionally or alternatively, in some examples, the ratio of a size of the second n-type transistor to a size of the first n-type transistor is 5. Additionally or alternatively, in some examples, the scanning system is included in a touch screen, the touch screen comprising: a plurality of sense regions including a plurality of first common electrodes; a plurality of drive regions including a plurality of second common electrodes, wherein a parasitic capacitance between the plurality of second common electrodes and the scan line is different than a parasitic capacitance between the plurality of first common electrodes and the scan line. Additionally or alternatively, in some examples, an overlap between the plurality of first common electrodes and a plurality of scan lines is less than an overlap between the plurality of second common electrodes and the plurality of scan lines, and wherein the plurality of scan lines includes the scan line. Additionally or alternatively, in some examples, the scanning system further comprises: a second gate line driver including: a second scan line, a second p-type transistor coupled to the first voltage line and the first scan line, the p-type transistor configured to control a rise time of the second scan line, a third n-type transistor coupled to the second voltage line and the second scan line, the third n-type transistor configured to control a fall time of the second scan line by providing the first shunting resistance, and a fourth n-type transistor coupled to the second voltage line and the second scan line, the fourth n-type transistor configured to provide the second shunting resistance. Additionally or alternatively, in some examples, the first gate line driver further comprises a first latch configured to receive a third scan line and a first clock signal, one or more outputs of the first latch coupled to one or more gates of the p-type transistor, first n-type transistor, and second n-type transistor. Additionally or alternatively, in some examples, the second gate line driver further comprises a second latch configured to receive the first scan line and a second clock signal, and wherein one or more outputs of the second latch are coupled to one or more gates of the p-type transistor, first n-type transistor, and second n-type transistor.
• A method of scanning a plurality of scan lines included a scanning system is disclosed. In some examples, the method comprises: receiving a first voltage line; connecting a scan line to a first voltage line through a first n-type transistor, in response to the first voltage line; receiving a previous scan line and a first clock signal; connecting the scan line to a second voltage line through a p-type transistor in response to the previous scan line and a rise of the first clock signal, the p-type transistor configured to control a rise time of the scan line; connecting the scan line to the first voltage line through a first n-type transistor in response to the previous scan line and a fall of the first clock signal, the first n-type transistor configured to control a fall time of the scan line; and connecting the scan line to the first voltage line through both the first n-type transistor and a second n-type transistor. Additionally or alternatively, in some examples, the method further comprises: receiving a second clock signal; connecting the scan line to the first voltage line through a second n-type transistor in response to a rise of the second clock signal, the second n-type transistor configured to provide a shunting resistance less than a predetermined amount. Additionally or alternatively, in some examples, the scan line is coupled to the first voltage line through the first n-type transistor at a same time as the scan line is coupled to the first voltage line through the second n-type transistor. Additionally or alternatively, in some examples, the method further comprising disconnecting the scan line from the first voltage line when the scan line is connected to the second voltage line. A system for driving one or more common electrode lines is disclosed. In some examples, the system comprises: a first p-type transistor and a second p-type transistor, wherein a size of the second p-type transistor is larger than a size of the first p-type transistor; and a first n-type transistor and a second n-type transistor, wherein a size of the second n-type transistor is larger than a size of the first n-type transistor. Additionally or alternatively, in some examples, the first p-type transistor and second p-type transistor are configured for coupling a first common electrode line to a first voltage source. Additionally or alternatively, in some examples, the first p-type transistor couples the first common electrode line to the first voltage source for a time period shorter than the second p-type transistor couples the first common electrode line to the first voltage source. Additionally or alternatively, in some examples, the first n-type transistor and the second n-type transistor are configured for coupling a second common electrode line to a second voltage source.
• Although the disclosed examples have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the disclosed examples as defined by the appended claims.

Claims (20)

What is claimed is:

1. A scanning system comprising:

a first gate line driver including:

a first scan line,

a first voltage line and a second voltage line,

a first p-type transistor coupled to the first voltage line and the first scan line, the p-type transistor configured to control a rise time of the first scan line,

a first n-type transistor coupled to the second voltage line and the first scan line, the first n-type transistor configured to control a fall time of the first scan line by providing a first shunting resistance greater than a predetermined amount, and

a second n-type transistor coupled to the second voltage line and the first scan line, the second n-type transistor configured to provide a second shunting resistance less than the predetermined amount, wherein the first and second n-type transistors are both configured to be on when the second n-type transistor provides the second shunting resistance.

2. The scanning system ofclaim 1, wherein a gate of the p-type transistor is directly coupled to the gate of the first n-type transistor.

3. The scanning system ofclaim 1, wherein each scan line includes a first time period, a second time period, and a third time period,

the first time period configured for activating the p-type transistor,

the second time period configured for activating the first n-type transistor, and

the third time period configured for activating both the first n-type transistor and the second n-type transistor.

4. The scanning system ofclaim 3, wherein the third time period begins one clock period after the second time period begins.

5. The scanning system ofclaim 1, wherein the first n-type transistor is configured with a size of 10 um.

6. The scanning system ofclaim 1, wherein the second n-type transistor is configured with a size of 50 um.

7. The scanning system ofclaim 1, wherein the ratio of a size of the second n-type transistor to a size of the first n-type transistor is 5.

8. The scanning system ofclaim 1, wherein the scanning system is included in a touch screen, the touch screen comprising:

a plurality of sense regions including a plurality of first common electrodes;

a plurality of drive regions including a plurality of second common electrodes, wherein a parasitic capacitance between the plurality of second common electrodes and the scan line is different than a parasitic capacitance between the plurality of first common electrodes and the scan line.

9. The scanning system ofclaim 8, wherein an overlap between the plurality of first common electrodes and a plurality of scan lines is less than an overlap between the plurality of second common electrodes and the plurality of scan lines, and wherein the plurality of scan lines includes the scan line.

10. The scanning system ofclaim 1, further comprising:

a second gate line driver including:

a second scan line,

a second p-type transistor coupled to the first voltage line and the first scan line, the p-type transistor configured to control a rise time of the second scan line,

a third n-type transistor coupled to the second voltage line and the second scan line, the third n-type transistor configured to control a fall time of the second scan line by providing the first shunting resistance, and

a fourth n-type transistor coupled to the second voltage line and the second scan line, the fourth n-type transistor configured to provide the second shunting resistance.

11. The scanning system ofclaim 10, wherein the first gate line driver further comprises a first latch configured to receive a third scan line and a first clock signal, one or more outputs of the first latch coupled to one or more gates of the p-type transistor, first n-type transistor, and second n-type transistor.

12. The scanning system ofclaim 11, wherein the second gate line driver further comprises a second latch configured to receive the first scan line and a second clock signal, and wherein one or more outputs of the second latch are coupled to one or more gates of the p-type transistor, first n-type transistor, and second n-type transistor.

13. A method of scanning a plurality of scan lines included a scanning system, the method comprising:

receiving a first voltage line;

connecting a scan line to a first voltage line through a first n-type transistor, in response to the first voltage line;

receiving a previous scan line and a first clock signal;

connecting the scan line to a second voltage line through a p-type transistor in response to the previous scan line and a rise of the first clock signal, the p-type transistor configured to control a rise time of the scan line;

connecting the scan line to the first voltage line through a first n-type transistor in response to the previous scan line and a fall of the first clock signal, the first n-type transistor configured to control a fall time of the scan line; and

connecting the scan line to the first voltage line through both the first n-type transistor and a second n-type transistor.

14. The method ofclaim 13, further comprising:

receiving a second clock signal;

connecting the scan line to the first voltage line through a second n-type transistor in response to a rise of the second clock signal, the second n-type transistor configured to provide a shunting resistance less than a predetermined amount.

15. The method ofclaim 14, wherein the scan line is coupled to the first voltage line through the first n-type transistor at a same time as the scan line is coupled to the first voltage line through the second n-type transistor.

16. The method ofclaim 13, further comprising disconnecting the scan line from the first voltage line when the scan line is connected to the second voltage line.

17. A system for driving one or more common electrode lines, the system comprising:

a first p-type transistor and a second p-type transistor, wherein a size of the second p-type transistor is larger than a size of the first p-type transistor; and

a first n-type transistor and a second n-type transistor, wherein a size of the second n-type transistor is larger than a size of the first n-type transistor.

18. The system ofclaim 17, wherein the first p-type transistor and second p-type transistor are configured for coupling a first common electrode line to a first voltage source.

19. The system ofclaim 18, wherein the first p-type transistor couples the first common electrode line to the first voltage source for a time period shorter than the second p-type transistor couples the first common electrode line to the first voltage source.

20. The system ofclaim 17, wherein the first n-type transistor and the second n-type transistor are configured for coupling a second common electrode line to a second voltage source.

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