US20150214331A1 - Replacement metal gate including dielectric gate material - Google Patents

Abstract

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Description

BACKGROUND
• The present invention relates to semiconductor device fabrication, and in particular, to a replacement metal gate process.
• A replacement metal gate (RMG) process, i.e., a gate last process, has been traditionally used in semiconductor fabrications processes to form a semiconductor device including one ormore gate elements102 that wrap around on one ormore semiconductor fins104. Thegate elements102 typically extend in a direction perpendicular to the direction of thesemiconductor fins104 as illustrated inFIG. 1. The RMG process utilizes a dummy gate element formed from amorphous silicon (a-Si) or polysilicon (PC), which is ultimately replaced with a metal gate element as understood by those ordinarily skilled in the art. However, the silicon material of the dummy gate element may be exposed when recessing the spacers formed on the sidewalls of the dummy gate element. Consequently, epitaxial material may be inadvertently grown on the exposed silicon of the dummy gate element which may result in a short between the epitaxially grown source/drain regions and the epitaxial material grown on the gate element.
SUMMARY
• According to at least one embodiment a method of fabricating a semiconductor device comprises forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer that is formed on one or more of the semiconductor fins. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.
• According to another exemplary embodiment, a method of fabricating a semiconductor device comprises forming at least one semiconductor fin on a semiconductor substrate. The at least one semiconductor fin includes an etch stop layer formed on an upper surface thereof. The method further comprises forming a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from a dielectric material and has a hardmask gate cap formed on an upper surface thereof. The method further comprises depositing a high-dielectric layer that conforms to an outer surface of each dummy gate element. A spacer layer is deposited on the high-dielectric layer. The method further comprises performing a first etching process that etches the spacer layer to form a spacer on each sidewall of dummy gate elements and exposes an upper portion of the high-dielectric layer. The method further comprises performing a second etching process that is different from the first etching process that selectively etches the upper portion of the high-dielectric layer to expose each hardmask gate cap. The method further comprises removing the hardmask gate caps and the dummy gate elements to form a trench between a respective pair of spacers. The method further comprises performing a third etching process after removing the dummy gates elements to remove a portion of the high-dielectric material from the sidewalls of the spacers such that a remaining portion of the high-dielectric material is interposed between the spacers and the etch stop layer.
• Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the features, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
• The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing features are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
• FIG. 1 is an isometric view of a conventional array of semiconductor fins having gate elements formed thereon;
• FIG. 2A is block diagram of a starting substrate including a plurality of gate formation layers formed on a semiconductor fin according to a first orientation extending along a Y-axis to define a length;
• FIG. 2B illustrates the starting substrate ofFIG. 2A according to a second orientation showing the gate formation layers formed on a plurality of semiconductor fins and extending along an X-axis to define a width;
• FIG. 3A illustrates the substrate ofFIGS. 2A-2B according to the first orientation following patterning of a photoresist layer;
• FIG. 3B illustrates the substrate ofFIG. 3A according to the second orientation;
• FIG. 4A illustrates the substrate ofFIGS. 3A-3B according to the first orientation following etching of an optical planar layer and hardmask layer to form individual hardmask gate caps;
• FIG. 4B illustrates the substrate ofFIG. 4A according to the second orientation;
• FIG. 5A illustrates the substrate ofFIGS. 4A-4B according to the first orientation after etching dummy gate layer according to the patterned hardmask layer to form individual dummy gate elements;
• FIG. 5B illustrates the substrate ofFIG. 5A according to the second orientation;
• FIG. 6 illustrates the substrate ofFIG. 5A following deposition of a conformal spacer layer on sidewalls of the dummy gates elements, gate caps, and on exposed surfaces of the etch stop layer located between each dummy gate element;
• FIG. 7 illustrates the substrate ofFIG. 6 following an etching process that partially etches the spacer layer formed on the dummy gate element and that removes the spacer layer formed on the etch stop layer;
• FIG. 8 illustrates the substrate ofFIG. 7 following a pre-clean process that removes a portion of the etch stop layer located between each dummy gate element to expose a portion of the underlying semiconductor fin;
• FIG. 9 illustrates the substrate ofFIG. 8 following an epitaxial growth process that grows an epitaxial material on the exposed portion of the semiconductor fin located between the dummy gate elements;
• FIG. 10 illustrates the substrate ofFIG. 9 following deposition of a block dielectric layer that fills the region between the dummy gate elements and that covers the gate caps;
• FIG. 11 illustrates the substrate ofFIG. 10 following a planarization process that recesses the block dielectric layer and a portion of the spacer layer to expose the dummy gate elements;
• FIG. 12 illustrates the substrate ofFIG. 11 following removal of the dummy gate elements to form respective gate trenches;
• FIG. 13 illustrates the substrate ofFIG. 12 following a high-dielectric layer deposition and work function metal filling process that fills the trenches with a gate metal to form respective metal gate elements;
• FIG. 14 illustrates another exemplary embodiment of the present disclosure where a conformal high-dielectric layer is deposited on sidewalls of the dummy gates elements, gate caps, and on exposed surfaces of the etch stop layer located between each dummy gate element, and a conformal spacer layer is formed on an upper surface of the high-dielectric layer;
• FIG. 15 illustrates the substrate ofFIG. 14 following an etching process that partially removes the spacer layer formed on the etch stop layer and that etches the spacer layer formed on the dummy gate element to expose an upper portion of the high-dielectric layer;
• FIG. 16 illustrates the substrate ofFIG. 15 following an etching process that removes an upper portion of the high-dielectric layer;
• FIG. 17 illustrates the substrate ofFIG. 16 following a planarization process that recesses a block dielectric layer and gate caps to expose the dummy gate elements;
• FIG. 18 illustrates the substrate ofFIG. 17 following removal of the dummy gate elements to form respective gate trenches and to expose the high-dielectric layer formed on sidewalls of the trenches;
• FIG. 19 illustrates the substrate ofFIG. 18 following an etching process that removes the high-dielectric layer formed on sidewalls of the trenches; and
• FIG. 20 illustrates the substrate ofFIG. 19 following a high-dielectric layer deposition and work function metal filling process that fills the trenches with a gate metal to form respective metal gate elements.
• FIG. 21 is a flow diagram illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure.
DETAILED DESCRIPTION
• With reference now toFIGS. 2A-2B, a startingsemiconductor substrate200 including a plurality of gate formation layers formed on one ormore semiconductor fins202 is illustrated according to an exemplary embodiment of the present disclosure. Thesubstrate200 extends along an X-axis to define a width and a Y-axis to define a length. Thesemiconductor fins202 may be formed on a buried oxide (BOX)layer204 formed on thesubstrate200. It is appreciated, however, that thesemiconductor fins202 may be formed on a bulk semiconductor layer of thesubstrate200. Anetch stop layer206 may be formed on an upper surface of thesemiconductor fins202. The BOX layer and the etch stop layer may be formed from a dielectric material including, but not limited to, silicon oxide (SiO₂). Although a finFET semiconductor device is described going forward, it is appreciated that the inventive teachings described herein may be applied to various other semiconductor topologies including, but not limited to, a planar semiconductor device, and a nanowire semiconductor device.
• The gate formation layers are formed on an upper surface of theetch stop layer206 formed on eachsemiconductor fin202. The plurality of gate formation layers include, for example, a dummygate dielectric layer208, agate hardmask layer210, an optical planar layer (OPL)212, an anti-reflective coating (ARC)layer214, and aphotoresist layer216. Although not illustrated, TheARC layer214 may be replaced with a silicon oxide layer.
• The dummygate dielectric layer208 may be formed directly on an upper surface of theetch stop layer206, for example. Unlike a conventional replacement metal gate (RMG) process, the dummygate dielectric layer208 is formed from a dielectric material instead of amorphous silicon (Si) or polysilicon (PC). The dummygate dielectric layer208 may be formed from various materials including, but not limited to, boron carbide (BC), a silicon boron carbide material that contains nitrogen (i.e., SiB:C(N)), carbon (C), compressed carbon, and SiO₂. Therefore, at least one exemplary embodiment of the present disclosure may prevent inadvertent epitaxially growth on exposed portions of the dummy gate element (described below). Accordingly, shorting between epitaxially grown source-drain regions and the dummy gate element may be prevented.
• Thegate hardmask layer210 is stacked on the dummygate dielectric layer208 and may be formed from various materials including, but not limited to, silicon nitride (SiN) and silicon dioxide (SiO₂). TheOPL212 is stacked on thegate hardmask layer210 to form a planarized upper surface. TheOPL212 may be formed from an organic dielectric layer (ODL) material including, but not limited to, amorphous carbon, CHM701B, commercially available from Cheil Chemical Co., Ltd., HM8006 and HM8014, commercially available from JSR Corporation, and ODL-102, commercially available from ShinEtsu Chemical, Co., Ltd.
• TheSiARC layer214 is stacked on theOPL212 and may comprise Si, for example, to form a silicon-containing ARC (SiARC) layer as described going forward. Thephotoresist layer216 may be deposited according to a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process as understood by those ordinarily skilled in the art.
• Referring toFIGS. 3A-3B, thephotoresist layer216 is patterned to form one or more individual gate resistelements218. The gate resistelements218 ultimately determine the pattern of respective dummy gate elements to be formed on thesubstrate200 as understood by those ordinarily skilled in the art. The stacked arrangement of thephotoresist layer216, theSiARC layer214 and theOPL212 may form a multilayer element (e.g., a trilateral element) such that a trilayer resist (TLR) patterning scheme may be performed that forms one or more dummy gate elements.
• According to at least embodiment, the TLR pattering scheme comprises, for example, patterning thephotoresist layer216 using lithography and trimming, performing first a reactive ion etching (RIE) plasma process to etch through theSiARC layer214 utilizing the patterned photoresist layer216 (i.e., the gate resist elements218) as a first pattern mask where a portion of thephotoresist layer216 is consumed during the during first etching, performing a second etching process to etch the ODL utilizing the patternedSiARC layer214 as a second pattern mask where thephotoresist layer216 is completely consumed during the second etching, performing a third etching process to remove (e.g., burn-off) theSiARC layer214, performing a fourth etching process to etch thegate hardmask layer210 utilizing the etched ODL as a third pattern mask where a portion of thegate hardmask layer210 is removed during the third etching such that individual hardmask gate caps220 are formed on the dummygate dielectric layer208, and stripping the etched ODL using an RIE or wet cleaning process to form one or more individual hardmask gate caps220 on the dummygate dielectric layer208 as illustrated inFIGS. 4A-4B. Accordingly, the pattern of thephotoresist layer216 may be transferred to thegate hardmask layer210 for ultimately forming the pattern of dummy gate elements as discussed in greater detail below
• Referring toFIGS. 5A-5B, the dummygate dielectric layer208 is patterned according to the patterned gate hardmask layer210 (i.e., the hardmask gate caps220) to form individualdummy gate elements222. The dummygate dielectric layer208 may be etched using a reactive ion etching (RIE) process as understood by those ordinarily skilled in the art. Accordingly, one or more individualdummy gate elements222 are formed that wrap around one ormore semiconductor fins202.
• Turning now toFIG. 6, aconformal spacer layer224 is deposited on sidewalls of thedummy gates elements222, hardmask gate caps220, and on exposed surfaces of theetch stop layer206 located between eachdummy gate element222. Theconformal spacer layer224 may be formed from, for example, silicon nitride (SiN).
• Referring toFIG. 7, thespacer layer224 formed on thedummy gate element222 is partially etched such thatspacers226 are formed on sidewalls of thedummy gate element222. Various etching processes may be used to etch thespacer layer224 including, but not limited to, RIE. A portion of thespacer layer224 formed on thehardmask gate cap220 may also be removed such that theunderlying gate cap220 is exposed as further illustrated inFIG. 7.
• Referring toFIG. 8, a pre-clean process is performed that removes a portion of theetch stop layer206 located between eachdummy gate element222. Accordingly, acavity228 is formed between eachdummy gate element222, which exposes a portion of theunderlying semiconductor fin202. The pre-clean process may be performed using a hydrogen fluoride (HF) based wet clean process, or a dry etching process that uses remote plasma that reacts with theetch stop layer206, while being selective to thespacers226.
• Turning now toFIG. 9, an epitaxial growth process is performed that grows anepitaxial semiconductor material230 on the exposed portion of thesemiconductor fin202 located between thedummy gate elements222. Well-known processes used to epitaxially grow anepitaxial semiconductor material230 including, but not limited to, silicon doped with germanium (Ge), carbon (C), and phosphorus (P), or any dopants desired to lower external resistance for forming a source/drain region. Theepitaxial semiconductor material230 may be grown from a portion of thesemiconductor fin202 exposed by arespective cavity228 and may extend therefrom to contact the sidewalls of a pair of opposingspacers226 to form one or more source/drain regions.
• Referring toFIG. 10, acontact dielectric layer232 is deposited on the hardmask gate caps220 and in the voids between thedummy gate elements222. Thecontact dielectric layer232 may also contact one or more source/drain regions of one ormore semiconductor fins202. Various methods may be used to deposit thecontact dielectric layer232 including, but not limited to, chemical vapor deposition (CVD) and atomic layer deposition (ALD). Thecontact dielectric layer232 may be formed from various materials including, but not limited to, SiO₂.
• Referring now toFIG. 11, a planarization process is performed, which partially recesses thecontact dielectric layer232 and a portion of thespacer layer224 to expose thedummy gate elements222. The planarization process may stop on the upper surface of thedummy gate elements222 such that the upper surface of thecontact dielectric layer232 is flush with the upper surfaces of thedummy gate elements222.
• Turning toFIG. 12, thedummy gate elements222 are removed according to a replacement metal gate (RMG) process as understood by those ordinarily skilled in the art. For example, thedummy gate elements222 may be removed using an RIE process or a wet etching process. Accordingly,gate trenches234 that expose the underlyingetch stop layer206 of thesemiconductor fin202 are formed between a respective pair ofspacers226. According to at least one embodiment, an anneal process may be performed after removing thedummy gate elements222 to activate the dopants of the source/drain regions. The anneal process may generate a temperature of approximately 900 degrees Celsius (C) or higher, for example.
• Referring toFIG. 13, a metal filling process is performed that fills the trenches with a gate metal to form respectivemetal gate elements236. The gate metal may include various metal materials including, but not limited to, tungsten (W), tantalum (Ta), titanium (Ti), Niobium (Nb), rhenium (Rh), aluminum (Al), tungsten nitride (WN), titanium nitride (TiN) and tantalum nitride (TaN). According to this exemplary embodiment, each metal may contact a respective pair ofspacers226 and a respectiveetch stop layer206. In another embodiment, one or more work function metal (WFM) layers may be deposited in thetrenches234 and formed on the sidewalls of thespacers226 before filling thetrenches234 with the metal gate material. The WFM layer may tune the threshold voltage of a resulting semiconductor device as understood by those ordinarily skilled in the art.
• Turning now toFIGS. 14-20, a process flow that interposes a high-dielectric constant layer238 (i.e., a high-k layer238) between thespacers226 and the sidewalls of eachdummy gate element222 is illustrated according to an exemplary embodiment of the present disclosure. In this regard,FIG. 14 illustrates a conformal high-k layer238 interposed between aconformal spacer layer224 and thedummy gate elements222. The conformal high-k layer238 may first be deposited on sidewalls of thedummy gates elements222, hardmask gate caps220, and exposed surfaces of theetch stop layer206 located between eachdummy gate element222. The high-k layer238 may be formed from various high-k materials including, but not limited to, hafnium oxide (HfO₂). Theconformal spacer layer224 may then be formed on an upper surface of the high-k layer238. Theconformal spacer layer224 may be formed from, for example, SiN.
• Referring toFIG. 15, an etching process is performed that partially removes thespacer layer224 formed on theetch stop layer206 and that etches thespacer layer224 formed on thedummy gate element222. Accordingly, an upper portion of the high-k layer238 is exposed.
• Referring toFIG. 16, a second etching process, such as a carina etch for example, is performed that removes the exposed upper portion of the high-k layer238. The carina etch is selective to thespacer layer224 such that the high-k layer238 is removed while thespacer layer224 is maintained. Accordingly, an upper portion of the underlyinghardmask gate cap220 is exposed.
• Referring toFIG. 17, a planarization process that partially recesses acontact dielectric layer232 is performed which exposes an upper portion of thedummy gate elements222. Thecontact dielectric layer232 is formed as previously discussed above. The planarization process may stop on the upper surface of thedummy gate elements222 such that the upper surface of thecontact dielectric layer232 is flush with the upper surfaces of thedummy gate elements222.
• Referring now toFIG. 18, thedummy gate elements222 are removed according to a replacement metal gate (RMG) process as understood by those ordinarily skilled in the art. For example, an RIE process or a wet etching process may be used to remove thedummy gate elements222. Accordingly,gate trenches234 are formed that expose portions of the underlyingetch stop layer206 located between the remaining high-k layer238 formed on sidewalls of thespacers226.
• Referring toFIG. 19, an etching process is performed that removes portions of the high-k layer238 from the sidewalls of thespacers226 such that the length of eachtrench234 increases. Various etchings process may be used to remove the high-k layer238 including, but not limited to, a carina etch. As illustrated inFIG. 19, for example, a portion of the high-k layer238′ may be maintained between thespacer226 and theetch stop layer206, while thetrench234 exposes a portion of theetch stop layer206 located between thespacers226. Although not illustrated, at least one exemplary embodiment of the present teachings utilizes the high-k layer238 as a gate oxide layer. In this regard, the properties of the high-k layer238 may change during the dummy gate pull process to affect work function properties. For purpose of gate work function control, the high-k layer238 may be best used as a sacrificial layer and may be omitted atFIG. 19, and deposited as a high-k gate oxide layer before performing a metal filling process described below. Accordingly, process of removing portions of the high-k layer238 from the sidewalls is optional and may be skipped at this stage of the exemplary process flow.
• Turning now toFIG. 20, a metal filling process is performed that fills thetrenches234 with a gate metal to form respectivemetal gate elements236. The gate metal may include various metal materials including, but not limited to, tungsten (W), tantalum (Ta), titanium (Ti), Niobium (Nb), rhenium (Rh), aluminum (Al), tungsten nitride (WN), titanium nitride (TiN) and tantalum nitride (TaN). According to this exemplary embodiment, themetal gate elements236 may contact thespacers226, the remaining high-k material, and theetch stop layer206. As discussed above, a high-k layer238 for forming a gate oxide layer may be deposited in thetrenches234 before depositing the gate metal in thetrenches234.
• FIG. 21 is a flow diagram illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure. The method begins atoperation2100, and proceeds tooperation2102 where a plurality of gate formation layers are formed on one or more semiconductor fins. The semiconductor fins are formed on a semiconductor substrate as understood by those ordinarily skilled in the art. Atoperation2104, the plurality of gate formation layers are etched such that a one or more hardmask gate caps are patterned atop a dummy gate dielectric layer. A trilayer resist (TLR) patterning scheme may be used to etch the gate formation layer, for example. Atoperation2106, the dummy gate dielectric layer is etched to form one or more dummy gate elements having a respective hardmask gate cap formed on an upper surface thereof. The pattern of the one or more gate elements may be based on a pattern of the one or more hardmask gate caps previously formed atop the dummy gate dielectric layer. Atoperation2108, a conformal spacer layer is deposited on sidewalls of the dummy gates elements, the gate caps, and on the exposed surfaces of the etch stop layer located between each dummy gate element. According to another exemplary embodiment, a conformal high-k layer may be deposited on sidewalls of the dummy gates elements, the gate caps, and on the exposed surfaces of the etch stop layer located between each dummy gate element. Thereafter, the conformal spacer layer is deposited on top of the high-k layer. In this regard, the high-k layer is interposed between the dummy gate elements and the spacer layer.
• Turning tooperation2110, the spacer layer formed on the dummy gate element is partially etched such that the spacers are formed on the sidewalls of the dummy gate element and a portion of the underlying gate cap is exposed. Atoperation2112, a pre-clean process is performed that removes a portion of the etch stop layer located between each dummy gate element. Accordingly, a portion of the underlying semiconductor fin located between each dummy gate element is exposed. Atoperation2114, an epitaxial material is grown on the exposed portion of the semiconductor fin located between the dummy gate elements. Atoperation2116, a contact dielectric layer is deposited on the gate caps and in the voids between the dummy gate elements. Atoperation2118, a portion of contact dielectric layer and a portion of the spacers are recessed using, for example, a chemical mechanical planarization (CMP) process. The planarization process may stop on the upper surface of the dummy gate elements such that the upper surface of the contact dielectric layer is flush with the upper surfaces of the dummy gate elements. Atoperation2120, the dummy gate elements are removed according to a replacement metal gate (RMG) process as understood by those ordinarily skilled in the art. For example, a wet etching process or RIE process may be used to remove the dummy gate elements. Accordingly, gate trenches that expose the underlying etch stop layer are formed between a respective pair of spacers. Atoperation2122, the trenches are filled with a metal gate material to form respective metal gate elements, and the method ends atoperation2124.
• The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
• The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the inventive teachings and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
• The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the operations described therein without departing from the spirit of the invention. For instance, the operations may be performed in a differing order or operations may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
• While various embodiments have been described, it will be understood that those skilled in the art, both now and in the future, may make various modifications which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims (20)

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:

forming at least one semiconductor fin on a semiconductor substrate;

forming an etch stop layer on an upper surface of the at least one semiconductor fin;

forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material;

patterning the plurality of gate formation layers to form a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from the dielectric material;

depositing a spacer layer that conforms with an outer surface of each dummy gate element; and

etching the spacer layer to form a spacer on each sidewall of the dummy gate elements and etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fin.

2. The method ofclaim 1, further comprising epitaxially growing a semiconductor material from the exposed portion of the semiconductor fin after etching the spacer layer and the portion of the etch stop layer.

3. The method ofclaim 2, wherein the dummy gate element is formed from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (SiO₂), and a silicon boron carbide material that contains nitrogen (SiB:C(N)).

4. The method ofclaim 3, wherein the patterning the plurality of gate formation layers includes patterning a photoresist layer to form a plurality of photoresist elements at a top surface of the plurality of gate formation layers.

5. The method ofclaim 4, wherein the patterning the plurality of gate formation layers further includes patterning a gate hardmask layer formed on an upper surface of the dummy gate layer according to the plurality of photoresist elements to form a plurality of respective gate caps on the dummy gate layer.

6. The method ofclaim 5, wherein the patterning the plurality of gate formation layers further includes patterning the dummy gate layer according to the plurality of gate caps to form the plurality of dummy gate elements.

7. The method ofclaim 6, wherein the patterning the plurality of gate formation layers is performed according to a trilayer resist patterning scheme.

8. A method of fabricating a semiconductor device, the method comprising:

forming at least one semiconductor fin on a semiconductor substrate;

forming an etch stop layer on an upper surface of the at least one semiconductor fin;

patterning a photoresist layer to form a plurality of photoresist elements above a dummy gate layer that is formed from a dielectric material;

patterning the dummy gate layer using the plurality of photoresist elements to form plurality of respective dummy gate elements on the etch stop layer, each dummy gate element formed from the dielectric material;

depositing a spacer layer that conforms to an outer surface of each dummy gate element;

etching the spacer layer to form a spacer on each sidewall of the dummy gate elements; and

etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fins.

9. The method ofclaim 8, wherein the etching a portion of the etch stop layer includes performing a pre-clean process after etching the spacer layer, the pre-clean process forming cavities in the etch stop layer located between the dummy gate elements to expose an underlying portion of the at least one semiconductor fin.

10. The method ofclaim 9, further comprising epitaxially growing semiconductor material from the cavities such that a portion of the epitaxially grown semiconductor material contacts a pair of opposing spacers to form a source/drain region.

11. The method ofclaim 10, further comprising depositing a contact dielectric layer that fills a void between the spacers and covers an upper portion of the dummy gate elements.

12. The method ofclaim 11, further comprising performing a planarization process that partially recesses the contact dielectric layer and stops on the dummy gate elements such that an upper portion of the dummy gate elements is flush with the contact dielectric layer.

13. The method ofclaim 12, further comprising removing the dummy gate elements to form respective trenches between a pair of respective spacers.

14. The method ofclaim 13, further comprising filling each trench with a metal gate material to form a respective metal gate element.

15. The method ofclaim 14, further comprising a plurality of gate formation layers formed on an upper surface of the dummy gate layer, the plurality of gate formation layers including a hardmask layer formed on a gate hardmask layer formed on an upper surface of the dummy gate layer, and an organic layer interposed between the hardmask layer and the photoresist layer.

16. A method of fabricating a semiconductor device, the method comprising:

forming at least one semiconductor fin on a semiconductor substrate;

forming an etch stop layer on an upper surface of the at least one semiconductor fin;

forming a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from a dielectric material and having a hardmask gate cap formed on an upper surface of the semiconductor fin;

depositing a high-dielectric constant layer that conforms to an outer surface of each dummy gate element and depositing a spacer layer on the high-dielectric constant layer;

performing a first etching process that etches the spacer layer to form a spacer on each sidewall of dummy gate elements and exposes an upper portion of the high-dielectric constant layer;

performing a second etching process different from the first etching process that selectively etches the upper portion of the high-dielectric constant layer to expose each hardmask gate cap;

removing the hardmask gate caps and the dummy gate elements to form a trench between a respective pair of spacers; and

performing a third etching process after removing the dummy gates elements to remove a portion of the high-dielectric constant material from the sidewalls of the spacers such that a remaining portion of the high-dielectric constant material is interposed between the spacers and the etch stop layer.

17. The method ofclaim 16, further comprising performing a planarization process before removing the dummy gate elements to recess the hardmask gate cap such that an upper portion of the dummy gate elements is exposed.

18. The method ofclaim 17, wherein the dummy gate element is formed from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (SiO₂), and a silicon boron carbide material that contains nitrogen (SiB:C(N)).

19. The method ofclaim 18, further comprising depositing a gate material in the trenches to form a metal gate element that contacts the spacers, the remaining portion of high-dielectric constant material and the etch stop layer.

20. The method ofclaim 19, wherein the first etching process is a reactive ion etching process, the second etching process is a carina etching process, and the third etching process is a carina etching process.

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