US20150162212A1 - Method for Fabricating CMOS Compatible Contact Layers in Semiconductor Devices - Google Patents

Abstract

A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Description

• CROSS-REFERENCE
• This application claims priority to EP 13195799.5, filed Dec. 5, 2013, which is incorporated by reference in its entirety.
TECHNICAL FIELD
• Embodiments of the present subject matter relate to III-V nitride-based semiconductor devices. More particularly, embodiments of the present subject matter relate to fabricating contact layers in the semiconductor devices.
BACKGROUND
• Typically, III-V nitride-based semiconductors are widely used in fabricating semiconductor devices because of their large energy band gap. However, due to the large energy band gap, high contact resistance may be seen between a metal electrode and a semiconductor interface or contact. For example, consider gallium nitride (GaN) including a p-type GaN layer having magnesium (Mg) dopants that form Mg—H complexes with hydrogen. In this case, the Mg—H complexes lead to passivation of the Mg dopants, which results in high contact resistance between the metal electrode and the contact of the p-type GaN layer.
• Additionally, wider market adoption of the semiconductor devices may depend on the fabrication cost. To reduce the fabrication cost, contacts used in the semiconductor devices may need to be made compatible with complementary metal oxide semiconductor (CMOS) fabrication technology. Existing method for fabricating CMOS compatible contacts includes usage of aluminum (Al), which is a CMOS compatible material. However, Al has bad adhesion to the p-type GaN layer. Another existing method for fabricating CMOS compatible contacts includes fabricating an interfacial layer of metals with high work function on the p-type GaN layer. However, even with the presence of the interfacial layer the contacts may have poor electrical characteristics and may not be CMOS compatible.
SUMMARY
• A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. According to one aspect of the present subject matter, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. For example, the Ni layer with a thickness of 5 nm to 15 nm is deposited on the p-type GaN layer. The GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. in an oxygen atmosphere, upon the deposition of the Ni layer. Further, the Ni layer is removed using an etchant. Furthermore, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer. For example, the CMOS compatible contact layer is titanium aluminum titanium (TiAlTi).
BRIEF DESCRIPTION OF THE DRAWINGS
• Various embodiments are described herein with reference to the drawings, wherein:
• FIG. 1 illustrates a flow chart of an example method for fabricating a complementary metal oxide semiconductor (CMOS) compatible contact layer on a p-type gallium nitride (GaN) layer of a GaN based structure, according to one embodiment.
• FIG. 2 is a cross-sectional view of an example GaN based structure having the CMOS compatible contact layer fabricated in accordance with the method described inFIG. 1.
• FIG. 3 illustrates a comparative chart, showing a comparison of threshold voltages of semiconductor devices having CMOS compatible contact layers fabricated without and with Ni layer.
• FIG. 4 illustrates a comparative chart, showing a comparison of threshold voltages of semiconductor devices having the CMOS compatible contact layers fabricated using a 2 nm Ni layer, a 10 nm Ni layer and a 50 nm Ni layer, in accordance with the method described inFIG. 1.
• FIG. 5 illustrates a comparative chart, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by thermally treating the GaN based structure in different atmospheres and for different time durations.
• FIG. 6 illustrates a comparative chart, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by removing the Ni layer using different etchants, in accordance with the method described inFIG. 1.
• The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.
DETAILED DESCRIPTION
• A method for fabricating complementary metal oxide semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In the following detailed description of the embodiments of the present subject matter, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present subject matter is defined by the appended claims.
• In the following detailed description, the term “GaN based structure” refers to a structure including a substrate and a heterogeneous layer stack of gallium nitride (GaN) based materials deposited on the substrate. The heterogeneous layer stack typically includes a p-type GaN layer and an n-type GaN layer deposited on the substrate. Further, the heterogeneous layer stack includes additional layers depending on the semiconductor device, in which the GaN based structure is used. For example, the GaN based structure used in a light emitting diode (LED) includes a substrate and a heterogeneous layer stack including a nucleation layer, a graded intermediate layer, a n-type GaN layer, a multiple quantum well, an electron blocking layer and a p-type GaN layer.
• The present invention relates to fabricating a CMOS compatible contact layer on a p-type GaN layer of a GaN based structure. The method includes deposition of a nickel (Ni) layer on top of the p-type GaN layer, followed by thermal treatment in an oxygen (O₂) atmosphere. Furthermore, the Ni layer is wet stripped in a solution of sulfuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂). Finally, the CMOS compatible contact layer (i.e., aluminum (Al) based) is deposited on the p-type GaN layer.
• FIG. 1 illustratesflow chart100 of an example method for fabricating a CMOS compatible contact layer on a p-type GaN layer of a GaN based structure, according to one embodiment. Atstep102, the GaN based structure is annealed at a temperature of about 750° C. in a nitrogen (N₂) atmosphere. In one example embodiment, the GaN based structure is annealed in a rapid thermal annealing (RTA) oven for 10 minutes in the N₂atmosphere. By annealing the GaN based structure, dopants (e.g., Mg dopants) in the p-type GaN layer are activated, which in turn increases net hole concentration of the p-type GaN layer.
• Atstep104, a Ni layer is deposited on the p-type GaN layer of the GaN based structure. For example, the Ni layer includes a thickness ranging from 5 nm to 15 nm. The deposition of the Ni layer on the p-type GaN layer provides better electrical characteristics, such as lower threshold voltage, as explained in detail with reference toFIG. 3. Further, the electrical characteristics also depend on the thickness of the Ni layer, as explained in detail with reference toFIG. 4.
• At step106, the GaN based structure is thermally treated at a temperature ranging from 350° C. to 500° C. In this case, deposition of additional layers, such as Au or alloys thereof, on the Ni layer is not required. In an example, the GaN based structure is thermally treated at 450° C. in a 100% O₂atmosphere. In another example, the thermal treatment of the GaN based structure is performed for a time period of 60 seconds. Further,FIG. 5 illustrates the improved electrical characteristics of semiconductor devices when the GaN based structure is thermally treated at 450° C. in the O₂atmosphere for 60 seconds.
• Atstep108, the Ni layer is removed using an etchant. In one embodiment, the Ni layer deposited on the p-type GaN layer is wet stripped using a wet etchant. Examples of wet etchants include, a solution of hydrochloric acid (HCl), nitric acid (HNO₃) and water (H₂O), a solution of H₂SO₄and H₂O₂(piranha solution) and the like. For example, the Ni layer can be etched for about 2 minutes using the solution of H₂SO₄+H₂O₂to provide better electrical characteristics.
• Atstep110, the CMOS compatible contact layer is deposited on the p-type GaN layer. For example, the CMOS compatible contact layer includes a multi-layer structure of titanium aluminum titanium (TiAlTi) having a thickness of 1/100/10 nm.
• Examples of the semiconductor devices fabricated with CMOS compatible contact layers, include light emitting diodes (LEDs), power devices and the like. In LEDs, the GaN based structure includes a silicon (Si) substrate, an aluminum nitride (AlN) nucleation layer, a graded aluminum gallium nitride (AlGaN) intermediate layer, a Si doped n-type GaN layer, a indium gallium nitride (InGaN)/GaN multiple quantum well, a AlGaN electron blocking layer, and the p-type GaN layer. Further, the GaN based structure is annealed at 750° C. for 10 min in the N₂atmosphere. Then, the Ni layer is deposited on the p-type GaN of the GaN based structure. Furthermore, the GaN based structure is thermally treated in the 100% O₂atmosphere at 450° C. for 60 seconds. Additionally, the Ni layer is etched using the solution of H₂SO₄+H₂O₂, in the ratio of 4:1. Thereafter, the CMOS compatible contact layer is deposited on the p-type GaN layer. After deposition of the CMOS compatible contact layer on the p-type GaN layer, a diode mesa structure is defined on the GaN based structure, by means of a chlorine based inductively coupled plasma (ICP) dry etch process. In addition, a contact layer is deposited on the Si doped n-type GaN layer of the GaN based structure.
• Referring now toFIG. 2, which illustrates a cross-sectional view of example GaN based structure220 having CMOScompatible contact layer216 fabricated in accordance with the method described inFIG. 1. As shown inFIG. 2, GaN based structure220 includes substrate202 on which a heterogeneous layer stack of GaN based materials is deposited. In an embodiment, the heterogeneous layer stack is deposited on substrate202 using a metalorganic vapor phase epitaxy (MOVPE) technique. The MOVPE technique refers to a process of depositing thin layers of atoms of the GaN based materials onto substrate202. In the MOVPE technique, precursor chemicals (i.e., precursors to the atoms deposited on substrate202) are vaporized and transported into a reactor together with other gases. In one embodiment, the atoms of the GaN based materials (i.e., atoms of Ga, Al and N) are deposited on a 200 mm Si (111) substrate, using the precursor chemicals trimethylgallium, trimethylaluminum and ammonia, respectively. In this case, trimethylgallium, trimethylaluminum and ammonia are vaporized and transported using hydrogen as a carrier gas, such that the heterogeneous layer stack is deposited on substrate202.
• As shown inFIG. 2, the heterogeneous stack of GaN based materials includes nucleation layer204, gradedintermediate layer206, n-type GaN layer208, multiple quantum well210,electron blocking layer212 and p-type GaN layer214. In an embodiment, nucleation layer204 is composed of AlN and gradedintermediate layer206 is composed of AlGaN. Further, n-type GaN layer208 is doped with Si dopants and p-type GaN layer214 is doped with Mg dopants. Furthermore, multiple quantum well210 has an InGaN/GaN quantum well structure. Additionally,electron blocking layer212 is composed of Mg doped AlGaN.
• FurtherFIG. 2 shows, GaN based structure220 having top surface220A and bottom surface220B. Top surface220A is formed by thermally treating a Ni layer (not shown inFIG. 2) at a temperature range of 350° C. to 500° C. for about 60 seconds and then removing the Ni layer. In one embodiment, the Ni layer has a thickness of 10 nm and is thermally treated at 450° C. for 60 seconds in an O₂atmosphere. Further, the Ni layer is removed using a solution of H₂SO₄+H₂O₂.
• Furthermore, CMOScompatible contact layer216 is present on p-type GaN layer214. In addition,contact layer218 is present on n-type GaN layer208. In one embodiment, CMOScompatible layer216 includes a multi-layer structure composed of TiAlTi, having a thickness of 1/100/10 nm. Additionally, GaN based structure220 has a mesa structure and is used in the fabrication of LEDs.
• Referring now toFIG. 3, which illustratescomparative chart300, showing a comparison of threshold voltages of semiconductor devices having CMOS compatible contact layers fabricated without and with Ni layer, with threshold voltage shown on y-axis.
• According tocomparative chart300,graph302 illustrates the threshold voltages of semiconductor devices having the CMOS compatible contact layers fabricated without using of the Ni layer. In contrast,graph304 ofcomparative chart300, illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers that are fabricated by using of the Ni layer having a thickness of 10 nm.
• As shown inFIG. 3, the threshold voltages ingraph302 are between 4.25 v to 5 v, whereas, the threshold voltages ingraph304 are between 3 v to 4.25 v. Fromcomparative chart300, it is observed that there is a significant reduction in the threshold voltages when the Ni layer is used. The reduction in the threshold voltages is attributed to improved hole concentration in the p-type GaN layers (e.g., p-type GaN layer214 ofFIG. 2), of the GaN based structures used in the semiconductor devices. For example, referringFIG. 2, the Mg dopants of p-type GaN layer214 form Mg—H complexes with hydrogen. The deposition of the Ni layer enhances hydrogen desorption from the Mg dopants, which results in improved hole concentration. The improved hole concentration in p-type GaN layer214 results in the reduction of the contact resistance, which in turn results in the reduction of the threshold voltages of the semiconductor devices. Therefore, better electrical characteristics are achieved when the Ni layer is deposited on the p-type GaN layer214.
• Referring now toFIG. 4, which illustratescomparative chart400, showing a comparison of threshold voltages of semiconductor devices having the CMOS compatible contact layers fabricated using a 2 nm Ni layer, a 10 nm Ni layer and a 50 nm Ni layer, in accordance with the method described inFIG. 1.
• According tocomparative chart400, graph402 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated with the 2 nm Ni layer. Further,graph404 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated with the 10 nm Ni layer. Furthermore, graph406 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated with the 50 nm Ni layer. Additionally, threshold voltage is shown on y-axis.
• As shown inFIG. 4, the threshold voltages in graph402 range from 3.75 v to 3.85 v. In contrast, the threshold voltages ingraph404 range mainly from 3.65 v to 3.725 v. Further, as observed in graph406 the threshold voltages range mainly from 4.535 v to 4.575 v. Therefore, lowest threshold voltage range is observed when the 10 nm Ni layers are used to fabricate the CMOS compatible contact layers.
• Referring now toFIG. 5, which illustratescomparative chart500, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by thermally treating the GaN based structure in different atmospheres and for different time durations. As shown incomparative chart500, graph502A and graph502B illustrate the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated in the N₂atmosphere for 60 seconds and 600 seconds, respectively. Furthermore,graph504A and graph504B illustrate the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated in the O₂atmosphere for 60 seconds and 600 seconds, respectively.
• As observed fromFIG. 5, threshold voltage range in graph502A and graph502B is mainly between 4.25 v to 4.45 v and 4.4 v to 4.6 v, respectively. In contrast threshold voltage range ingraph504A and graph504B is mainly between 3.625 v to 3.7 v and 3.4 v to 3.45 v, respectively. Therefore, it is observed that there is a significant reduction in the threshold voltages when the CMOS compatible contact layers fabricated in the O₂atmosphere.
• Further fromgraph504A and graph504B, it is observed that lower threshold voltages can be achieved when the thermal treatment step is performed for 600 seconds in the O₂atmosphere. However, it is also observed that there is only a slight increase in the threshold voltage range when the thermal treatment step is performed for 60 seconds in the O₂atmosphere. Further, in light of the considerable reduction in the time duration (i.e., from 600 seconds to 60 seconds), the slight increase in the threshold voltage range is considered to have a negligible impact on the electrical characteristics of the semiconductor devices.
• Referring now toFIG. 6, which illustratescomparative chart600, showing a comparison of threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated by removing the Ni layer using different etchants, in accordance with the method described inFIG. 1. As shown inFIG. 6,graph602 illustrates the threshold voltages of the semiconductor devices having the CMOS compatible contact layers fabricated without the Ni layer. Furthermore,graph604 illustrates the threshold voltages of the semiconductor devices, when the Ni layer is etched for 10 minutes using HCl+HNO₃+H₂O having the ratio of 3:1:2. In addition,graph606 illustrates the threshold voltages of the semiconductor devices, when the Ni layer is etched for 2 minutes using H₂SO₄+H₂O₂.
• As shown ingraph602, when the Ni layer is not used to fabricate the CMOS compatible contact layers, threshold voltage range is 3.8 v to 4.4 v. Further with regards to graph604, it is observed that when the Ni layer is etched using HCl+HNO₃+H₂O the threshold voltages of the semiconductor devices are in the range of 3.2 v to 4.1 v. Furthermore, as shown ingraph606, when the Ni layer is etched using H₂SO₄+H₂O₂the threshold voltages of the semiconductor devices are in the range of 2.9 v to 3 v. Therefore, it is observed that there is a significant drop in the threshold voltages of the semiconductor devices when the Ni layer is etched using H₂SO₄+H₂O₂.
• As apparent from the above description, the semiconductor devices having the CMOS compatible contact layers fabricated in accordance with the method described inFIG. 1, show better electrical characteristics as compared to the approaches used in the prior art. Further, by using the CMOS compatible contact layers there is a reduction in the cost of fabricating the semiconductor devices. In other words, by using the CMOS compatible contact layers, the economy-of-scale of existing CMOS production lines is effectively used during the fabrication of the semiconductor devices.
• It should be understood that the embodiments and the accompanying drawings as described above have been described for illustrative purposes and the present invention is limited by the following claims. Further, this patent covers all methods fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.

Claims (7)

1. A method for fabricating a complementary metal oxide semiconductor (CMOS) compatible contact layer on a p-type gallium nitride (GaN) layer of a GaN based structure, the method comprising:

depositing a nickel (Ni) layer on the p-type GaN layer;

thermally treating the GaN based structure at a temperature range of 350° C. to 500° C., upon depositing the Ni layer;

removing the Ni layer using an etchant, upon thermally treating the GaN based structure; and

depositing the CMOS compatible contact layer on the p-type GaN layer, upon removing the Ni layer.

2. The method ofclaim 1, wherein the p-type GaN layer comprises magnesium (Mg) dopants.

3. The method ofclaim 1, further comprising:

annealing the GaN based structure at about 750° C. in a nitrogen atmosphere, prior to depositing the Ni.

4. The method ofclaim 1, wherein thermally treating the GaN based structure further comprises: thermally treating the GaN based structure in an oxygen atmosphere for about 60 seconds.

5. The method ofclaim 1, wherein the Ni layer comprises thickness of 5 nm to 15 nm.

6. The method ofclaim 1, wherein the etchant comprises a solution of sulfuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂).

7. The method ofclaim 1, wherein the CMOS compatible contact layer comprises a multi layer structure of titanium aluminum titanium (TiAlTi).

Images