US20150102418A1 - Semiconductor device and method for manufacturing the device - Google Patents

Abstract

A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application is a continuation of U.S. application Ser. No. 13/733,936 filed on Jan. 4, 2013, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0051036 filed on May 14, 2012 in the Korean Intellectual Property Office, and the disclosure of which is incorporated by reference herein in its entirety.
TECHNICAL FIELD
• The inventive concept relates to a semiconductor device and a method for manufacturing the device.
DESCRIPTION OF THE RELATED ART
• Metal-oxide-semiconductor (MOS) transistors using polysilicon gate electrodes are widely known. Polysilicon gate electrodes may be annealed at a high temperature with source and drain regions. Polysilicon gate electrodes may also serve as ion implantation masks when source and drain regions are formed.
• As transistors shrink, resistance of polysilicon electrodes increases, which prevents transistors from operating at high speed. Recently, integrated structures of a high dielectric constant gate oxide and a metal gate has been proposed. The introduction of new materials may cause other problems such as incompatibility of metal gates with high temperature processes and work function controls of the integrated structures. Accordingly, there is a need for an improved process for integrating a high dielectric constant gate oxide and a metal gate.
SUMMARY
• According to an exemplary embodiment of the inventive concept, a semiconductor device comprises a N-type field effect transistor including a first high dielectric constant (high-k) layer disposed on a substrate. A diffusion layer including a metal oxide is disposed on the first high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer.
• According to an exemplary embodiment of the inventive concept, a static random access memory (SRAM) device comprises a N-type field effect transistor and a P-type field effect transistor. The N-type field effect transistor comprises a high dielectric constant (high-k) layer disposed on a substrate. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The P-type field effect transistor comprises the high-k layer disposed on the substrate.
• According to an exemplary embodiment of the inventive concept, a semiconductor device comprises a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.
• According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device comprises a step where a first trench and a second trench are formed in a substrate and defined by spacers formed on a substrate. A high-k layer is formed in the first and the second trenches. A diffusion layer is formed on the high-k layer of the first trench which includes a metal oxide. A passivation layer is formed on the diffusion layer for preventing the diffusion layer from being oxidized. Metal atoms of the metal oxide are diffused into the high-k layer of the first trench and the substrate under the first trench by thermally heating the substrate. A first metal gate is formed on the passivation layer formed in the first trench.
BRIEF DESCRIPTION OF THE DRAWINGS
• The above and other aspects and features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings of which:
• FIG. 1 is a cross-sectional view of a semiconductor device in accordance with an exemplary embodiment of the inventive concept;
• FIGS. 2 to 6 illustrate intermediate steps for explaining a method for manufacturing the semiconductor device ofFIG. 1 in accordance with an exemplary embodiment of the inventive concept;
• FIG. 7 is a cross-sectional view of a semiconductor device in accordance with an exemplary embodiment of the inventive concept;
• FIGS. 8 to 10 illustrate intermediate steps for explaining the method for manufacturing the semiconductor device in accordance with the exemplary embodiment of the inventive concept;
• FIG. 11 is a cross-sectional view of a semiconductor device in accordance with the exemplary embodiment of the inventive concept;
• FIG. 12 is a cross-sectional view of a semiconductor device in accordance with an exemplary embodiment of the inventive concept;
• FIG. 13 is a diagram for explaining a fin-type transistor (FinFET) in accordance with an exemplary embodiment of the inventive concept;
• FIG. 14 is a cross-sectional view taken along line A-A′ ofFIG. 13;
• FIG. 15 is a cross-sectional view taken along line B-B′ ofFIG. 13;
• FIG. 16 is a diagram for explaining a fin-type transistor (Fin-FET) in accordance with the embodiment of the inventive concept;
• FIG. 17 is a cross-sectional view taken along line C-C′ ofFIG. 16;
• FIG. 18 is a cross-sectional view taken along line D-D′ ofFIG. 16;
• FIG. 19 is a layout of the semiconductor device in accordance with an exemplary embodiment of the inventive concept;
• FIG. 20 is a circuit diagram of a static random access memory (SRAM) cell of the semiconductor device ofFIG. 19;
• FIG. 21 is a cross-sectional view of a NFET and a PFET of the SRAM cell and a PFET of a logic region of the semiconductor device ofFIG. 20 according an exemplary embodiment of the invention;
• FIG. 22 is a cross-sectional view of a NFET and a PFET of the SRAM cell and a PFET of a logic region of the semiconductor device ofFIG. 20 according an exemplary embodiment of the invention.
• FIG. 23 is a layout of a semiconductor device in accordance with an exemplary embodiment of the inventive concept;
• FIG. 24 is a cross-sectional view of the semiconductor device of the semiconductor device ofFIG. 23; and
• FIG. 25 is a block diagram of an electronic system including a semiconductor device according to an embodiment of the inventive concept.
DETAILED DESCRIPTION OF THE EMBODIMENTS
• Exemplary embodiments of the inventive concept will be described below in more detail with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity.
• It will be understood that when an element or layer is referred to as being “on” another element or layer, it may be directly on the other layer or intervening layers may be present. Like numbers may refer to like elements throughout.
• FIG. 1 is a cross-sectional view of a semiconductor device in accordance with an exemplary embodiment of the inventive concept.
• Referring toFIG. 1, asemiconductor substrate100 may include a first region (e.g., NFET region) and a second region (e.g., PFET region). Here, the first region NFET may be a region where an N-type field effect transistor (NFET) is formed, and the second region PFET may be a region where a P-type field effect transistor (PFET) is formed.
• Each of the first and second regions NFET and PFET may include a channel region C and source/drain regions101 and102. Here, the channel region C of the first region NFET may be a N-channel region through which N-type carriers of the source/drain regions101 move, and the channel region C of the second region PFET may be a P-channel region through which P-type carriers of the source/drain regions102 move. An isolation (not shown) may be formed the outside of the source and drainregions101 and102 in thesemiconductor substrate100 to isolate the NFET and the PFET.
• The NFET may include afirst trench111. Thefirst trench111 may be surrounded byspacers120 disposed on the channel region C of NFET, and an interlayer insulatinglayer110 may be formed on the outside of thespacers120. In some embodiments of the inventive concept, the NFET may include a tensile stress layer (not shown) on the source/drain regions101 for providing tensile stress to the channel region C of the NFET. In an embodiment according to the inventive concept, the shape of thespacers120 may have an L shape.
• Aninterface layer125, a first high dielectric constant (high-k)layer131, adiffusion layer140, apassivation layer150, and afirst metal gate161 may be sequentially disposed in thefirst trench111. In this case, the first high-k layer131, thediffusion layer140, thepassivation layer150 and thefirst metal gate161 may be configured to extend upward along the sidewall of thefirst trench111 as shown inFIG. 1.
• Theinterface layer125 may serve to prevent a defect interface between thesemiconductor substrate100 and the first high-k layer131. Theinterface layer125 may include a low-k material layer whose dielectric constant (k) is equal to or less than about 9. For example, theinterface layer125 may include a silicon oxide layer (k is about 4) or a silicon oxynitride layer (k is about 4 to 8 according to the content of oxygen atoms and nitrogen atoms). In an embodiment of the inventive concept, theinterface layer125 may be formed of silicate, or may be formed of a combination of the above illustrated layers.
• The first high-k layer131 having a dielectric constant equal to or more than about 10 may be disposed on theinterface layer125. In some embodiments of the inventive concept, the first high-k layer131 may be formed of, e.g., HfO₂, Al₂O₃, ZrO₂, TaO₂or the like, but the inventive concept is not limited thereto.
• Thediffusion layer140 may be formed on the first high-k layer131. In this embodiment, thediffusion layer140 may be, e.g., a metal oxide layer. For example, thediffusion layer140 may be formed of LaO, Y₂O₃, Lu₂O₃, SrO or a combination thereof, but the inventive concept is not limited thereto. A material (e.g., metal) included in thediffusion layer140 is diffused into the channel region C of the NFET so that a work function of the NFET may be adjusted. Accordingly, it is possible to improve the performance of the NFET.
• Further, the material (e.g., metal) included in thediffusion layer140 may be diffused into the first high-k layer131 disposed under thediffusion layer140. Accordingly, the dielectric constant of the first high-k layer131 may increase to reduce the gate leakage current of the NFET. Meanwhile, thediffusion layer140 may prevent metal atoms of thefirst metal gate161 from infiltrating into the first high-k layer131, thereby contributing to improvement of the performance of the NFET. This function of thediffusion layer140 according to inventive concept will be described in detail later in explaining a method for manufacturing the semiconductor device according to the inventive concept.
• In some embodiments of the inventive concept, thediffusion layer140 may be formed on the first high-k layer131 to have a first thickness. Here, the first thickness may be about 3 to about 10 Å, but the inventive concept is not limited thereto.
• Thepassivation layer150 may be disposed on thediffusion layer140. Thepassivation layer150 may prevent thediffusion layer140 from being oxidized in a manufacturing process to be described later. In this embodiment, thepassivation layer150 may be formed of a metal nitride layer. For example, thepassivation layer150 may be formed of at least one of TiN and TaN. In an embodiment of the inventive concept, thepassivation layer150 may be formed of a single layer of TiN, a double layer including a lower layer of TiN and an upper layer of TaN, or the like, but the inventive concept is not limited thereto.
• In some embodiments of the inventive concept, thepassivation layer150 may be formed to have a second thickness larger than a first thickness of thediffusion layer140. For example, thepassivation layer150 may be formed to have a thickness of about 11 to about 70 Å, but the inventive concept is not limited thereto.
• Thefirst metal gate161 may be disposed on thepassivation layer150. Thefirst metal gate161 may have a single layer structure formed of a metal layer or a multilayer layer structure formed of a metal nitride layer and a metal layer. The metal layer of thefirst metal gate161 may be, e.g., Al, W, Ti or a combination thereof, and the metal nitride of thefirst metal gate161 may be TiN, TaN or a combination thereof, but the inventive concept is not limited thereto. In this embodiment, thefirst metal gate161 may be formed by using a replacement metal gate (RMG) process. This will be described in detail later in explaining a method for manufacturing the semiconductor device according to an embodiment of the inventive concept.
• In some embodiments of the inventive concept, thefirst metal gate161 may include an N-type work function layer. The N-type work function layer may be formed of, e.g., TiAl, TiAlN, TaC, TaAlN, TiC, HfSi or the like, but the inventive concept is not limited thereto. The N-type work function layer may be formed to have a thickness of about 30 to about 120 Å, but the inventive concept is not limited thereto.
• The PFET may include asecond trench112 disposed on the channel region C of the PFET. Specifically, thesecond trench112 may be surrounded by thespacers120. The interlayer insulatinglayer110 may be disposed on the outside of thespacers120. In some embodiments of the inventive concept, the PFET may include a compressive stress layer (not shown) on the substrate the source/drain regions102. In an embodiment of the inventive concept, thespacers120 may have an L shape.
• The PFET may include theinterface layer125, a second high dielectric constant (high-k)layer132, and asecond metal gate162. Thelayers125,132, and162 may be sequentially disposed in thesecond trench112. The second high-k layer132 and thesecond metal gate162 may extend upward along the sidewall of thesecond trench112 as shown inFIG. 1. The second high-k film132 may include substantially the same high-k material as that of the first high-k layer131.
• Thesecond metal gate162 may be disposed on the second high-k layer132. Thesecond metal gate162 may have a single layer structure formed of a metal layer or a multilayer metal layer including a metal nitride layer and a metal layer.
• In some embodiments of the inventive concept, the PFET may include thesecond metal gate162 which is different from that of the NFET. For example, thefirst metal gate161 may include a metal gate having four layers of TiAl/TiN/Ti/Al, and thesecond metal gate162 may include a metal gate having four layers of TiN/TaN/TiN/Al, but the inventive concept is not limited thereto.
• In some embodiments of the inventive concept, thesecond metal gate162 may include a P-type work function layer. The P-type work function layer may be formed to have a thickness of about 50 to about 100 Å, but the inventive concept is not limited thereto.
• In some embodiments of the inventive concept, thesecond metal gate162 may include both a lower P-type work function layer and an upper N-type work function layer.
• Connection wirings (not shown) may electrically connect contacts (not shown) to the NFET and the PFET through the interlayer insulatinglayer110.
• As described above, the NFET may include thediffusion layer140 according to embodiments of the inventive concept to improve the performance of the NFET. The PFET may include the P-type work function layer to improve the performance of the PFET.
• Hereinafter, an exemplary method for manufacturing the semiconductor device ofFIG. 1 will be described below.
• FIGS. 2 to 6 illustrate intermediate steps for explaining a method for manufacturing the semiconductor device ofFIG. 1 in accordance with an exemplary embodiment of the inventive concept.
• First, referring toFIG. 2, adummy gate105 including agate insulating layer102 and afirst poly gate104 is formed on thesemiconductor substrate100. Impurities are implanted into thesemiconductor substrate100 using thedummy gate105 as a mask to form the source and drainregions101 and102. Then, thespacers120 are formed at both sides of thedummy gate105. The shape of thespacers120 is not limited to the illustrated shape as described above. For example, the spacers may have L-shaped spacers. The interlayer insulatinglayer110 is formed on thesemiconductor substrate100 to cover thedummy gate105. Then, theinterlayer insulating layer110 is planarized to the level of the upper surface of thedummy gate105.
• Next, referring toFIG. 3, thedummy gate105 of is removed. Removing thedummy gate105 may be performed in various ways including a method of removing thedummy gate105 in a replacement metal gate (RMG) process. In this way, when thedummy gate105 ofFIG. 2 is removed, thefirst trench111 and thesecond trench112 are formed.
• Next, referring toFIG. 4, theinterface layer125 is formed in the first andsecond trenches111 and112. Here, theinterface layer125 may serve to prevent a defect interface between thesemiconductor substrate100 and a high dielectric constant (high-k)layer130 which will be described later. Theinterface layer125 may include a low-k material layer whose dielectric constant (k) is equal to or less than about 9. For example, theinterface layer125 may be formed of a silicon oxide layer (k is about 4) or a silicon oxynitride layer (k is about 4 to 8 according to the content of oxygen atoms and nitrogen atoms in the layer). In an embodiment of the inventive concept, theinterface layer125 may be formed of silicate, or may be formed of a combination of the layers illustrated above layer.
• Subsequently, the high-k layer130, thediffusion layer140 and thepassivation layer150 are sequentially formed in the first andsecond trenches111 and112. In this embodiment, thediffusion layer140 may be formed a metal oxide layer, and thepassivation layer150 may be formed of a metal nitride layer. For example, thediffusion layer140 may be formed of LaO and thepassivation layer150 may be formed of TiN. In some embodiments, thediffusion layer140 may be formed of LaO, Y₂O₃, Lu₂O₃, SrO or a combination thereof, and thepassivation layer150 may be formed of TiN, TaN or a combination thereof.
• Thediffusion layer140 may have a thickness of about 3 to 10 Å. Thediffusion layer140 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or the like. Thepassivation layer150 may have a thickness of about 11 to 70 Å using CVD, ALD or the like.
• Next, referring toFIG. 5, apolysilicon layer135 is selectively formed on the first region NFET of thesemiconductor substrate100. Subsequently, the exposedpassivation layer150 and thediffusion layer140 are sequentially removed. Accordingly, as shown inFIG. 5, thepassivation layer150 and thediffusion layer140 formed in thesecond trench112 may be removed.
• Then, thesemiconductor substrate100 is thermally treated. In such thermal treatment, the metal of thediffusion layer140 formed in thefirst trench111 may be diffused into the channel region C of the NFET and the high-k layer130 formed in thefirst trench111. For example, when thediffusion layer140 is formed of LaO, the La atoms are diffused out of thediffusion layer140 to the channel region of C and the high-k layer130 in the first region NFET. Meanwhile, since thediffusion layer140 is not formed in thesecond trench112, the channel region C of the PFET and the high-k layer130 formed in thesecond trench112 are not influenced by thediffusion layer140 in the thermal treatment.
• As described above, the atoms of thediffusion layer140 diffused into the high-k layer130 formed in thefirst trench111 may increase the dielectric constant of the high-k layer130 formed in thefirst trench111. Further, the La atoms of thediffusion layer140 diffused into the channel region C of the NFET may adjust a work function of the NFET to improve the performance of the NFET. The metal atoms diffused may not be limited to La atoms, but when thediffusion layer140 is formed of other metal oxides layer, other metal atoms included in the metal oxides layer may be diffused in the thermal treatment.
• In an exemplary embodiment of the inventive concept, thepassivation layer150 may prevent thediffusion layer140 from being oxidized in the thermal treatment. When thepolysilicon layer135 is formed on thepassivation layer150, thepassivation layer150 may serve to prevent thediffusion film140 from being oxidized from oxygens which may diffuse through thepolysilicon film135 in the thermal treatment.
• Next, thepolysilicon layer135 formed on the first region NFET of thesemiconductor substrate100 is removed by ashing or the like. Then, TiAl, TiN, Ti and Al layers are sequentially formed on thepassivation layer150. Using an Al CMP process, thefirst metal gate161 shown inFIG. 1 may be formed. However, thefirst metal gate161 ofFIG. 1 according to an exemplary embodiment is not limited thereto, but may be modified according to design choice. In an embodiment of the inventive concept, thefirst metal gate161 may include the N-type work function layer to adjust the work function of thefirst metal gate161.
• The second metal gate ofFIG. 1 may be formed by forming TaN, TiN and Al layers sequentially on the high-k layer130 ofFIG. 5 formed in thesecond trench112. An Al CMP process may be performed to form thesecond metal gate162. Thesecond metal gate162 may also include the P-type work function layer or a two layer work function layer including a P-type work function layer and an N-type work function layer disposed on the P-type work function layer to improve the performance of the PFET as described above.
• After the formation of the first andsecond metal gates161 and162 is completed, connection wirings may be formed. The connection wirings may connect contacts to the NFET and the PFET through the interlayer insulatinglayer110.
• Hereinafter, a method for manufacturing the semiconductor device ofFIG. 1 in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIGS. 2-4 and6.
• As shown inFIGS. 2 to 4, thesemiconductor substrate100 includes the first andsecond trenches111 and112 formed in the first region NFET and the second region PFET, respectively. Theinterface layer125, the high-k layer130, thediffusion layer140 and thepassivation layer150 are sequentially formed in the first andsecond trenches11 and112. Since these processes have been described above, further description will be omitted here.
• Referring toFIG. 6, a polysilicon layer (not shown) is selectively formed on the first region NFET of thesemiconductor substrate100. The exposedpassivation layer150 and thediffusion layer140 formed in thesecond trench112 are sequentially removed. The polysilicon layer (not shown) formed on the first region NFET of thesemiconductor substrate100 is removed by ashing or the like.
• Then, thesemiconductor substrate100 is thermally treated. While thesemiconductor substrate100 is thermally treated, the material (e.g., metal) included in thediffusion layer140 formed in thefirst trench111 may be diffused into the channel region C of the NFET and the high-k layer130 formed in thefirst trench111.
• At this time, since thepolysilicon layer135 ofFIG. 5 is not formed on the first region NFET of thesemiconductor substrate100, thepassivation layer150 may be exposed to the ambient environment including oxygen. Accordingly, in this case, thepassivation layer150 may prevent the oxygen content of thediffusion layer140 from being changed due to the oxygen from the ambient environment in the thermal treatment.
• Then, since forming thefirst metal gate161 in thefirst trench111 and forming thesecond metal gate162 in thesecond trench112 are the same as described above, further description will be omitted.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIG. 7.
• FIG. 7 is a cross-sectional view of a semiconductor device in accordance with an exemplary embodiment of the inventive concept. The semiconductor device ofFIG. 7 may have similar structure of that ofFIG. 1 except a PFET. The following description will focus on that difference.
• Referring toFIG. 7, thediffusion layer140 and thepassivation layer150 may be sequentially formed in thesecond trench112 of the semiconductor device of the second embodiment, similarly to thefirst trench111. However, in this embodiment, adiffusion barrier layer170 for preventing the diffusion of thediffusion layer140 may be additionally formed below thediffusion layer140 formed in thesecond trench112.
• Thediffusion barrier layer170 may be formed to extend upward along the sidewall of thesecond trench112 as shown inFIG. 7. Thediffusion barrier layer170 may serve to prevent metal of thediffusion layer140 formed of, e.g., a metal oxide layer from being diffused into the second high-k layer132 or the channel region C of the PFET. Accordingly, in the semiconductor device according to an exemplary embodiment of the inventive concept, differently from the above-described embodiment, thediffusion layer140 and thepassivation layer150 are sequentially formed also in thesecond trench112, but the same effect as that of the above-described embodiment may be obtained due to the presence of thediffusion barrier layer170.
• In some embodiments of inventive concept, thediffusion barrier layer170 may include a P-type work function layer. A metal nitride layer may be mentioned as an example of thediffusion barrier layer170. Specifically, thediffusion barrier layer170 may be formed of, e.g., TiN, but the inventive concept is not limited thereto. Further, in some other embodiments of the inventive concept, thediffusion barrier layer170 may have a double layer structure including a metal nitride layer and a metal layer. Specifically, thediffusion barrier layer170 may have a double layer structure including, e.g., TiN and Al, but the inventive concept is not limited thereto. In some other embodiments of the inventive concept, thediffusion barrier layer170 may have a three-layer layer structure including, e.g., a first metal nitride layer, a metal layer and a second metal nitride layer. Specifically, thediffusion barrier layer170 may have a three-layer layer structure including, e.g., TiN, Al and TiN, but the inventive concept is not limited thereto. Thediffusion barrier layer170 may have a thickness of, e.g., 1 to 100 Å, but the inventive concept is not limited thereto.
• Hereinafter, a method for manufacturing the semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described.
• FIGS. 8 to 10 illustrate intermediate steps for explaining the method for manufacturing the semiconductor device in accordance with the exemplary embodiment of the inventive concept.
• First, as shown inFIG. 3, thefirst trench111 is formed in the first region NFET of thesemiconductor substrate100, and thesecond trench112 is formed in the second region PFET of thesemiconductor substrate100. Since this has been described sufficiently in the above, a repeated description will be omitted.
• Then, referring toFIG. 8, theinterface layer125 is formed in the first andsecond trenches111 and112. Then, the high-k layer130 and thediffusion barrier layer170 are sequentially formed in the first andsecond trenches111 and112 by CVD, ALD or the like.
• In an exemplary embodiment of the inventive concept, thediffusion barrier layer170 may include a P-type work function layer. For example, thediffusion barrier layer170 may be formed of TiN, but the inventive concept is not limited thereto.
• In an embodiment of the inventive concept, thediffusion barrier layer170 may have a double layer structure including a metal nitride layer and a metal layer. For example, the metal nitride layer is formed of TiN and the metal layer is formed of Al, but the inventive concept is not limited thereto.
• In an embodiment of the inventive concept, thediffusion barrier layer170 may have a three-layer structure including a first metal nitride layer, a metal layer and a second metal nitride layer. For example, the first and the second metal nitrides are formed of TiN, and the metal is formed of Al, but the inventive concept is not limited thereto. Thediffusion barrier layer170 may have a thickness of about 1 to 100 Å, but the inventive concept is not limited thereto.
• Then, after masking the second region PFET of thesemiconductor substrate100, thediffusion barrier layer170 formed on the first region NFET of thesemiconductor substrate100 is selectively removed. As a result, thediffusion barrier layer170 may exist in thesecond trench112, but may not exist in thefirst trench111.
• Then, referring toFIG. 9, thediffusion layer140 and thepassivation layer150 are sequentially formed in each of thefirst trench111 and thesecond trench112 by CVD, ALD or the like. In this case, thediffusion layer140 may be formed to have a thickness of about 3 to 10 Å, and thepassivation layer150 may be formed to have a thickness of about 11 to 70 Å. Accordingly, thediffusion barrier layer170 is not formed under thediffusion layer140 formed in thefirst trench111, and thediffusion barrier layer170 may be formed under thediffusion layer140 formed in thesecond trench112.
• Then, referring toFIG. 10, thesemiconductor substrate100 in which thediffusion layer140 and thepassivation layer150 are formed respectively in thefirst trench111 and thesecond trench112 is thermally treated. In this case, since thediffusion barrier layer170 is formed under thediffusion layer140 formed in thesecond trench112, the material (e.g., metal) included in thediffusion layer140 is not diffused into the channel region C of the PFET or the high-k layer130 formed in thesecond trench112. Accordingly, the material (e.g., metal) included in thediffusion layer140 is selectively diffused into only the channel region C of the NFET and the high-k layer130 formed in thefirst trench111 as shown inFIG. 10.
• Then, referring toFIG. 7, thefirst metal gate161 is formed on thepassivation layer150 formed in thefirst trench111. Also, thesecond metal gate162 is formed on thepassivation layer150 formed in thesecond trench112. Since this has been described sufficiently in the above, a repeated description will be omitted.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIG. 11.
• FIG. 11 is a cross-sectional view of a semiconductor device in accordance with the exemplary embodiment of the inventive concept. The semiconductor device ofFIG. 11 is substantially the same structure as that ofFIG. 7 except that the PFET ofFIG. 11 further includes acobalt layer175. The following description will focus on the difference.
• Referring toFIG. 11, acobalt layer175 may be further formed under thesecond metal gate162 formed in thesecond trench112 of the semiconductor device according to the exemplary embodiment. Thecobalt layer175 may improve metal-fill characteristics of themetal gate162 when themetal gate162 is formed on thecobalt layer175. For example, when thesecond metal gate162 is formed on thecobalt layer175, themetal gate162 may fill in thetrench112 without forming a void. Accordingly, thesecond metal gate162 may be formed more reliably in thesecond trench112.
• Thecobalt layer175 may be formed on thepassivation layer150 by CVD or the like. In this case, the thickness of thecobalt layer175 may be about 1 to 20 Å, but the inventive concept is not limited thereto.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIG. 12. The semiconductor device ofFIG. 12 may have substantially the same structure as that ofFIG. 7 except for a PFET. The following description will focus on this difference.
• Referring toFIG. 12, thediffusion barrier layer170 may be disposed on a second high dielectric constant (high-k)layer132 in thesecond trench112. Thediffusion barrier layer170 may have a U shape which partially covers the lower portion of the second high-k layer132, so the upper portion of the second high-k layer132 is not covered with the U shapediffusion barrier layer170. For example, the ends of the U shapediffusion barrier layer170 are positioned lower than the upper surface of the PFET.
• The U shapediffusion barrier layer170 may improve the metal-fill characteristics of ametal gate162 because themetal gate162 is formed in thetrench112. to be formed on thediffusion barrier layer170. Accordingly, since the metal-fill characteristics are improved when thesecond metal gate162 is formed on thediffusion barrier layer170 as illustrated, thesecond metal gate162 may be formed more reliably in thesecond trench112.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIGS. 13 to 15.
• FIG. 13 is a diagram for explaining a fin-type transistor (FinFET) in accordance with an exemplary embodiment of the inventive concept.FIG. 14 is a cross-sectional view taken along line A-A′ ofFIG. 13.FIG. 15 is a cross-sectional view taken along line B-B′ ofFIG. 13.FIGS. 13 to 15 illustrate a fin-type transistor (FinFET) including the metal gate of the NFET ofFIG. 1 in accordance with an exemplary embodiment of the inventive concept.
• Referring toFIGS. 13 to 15, the FinFET may include a fin F1, a gate electrode222, arecess225, and a source/drain261.
• The fin F1 may extend in a second direction Y1. The fin F1 may be a portion of asubstrate200 and may include an epitaxial layer grown from thesubstrate200. Anisolation201 may cover the side surface of the fin F1.
• The gate electrode222 may be disposed on the fin F1, extending in a first direction X1. The gate electrode222 formed on the first high-k layer131 and theinterface layer125 may include thediffusion layer140, thepassivation layer150, and thefirst metal gate161.
• Therecess225 may be formed in a firstinterlayer insulating layer202 at both sides of the gate electrode222. The sidewall of therecess225 is inclined and the shape of therecess225 may be widened as it goes farther away from thesubstrate100. Meanwhile, as shown inFIG. 13, the width of therecess225 may be larger than the width of the fin F1.
• The source/drain261 may be formed in therecess225. The source/drain261 may have an elevated shape. For example, the upper surface of the source/drain261 may be higher than the upper surface of theisolation201. Further, the source/drain261 and the gate electrode222 may be isolated from each other by thespacers120.
• The source/drain261 may include the same material as that of thesubstrate200. For example, when thesubstrate200 includes Si, the source/drain261 may be formed of Si. In an embodiment, the source/drain261 of the NFET may be formed of a material having tensile stress for NFET. For example, when thesubstrate200 includes Si, the source/drain261 may include SiC having a lattice constant smaller than that of Si. The tensile stress may improve the mobility of carriers of the channel region of the fin F1.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIGS. 16 to 18.
• FIG. 16 is a diagram for explaining a fin-type transistor (Fin-FET) in accordance with the embodiment of the inventive concept.FIG. 17 is a cross-sectional view taken along line C-C′ ofFIG. 16.FIG. 18 is a cross-sectional view taken along line D-D′ ofFIG. 16.FIGS. 16 to 18 illustrate the gate of the PFET shown inFIG. 12 applied to a fin-type transistor (Fin-FET). The semiconductor device ofFIG. 16 is substantially the same structure as that of theFIG. 13 except that the gate of PFET ofFIG. 12 is applied to FinFET. The gate of PFET ofFIG. 12 was explained above with reference toFIG. 12, and further description is omitted here.
• For the PFET, the source/drain261 may include a material having compressive stress. For example, thesubstrate200 includes Si, the source/drain261 may be formed of SiGe having a lattice constant larger than that of Si. The compressive stress may improve the mobility of carriers of the channel region of the fin F1.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIGS. 19 to 21.
• FIG. 19 is a layout of the semiconductor device in accordance with an exemplary embodiment of the inventive concept.FIG. 20 is a circuit diagram of a static random access memory (SRAM) cell of the semiconductor device ofFIG. 19.FIG. 21 is a cross-sectional view of a NFET and a PFET of the SRAM cell and a PFET of alogic region410 of the semiconductor device ofFIG. 20 according an exemplary embodiment of the invention.
• Referring toFIG. 19, the semiconductor device may include amemory region300 and a peripheral region400. Thememory region300 may be, e.g., a region where a memory device is formed, and the peripheral region400 may be, e.g., a region where a peripheral circuit device is formed.
• In an exemplary embodiment of the inventive concept, an SRAM cell ofFIG. 20 may be formed in thememory region300. Referring toFIG. 20, the memory device may include a pair of inverters INV1 and INV2 connected in parallel between a power supply node Vcc and a ground node Vss, and a first transmission transistor T1 and a second transmission transistor T2 respectively connected to output nodes of the inverters INV1 and INV2. The first transmission transistor T1 and the second transmission transistor T2 may be connected to a bit line BL and a complementary bit line BL/, respectively. The gates of the first transmission transistor T1 and the second transmission transistor T2 may be connected to word lines WL1 and WL2, respectively.
• The first inverter INV1 may include a first load transistor T5 and a first drive transistor T3 which are connected in series. The second inverter INV2 may include a second load transistor T6 and a second drive transistor T4 which are connected in series. Further, the first inverter INV1 and the second inverter INV2 are configured such that the input node of the first inverter INV1 is connected to the output node NC2 of the second inverter INV2 and the input node of the second inverter INV2 is connected to the output node NC1 of the first inverter INV1, thereby forming a latch circuit.
• Here, at least one of the first load transistor T5 and the second load transistor T6 may be formed of the P-type field effect transistor (PFET) according to the exemplary embodiments of the inventive concept. Further, at least one of the first transmission transistor T1, the second transmission transistor T2, the first drive transistor T3 and the second drive transistor T4 may be formed of the N-type field effect transistor (NFET) according to the exemplary embodiments of the inventive concept.
• In some embodiments of the inventive concept, the peripheral region400 may include, e.g., an input/output (I/O) region. The peripheral region400 may be a lower density one than thememory region300, and distance between transistors larger than that of thememory region300. The peripheral region400 may include alogic region410. Further, a P-type field effect transistor (PFET) according to the embodiments of the inventive concept may be formed in thelogic region410.
• For example, the semiconductor device ofFIG. 19 may include the NFET and PFET ofFIG. 1 as part of the SRAM cell in thememory region300. The semiconductor device also includes the PFET ofFIG. 7 for the peripheral circuit device in thelogic region410.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIGS. 19,20, and22. In this exemplary embodiment, the NFET and PFET ofFIG. 7 may be formed as the SRAM cell in thememory region300, and the PFET ofFIG. 12 may be formed for the peripheral circuit device in thelogic region410. However, the inventive concept is not limited thereto, and the above-described embodiments may be combined to a semiconductor device.
• Next, a semiconductor device in accordance with an exemplary embodiment of the inventive concept will be described with reference toFIGS. 23 and 24.
• FIG. 23 is a layout of a semiconductor device in accordance with an exemplary embodiment of the inventive concept.FIG. 24 is a cross-sectional view of the semiconductor device of the semiconductor device ofFIG. 23.
• Referring toFIGS. 23 and 24, the semiconductor device may include amemory region500 and aperipheral region600. In this case, theperipheral region600 may include first to third logic regions610 to630.
• In this embodiment, the FETs according to the embodiments of the inventive concept may be formed in the logic regions610 to630. For example, the PFET ofFIG. 1 may be formed in the first logic region610, the PFET ofFIG. 7 may be formed in thesecond logic region620, and the PFET ofFIG. 12 may be formed in thethird logic region630. However, the inventive concept is not limited thereto, and the first to third logic regions610 to630 may include a different combination of the PFETs according to the above-described embodiments.
• FIG. 25 is a block diagram of an electronic system including a semiconductor device according to an embodiment of the inventive concept.
• Referring toFIG. 25, the electronic system900 may include a memory system912, a processor914, aRAM916 and auser interface918. For example, the electronic system900 may be a mobile apparatus, computer or the like.
• The memory system912, the processor914, theRAM916 and theuser interface918 may communicate with each other through a bus920. The processor914 may control the electronic system900. TheRAM916 may be used as an operating memory of the processor914.
• For example, the processor914, theRAM916 and/or the memory system912 may include the semiconductor device according to the embodiments of the inventive concept. Further, in some embodiments of the inventive concept, the processor914 and theRAM916 may be packaged together in the same package.
• Theuser interface918 may be used to input/output data to/from the electronic system900. The memory system912 may store data processed by the processor914, or data inputted from the outside. The memory system912 may include a controller and a memory.
• While the inventive concept has been shown and described with reference to exemplary embodiments thereof it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the sprit and scope of the inventive concept as defined by the following claims.

Claims (4)

What is claimed is:

1. A static random access memory (SRAM) device comprising: a N-type field effect transistor comprising: a high dielectric constant (high-k) layer disposed on a substrate, a diffusion layer including a metal oxide disposed on the high-k layer, a passivation layer disposed on the diffusion layer, and a first metal gate disposed on the passivation layer; and a P-type field effect transistor comprising: the high-k layer disposed on the substrate.

2. The SRAM device ofclaim 1, wherein the P-type field effect transistor further comprising; a diffusion barrier layer formed on the second high-k layer; the diffusion layer disposed on the diffusion barrier layer; the passivation layer disposed on the diffusion layer; and a second metal gate disposed on the passivation layer, wherein the diffusion barrier layer prevents metal atoms of the diffusion layer from being diffused into the high-k layer.

3. The SRAM device ofclaim 1, wherein the first metal gate includes a first plurality of conductive layers and the second metal gate includes a second plurality of conductive layers, wherein first plurality of conductive layers include a conductive layer different from that of the second plurality of conductive layers.

4. The SRAM device ofclaim 1, wherein the N-type field effect transistor and the P-type field effect transistor is configured to be a fin-type transistor.

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