US20150084203A1

Movatterモバイル変換

Info

Publication number: US20150084203A1
Application number: US14/038,526
Authority: US
Inventors: Shih-Hung Chen
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2013-09-26
Filing date: 2013-09-26
Publication date: 2015-03-26
Anticipated expiration: 2033-09-26
Also published as: US8970040B1

Abstract

A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.

Description

BACKGROUND

The present invention relates to high density devices. In particular, embodiments of the present invention provide methods for forming contact structure in which conductors connected to multiple active layers in a three-dimensional high density semiconductor device, such as memory device.

Three dimensional (3D) semiconductor devices are characterized by multiple layers forming a stack of alternating active layers and insulating layers. In a memory device, each of the layers can include a planar array of memory cells. For certain three-dimensionally stacked memory devices, active layers can comprise active strips of materials configured as bit lines or word lines for memory cells stacked in spaced-apart ridge-like structures. The active layers can be made from a doped (p-type or n-type) or undoped semiconductor material. In such 3D memory, memory cells can be disposed at the cross-points of the stacked bit lines or word lines and the crossing word lines or bit lines, forming a 3D memory array.

One way of connecting interlayer conductors to the active layers in the stack can be referred to as a multiple lithographic-etch process, disclosed in commonly owned U.S. Pat. No. 8,383,512, entitled Method for Making Multilayer Connection Structure, the disclosure of which is incorporated by reference. Another way of doing so, which can be referred to as a trim-etch process, is disclosed in commonly owned U.S. patent application Ser. No. 13/735,922, filed 7 Jan. 2013, entitled Method for Forming Interlayer Conductors to a Stack of Conductor Layers, the disclosure of which is incorporated by reference.

SUMMARY

An example of a method for forming a stairstep contact structure is carried out as follows. A stack of alternating active layers and insulating layers is formed by the following. A first sub stack is formed. The first stack includes N active layers separated by insulating layers, the N active layers including an upper boundary active layer. A second sub stack is formed over the first sub stack. The second sub stack includes M active layers separated by insulating layers, the M active layers including an upper boundary active layer. A first sub stack insulating layer is formed between the first and second sub stacks. The first sub stack insulating layer has an etching time different from the etching times of the insulating layers of the second sub stack for a given etching process. The upper boundary active layers are accessed. After accessing the upper boundary active layers, the remainder of the active layers of the first and second sub stacks are accessed create a stairstep structure of landing areas on the active layers of the first and second sub stacks. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.

An example of a method for forming a contact structure is carried out as follows. A stack of alternating active layers and insulating layers is formed. The stack includes sub stacks having upper boundary active layers, the sub stacks having insulating layer and active layer pairs below the upper boundary active layer. The insulating layer and active layer pairs constitute first layer pairs with uniform first sub stack etch times for a given etch process. The stack also includes second layer pairs, the second layer pairs including sub stack insulating layers between the sub stacks. The second layer pairs have second etch times for the given etch process different from the first sub stack etch times. A plurality of openings are etched in the stack, the openings stopping on the boundary layer active layers. Selected openings are etched to form vias that expose active layers inside each of the sub stacks. Interlayer conductors are formed (1) in the vias to extend to the active layers, and (2) in the openings that were not etched during the etching to deepen step to extend to upper boundary active layers.

An example of a stairstep contact structure includes a stack of alternating active layers and insulating layers having non-simple periods so that for the same etch process, at least one of (1) the active layers have different etch times, or (2) the insulating layers have different etch times. A stairstep structure of landing areas is on the active layers. Interlayer conductors extend to the stairstep structure of landing areas. The interlayer conductors are separated from one another by insulating material.

Other aspects and advantages of the technology are described with reference to the drawing in the detailed description and claims which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective drawing of a semiconductor device including semiconductor pads for interlayer conductors.

FIGS. 2A,2B,2C,2D,2E and2F are simplified views of the process steps performed for an example of a multiple lithographic-etch process when the stack has a simple period.

FIGS. 3A,3B,3C,3D and3E are simplified views a multiple lithographic-etch process when the stack has a non-simple period illustrating etching depth problems created during the process.

FIGS. 4A,4B,4C,4D,4E,4F and4G are simplified views of the process steps performed for an example of a trim-etch process when the stack has a simple period.

FIGS. 5A,5B,5C and5D are simplified views of a trim-etch process when the stack has the non-simple period illustrating etching depth problems created during the process.

FIG. 6 is an example of a contact structure including a stack of alternating active and insulating layers which do not have a simple period.

FIGS. 7-25 show an example for making the contact structure ofFIG. 6 using a multi-lithographic etching process.

FIG. 7 shows a stack of active and insulating layers.

FIG. 8 shows the structure ofFIG. 7 with a first etch mask.

FIG. 9 shows the structure ofFIG. 8 after etching.

FIG. 10 shows the structure ofFIG. 9 after removal of the first etch mask.

FIG. 11 shows the structure ofFIG. 10 with a second etch mask.

FIG. 12 shows the structure ofFIG. 11 after etching.

FIG. 13 shows the structure ofFIG. 12 after removal of the second etch mask.

FIG. 14 shows the structure ofFIG. 13 with a third etch mask.

FIG. 15 shows the structure ofFIG. 14 after etching.

FIG. 16 shows the structure ofFIG. 15 after removal of the third etch mask.

FIG. 17 shows the structure ofFIG. 16 with a fourth etch mask.

FIG. 18 shows the structure ofFIG. 17 after etching.

FIG. 19 shows the structure ofFIG. 18 after removal of the fourth etch mask.

FIG. 20 shows the structure ofFIG. 19 with a fifth etch mask.

FIG. 21 shows the structure ofFIG. 20 after etching.

FIG. 22 shows the structure ofFIG. 21 after removal of the fifth etch mask and showing vias formed in the stack.

FIG. 23 shows the structure ofFIG. 22 after deposition of an insulating layer.

FIG. 24 shows the structure ofFIG. 23 after removal of portions of the insulating layer leaving sidewall insulation within the vias.

FIG. 25 shows the structure ofFIG. 24 with interconnect conductors creating the contact structure ofFIG. 6.

FIGS. 26-43 show an example of making a contact structure using a trim-etch process.

FIG. 26 shows a stack of alternating active and insulating layers with a first etch mask.

FIG. 27 shows the structure ofFIG. 26 after etching.

FIG. 28 shows the structure ofFIG. 27 after replacing the first etch mask with a second etch mask.

FIG. 29 shows the structure ofFIG. 28 after etching.

FIG. 30 shows the structure ofFIG. 29 after removal of the second etch mask.

FIG. 31 shows the structure ofFIG. 30 with a third etch mask.

FIG. 32 shows the structure ofFIG. 31 after etching.

FIG. 33 shows the structure ofFIG. 32 after a first trimming the third etch mask.

FIG. 34 shows the structure ofFIG. 33 after etching.

FIG. 35 show the structure ofFIG. 34 after a second trimming of the third etch mask.

FIG. 36 shows the structure ofFIG. 35 after etching.

FIG. 37 shows the structure ofFIG. 36 after removal of the trimmed third etch mask.

FIG. 38 shows the structure ofFIG. 37 after depositing an insulating/stopping layer.

FIG. 39 shows the structure ofFIG. 38 after depositing an insulating material.

FIG. 40 shows the structure ofFIG. 38 with a fourth etch mask.

FIG. 41 shows the structure ofFIG. 40 after etching.

FIG. 42 shows the structure ofFIG. 41 after removal of the fourth etch mask and showing the vias formed in the structure.

FIG. 43 shows the structure ofFIG. 42 with interlayer conductors within the vias.

FIG. 44 is a simplified flowchart outlining the steps carrying out the method for forming a contact structure described below with regard toFIGS. 7-25.

FIG. 45 is a simplified flowchart outlining the steps carrying out the method for forming a contact structure described below with regard toFIGS. 26-43.

FIG. 46 is a simplified flowchart outlining the steps carrying out the method for forming a contact structure described below with regard toFIGS. 7-25 andFIGS. 26-43.

FIG. 47 is a simplified block diagram of an integrated circuit.

DETAILED DESCRIPTION

A detailed description of various embodiments is described with reference to the figures. The following description will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods, but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Unless otherwise stated, in this application, specified relationships, such as parallel to, aligned with, having uniform characteristics, or in the same plane as, mean that the specified relationships are within limitations of manufacturing processes and within manufacturing variations. When components are described as being coupled, connected, being in contact or contacting one another, they need not be physically directly touching one another unless specifically described as such. Like elements in various embodiments are commonly referred to with like reference numerals.

FIG. 1 is a perspective view of an example of a 3D semiconductor device (for example, a memory device)100 as described in commonly owned U.S. Patent Publication No. 2012/0182806, filed Apr. 1, 2011, entitled Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures. Various insulating materials are formed but not shown to better illustrate active layers, including semiconductor strips and semiconductor pads for connecting to interlayer conductors, and others.3D semiconductor device100 is formed overlying a substrate (not shown) having an insulating layer (not shown) formed thereon. The substrate can include one or more integrated circuits and other structures. Four

semiconductor pads

102B,103B,104B, and105B on a proximal end of a stack of active layers and four

semiconductor pads

112B,113B,114B, and115B on a distal end of the stack, are shown, but the number of active layers and the corresponding semiconductor pads can be extended to any number of layers N, where N is an integer having a value greater than one. As shown, the3D semiconductor device100 includes stacks of active strips (e.g.102,103,104,105) separated by insulating material. Semiconductor pads (e.g.102B,103B,104B, and105B) terminate the strips in corresponding active layers. As illustrated, the

semiconductor pads

102B,103B,104B, and105B are electrically coupled to the active layers for connection to decoding circuitry to select layers within the array.

Semiconductor pads

102B,103B,104B, and105B can be patterned concurrently as the active layers are patterned, with the possible exception of vias for the interlayer conductors. Each of the active strips includes a semiconductor material suitable to act as a channel region in the illustrated embodiment. The strips are ridge-shaped extending on the Y-axis as illustrated, so that the

active strips

102,103,104,105 can be configured as bodies including channel regions of flash memory cell strings, for example, in horizontal NAND string configurations. As illustrated, alayer152 of memory material coats the plurality of stacks of active strips in this example, and at least on the side walls of the active strips in other examples. In other embodiments, the active strips can be configured as word lines for vertical NAND string configurations. See, for example, commonly owned U.S. Pat. No. 8,363,476, filed 19 Jan. 2011, entitled Memory Device, Manufacturing Method and Operating Method of the Same.

Each stack of active strips is terminated at one end by semiconductor pads and the other end by a source line. Therefore,

active strips

102,103,104,105 terminate on the proximal end by

semiconductor pads

102B,103B,104B, and105B and asource line terminal119 on the distal end of the strips passing through gateselect line127. Active strips112,113,114,115 terminate on the distal end by

semiconductor pads

112B,113B,114B, and115B and a source line terminal (for example, source line128) passing through gateselect line126 near the proximal end of the strips.

In the embodiment ofFIG. 1, a plurality of conductors125-1 through125-N is arranged orthogonally over the plurality of stacks of active strips. The conductors125-1 through125-N, have surfaces conformal with the plurality of stacks of active strips, within the trenches defined by the plurality of stacks, and defining a multilayer array of interface regions at cross-points between side surfaces of the

active strips

102,103,104,105 on the stacks and conductors125-1 through125-N (for example, word lines or source select lines). As shown, a layer of silicide (e.g. tungsten silicide, cobalt silicide, titanium silicide or nickel silicide)154 can be formed over the top surfaces of conductors (for example, word lines or source select lines).

Depending upon the implementation,layer152 of memory material can comprise multilayer dielectric charge storage structures. For example, a multilayer dielectric charge storage structure includes a tunneling layer comprising a silicon oxide, a charge trapping layer comprising a silicon nitride, and a blocking layer comprising a silicon oxide. In some examples, the tunneling layer in the dielectric charge storage layer can comprise a first layer of silicon oxide less than about 2 nanometers thick, a layer of silicon nitride less than about 3 nanometers thick and a second layer of silicon oxide less than about 3 nanometers thick. In other implementations,layer152 of memory material can comprise only a charge trapping layer without the tunneling layer or the blocking layer.

In the alternative, an anti-fuse material such as a silicon dioxide, silicon oxynitride or other silicon oxides, for example, having a thickness on the order of 1 to 5 nanometers, can be utilized. Other anti-fuse materials may be used, such as silicon nitride. For anti-fuse embodiments,

active strips

102,103,104,105 can be a semiconductor material with a first conductivity type (e.g. p-type). Conductors (for example, word lines or source select lines)125-N can be a semiconductor material with a second conductivity type (e.g. n-type). For example, the

active strips

102,103,104,105 can be made using p-type polysilicon while the conductors125-N can be made using relatively heavily doped n+-type polysilicon. For anti-fuse embodiments, the width of the active strips should be enough to provide room for a depletion region to support the diode operation. As a result, memory cells comprising a rectifier formed by the p-n junction with a programmable anti-fuse layer in between the anode and cathode are formed in the 3D array of cross-points between the polysilicon strips and conductor lines.

In other embodiments, different programmable resistance memory materials can be used as the memory material, including metal oxides like tungsten oxide on tungsten or doped metal oxide, and others. Some of such materials can form devices that can be programmed and erased at multiple voltages or currents, and can be implemented for operations for storing multiple bits per cell.

As can be seen inFIG. 1, the

semiconductor pads

102B,103B,104B, and105B are coupled on one side to active strips in the corresponding layer of the device, such as by being formed of a continuous patterned layer of semiconductor. In some embodiments, the pad can be coupled on two sides to active strips in the corresponding layer. In other embodiments, the pads can be connected to the active strips using other materials and structures that allow for electrical communication of the voltages and currents needed for operation of the device. Also, an overlying insulator layer (not shown) and

semiconductor pads

102B,103B,104B,105B, except the lowermost pad, include openings102C1,102C2,102C3,103C1,103C2,104C1, that expose landing areas on underlying pads forming a stairstep structure in this example.

FIGS. 2A-2F illustrate a simplified example of a multiple lithographic-etch process used to make a contact structure.FIG. 2A shows astack200 of alternating active layers202 and insulating layers204 with afirst etch mask206 formed on the uppermost active layer202.1.First etch mask206 has firstetch masks openings208.FIG. 2B shows the structure ofFIG. 2A after etching through one level, that is one active layer202 and one insulating layer204. This first etching takes place at the firstetch mask openings208 to createfirst etch openings210. After stripping offirst etch mask206, seeFIG. 2C, asecond etch mask212 is formed over thestack200, seeFIG. 2D. Second etch mask to 12 has secondetch mask openings214, one being aligned with a first etch masks opening208 and the other not. Next, as shown inFIG. 2E, a second etching takes place through two levels. The result is formation of vias and extending to the second, third and fourth active layers202.2,202.3 and202.4 with the first active layer202.1 being exposed by the removal ofsecond etch mask212 as illustrated inFIG. 2F.

Stack

200 is made of active layers202 having common etching characteristics and insulating layers204 having common etching characteristics. In this example, active layers202 are made of the same conductive material and have the same nominal thickness. Likewise, insulating layers204 are made of the same insulating material with the same nominal thickness. Therefore each pair of insulating layer and active layer will have a uniform etch time for a given etch process. This arrangement of the pairs of insulating and active layers can be referred to as stacked layers with a simple period.

FIGS. 3A-3D illustrate an example similar to that ofFIGS. 2A-2F in which the stacked layers do not have a simple period. In this case, the third insulating layer204.3 is thicker than either of insulating layers204.1 or204.2 above it. Therefore, the time it would take to etch through first, upper boundary active layer202.1, first insulating layer204.1, second active layer202.4 and second insulating layer204.2 at second etch masks opening214.1 would only be sufficient to etch part way through third insulating layer204.3 at second etch masks opening214.2.

As described herein, structures are provided that have non-simple periods, in which the active and/or insulating layers have different etch times, typically because the active and/or insulating layers are made of different materials with different etching characteristics, or different thicknesses, or a combination of different materials and different thicknesses for the active and/or insulating layers.

FIGS. 4A-4G illustrate a simplified example of a trim-etch process. Anetch mask220 is formed on the uppermost active layer202.1 with an etch masks opening222 exposing aportion224 of the uppermost active layer. A first etching step etches through active layer202.1 and insulating layer204.1 to expose aportion226 of active layer202.2 as shown inFIG. 4B. Next, during a first trim step, a portion ofetch mask220 is removed to expose anotherportion228 of active layer202.1. The next etching step, shown inFIG. 4D, etches through one active layer202 and one insulating layer204 to expose aportion230 of active layer202.2 and aportion232 of active layer202.3. Next, during a second trim step, seeFIG. 4E, a portion ofetch mask220 is removed exposing aportion234 of active layer202.1. This is followed by another etch step, seeFIG. 4F, through one active layer and one insulating layer at each of

portions

234,230 and232 to create the structure ofFIG. 4F.FIG. 4G shows the structure ofFIG. 4F after stripping the remainder ofetch mask220 to create astairstep structure236 having a number of landing areas238 at the different active layers202.1-202.4 for connection with interlayer conductors.

FIGS. 5A-5D illustrate an example similar to that ofFIGS. 4A-4G in which the stacked layers do not have a simple period. In this example, the second insulating layer204.2 is much thicker than either of insulating layers below or above it. During the etching step ofFIG. 5D, which corresponds to the etching step ofFIG. 4D, etching is sufficient to etchportion228 of active layer202.1 and is the portion of underlying insulating layer204.1 to exposeportion230 of active layer202.2. However, as illustrated inFIG. 5D, such etching is only sufficient to etch part way through the second insulating layer204.2 because it is greater thickness takes longer to etch through. Therefore, unlikeFIG. 4D, the third active layer202.3 is not exposed by the second etching step. However, continuing the second etching step to etch through second insulating layer204.2 until third active layer202.3 is exposed can damage or destroyexpose portion230 of active layer202.2.

With that as a background, an example of acontact structure250 in which the stack of active and insulating layers do not have a simple period is shown inFIG. 6.Contact structure250 includes astack200 of alternating active layers202 and insulating layers204.Stack200 also includes sub stacks252 having upper boundary active layers202.1. The sub stacks252 also include the first layer pairs254 of insulating and active layers202,204 below each upper boundary active layer202.1. In the example ofFIG. 6, there are four sub stacks252 labeled252.1 through252.4.Pairs254 of insulating and active layers202,204 have uniform, first etch times for a given etch process.Stack200 also includes sub

stack insulating layers

256,258 and260 between the sub stacks252. In this example, the composition of insulating

layers

256,258 and260 is the same, typically silicon dioxide SiO2 while the composition of substack insulating layer258 is different, such as silicon nitride SiN. Thickness and composition of sub

stack insulating layers

256 and260 are substantially the same so that each has substantially the same etching characteristics. However, the thickness of insulating

layers

256 and260 is greater than the thickness of insulating layers204 so that the time to etch through insulating

layers

256 and260 is greater than the time it takes to etch through an insulating layer204 for a given etch process.

Substack insulating layer256 and the underlying, adjacent active layer202.1 constitute asecond layer pair262 having a second etch time for the given etch process. Substack insulating layer260 and the underlying, adjacent active layer202.1 constitute athird layer pair264, also having the second etch time for the given etch process. Substack insulating layer258 and the underlying, adjacent active layer202.1 constitute afourth layer pair266 having a fourth etch time different from any of the first through third etch times. Etch times for the different layer pairs254,262,264,266 can be made the same or different using a wide range of different materials having different etch rates together with the same or different thickness of the insulating and active layers.

Contact structure

250 also includes an upper insulatinglayer268 overlying active layer202.1 of stack252.1 and a lower insulatinglayer270 underlying active layer202.4 of sub stack252.4; both can made of silicon dioxide. A set ofinterlayer conductors272 extend through upper insulatinglayer268 to make contact with each active layer202 of each sub stack252 in a stairstep fashion. Eachinterlayer conductor272 is surrounded by sidewall insulation274, which can be made of silicon nitride.

FIGS. 7-25 will be discussed showing one example of steps for making thecontact structure250 ofFIG. 6 using a multi-lithographic etching process, such as discussed with regard toFIGS. 2A-2F.

FIG. 7 shows stack200 including sub stacks252.1-252.4 between upper insulatinglayer268 and lower insulatinglayer270, the sub stacks separated by sub

stack insulating layers

256,258,260.FIG. 8 shows the structure ofFIG. 7 with afirst etch mask278 with firstetch mask openings280 formed therein.FIG. 9 shows a result of etching the structure ofFIG. 8 atopenings280 through upper insulatinglayer268 to create firstetched openings282 withinlayer268 down to the upper boundary active layer202.1 of sub stack252.1.FIG. 10 shows the structure ofFIG. 9 afterfirst etch mask278 has been stripped.

FIG. 11 shows the structure ofFIG. 10 after forming asecond etch mask284 covering half of the firstetched openings282 and having secondetch mask openings286 aligned with the other half ofetched openings282. InFIG. 12, the structure ofFIG. 11 is etched throughopenings286 to create secondetched openings288 down to an upper boundary active layer202.1 of sub stack252.3. InFIG. 13,second etch mask284 has been stripped exposing firstetched openings282.

FIG. 14 shows the structure ofFIG. 13 after forming athird etch mask290 having third etch mask openings292.1 exposing half of firstetched openings282 and third etch mask openings292.2 exposing half of the secondetched openings288.FIG. 15 shows the structure ofFIG. 14 after etching through first sub stack252.1 and substack insulating layer256 at third etch mask openings292.1.FIG. 15 also shows a result of etching through third sub stack252.3 and substack insulating layer260 at third etch mask openings292.2. Doing so creates thirdetched openings294 and fourthetched openings296.FIG. 16 shows the structure ofFIG. 15 afterthird etch mask290 has been stripped.

FIG. 17 shows the structure ofFIG. 16 with afourth etch mask298 havingopenings299 exposing every other firstetched opening282, secondetched opening288, thirdetched opening294 and fourthetched opening296.FIG. 18 shows a result of etching through the upper boundary active layer202.1 and underlying insulation layer204.1 for each of sub stacks252.1,252.2,252.3 and252.4. This creates a partially etchedstructure300, shown withfourth etch mask298 removed inFIG. 19. Partially etchedstructure300 hasopenings302 extending to different levels withinstack200.FIG. 20 shows the structure ofFIG. 19 with afifth etch mask304 alternatingly covering and exposing twoopenings302.Fifth etch mask304 hasopenings306 overlying the exposedopenings302 ofFIG. 19.FIG. 21 shows a result of a second etching procedure in which two active layers202 and two insulating layers204 are etched through eachopening306.

FIG. 22 shows the result of stripping offfifth etch mask304 from the structure ofFIG. 21 showing vias308 extending down tolanding areas310 of active layers202. The structure ofFIG. 22 has a stairstep arrangement oflanding areas310.FIG. 23 shows an insulating layer312, such as silicon nitride SiN, deposited over the structure ofFIG. 22 thus creating a layer ofsidewall insulation314 lining each via308. InFIG. 24, insulation layer312 overlying upper insulatinglayer268 and at the bottom of each via308 has been removed to exposelanding areas310.FIG. 25 shows the structure ofFIG. 24 after fillingvias308 with a conductor, such as tungsten W, to createinterlayer conductors272 extending from the upper surface318 of the upper insulatinglayer268 tolanding areas310 at each active layer202, thus creating thecontact structure250 ofFIG. 6.

FIGS. 26-43 will be discussed showing one example of steps for making a contact structure using a trim-etch process, a simplified example of which is discussed above with regard toFIGS. 4A-4G.

FIG. 26 illustrates astack330 identical to stack200 ofFIG. 7 except for the absence of upper insulatinglayer268. Afirst etch mask332 is formed overstack330 covering aportion331 of active layer202.1 of first substrate252.1 and exposing about half of the active layer. During the first etching step, the result of which is shown inFIG. 27,stack330 is etched at the exposed portion of active layer202.1 through half of the sub stacks, that is through first sub stack252.1, substack insulating layer256, second sub stack252.2 and substack insulating layer258, thereby exposing aportion334 of upper boundary active layer202.1 of third sub stack252.3

FIG. 28 shows the structure ofFIG. 27 with asecond etch mask336 covering about one half ofportion331 and about one half ofportion334. The exposed region ofportion331 is then etched through sub stack252.1 and substack insulating layer256. The exposed region ofportion334 is etched through sub stack252.3 and substack insulating layer260. Doing so creates the structure ofFIG. 29 with the

surface areas

338,340,342 and344. InFIG. 30,second etch mask336 has been removed from the structure ofFIG. 29.

FIG. 31 shows athird etch mask346 formed over surfaces338-344 exposing a portion of each of those surfaces. Those exposed portions of surfaces338-344 are etched through one active layer202 and one insulating layer204 to create the structure ofFIG. 32 with exposed surface areas348-351. Thereafter, as shown inFIG. 33, a third etch mask352 is trimmed to create trimmedetch mask354 which exposes the additional portions of upper boundary active layers202.1 for each of sub stacks252.1-252.4. This is followed by another etching step through one active layer202 and the underlying insulating layer204, the result of which is shown inFIG. 34.FIG. 35 shows the result of trimming trimmedetch mask354 to create trimmedetch mask356, again exposing additional portions of upper boundary active layers202.1 for each of sub stacks252.1-252.4. Again, this is followed by another etching step through one active layer202 and the underlying insulating204, the result of which is shown inFIG. 36.

FIG. 37 shows the structure ofFIG. 36 after removal of trimmedetch mask356 resulting in a stairstep arrangement oflanding areas358. As shown inFIG. 38, this is followed by deposition of an insulatinglayer360, sometimes referred to as stoppinglayer360, which can be, for example, SiN. Next, as shown inFIG. 39, the structure ofFIG. 38 is covered by an insulatingmaterial362 made of, for example, SiO2. Next, afourth etch mask364 havingopenings366 aligned withlanding areas358 is formed on insulatingmaterial362.Vias368 are formed through insulatingmaterial362 and insulatinglayer360 down tolanding areas358. This is shown inFIG. 41.FIG. 42 shows the structure ofFIG. 41 after removal offourth etch mask364.FIG. 43 shows interlayerconductors272, which can be made of tungsten W, formed withinvias368 to createcontact structure370.

FIG. 44 is a simplified flowchart outlining the basic steps for carrying out a method for forming a contact structure as described above with regard toFIGS. 7-25. At step380 astack200 of alternating active and insulating layers202 and204 is formed. A plurality of

openings

294,288 and296 are etched in the stack atstep382, the openings stopping on the boundary layer active layers202.1. Selected ones of the

openings

294,288 and296 are etched to deepen them atstep384 to createvias308. At

steps

386 and388,insulation314 is formed in thevias308 and in the

openings

294,288 and296 that were not etched. This is followed by the formation ofinterlayer conductors272 therein atstep390.Interlayer conductors272 connect tolanding areas310 of the active areas202.

FIG. 45 is a simplified flowchart outlining the basic steps for carrying out a method for forming a contact structure as described above with regard toFIGS. 26-43. At step392 astack330 of alternating active and insulating layers202 and204 is formed.Stack330 is then etched atstep394 to expose

sections

338,342 and344 of the upper boundary active layers202.1 of sub stacks252.

Sections

338,342 and344 are also referred to as

surface areas

338,342344. Atstep396 these exposed sections are etched to expose active layers202.2,202.3 and202.4 below the upper boundary active layers202.1 and to create a stairstep structure. Aninsulation layer360 is formed on the stairstep structure atstep398. Theinsulation layer360 is covered with an insulatingmaterial362 atstep400. Atstep402

vias

368 are formed through the insulatingmaterial362 and the insulatinglayer360. Interlayer conductors372 are formed within thevias368 atstep404 to createcontact structure370.

FIG. 46 is a simplified flowchart outlining the basic steps for carrying out a method for forming a contact structure as described above with regard toFIGS. 7-25 andFIGS. 26-43. Instep410, a

stack

200,380 of alternating active and insulating layers202 and204 is formed by forming first, second, third and fourth sub stacks252 each comprising active layers202 separated by insulating layers204. The active layers202 of each sub stack include an upper boundary active layer202.1. Atstep412, first, second and third sub

stack insulating layers

256,258 and260 are formed between the sub stacks252, at least two of which have etching times different from the etching time of the insulating layers204 of the sub stacks for a given etching process. The upper boundary active layers202.1 are accessed atstep414. After accessing the upper boundary active layers202.1, the other active layers202.2-202.4 are accessed atstep416 to create a stairstep structure such as shown inFIGS. 22 and 42. Atstep418,interlayer conductors272 are formed to extend to the

landing areas

310,358, the interlayer conductors separated from one another by insulating material.

FIG. 47 is a simplified block diagram of an integrated circuit. Theintegrated circuit975 includes a 3D NANDflash memory array960, having a structure like that ofFIG. 1, for example, on a semiconductor substrate with high density and narrow pitch global bit lines. Arow decoder961 is coupled to a plurality ofword lines962, and arranged along rows in thememory array960. Acolumn decoder963 is coupled to a plurality ofSSL lines964 arranged along columns corresponding to stacks in thememory array960 for reading and programming data from the memory cells in thearray960. Aplane decoder958 is coupled to a plurality of planes in thememory array960 via bit lines959. Addresses are supplied onbus965 tocolumn decoder963,row decoder961 andplane decoder958. Sense amplifiers and data-in structures inblock966 are coupled to thecolumn decoder963, in this example, viadata bus967. Data is supplied via the data-inline971 from input/output ports on theintegrated circuit975 or from other data sources internal or external to theintegrated circuit975, to the data-in structures inblock966. In the illustrated embodiment,other circuitry974 is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the NAND flash memory cell array. Data is supplied via the data-outline972 from the sense amplifiers inblock966 to input/output ports on theintegrated circuit975, or to other data destinations internal or external to theintegrated circuit975.

A controller implemented, in this example, using biasarrangement state machine969 controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies inblock968, such as read, erase, program, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.

In various embodiments, a 3D array of devices, for example, memory devices, is provided. The 3D array of devices includes a plurality of patterned layers of semiconductor material. Each patterned layer includes parallel strips of semiconductor material with one of their ends connected to a first side of a semiconductor pad. The semiconductor pads connected to the plurality of patterned layers are disposed in a stack. Each of the semiconductor pads includes a landing area for an interlayer conductor connected to an overlying interconnect conductor aligned along the parallel strips of semiconductor material. The interlayer conductors are arranged in rows in a top view and disposed in a via structure surrounded by an insulating material. Each of the rows is aligned along an X direction, parallel to the first side. In various embodiments, the interlayer conductors can be partially offset in a Y direction, perpendicular to the X direction. In various embodiments, the landing areas can be formed in various types of stair step arrangements, such as illustrated inFIG. 6 andFIG. 43.

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

Claims

What is claimed is:

1. A method for forming a stairstep contact structure comprising:

forming a stack of alternating active layers and insulating layers, comprising:

forming a first sub stack comprising N active layers separated by insulating layers, the N active layers comprising an upper boundary active layer;

forming a second sub stack over the first sub stack, the second sub stack comprising M active layers separated by insulating layers, the M active layers comprising an upper boundary active layer; and

forming a first sub stack insulating layer between the first and second sub stacks, the first sub stack insulating layer having an etching time different from the etching times of the insulating layers of the second sub stack for a given etching process;

accessing the upper boundary active layers;

following the upper boundary active layers accessing step, accessing the remainder of the active layers of the first and second sub stacks create a stairstep structure of landing areas on the active layers of the first and second sub stacks; and

forming interlayer conductors extending to the landing areas, the interlayer conductors separated from one another by insulating material.

2. The method according toclaim 1, wherein the stack forming step comprises:

forming a stack including first, second, third and fourth sub stacks;

forming a second sub stack insulating layer between the second and third sub stacks; and

forming a third sub stack insulating layer between the third and fourth sub stacks.

3. The method according toclaim 2, wherein each of the first, second, third and fourth sub stacks comprises the same number of active layers.

4. The method according toclaim 3, wherein:

the insulating layers of the first, second, third and fourth sub stacks have substantially equal thicknesses and are made of a first insulating material;

the first, second and third sub stack insulating layers are made of a second, third and fourth insulating materials; and

at least two of the first, second, third and fourth insulating materials are of different insulating materials having different etching characteristics.

5. The method according toclaim 3, wherein:

the insulating layers of each of the first, second, third and fourth sub stacks have substantially equal etching times for a given etch process; and

each of the first, second and third sub stack insulating layers having an etching time different from the etching times of the insulating layers of the first, second, third and fourth sub stacks for the given etch process.

6. The method according toclaim 5, where the etching times for the first and third sub stack insulating layers are substantially equal for the given etch process.

7. The method according toclaim 1, wherein:

the upper boundary active layers accessing step comprises:

in one or more etching steps, exposing a section of the upper boundary active layers of selected ones of the sub stacks; and

the remainder of the active layers accessing step comprising:

etching the exposed sections of the upper boundary active layers to expose active layers below the upper boundary active layers of the selected ones of the sub stacks;

covering the exposed active layers, including upper boundary active layers, with a material; and

etching vias through the material to expose active layers of the selected ones of the sub stacks.

8. The method according toclaim 7, wherein:

the one or more etching steps exposing sections of the upper boundary active layers creates a stairstep structure of said sections; and

the exposed sections etching step is carried out to create a stairstep structure of interlayer conductor contact areas on said active layers.

9. A method for forming a contact structure, comprising

forming a stack of alternating active layers and insulating layers, the stack including sub stacks having upper boundary active layers, the sub stacks having insulating layer and active layer pairs below the upper boundary active layer, said insulating layer and active layer pairs constituting first layer pairs, the first layer pairs have uniform first sub stack etch times for a given etch process, the stack also including second layer pairs, the second layer pairs including sub stack insulating layers between the sub stacks, the second layer pairs have second etch times for the given etch process different from the first sub stack etch times;

in one or more etching steps, etching a plurality of openings in the stack, the openings stopping on the boundary layer active layers;

etching to deepen selected openings to form vias that expose active layers inside each of the sub stacks; and

forming interlayer conductors:

in the vias, said interlayer conductors extending to the active layers; and

in the openings that were not etched during the etching to deepen step, said interlayer conductors extending to upper boundary active layers.

10. The method according toclaim 9, wherein the stack forming step comprises forming a stack including first, second and third sub stacks.

11. The method according toclaim 10, wherein each of the first, second and third sub stacks comprises the same number of first layer pairs.

12. The method according toclaim 10, wherein:

the insulating layers of the first, second and third sub stacks are made of a first insulating material;

the sub stack insulating layer between the first and second sub stacks is made of a second insulating material; and

the sub stack insulating layer between the second and third sub stacks is made of a third insulating material, at least two of the first, second and third insulating materials being different insulating materials having different etching characteristics.

13. The method according toclaim 9, wherein each sub stack comprises at least three first layer pairs.

14. The method according toclaim 9, further comprising:

forming sidewall insulation in the vias; and

forming sidewall insulation in the openings that were not etched during the etching to deepen step.

15. The method according toclaim 14, wherein the steps of forming interlayer conductors in the vias and in the opening that was not etched during the etching to deepen step are carried out substantially simultaneously.

16. A stairstep contact structure comprising:

a stack of alternating active layers and insulating layers having non-simple periods;

a stairstep structure of landing areas on the active layers; and

interlayer conductors extending to the landing areas, the interlayer conductors separated from one another by insulating material.

17. The stairstep contact structure according toclaim 16, wherein the stack of alternating active layers and insulating layers comprises:

a first sub stack comprising N active layers separated by insulating layers, the N active layers comprising an upper boundary active layer;

a second sub stack over the first sub stack, the second sub stack comprising M active layers separated by insulating layers, the M active layers comprising an upper boundary active layer; and

a first sub stack insulating layer between the first and second sub stacks, the first sub stack insulating layer having an etching time different from the etching times of the insulating layers of the second sub stack for a given etching process.

18. The stairstep contact structure according toclaim 17, wherein the stack comprises:

third and fourth sub stacks;

a second sub stack insulating layer between the second and third sub stacks;

a third sub stack insulating layer between the third and fourth sub stacks; and wherein:

19. The stairstep contact structure according toclaim 18, wherein:

20. The stairstep contact structure according toclaim 19, where the etching times for the first and third sub stack insulating layers are substantially equal for the given etch process.

21. The stairstep contact structure according toclaim 16, wherein for the same etch process at least one of (1) the active layers have different etch times, or (2) the insulating layers have different etch times.