US20150041993A1 - Method for manufacturing a chip arrangement, and a chip arrangement - Google Patents
Method for manufacturing a chip arrangement, and a chip arrangementDownload PDFInfo
- Publication number
- US20150041993A1 US20150041993A1US13/959,795US201313959795AUS2015041993A1US 20150041993 A1US20150041993 A1US 20150041993A1US 201313959795 AUS201313959795 AUS 201313959795AUS 2015041993 A1US2015041993 A1US 2015041993A1
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- US
- United States
- Prior art keywords
- chip
- stabilizing structure
- carrier
- contact
- electrically conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- Various embodimentsrelate to a method for manufacturing a chip arrangement, and a chip arrangement.
- Chip arrangementsfor example chip packages, may include at least one chip (or die) embedded in a material (e.g. an encapsulant). Electrical and/or thermal and/or mechanical properties of a chip arrangement may depend on a process with which the chip arrangement is manufactured. Some manufacturing processes may adversely affect the electrical and/or thermal and/or mechanical properties of a chip arrangement and/or the at least one chip included in the chip arrangement. New ways of manufacturing chip arrangements may be needed.
- a materiale.g. an encapsulant
- FIG. 1A to FIG. 1Gillustrate a conventional method for manufacturing a chip arrangement.
- FIG. 2shows a method for manufacturing a chip arrangement.
- FIG. 3A to FIG. 3Kshow a process-flow illustrating an example of the method shown in FIG. 2 .
- FIG. 4A and FIG. 4Bshow an example of a method for forming a bonding layer and a thru-opening.
- FIG. 5A and FIG. 5Bshow a carrier including at least one opening, which may be filled with material of a bonding layer of a stabilizing structure.
- FIG. 6A to FIG. 6Ishow a process-flow illustrating another example of the method shown in FIG. 2 .
- FIG. 7A to FIG. 7Kshow a process-flow illustrating yet another example of the method shown in FIG. 2 .
- FIG. 8A to FIG. 8Kshow a process-flow illustrating an example of the method shown in FIG. 2 applied to a manufacture of a three-dimensional chip arrangement.
- FIG. 9A to FIG. 9Cshow flow diagrams illustrating other examples of the method shown in FIG. 2 .
- FIG. 10shows a chip arrangement
- the word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface,may be used to mean that the feature, e.g. the layer, may be formed “directly on”, e.g. in direct contact with, the implied side or surface.
- the word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface,may be used to mean that the feature, e.g. the layer, may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.
- the word “cover”, used herein to describe a feature disposed over another, e.g. a layer “covering” a side or surface,may be used to mean that the feature, e.g. the layer, may be disposed over, and in direct contact with, the implied side or surface.
- the word “cover”, used herein to describe a feature disposed over another, e.g. a layer “covering” a side or surface,may be used to mean that the feature, e.g. the layer, may be disposed over, and in indirect contact with, the implied side or surface with one or more additional layers being arranged between the implied side or surface and the covering layer.
- Coupledand/or “electrically coupled” and/or “connected” and/or “electrically connected”, used herein to describe a feature being connected to at least one other implied feature, are not meant to mean that the feature and the at least one other implied feature must be directly coupled or connected together; intervening features may be provided between the feature and at least one other implied feature.
- Modem chip (or die) arrangementsmay include at least one chip (or die), which may be embedded in a material (e.g. an encapsulant).
- a materiale.g. an encapsulant
- FIG. 1A to FIG. 1Gillustrate a conventional method for manufacturing a chip arrangement.
- FIG. 1Ashows cross-sectional view 100 of a chip arrangement including a leadframe 102 and a chip 104 (or die).
- the chip 104(or die) may include a front-side 104 a and a back-side 104 b .
- a metallization layer 104 cmay be formed at the back-side 104 b of the chip 104 and at least one contact 104 d (e.g. a bonding pad) may be formed at the front-side 104 a of the chip 104 .
- the chip 104may be bonded to the leadframe 102 by means of a bonding process (indicated by arrows 100 a ), which may be performed at a temperature in the range from about 200° C. to about 350° C.
- a surface of the leadframe 102e.g. copper leadframe
- the front-side 104 a of the chip 104may be roughened (e.g. by means of a micro-etching process) in order to, for example, promote adhesion of subsequent layers that may be formed over the chip 104 and/or the leadframe 102 .
- the chip 104may be inspected (e.g. optically inspected) to determine a relative spatial shift between adjacent chips 104 (or dies) bonded to the leadframe 102 .
- the chip 104 on the left and the chip 104 on the rightmay be inspected (e.g. optically inspected) by an apparatus 103 a , and a relative position between the left chip 104 and the right chip 104 may be determined.
- a layup 105 amay be formed over the chip 104 and the leadframe 102 .
- the layup 105 amay include a structured prepreg layer 106 , an insulating layer 108 (e.g. a resin and/or an uncured prepreg) and a conductive layer 110 .
- the structured prepreg layer 106may be disposed over (e.g. disposed directly over) the leadframe 102 .
- the structured prepreg layer 106may be configured to occupy a gap between adjacent chips 104 bonded to the leadframe 102 . For example, as shown in FIG.
- the structured prepreg layer 106may occupy the gap between the chip 104 on the left and the chip 104 on the right. Additionally, the structured prepreg layer 106 may be configured to occupy a gap between a chip 104 and an edge of a leadframe 102 , as shown in FIG. 1D .
- the insulating layer 108may be disposed over the structured prepreg layer 106 , and the conductive layer 110 may be disposed over the insulating layer 108 , as shown in FIG. 1D .
- Heat and/or pressuremay be applied to the layup 105 a and the leadframe 102 to bond (e.g. by lamination) the structured prepreg 106 , the insulating layer (e.g. a resin) 108 and the conductive layer 110 to the leadframe 102 and the chip 104 .
- Bonding the layup 105 a(e.g. by lamination) may be performed over a plurality of leadframes 102 at one time. For example, in BLADE production, eight leadframes 102 may be laminated at one time, and each leadframe may be connected to another leadframe by means of a stencil that may be included in the layup 105 a.
- vias 112may be formed in the conductive layer 110 (e.g. by means of an etching process).
- the vias 112may be extended to expose a part of the leadframe 102 and/or a part of the chip 104 .
- the vias 112may be extended to expose at least one contact 104 c (e.g. a bonding pad) of the chip 104 .
- the vias 112may be extended by means of a drilling process, for example a laser drilling process.
- the vias 112may be filled with a conductive material 114 (e.g. copper or copper alloy or any other suitable metal or metal alloy such as e.g. tungsten).
- the conductive material 114may subsequently be structured (e.g. patterned), for example by means of etching.
- the conventional method for manufacturing a chip arrangement shown in FIG. 1A to FIG. 1Gmay suffer from undesirable effects.
- bonding the chip 104 to the leadframe 102e.g. a thick copper layer
- bonding the chip 104 to the leadframe 102may be performed at high temperatures (e.g. in the range from about 200° C. to about 350° C.).
- High bonding temperaturesmay cause warpage of the leadframe 102 .
- a thicker leadframe 102may reduce warpage caused by the high bonding temperatures, use of a thicker leadframe 102 may lead to a higher bill-of-materials (BOM).
- BOMbill-of-materials
- High bonding temperaturesmay result in a coefficient-of-thermal-expansion (CTE) mismatch between the chip 104 and the leadframe 102 . Accordingly, the chip arrangement manufactured using the method shown in FIG. 1A to FIG. 1G may suffer from high residual stress, which may affect the performance of the chip arrangement.
- CTEcoefficient-of-thermal-expansion
- High bonding temperaturesmay also result in a high risk of failure caused by copper silicides that may be produced during the bonding process.
- heat and/or pressuremay be applied to the layup 105 a and the leadframe 102 to bond (e.g. by lamination) the structured prepreg 106 , the insulating layer (e.g. a resin) 108 and the conductive layer 110 to the leadframe 102 and the chip 104 .
- Bonding the layup 105 ae.g. by lamination
- the leadframe 102upon which the chip 104 is bonded to, may have a small size (e.g. about 165 ⁇ 68 mm 2 ). As described above, a plurality of leadframes 102 may be connected to each other with stencil (e.g. additional PCB stencil) which may be included in the layup 105 a . This may lead to a complex layup structure, and a complex leadframe structure. The complex structure may result in poor aligning accuracy between the plurality of leadframes and may suffer from nonlinear dimension changes. For example, small changes in the dimension of a leadframe 102 and/or a chip 104 may lead to disproportionate changes in the dimensions of the stencil and/or layup 105 that may be formed over a plurality of leadframes 102 .
- stencile.g. additional PCB stencil
- FIG. 1A to FIG. 1Gillustrate one example of a conventional method for manufacturing a chip arrangement.
- the chip 104may be bonded to a foil (e.g. a copper foil) by means of a non-conductive adhesive and/or non-conductive paste.
- the front-side 104 a of the chip 104may face the leadframe 102 (which may include, or may be, a foil, e.g. copper foil).
- a local non-conductive adhesive and/or non-conductive pastemay be disposed between the front-side 104 a of the chip 104 and the leadframe 102 (e.g. foil, e.g. copper foil).
- Such a method for manufacturing a chip arrangementmay suffer from a high risk of having voids in the non-conductive adhesive and/or non-conductive paste. These voids may consequently lead to yield loss during a patterning process that may be performed, e.g. patterning an electrical connection to and/or at the front-side 104 a of the chip 104 . Furthermore, the voids may result in delamination of the chip 104 from the leadframe 102 (e.g. foil) and/or HAST (Highly Accelerated Stress Test) problems (e.g. due to trapped plating chemistry).
- the leadframe 102e.g. foil
- HASTHighly Accelerated Stress Test
- the voidsmay consequently lead to a loss of reliability of chip arrangements manufactured using such processes that may use a local non-conductive adhesive and/or non-conductive paste disposed between the front-side 104 a of the chip 104 and the leadframe 102 (e.g. foil, e.g. copper foil).
- a local non-conductive adhesive and/or non-conductive pastedisposed between the front-side 104 a of the chip 104 and the leadframe 102 (e.g. foil, e.g. copper foil).
- an eWLB (embedded wafer level ball grid array) processmay be used.
- wafer level processesmay be used to manufacture the chip arrangement.
- the chip 104may be disposed (e.g. over a carrier) such that the front-side 104 a of the chip 104 may face a carrier during the manufacturing process.
- an eWLB processmay not have the flexibility of placing the chip 104 in any other orientation (e.g. such that the back-side 104 b of the chip 104 may face the carrier).
- a method for manufacturing a chip arrangementis provided.
- One or more embodiments of the method for manufacturing the chip arrangementmay have at least one of the following effects and/or aspects:
- An aspect of one or more embodimentsmay be the use of simple PCB (printed circuit board) manufacturing processes and/or materials to manufacture a chip (or die) arrangement.
- An aspect of one or more embodimentsmay be the use of a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
- PCBprinted circuit board
- An aspect of one or more embodimentsmay be replacement of at least a part of a layup (e.g. the layup 105 a shown in FIG. 1D ) with a stabilizing structure that may not shrink during a lamination process.
- An effect of one or more embodimentsmay be prevention or substantially reduction of warping in at least a part of a leadframe.
- An effect of one or more embodimentsmay be prevention or substantial reduction of the formation of compounds (e.g. copper silicides) that may damage a chip.
- compoundse.g. copper silicides
- An effect of one or more embodimentsmay be prevention or substantial reduction of CTE mismatch and/or high residual stress.
- An effect of one or more embodimentsmay be manufacture of an interconnection (e.g. metallurgical interconnection) between a chip and a conductive layer in relatively low temperature.
- an interconnectione.g. metallurgical interconnection
- An effect of one or more embodimentsmay be prevention or substantial reduction of warpage in a conductive layer and/or a chip.
- An effect of one or more embodimentsmay be accurate alignment of a chip on a carrier, which may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
- a carrierwhich may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
- PCBprinted circuit board
- FIG. 2shows a method 200 for manufacturing a chip arrangement.
- the method 200may, for example, be used to manufacture an embedded chip (or die) arrangement.
- the method 200 for manufacturing the chip arrangementmay include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier (in 202 ); encapsulating the chip and the stabilizing structure by means of an encapsulating structure (in 204 ); and forming an electrically conductive connection to the at least one contact of the chip (in 206 ).
- An effect provided by the method 200may be prevention or substantially reduction of warping of at least a part of a leadframe.
- An effect provided by the method 200may be prevention or substantial reduction of the formation of compounds (e.g. copper silicides) that may damage a chip.
- compoundse.g. copper silicides
- An effect provided by the method 200may be prevention or substantial reduction of CTE mismatch and/or high residual stress.
- An effect provided by the method 200may be manufacture of an interconnection (e.g. metallurgical interconnection) between a chip and a conductive layer in relatively low temperature.
- an interconnectione.g. metallurgical interconnection
- An effect provided by the method 200may be prevention or substantial reduction of warpage in a conductive layer and/or a chip.
- An effect provided by the method 200may be accurate alignment of a chip on a carrier, which may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
- a carrierwhich may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
- PCBprinted circuit board
- FIG. 3A to FIG. 3Kshow a process-flow illustrating an example of the method 200 shown in FIG. 2 .
- FIG. 3A to FIG. 3Cshow that manufacturing a chip arrangement may include disposing a stabilizing structure 304 and a chip 306 next to each other and over a carrier 302 .
- the stabilizing structure 304may be disposed over the carrier 302 (e.g. as shown in FIG. 3B ), and the chip 306 may subsequently be disposed next to the stabilizing structure 304 and over the carrier 302 (e.g. as shown in FIG. 3C ). In other words, the stabilizing structure 304 may be disposed over the carrier 302 prior to the chip 306 (e.g. as shown in FIG. 3B and FIG. 3C ).
- the chip 306may be disposed over the carrier 302 , and the stabilizing structure 304 may subsequently be disposed next to the chip 306 and over the carrier 302 .
- the chip 306may be disposed over the carrier 302 prior to the stabilizing structure 304 (e.g. see description below in respect of FIG. 7B and FIG. 7C ).
- FIG. 3Ashows a cross-sectional view 300 of the carrier 302 .
- the carrier 302may include, or may consist of, a plate 302 a and an adhesive layer 302 b . As shown in FIG. 3A , the adhesive layer 302 b may be disposed over (e.g. disposed on) the plate 302 a .
- the adhesive layer 302 b of the carrier 302may, for example, be formed over the plate 302 a of the carrier 302 by means of a lamination process (e.g. vacuum lamination process) and/or a deposition process, although other processes may be possible as well.
- the carrier 302may include, or may be, a panel.
- the carrier 302e.g. the plate 302 a of the carrier 302
- the carrier 302may include, or may be, a panel measuring about 300 ⁇ 400 mm 2 that may be commonly used as a PCB (printed circuit board) material.
- the carrier 302e.g. the plate 302 a of the carrier 302
- the carrier 302may include, or may be, a panel that may have a large panel size (e.g. a panel measuring about 300 ⁇ 400 mm 2 or larger, for example about 500 ⁇ 600 mm 2 or larger, although other values may be possible as well).
- the carrier 302(e.g. the plate 302 a of the carrier 302 ) may be a large panel (e.g. measuring about 300 ⁇ 400 mm 2 ), the contraction and/or expansion of the carrier 302 may be more predictable over a whole panel area, as compared to, e.g., the leadframe 102 shown in FIG. 1A to FIG. 1G , which may be of a smaller size, e.g. 165 ⁇ 68 mm 2 .
- the carrier 302may include, or may consist of, a metal or metal alloy.
- the metalmay include at least one metal selected from a group of metals, the group consisting of: aluminium, iron, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well.
- the carrier 302e.g. the plate 302 a of the carrier 302
- the carrier 302may include, or may consist of, an alloy including, or consisting of, iron and at least one other element (e.g. carbon).
- the carrier 302e.g. the plate 302 a of the carrier 302
- the carrier 302may include, or may consist of, a non-conductive material.
- the carrier 302e.g. the adhesive layer 302 b of the carrier 302
- the carrier 302may include, or may consist of, a double-sided sticky tape with thermo-release properties (namely, elements and/or components may be separated and/or released from the double-sided sticky tape by means of heating and/or curing the double-sided sticky tape).
- the carrier 302may include at least one alignment mark 302 AL, which may be configured to align a structure and/or a component and/or a layer, which may be subsequently formed and/or disposed over the carrier 302 .
- FIG. 3Bshows a cross-sectional view 301 of a stabilizing structure 304 disposed over the carrier 302 .
- the stabilizing structure 304may be disposed over the carrier 302 by means of a lamination process (e.g. vacuum lamination process), although other processes may be possible as well.
- the stabilizing structure 304may be laminated to the adhesive layer 302 b of the carrier 302 .
- the stabilizing structure 304may include at least one alignment mark 304 AL, which may be configured to align the stabilizing structure 304 to the carrier 302 .
- the at least one alignment mark 304 AL of the stabilizing structure 304may be aligned to the at least one alignment mark 302 AL of the carrier 302 , thus aligning the stabilizing structure 304 to the carrier 302 .
- disposing the stabilizing structure 304 over the carriermay include aligning the stabilizing structure 304 to the carrier 302 , e.g. by means of the at least one alignment mark 304 AL of the stabilizing structure 304 and the at least one alignment mark 302 AL of the carrier 302 .
- the stabilizing structure 304may include a thru-opening 304 O (e.g. one or more thru-openings), which may be formed by means of at least one of a punching process, a routing process, a drilling process, an etching process (e.g. a wet and/or dry etch process), and a laser structuring process, although other processes may be possible as well.
- the thru-opening 304 Omay be formed prior to disposing the stabilizing structure 304 over the carrier 302 .
- the stabilizing structure 304may include a substrate layer 304 A and a bonding layer 304 BL disposed over the substrate layer 304 A.
- the bonding layer 304 BLmay be formed over the substrate layer 304 A by means of a lamination process (e.g. vacuum lamination process), although other processes may be possible as well.
- the bonding layer 304 BLmay be formed over the substrate layer 304 A prior to disposing the stabilizing structure 304 over the carrier 302 .
- the bonding layer 304 BL of the stabilizing structure 304may be configured to attach the substrate layer 304 A of the stabilizing structure 304 to the carrier 302 .
- disposing the stabilizing structure 304 over the carrier 302may include attaching the substrate layer 304 A of the stabilizing structure 304 to the carrier 302 (e.g. the adhesive layer 302 b of the carrier 302 ) by means of the bonding layer 304 BL of the stabilizing structure 304 , as shown in FIG. 3B .
- the bonding layer 304 BL of the stabilizing structure 304may be disposed between the substrate layer 304 A of the stabilizing structure 304 and the carrier 302 (e.g. the adhesive layer 302 b of the carrier 302 ), as shown in FIG. 3B .
- the bonding layer 304 BLmay include, or may be, a resin film (e.g. a B-stage resin film).
- the bonding layer 304 BLmay include, or may consist of, a material that may be used for laminating PCB layers together, although other materials may be possible as well.
- FIG. 4A and FIG. 4Bshow an example of a method for forming the bonding layer 304 BL and the thru-opening 304 O of the stabilizing structure 304 prior to disposing the stabilizing structure 304 over the carrier 302 .
- the bonding layer 304 BLmay be disposed over the substrate layer 304 A. As described above, the bonding layer 304 BL may be formed over the substrate layer 304 A by means of a lamination process.
- a thickness T1 of the bonding layer 304 BLmay depend on a material of the bonding layer 304 BL.
- the thickness T1 of the bonding layer 304 BLmay be in the range from about 5 ⁇ m to about 150 ⁇ m, e.g. in the range from about 10 ⁇ m to about 100 ⁇ m, e.g. in the range from about 20 ⁇ m to about 90 ⁇ m, e.g. in the range from about 20 ⁇ m to about 60 ⁇ m, e.g. in the range from about 20 ⁇ m to about 40 ⁇ m, e.g. about 30 ⁇ m.
- the thru-opening 304 O(e.g. at least one thru-opening) may be formed (e.g. through the substrate layer 304 A and the bonding layer 304 BL) subsequent to forming the bonding layer 304 BL over the substrate layer 304 A.
- the thru-opening 304 Omay be formed by means of at least one of a punching process, a routing process, a drilling process, an etching process (e.g. a wet and/or dry etch process), and a laser structuring process, although other processes may be possible as well.
- the thickness T1 of the bonding layer 304 BLmay be determined such that there may be at least enough material of the bonding layer 304 BL that may fill an opening (e.g. a cavity) of the carrier 302 , in case the carrier 302 includes an opening (e.g. cavity). This is illustrated by way of an example in FIG. 5A and FIG. 5B .
- FIG. 5A and FIG. 5Bshow the carrier 302 including at least one opening 302 O, which may be filled with material of the bonding layer 304 BL of the stabilizing structure 304 .
- the carrier 302(e.g. the plate 302 a of the carrier 302 ) may include at least one opening 302 O.
- FIG. 5Amay, for example, be a magnified view of a portion of the carrier 302 shown in FIG. 3A .
- the at least one opening 302 O of the carrier 302may be filled with the bonding layer 304 BL of the stabilizing structure 304 .
- FIG. 5Bmay, for example, be a magnified view of a portion of the carrier 302 and the bonding layer 304 BL of the stabilizing structure 304 shown in FIG. 3B .
- a first portion 304 BL- 1 of the bonding layer 304 BLmay fill the at least one opening 302 O of the carrier 302
- a second portion 304 BL- 2 of the bonding layer 304 BLmay be disposed over at least a part of a surface of the carrier 302 outside the at least one opening 302 O.
- the thickness T1 of the bonding layer 304 BLmay be determined such that there may be enough material to fill the at least one opening 302 O of the carrier and to line (e.g. coat) the part of the surface of the carrier 302 outside the at least one opening 302 O, as shown in FIG. 5B .
- the at least one opening 302 O of the carrier 302may be filled with material of the bonding layer 304 BL, without having to depend on material of a subsequent layer and/or structure (e.g. an encapsulating structure) to fill the at least one opening 302 O of the carrier 302 . Consequently, material of a subsequent layer and/or structure (e.g. encapsulating structure) may only need to fill at least a part of the thru-opening 304 O of the stabilizing structure 304 , without having to fill the at least one opening 302 O of the carrier 302 .
- material of a subsequent layer and/or structuree.g. encapsulating structure
- disposing the stabilizing structure 304 over the carrier 302may include disposing the stabilizing structure over the at least one opening 302 O of the carrier 302 , wherein the first portion 304 BL- 1 of the bonding layer 304 BL may fill the at least one opening 302 O of the carrier 302 , and wherein the a second portion 304 BL- 2 of the bonding layer 304 BL may be disposed over at least a part of the surface of the carrier 302 outside the at least one opening 302 O.
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may be configured to prevent or substantially reduce warpage in a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may be configured to prevent or substantially reduce CTE mismatch and/or high residual stress in a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may be configured to prevent or substantially reduce shrinkage in a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may be configured to cool a chip that may be included in a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304may include, or may consist of, a laminate material (e.g. a cured laminate material).
- the stabilizing structure 304e.g. the substrate layer 304 A of the stabilizing structure 304
- the stabilizing structure 304e.g. the substrate layer 304 A of the stabilizing structure 304
- the stabilizing structure 304 including, or consisting of, the laminate materialmay, for example, be configured to prevent or substantially reduce warpage and/or CTE mismatch and/or high residual stress and/or shrinkage in a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304 including, or consisting of, the laminate materialmay, for example, be configured to improve (e.g. optimize) mechanical properties of a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304may include at least one chip (or die) that may, for example, be embedded in the substrate layer 304 A of the stabilizing structure 304 .
- the at least one chip (or die)may, for example, be configured to operate in conjunction with a chip, which may be included in the stabilizing structure 304 (e.g. embedded in the substrate layer 304 A of the stabilizing structure) and/or which may be external to the stabilizing structure 304 .
- the stabilizing structure 304 including the at least one chip (or die)may, for example, be configured to improve (e.g. optimize) electrical properties of a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304may include at least one via (e.g. a through-via, e.g. a matrix of through-vias) that may, for example, be embedded in the substrate layer 304 A of the stabilizing structure 304 .
- the stabilizing structure 304 including the at least one viamay, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of method 200 .
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may include at least one electrically conductive layer (e.g. a copper layer), which may be suitable for routing and/or redistribution of electrical signals.
- at least one electrically conductive layere.g. a copper layer
- the stabilizing structure 304may include one electrically conductive layer
- the stabilizing structure 304e.g. the substrate layer 304 A of the stabilizing structure 304
- the stabilizing structure 304may include, or may be, a single layer RDL (redistribution layer).
- the stabilizing structure 304may include a plurality of electrically conductive layers
- the stabilizing structure 304may include, or may be, a multi-layer RDL.
- the stabilizing structure 304e.g. the substrate layer 304 A of the stabilizing structure 304
- the at least one viamay, for example, electrically connect a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers.
- at least two electrically conductive layers of the plurality of electrically conductive layersmay be electrically connected to each other.
- the stabilizing structure 304(e.g. the substrate layer 304 A of the stabilizing structure 304 ) may include, or may consist of, a polymer material (e.g. a polyimide material).
- the stabilizing structure 304 including, or consisting of, the polymer materialmay, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of the method 200 .
- the stabilizing structure 304 including, or consisting of, the polymer materialmay, for example, be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of method 200 .
- the stabilizing structure 304may include, or may consist of, a metal or metal alloy.
- the metalmay include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well.
- the stabilizing structure 304e.g. the substrate layer 304 A of the stabilizing structure 304
- the stabilizing structure 304 including, or consisting of, the metal or metal alloymay be configured to cool a chip that may be included in a chip arrangement manufactured by means of method 200 .
- the stabilizing structure 304 including, or consisting of, the metal or metal alloymay, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of method 200 .
- the stabilizing structure 304may include, or may consist of, a ceramic material.
- the stabilizing structure 304 including, or consisting of, the ceramic materialmay, for example, be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of method 200 .
- the stabilizing structure 304 including, or consisting of, the ceramic materialmay, for example, be configured to seal a chip that may be included in a chip arrangement manufactured by means of method 200 .
- the stabilizing structure 304 including, or consisting of, the ceramic materialmay, for example, be configured to optimize mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of method 200 .
- FIG. 3Cshows a cross-sectional view 303 of a chip 306 disposed next to the stabilizing structure 304 and over the carrier 302 .
- chips 306Only two chips 306 are shown as an example, however the number of chips may be less than two (e.g. one) or greater than two, and may, for example, be three, four, five, six, seven, eight, nine, or on the order of tens, or even more chips.
- the chip 306may, for example, be a chip used for MEMS and/or logic and/or memory and/or power applications, although chips used for other applications may be possible as well.
- chip 306may include a first side 306 a and a second side 306 b opposite the first side 306 a .
- the first side 306 a and the second side 306 b of the chip 306may include, or may be, a frontside and a backside of the chip 306 , respectively.
- the first side 306 a of the chip 306may include, or may be, an active side of the chip 306 .
- the chip 306may include at least one contact 306 c .
- the at least one contact 306 c of the chip 306may, for example, provide an interface (e.g. an electrical and/or thermal interface) for the chip 306 .
- signalse.g. electrical signals, power supply potentials, ground potentials, etc.
- heatmay be conducted away from the chip 306 by means of the at least one contact 306 c.
- the at least one contact 306 c of the chip 306may, for example, be disposed at the first side 306 a (e.g. active side), the second side 306 b (e.g. backside), or both.
- the at least one contact 306 cmay include, or may be, a metallization layer which may, for example, be disposed over the second side 306 b (backside) of the chip 306 .
- the at least one contact 306 cmay be disposed at the first side 306 a (e.g. active side) and the second side 306 b (e.g.
- the at least one contact 306 cmay be disposed at one of the first side 306 a and the second side 306 b of the chip 306
- the first side 306 a(e.g. active side) of the chip 306 may face the carrier 302 and/or may be in contact (e.g. physical contact) with the carrier 302 .
- Such an arrangement of the chip 306may, for example, be referred to as a face-down arrangement of the chip 306 .
- the second side 306 b(e.g. backside) of the chip 306 may face the carrier 302 and/or may be in contact (e.g. physical contact) with the carrier 302 (e.g. see description below in respect of FIG. 6C ).
- such an arrangement of the chip 306may be referred to as a face-up arrangement of the chip 306 .
- the chip 306may be disposed over the adhesive layer 302 b of the carrier 302 . Accordingly, disposing the stabilizing structure 304 and the chip 306 next to each other and over the carrier 302 may include disposing the stabilizing structure 304 and the chip 306 next to each other and over the adhesive layer 302 b of the carrier 302 .
- the stabilizing structure 304may include the at least one alignment mark 304 AL and the carrier 302 may include the at least one alignment mark 302 AL.
- disposing the chip 306 and the stabilizing structure 304 next to each other and over the carrier 302may include aligning the chip 306 to the stabilizing structure 304 by means of the at least one alignment mark 304 AL and/or the at least one alignment mark 302 AL, and disposing the chip 306 next to the stabilizing structure 304 and over the carrier 302 .
- the chip 306may be aligned (e.g. accurately aligned) by means of the at least one alignment mark 304 AL of the stabilizing structure 304 and/or the at least one alignment mark 302 AL of the carrier 302 .
- each of the one or more chips 306may be mounted on a large carrier 302 (e.g. 300 ⁇ 400 mm 2 ) and aligned using same aligning marks (e.g. of the stabilizing structure 304 and/or the carrier 302 ). Accordingly, the aligning accuracy may be good all over an entire area of the carrier 302 (e.g. the whole panel area).
- FIG. 3A to FIG. 3Cshow an example in which the stabilizing structure 304 may be disposed over the carrier 302 (e.g. as shown in FIG. 3B ), and the chip 306 may subsequently be disposed next to the stabilizing structure 304 and over the carrier 302 (e.g. as shown in FIG. 3C ).
- the chip 306may be disposed over the carrier 302
- the stabilizing structure 304may subsequently be disposed next to the chip 306 and over the carrier 302 .
- the chip 306may be aligned to the carrier 302 by means of the at least one alignment mark 302 AL of the carrier 302 .
- the stabilizing structure 304may subsequently be aligned to the chip 306 and/or the carrier 302 by means of the at least one alignment mark 302 AL of the carrier 302 and/or the at least one alignment mark 304 AL of the stabilizing structure 304 .
- the stabilizing structure 304may include the thru-opening 304 O.
- disposing the chip 306 and the stabilizing structure 304 next to each other and over the carrier 302may include disposing the chip 306 within the thru-opening 304 O of the stabilizing structure 304 and over the carrier 302 , as shown in FIG. 3C .
- FIG. 3A to FIG. 3Cmay, for example, be identified with “disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier” disclosed in 202 of method 200 .
- FIG. 3D and FIG. 3Eshow cross-sectional views 305 and 307 of the chip 306 and the stabilizing structure 304 encapsulated by means of an encapsulating structure 308 .
- FIG. 3D and FIG. 3Emay, for example, be identified with “encapsulating the chip and the stabilizing structure by means of an encapsulating structure” disclosed in 204 of method 200 .
- encapsulating the chip 306 and the stabilizing structure 304may include laying-up the encapsulating structure 308 over the chip 306 , the stabilizing structure 304 , and the carrier 302 .
- the encapsulating structure 308may include an insulating layer 308 a .
- the encapsulating structure 308 shown in FIG. 3Dmay additionally include a conductive layer 308 b .
- the encapsulating structure 308may include the insulating layer 308 a only. As illustrated in the example shown in FIG. 3D , the insulating layer 308 a may be disposed between the chip 306 and the conductive layer 308 b.
- the encapsulating structure 308(e.g. the insulating layer 308 a of the encapsulating structure 308 ) may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material (e.g. an uncured laminate material), although other materials may be possible as well.
- the encapsulating structure 308may include, or may consist of, an electrically conductive material and/or a thermally conductive material.
- the encapsulating structure 308e.g. the conductive layer 308 b of the encapsulating structure 308
- the metalmay include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well.
- the encapsulating structure 308e.g. the conductive layer 308 b of the encapsulating structure 308
- the at least one contact 306 cmay be disposed at the first side 306 a (e.g. active side) and/or the second side 306 b (e.g. backside) of the chip 306 .
- the conductive layer 308 b of the encapsulating structure 308may be suitable for forming a subsequent electrical and/or thermal connection with the stabilizing structure 304 and/or the chip 306 .
- the conductive layer 308 b of the encapsulating structure 308may be at least a part of an electrical and/or thermal connection to the at least one contact 306 c disposed at the second side 306 b of the chip 306 .
- encapsulating the chip 306 and the stabilizing structure 304 by means of the encapsulating structure 308may include applying heat and pressure (indicated by arrows 310 ) to fuse the encapsulating structure 308 , the chip 306 , and the stabilizing structure 304 together. Applying heat and pressure (indicated by arrows 310 ) may include, or may be, a lamination process. In other words, encapsulating the chip 306 and the stabilizing structure 304 by means of the encapsulating structure 308 may include, or may consist of, a lamination process.
- the applied heat and/or pressuremay soften (e.g. melt) the encapsulating structure 308 (e.g. the insulating layer 308 a of the encapsulating structure 308 ) such that the encapsulating structure 308 (e.g. the insulating layer 308 a of the encapsulating structure 308 ) flows into and fills the thru-opening 304 O of the stabilizing structure 304 . At least a portion of the encapsulating structure 308 (e.g.
- the insulating layer 308 a and/or the conductive layer 308 b of the encapsulating structure 308may be additionally disposed over the chip 306 and the stabilizing structure 304 after the application of heat and/or pressure, as shown in FIG. 3E .
- FIG. 3F to FIG. 3Kshow cross-sectional views illustrating the forming of at least one electrically conductive connection to the at least one contact 306 c of the chip 306 .
- FIG. 3F to FIG. 3Kmay, for example, be identified with “forming an electrically conductive connection to the at least one contact of the chip” disclosed in 206 of method 200 .
- forming the at least one electrically conductive connection to the at least one contact 306 c of the chip 306may include removing the carrier 302 e.g. to expose the at least one contact 306 c of the chip 306 .
- the at least one contact 306 c of the chip 306may be visible and/or exposed with the removal of the carrier 302 .
- the at least one contact 306 c disposed at the first side 306 a (e.g. active side) of the chip 306may be visible and/or exposed by the removal of the carrier 302 .
- the bonding layer 304 BLmay be removed with the carrier 302 (e.g. by means of at least one of dissolving, peeling off, and curing).
- the carrier 302may include the plate 302 a and the adhesive layer 302 b . Accordingly, removing the carrier 302 may include removing the plate 302 a and the adhesive layer 302 b of the carrier 302 , e.g. to expose the at least one contact 306 c of the chip 306 . Removing the adhesive layer 302 b of the carrier 302 may include at least one of dissolving the adhesive layer 302 b (e.g. by means of a solvent), peeling off the adhesive layer 302 b , and curing the adhesive layer 302 b .
- the carrier 302e.g.
- the adhesive layer 302 b of the carrier 302may include, or may consist of, a double-sided sticky tape with thermo-release properties (namely, elements may be separated and/or released from the double-sided sticky tape by means of heating and/or curing the double-sided sticky tape).
- the adhesive layer 302 bmay be cured, thus separating the chip 306 and the stabilizing structure 304 from the carrier 302 .
- the stabilizing structure 304 and the chip 306may be held in place by means of the encapsulating structure 308 (e.g. the insulating layer 308 a of the encapsulating structure 308 ).
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include disposing a second conductive layer 312 b over the at least one contact 306 c of the chip 306 (e.g. the at least one exposed contact 306 c of the chip 306 ).
- the second conductive layer 312 bmay be disposed over the at least one contact 306 c disposed at the first side 306 a of the chip 306 , which may be exposed and/or visible (e.g. due to the removal of the carrier 302 ). Since the stabilizing structure 304 is disposed next to the chip 306 , the second conductive layer 312 b may be disposed over the stabilizing structure 304 as well.
- the second conductive layer 312 bmay include, or may consist of, an electrically conductive material and/or a thermally conductive material.
- the second conductive layer 312 bmay include, or may consist of, a metal or metal alloy.
- the metalmay include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well.
- the second conductive layer 312 bmay include, or may consist of, copper or a copper alloy.
- disposing the second conductive layer 312 b over the at least one contact 306 c of the chip 306may include disposing a second insulating layer 312 a between the second conductive layer 312 b and the at least one contact 306 c of the chip 306 (e.g. the exposed contact of the chip, e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ).
- the second insulating layer 312 amay include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material (e.g. an uncured laminate material), although other materials may be possible as well.
- the at least one contact 306 cmay be disposed at the first side 306 a (e.g. active side) and/or the second side 306 b (e.g. backside) of the chip 306 .
- the second conductive layer 312 bmay be suitable for forming the electrically conductive connection with the stabilizing structure 304 and/or the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ).
- disposing the second conductive layer 312 b over the at least one contact 306 c of the chip 306may include applying heat and pressure (indicated by arrows 314 ) to fuse the second conductive layer 312 b , the second insulating layer 312 a , the encapsulating structure 308 , the chip 306 , and the stabilizing structure 304 together.
- Applying heat and pressuremay include, or may be, a lamination process.
- disposing the second conductive layer 312 b over the at least one contact 306 c of the chip 306may include, or may consist of, a lamination process.
- a distance D between the at least one contact 306 c of the chip 306 (e.g. the at least one exposed contact 306 c of the chip 306 c ) and the second conducting layer 312 bmay be at least substantially equal over a lateral extent of the chip arrangement shown in FIG. 3H .
- the distance Dmay be easily controlled by controlling a thickness of the second insulating layer 312 a.
- an electrically conductive connectionmay be formed with the at least one contact 306 c of the chip 306 .
- the at least one contact 306 c of the chip 306 shown in FIG. 3C to FIG. 3Kmay be disposed at the first side 306 a and the second side 306 b of the chip 306 .
- the electrically conductive connectionmay be formed with the first side 306 a and the second side 306 b of the chip 306 .
- the electrically conductive connectionmay be formed to the first side 306 a or the second side 306 b of the chip 306 , depending on where the at least one contact 306 c of the chip 306 may be disposed.
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include forming at least one opening 316 in the encapsulating structure 308 to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the second side 306 b of the chip 306 ).
- the at least one opening 316may be formed in the conductive layer 308 b of the encapsulating structure 308 , as shown in FIG. 3I .
- the at least one opening 316may be formed in the encapsulating structure 308 by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process).
- the at least one opening 316may be subsequently deepened (e.g. extended through the insulating layer 308 a of the encapsulating structure 308 ) to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the second side 306 b of the chip 306 ), as shown in FIG. 3J .
- the at least one opening 316may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process).
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include forming at least one opening 318 in the second conductive layer 312 b and the second insulating layer 312 a to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ).
- the at least one opening 318may be formed in the second conductive layer 312 b , as shown in FIG. 3I .
- the at least one opening 318may be formed in the second conductive layer 312 b by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process).
- an etching processe.g. a micro-etching process, e.g. a micro-via etching process
- a drilling processe.g. a micro-drilling process
- the at least one opening 318may be subsequently deepened (e.g. extended through the second insulating layer 312 a ) to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ), as shown in FIG. 3J .
- the at least one opening 318may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process).
- At least one opening 323may be formed to expose at least a part of the stabilizing structure 304 .
- the at least one opening 323may be formed and/or deepened by means of similar processes used in relation to the at least one opening 316 and the at least one opening 318 . In another example, however, there may not be an opening that may expose at least a part of the stabilizing structure 304 .
- Forming the at least one opening 316 and/or 318 and/or 323may include using the at least one alignment mark 304 AL of the stabilizing structure, which may improve accuracy and/or precision of the etching process and/or micro-via cleaning and/or drilling process.
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include a plating process (indicated by arrows 320 ).
- a seed metal or seed metal alloye.g. seed copper
- the plating processmay, for example, fill the at least one opening 316 , 318 and/or 323 with an electrically conductive material.
- the electrically conductive connection between the second conductive layer 312 b and the at least one contact 306 c of the chip 306may be formed by means of the plating process (indicated by arrows 320 ).
- the electrically conductive connection between the conductive layer 308 b of the encapsulating structure 308 and the at least one contact 306 c of the chip 306may be formed by means of the plating process (indicated by arrows 320 ).
- an electrically conductive connectionmay also be formed between the conductive layer 308 b of the encapsulating structure 308 and the stabilizing structure 304 by means of the plating process (indicated by arrows 320 ).
- the plating process (indicated by arrows 320 ) for forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include an electroless plating process or an electrochemical plating process or a direct metallization process.
- Forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include patterning the conductive layer 308 a of the encapsulating structure 308 and/or the second conductive layer 312 b , e.g. subsequent to the plating process shown in FIG. 3K .
- Patterning the conductive layer 308 a of the encapsulating structure 308 and/or the second conductive layer 312 bmay include, or may consist of, an etching process (e.g. a dry and/or wet etch process).
- the patterning processmay, for example, make use of at least one alignment mark, which may improve accuracy and/or precision of the patterning process.
- the at least one alignment markmay, for example, be disposed at the conductive layer 308 b and/or the second conductive layer 312 b .
- This alignment markmay, for example, be formed by means of reproducing the at least one alignment mark 304 AL of the stabilizing structure 304 and/or the at least one alignment mark 302 AL of the carrier 302 , e.g. prior to the removal of the carrier 302 .
- the patterning processmay be performed subsequent to the plating process shown in FIG. 3K .
- the at least one opening 316 and/or 318 and/or 323may be filled with electrically conductive material by means of a structured deposition process and/or a selective plating process.
- a patterned resist materiale.g. a photo-resist material
- a plating processmay be performed, which may form the electrically conductive connection to the at least one contact 306 c of the chip 306 .
- the electrically conductive connectionmay be formed (e.g. by means of selective deposition and/or selective plating) over a part of the chip 306 and/or the stabilizing structure 304 that is not covered by the patterned resist material.
- FIG. 6A to FIG. 6Ishow a process-flow illustrating another example of the method 200 shown in FIG. 2 .
- FIG. 6A to FIG. 6Ithat are the same as in FIG. 3A to FIG. 3K denote the same or similar elements as in FIG. 3A to FIG. 3K . Thus, those elements will not be described in detail again here; reference is made to the description above. Differences between FIG. 6A to FIG. 6I and FIG. 3A to FIG. 3K are described below.
- the chip 306may be arranged in a face-up arrangement.
- the second side 306 be.g. backside
- the chip 306may face and/or may be in contact (e.g. physical contact) with the carrier 302 .
- forming the at least one electrically conductive connection to the at least one contact 306 c of the chip 306may include removing the carrier 302 e.g. to expose the at least one contact 306 c of the chip 306 .
- the at least one contact 306 c disposed at the second side 306 b (e.g. backside) of the chip 306may be exposed with the removal of the carrier 302 .
- the at least one contact 306 c disposed at the second side 306 b (e.g. backside) of the chip 306may include, or may be, a metallization layer. Accordingly, in the example shown in FIG. 6F , the metallization layer of the chip 306 may be exposed with the removal of the carrier 302 .
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include forming at least one opening 316 in the encapsulating structure 308 to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ).
- the at least one opening 316may be formed in the conductive layer 308 b of the encapsulating structure 308 , as shown in FIG. 6G .
- the at least one opening 316may be formed in the encapsulating structure 308 by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process).
- the at least one opening 316may be subsequently deepened (e.g. extended through the insulating layer 308 a of the encapsulating structure 308 ) to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ), as shown in FIG. 6H .
- the at least one opening 316may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process).
- the at least one opening 323may be formed to expose at least a part of the stabilizing structure 304 .
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include the plating process (indicated by arrows 320 ).
- the electrically conductive connection between the conductive layer 308 b of the encapsulating structure 308 and the at least one contact 306 c of the chip 306e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306
- the electrically conductive connection to the at least one contact 306 c disposed at the second side 306 b of the chip 306may be formed by means of the plating process (indicated by arrows 320 ).
- the plating process (indicated by arrows 320 ) for forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include an electroless plating process or an electrochemical plating process or a direct metallization process.
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include patterning the plated electrically conductive connection.
- the features of the patterning process described abovemay be analogously applicable to the example shown in FIG. 6A to FIG. 6I .
- FIG. 7A to FIG. 7Kshow a process-flow illustrating yet another example of the method 200 shown in FIG. 2 .
- FIG. 7A to FIG. 7Kthat are the same as in FIG. 3A to FIG. 3K denote the same or similar elements as in FIG. 3A to FIG. 3K . Thus, those elements will not be described in detail again here; reference is made to the description above. Differences between FIG. 7A to FIG. 7K and FIG. 3A to FIG. 3K are described below.
- the chip arrangementmay include a plurality of chips 306 .
- At least one chip 306may be arranged in a face-up arrangement (namely, the second side 306 b may face and/or be in contact (e.g. physical contact) with the carrier 302 ), and at least one other chip 306 may be arranged in a face-down arrangement (namely, the first side 306 a may face and/or be in contact (e.g. physical contact) with the carrier 302 ).
- the chip 306may be disposed over the carrier 302 prior to the stabilizing structure 304 .
- the at least one alignment mark 302 AL of the carriermay be used to align the chip 306 to the carrier 302 .
- the stabilizing structure 304may be disposed subsequent to disposing the chip 306 .
- the least one alignment mark 302 AL of the carriermay be used to align the stabilizing structure 304 .
- the at least one alignment mark 304 AL of the stabilizing structure 304 and the at least one alignment mark 302 AL of the carrier 302may be used to align the stabilizing structure 304 .
- FIG. 7D to FIG. 7Kshow a process-flow, which may be performed using processes described above in respect of FIG. 3D to FIG. 3K .
- FIG. 8A to FIG. 8Kshow a process-flow illustrating an example of the method 200 shown in FIG. 2 applied to a manufacture of a three-dimensional (3D) chip arrangement.
- FIG. 8A to FIG. 8Kthat are the same as in FIG. 7A to FIG. 7K denote the same or similar elements as in FIG. 7A to FIG. 7K . Thus, those elements will not be described in detail again here; reference is made to the description above. Differences between FIG. 8A to FIG. 8K and FIG. 7A to FIG. 7K are described below.
- a first module 802may be arranged over a second module 804 .
- a third insulating layer 806may be disposed between the first module 802 and the second module 804 .
- the first and second modules 802 , 804may each include, or may be, the chip arrangement shown in FIG. 8E . Namely, each of the first and second modules 802 , 804 may include the carrier 302 , the chip 306 , the stabilizing structure 304 , and the encapsulating structure 308 (e.g. which may include the insulating layer 308 a , and which may be free from the conducting layer 308 b ).
- the first module 802 , the second module 804 , and the third insulating layer 806may be disposed over a workpiece 808 .
- the first module 802 , the second module 804 , and the third insulating layer 806may be aligned to each other by means of the at least one alignment mark 302 AL of the carrier 302 of the first module 802 and/or the second module 804 .
- the first module 802 , the second module 804 , and the third insulating layer 806may be pressed together (indicated by arrows 812 ) to form a 3D chip arrangement.
- the respective carriers of the first and second modules 802 , 804may be removed to expose the at least one contact 306 c of the chip 306 of the first module 802 and the second module 804 .
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include disposing the second conductive layer 312 b over the at least one contact 306 c of the chip 306 of the first and second modules 802 , 804 .
- the second conductive layer 312 bmay be disposed over the at least one contact 306 c disposed at the first side 306 a of the chip 306 of the first and second modules 802 , 804 .
- FIG. 8Iforming the electrically conductive connection to the at least one contact 306 c of the chip 306 may include disposing the second conductive layer 312 b over the at least one contact 306 c of the chip 306 of the first and second modules 802 , 804 .
- disposing the second conductive layer 312 b over the at least one contact 306 c of the chip 306may include disposing the second insulating layer 312 a between the second conductive layer 312 b and the at least one contact 306 c of the chip 306 .
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include forming at least one opening 318 in the second conductive layer 312 b and the second insulating layer 312 a to expose the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ).
- the at least one opening 318may be formed and/or deepened by means of the processes described above in respect of FIG. 3I and FIG. 3J .
- Forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include forming at least one through-via 814 in the 3D chip arrangement.
- the at least one through-via 814may be formed by means of similar or identical processes as those described above in respect of the at least one opening 316 , 318 and/or 323 .
- forming the electrically conductive connection to the at least one contact 306 c of the chip 306may include a plating process (indicated by arrows 320 ).
- the electrically conductive connection between the conductive layer 308 b of the encapsulating structure 308 and the at least one contact 306 c of the chip 306e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306
- the plating process(indicated by arrows 320 ) may line the at least one through-via 814 and/or fill the at least one opening 318 with an electrically conductive material.
- the plated electrically conductive connectionmay be patterned, as described above in relation to FIG. 3K .
- a conventional method for manufacturing a chip arrangementmay include embedding a chip inside a prepreg, and may include bonding chips that may be disposed face-down on a copper foil with non-conductive adhesives.
- the method 200may avoid the disadvantages of such a conventional method (e.g. HAST problems, delamination, etc.) since the second insulating layer 312 a between the second conductive layer 312 b and the at least one contact 306 c of the chip 306 (e.g. the at least one contact 306 c disposed at the first side 306 a of the chip 306 ) is formed after using vacuum lamination.
- a conventional method for manufacturing a chip arrangementmay include an eWLB manufacturing process.
- the method 200may allow manufacturing double sided arrangements where the chip 306 may be arranged in a face-up and/or face-down arrangement.
- the method 200may allow the forming of a plated electrical connection with the first side 306 a and/or the second side 306 b of the chip 306 .
- the method 200may allow the forming of an electrical connection with the second side 306 b (e.g. backside) of the chip 306 by means of a plating process.
- the method 200may allow the use of standard PCB material (e.g. standard reinforced PCB material), large panel size and low cost PCB manufacturing processes, instead of wafer level processes. This may be easy to incorporate and/or include in a standard PCB production.
- standard PCB materiale.g. standard reinforced PCB material
- large panel size and low cost PCB manufacturing processesinstead of wafer level processes. This may be easy to incorporate and/or include in a standard PCB production.
- a conventional method for manufacturing a chip arrangementmay include the example shown in FIG. 1A to FIG. 1G .
- the method 200may allow manufacturing double sided arrangements where the chip 306 may be arranged in a face-up and/or face-down arrangement.
- the method 200may allow the forming of a plated electrical connection with the first side 306 a and/or the second side 306 b of the chip 306 .
- the method 200may allow the forming of an electrical connection with the second side 306 b (e.g. backside) of the chip 306 by means of a plating process.
- the chip 306may be aligned to the carrier 302 that may have a large size (e.g. same size as a production panel) using the at least one alignment mark 302 AL of the carrier 302 .
- the method 200may provide accurate alignment of the chip 306 to the carrier 302 . Since a plurality of leadframes 102 may not be needed compared with the example shown in FIG. 1A to FIG. 1G , an effect of the method 200 may be reduction or prevention of additional tolerances between a plurality of leadframes 102 (which may also be referred to as sub-panels).
- the chip 306may be disposed in a face-down arrangement.
- a distance between the at least one contact 306 c of the chip 306 and the second conducting layer 312 bmay be at least substantially equal over a lateral extent of the chip arrangement.
- the distancemay be easily controlled by controlling a thickness of the second insulating layer 312 a . This may allow for easier forming of the at least one opening 316 , 318 , and 323 .
- the method 200may allow arrangement of the chip 306 in a face-up or face-down arrangement, or both, and forming of an electrically conductive connection to the chip 306 from the first side 306 a and/or the second side 306 b , thus enabling a manufacture of a 3D chip arrangement.
- FIG. 9A to FIG. 9Cshow flow diagrams illustrating other examples of the method 200 shown in FIG. 2 .
- the flow diagram 900 shown in FIG. 9Ashows a process 902 , which may, for example, be identified with the process shown in FIG. 4A and FIG. 4B .
- the process 904 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the process shown in FIG. 6B .
- the process 906 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the process shown in FIG. 6C .
- the process 908 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the process shown in FIG. 6D .
- the process 910 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the process shown in FIG. 6E .
- the process 912 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the process shown in FIG. 6F .
- the process 914 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the processes shown in FIG. 6G and FIG. 6H .
- the process 916 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the seed metal or seed metal alloy (e.g. seed copper) described above, which may be sputtered prior to or as part of the plating process (indicated by arrows 320 ).
- seed metal or seed metal alloye.g. seed copper
- the process 918 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the process shown in FIG. 6I .
- the process 920 shown in the flow diagram 900 of FIG. 9Amay, for example, be identified with the patterning process described above.
- the flow diagram 901 shown in FIG. 9Bshows a process 901 , which may, for example, be identified with the process shown in FIG. 4A and FIG. 4B .
- the process 922 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the process shown in FIG. 7B .
- the process 924 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the processes shown in FIG. 7C and FIG. 7D .
- the process 926 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the process shown in FIG. 7E .
- the process 928 shown in the flow diagram 901 of FIG. 9Bmay, for example, indicate that the at least one alignment mark 302 AL of the carrier 302 and/or the at least one alignment mark 304 AL of the stabilizing structure 304 may be reproduced at (e.g. reproduced over a surface of) the encapsulating structure 308 .
- the process 930 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the process shown in FIG. 7F .
- the process 932 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the processes shown in FIG. 7G and FIG. 7H .
- the process 934 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the processes shown in FIG. 7I and FIG. 7J .
- the process 936 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the process shown in FIG. 7K .
- the process 938 shown in the flow diagram 901 of FIG. 9Bmay, for example, be identified with the patterning process described above.
- the flow diagram 903 shown in FIG. 9Cshows a process 902 , which may, for example, be identified with the process shown in FIG. 4A and FIG. 4B .
- the process 940 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the process shown in FIG. 3B .
- the process 942 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the process shown in FIG. 3C .
- the process 944 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the process shown in FIG. 3D .
- the process 946 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the process shown in FIG. 3E .
- the process 948 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the process shown in FIG. 3F .
- the process 950 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the processes shown in FIG. 3G and FIG. 3H .
- the process 952 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the processes shown in FIG. 3I and FIG. 3J .
- the process 954 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the process shown in FIG. 3K .
- the process 956 shown in the flow diagram 903 of FIG. 9Cmay, for example, be identified with the patterning process described above.
- FIG. 10shows a chip arrangement 1000 .
- FIG. 10that are the same as in FIG. 3A to FIG. 3K denote the same or similar elements as in FIG. 3A to FIG. 3K . Thus, those elements will not be described in detail again here; reference is made to the description above.
- the chip arrangement 1000may, for example, be manufactured by means of the method 200 shown in FIG. 2 .
- the chip arrangement 1000may include: a chip 306 , a stabilizing structure 304 disposed next to the chip 306 ; and an encapsulating structure 308 encapsulating the chip 306 and the stabilizing structure 304 .
- a chip arrangementmay be manufactured using large panel sizes and standard PCB materials and/or processes.
- a chipmay be bonded to a temporary thermal release tape of a carrier in a face-up and/or face-down arrangement.
- an insulating layermay be manufactured with standard PCB prepreg foils or prepregs and laminates. The insulating layer may be laminated over the chip bonded to the temporary release tape e.g. by means of a lamination process.
- the carrier and the release tapemay be removed and the whole top or bottom side of the chip may be visible.
- an insulation layermay be laminated over of the chip, and microvias may be manufactured on both side of the panel to contact the chip to conductor layers that may be laminated on the chip.
- Plating and patterningmay be performed either with direct metallization and subtractive process or normal pattern plating process (e.g. standard PCB processes). Because the process uses standard low cost, high volume PCB materials and manufacturing equipment, the manufacturing process may be low cost and can be performed on large panels.
- the manufacturing processmay allow exposure of the whole front side and/or or backside of the chip. Furthermore, a distance between a side of the chip and a conducting layer (e.g. copper surface) can be accurately fixed and manufactured without any voids.
- a conducting layere.g. copper surface
- PCB laminatecured FR4
- the warpage of the chip arrangementis smaller. Furthermore, dimensional stability of the chip arrangement may be improved (e.g. since cured laminate has remarkable smaller shrinkage than prepreg).
- This PCB laminatecan also be patterned (conductors and vias) to improve the routing capability.
- a foile.g. copper foil
- thick carriere.g. aluminium or copper
- the manufacture of at least one thru-opening of the stabilizing structuremay be easier and cheaper because instead of slow and expensive laser cutting, a routing or punching process can be used. This may also reduce a potential risk caused by the carbon that may be formed on the prepregs during laser cutting.
- the properties of this core layercan also be selected to suit for application (e.g. low CTE, ultralow CTE).
- a method for manufacturing a chip arrangementmay be provided.
- the methodmay include disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip.
- the stabilizing structuremay include, or may consist of, at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.
- the laminate materialmay include, or may consist of, a cured laminate material.
- the stabilizing structuremay include at least one electrically conductive layer.
- the at least one electrically conductive layermay include a plurality of electrically conductive layers
- the stabilizing structuremay include at least one via extending through at least a portion of the stabilizing structure and electrically connecting a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers.
- the stabilizing structuremay include a bonding layer configured to attach the stabilizing structure to the carrier, wherein disposing the stabilizing structure and the chip may include the at least one contact next to each other and over the carrier may include attaching the stabilizing structure to the carrier by means of the bonding layer.
- a thickness of the bonding layer of the stabilizing structuremay be in the range from about 5 ⁇ m to about 150 ⁇ m.
- the carriermay include at least one opening, wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier includes disposing the stabilizing structure over the at least one opening of the carrier, wherein a first portion of the bonding layer fills the at least one opening of the carrier, and wherein a second portion of the bonding layer is disposed over at least a part of a surface of the carrier outside the at least one opening.
- Encapsulating the chip and the stabilizing structuremay include a lamination process.
- the encapsulating structuremay include, or may consist of, at least one of a molding material, a prepreg material, a resin material, a laminate material, an electrically conductive material, and a thermally conductive material.
- the laminate materialmay include, or may consist of, an uncured laminate material.
- the stabilizing structuremay include a thru-opening, wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include disposing the chip within the thru-opening of the stabilizing structure and over the carrier.
- the thru-openingmay be formed by means of at least one of a punching process, a routing process, a drilling, an etching process, and a laser structuring process.
- the chipmay include a first side facing the carrier and a second side opposite the first side, and wherein the at least one contact of the chip is disposed at the first side of the chip or the second side of the chip, or both.
- Forming the electrically conductive connection to the at least one contact of the chipmay include forming at least one opening in the encapsulating structure to expose the at least one contact of the chip.
- Forming the electrically conductive connection to the at least one contact of the chipmay include removing the carrier to expose the at least one contact of the chip.
- Forming the electrically conductive connection to the at least one contact of the chipmay include a plating process.
- Forming the electrically conductive connection to the at least one contact of the chipmay include: disposing a conductive layer over the at least one contact of the chip; forming the electrically conductive connection between the conductive layer and the at least one contact of the chip; and patterning the conductive layer.
- Patterning the conductive layermay include an etching process.
- Forming the electrically conductive connection between the conductive layer and the at least one contact of the chipmay include a plating process.
- Disposing the conductive layer over the at least one contact of the chipmay include a lamination process.
- Disposing the conductive layer over the at least one contact of the chipmay include: disposing an insulating layer between the conductive layer and the at least one contact of the chip.
- Forming the electrically conductive connection between the conductive layer and the at least one contact of the chipmay include forming at least one opening in the conductive layer and the insulating layer to expose the at least one contact of the chip.
- the carriermay include a plate and an adhesive layer disposed over the plate, wherein the adhesive layer faces the stabilizing structure and the chip, and wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include disposing the stabilizing structure and the chip over the adhesive layer of the carrier.
- Forming the electrically conductive connection to the at least one contact of the chipmay include removing the plate and the adhesive layer of the carrier to expose the at least one contact of the chip.
- Removing the adhesive layer of the carriermay include at least one of dissolving the adhesive layer, peeling off the adhesive layer, and curing the adhesive layer.
- the adhesive layermay include, or may be, a release tape.
- the stabilizing structuremay include at least one alignment mark, and wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include: disposing the stabilizing structure over the carrier; aligning the chip to the stabilizing structure by means of the at least one alignment mark; and disposing the chip next to the stabilizing structure and over the carrier.
- a chip arrangementmay be provided.
- the chip arrangementmay include: a chip; a stabilizing structure disposed next to the chip; and an encapsulating structure encapsulating the chip and the stabilizing structure.
- the stabilizing structuremay include at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.
- the laminate materialmay include a cured laminate material.
- the stabilizing structuremay include at least one electrically conductive layer.
- the at least one electrically conductive layermay include a plurality of electrically conductive layers
- the stabilizing structuremay include at least one via extending through at least a part of the stabilizing structure and electrically connecting an electrically conductive layer of the plurality of electrically conductive layers to another electrically conductive layer of the plurality of electrically conductive layers.
- the encapsulating structuremay include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material.
- the laminate materialmay include, or may consist of, an uncured laminate material.
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Abstract
Description
- Various embodiments relate to a method for manufacturing a chip arrangement, and a chip arrangement.
- Chip arrangements, for example chip packages, may include at least one chip (or die) embedded in a material (e.g. an encapsulant). Electrical and/or thermal and/or mechanical properties of a chip arrangement may depend on a process with which the chip arrangement is manufactured. Some manufacturing processes may adversely affect the electrical and/or thermal and/or mechanical properties of a chip arrangement and/or the at least one chip included in the chip arrangement. New ways of manufacturing chip arrangements may be needed.
- In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
FIG. 1A toFIG. 1G illustrate a conventional method for manufacturing a chip arrangement.FIG. 2 shows a method for manufacturing a chip arrangement.FIG. 3A toFIG. 3K show a process-flow illustrating an example of the method shown inFIG. 2 .FIG. 4A andFIG. 4B show an example of a method for forming a bonding layer and a thru-opening.FIG. 5A andFIG. 5B show a carrier including at least one opening, which may be filled with material of a bonding layer of a stabilizing structure.FIG. 6A toFIG. 6I show a process-flow illustrating another example of the method shown inFIG. 2 .FIG. 7A toFIG. 7K show a process-flow illustrating yet another example of the method shown inFIG. 2 .FIG. 8A toFIG. 8K show a process-flow illustrating an example of the method shown inFIG. 2 applied to a manufacture of a three-dimensional chip arrangement.FIG. 9A toFIG. 9C show flow diagrams illustrating other examples of the method shown inFIG. 2 .FIG. 10 shows a chip arrangement.- The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practised. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Various embodiments are described for structures or devices, and various embodiments are described for methods. It may be understood that one or more (e.g. all) embodiments described in connection with structures or devices may be equally applicable to the methods, and vice versa.
- The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
- The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer, may be formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer, may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.
- In like manner, the word “cover”, used herein to describe a feature disposed over another, e.g. a layer “covering” a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed over, and in direct contact with, the implied side or surface. The word “cover”, used herein to describe a feature disposed over another, e.g. a layer “covering” a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed over, and in indirect contact with, the implied side or surface with one or more additional layers being arranged between the implied side or surface and the covering layer.
- The terms “coupled” and/or “electrically coupled” and/or “connected” and/or “electrically connected”, used herein to describe a feature being connected to at least one other implied feature, are not meant to mean that the feature and the at least one other implied feature must be directly coupled or connected together; intervening features may be provided between the feature and at least one other implied feature.
- Directional terminology, such as e.g. “upper”, “lower”, “top”, “bottom”, “left-hand”, “right-hand”, etc., may be used with reference to the orientation of figure(s) being described. Because components of the figure(s) may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that structural or logical changes may be made without departing from the scope of the invention.
- Modem chip (or die) arrangements, e.g. chip (or die) packages, may include at least one chip (or die), which may be embedded in a material (e.g. an encapsulant).
FIG. 1A toFIG. 1G illustrate a conventional method for manufacturing a chip arrangement.FIG. 1A showscross-sectional view 100 of a chip arrangement including aleadframe 102 and a chip104 (or die). The chip104 (or die) may include a front-side 104aand a back-side 104b. Ametallization layer 104cmay be formed at the back-side 104bof thechip 104 and at least onecontact 104d(e.g. a bonding pad) may be formed at the front-side 104aof thechip 104. Thechip 104 may be bonded to theleadframe 102 by means of a bonding process (indicated byarrows 100a), which may be performed at a temperature in the range from about 200° C. to about 350° C.- As shown in
FIG. 1B in aview 101, a surface of the leadframe102 (e.g. copper leadframe) and/or the front-side 104aof thechip 104 may be roughened (e.g. by means of a micro-etching process) in order to, for example, promote adhesion of subsequent layers that may be formed over thechip 104 and/or theleadframe 102. - As shown in
FIG. 1C in aview 103, thechip 104 may be inspected (e.g. optically inspected) to determine a relative spatial shift between adjacent chips104 (or dies) bonded to theleadframe 102. For example, thechip 104 on the left and thechip 104 on the right may be inspected (e.g. optically inspected) by anapparatus 103a, and a relative position between theleft chip 104 and theright chip 104 may be determined. - As shown in
FIG. 1D in aview 105, alayup 105amay be formed over thechip 104 and theleadframe 102. Thelayup 105amay include astructured prepreg layer 106, an insulating layer108 (e.g. a resin and/or an uncured prepreg) and aconductive layer 110. The structuredprepreg layer 106 may be disposed over (e.g. disposed directly over) theleadframe 102. The structuredprepreg layer 106 may be configured to occupy a gap betweenadjacent chips 104 bonded to theleadframe 102. For example, as shown inFIG. 1D , the structuredprepreg layer 106 may occupy the gap between thechip 104 on the left and thechip 104 on the right. Additionally, the structuredprepreg layer 106 may be configured to occupy a gap between achip 104 and an edge of aleadframe 102, as shown inFIG. 1D . The insulatinglayer 108 may be disposed over the structuredprepreg layer 106, and theconductive layer 110 may be disposed over the insulatinglayer 108, as shown inFIG. 1D . - Heat and/or pressure (indicated by
arrow 105b) may be applied to thelayup 105aand theleadframe 102 to bond (e.g. by lamination) the structuredprepreg 106, the insulating layer (e.g. a resin)108 and theconductive layer 110 to theleadframe 102 and thechip 104. Bonding thelayup 105a(e.g. by lamination) may be performed over a plurality ofleadframes 102 at one time. For example, in BLADE production, eightleadframes 102 may be laminated at one time, and each leadframe may be connected to another leadframe by means of a stencil that may be included in thelayup 105a. - As shown in
FIG. 1E in aview 107, vias112 may be formed in the conductive layer110 (e.g. by means of an etching process). - As shown in
FIG. 1F in aview 109, thevias 112 may be extended to expose a part of theleadframe 102 and/or a part of thechip 104. For example, as shown inFIG. 1F , thevias 112 may be extended to expose at least onecontact 104c(e.g. a bonding pad) of thechip 104. Thevias 112 may be extended by means of a drilling process, for example a laser drilling process. - As shown in
FIG. 1G in aview 111, thevias 112 may be filled with a conductive material114 (e.g. copper or copper alloy or any other suitable metal or metal alloy such as e.g. tungsten). Theconductive material 114 may subsequently be structured (e.g. patterned), for example by means of etching. - The conventional method for manufacturing a chip arrangement shown in
FIG. 1A toFIG. 1G may suffer from undesirable effects. For example, bonding thechip 104 to the leadframe102 (e.g. a thick copper layer), for example as shown inFIG. 1A , may be performed at high temperatures (e.g. in the range from about 200° C. to about 350° C.). - High bonding temperatures may cause warpage of the
leadframe 102. Whilst it may be noted that athicker leadframe 102 may reduce warpage caused by the high bonding temperatures, use of athicker leadframe 102 may lead to a higher bill-of-materials (BOM). - High bonding temperatures may result in a coefficient-of-thermal-expansion (CTE) mismatch between the
chip 104 and theleadframe 102. Accordingly, the chip arrangement manufactured using the method shown inFIG. 1A toFIG. 1G may suffer from high residual stress, which may affect the performance of the chip arrangement. - High bonding temperatures may also result in a high risk of failure caused by copper silicides that may be produced during the bonding process.
- As described above in relation to
FIG. 1D , heat and/or pressure (indicated byarrow 105b) may be applied to thelayup 105aand theleadframe 102 to bond (e.g. by lamination) the structuredprepreg 106, the insulating layer (e.g. a resin)108 and theconductive layer 110 to theleadframe 102 and thechip 104. Bonding thelayup 105a(e.g. by lamination) may cause at least a part of thelayup 105a(e.g. the structuredprepreg 106 and/or the insulating layer (e.g. a resin)108) to shrink. This may lead to warpage of theleadframe 102. - The
leadframe 102, upon which thechip 104 is bonded to, may have a small size (e.g. about 165×68 mm2). As described above, a plurality ofleadframes 102 may be connected to each other with stencil (e.g. additional PCB stencil) which may be included in thelayup 105a. This may lead to a complex layup structure, and a complex leadframe structure. The complex structure may result in poor aligning accuracy between the plurality of leadframes and may suffer from nonlinear dimension changes. For example, small changes in the dimension of aleadframe 102 and/or achip 104 may lead to disproportionate changes in the dimensions of the stencil and/orlayup 105 that may be formed over a plurality ofleadframes 102. FIG. 1A toFIG. 1G illustrate one example of a conventional method for manufacturing a chip arrangement. In another example of a conventional method for manufacturing a chip arrangement, thechip 104 may be bonded to a foil (e.g. a copper foil) by means of a non-conductive adhesive and/or non-conductive paste. In such an example, the front-side 104aof thechip 104 may face the leadframe102 (which may include, or may be, a foil, e.g. copper foil). In other words, in such an example, a local non-conductive adhesive and/or non-conductive paste may be disposed between the front-side 104aof thechip 104 and the leadframe102 (e.g. foil, e.g. copper foil). Such a method for manufacturing a chip arrangement may suffer from a high risk of having voids in the non-conductive adhesive and/or non-conductive paste. These voids may consequently lead to yield loss during a patterning process that may be performed, e.g. patterning an electrical connection to and/or at the front-side 104aof thechip 104. Furthermore, the voids may result in delamination of thechip 104 from the leadframe102 (e.g. foil) and/or HAST (Highly Accelerated Stress Test) problems (e.g. due to trapped plating chemistry). The voids may consequently lead to a loss of reliability of chip arrangements manufactured using such processes that may use a local non-conductive adhesive and/or non-conductive paste disposed between the front-side 104aof thechip 104 and the leadframe102 (e.g. foil, e.g. copper foil).- In another example of a conventional method for manufacturing a chip arrangement, an eWLB (embedded wafer level ball grid array) process may be used. In such an example, wafer level processes may be used to manufacture the chip arrangement. Furthermore, in an eWLB process, the
chip 104 may be disposed (e.g. over a carrier) such that the front-side 104aof thechip 104 may face a carrier during the manufacturing process. In other words, an eWLB process may not have the flexibility of placing thechip 104 in any other orientation (e.g. such that the back-side 104bof thechip 104 may face the carrier). - In view of the above-mentioned features of the conventional method for manufacturing a chip arrangement, a method for manufacturing a chip arrangement is provided. One or more embodiments of the method for manufacturing the chip arrangement may have at least one of the following effects and/or aspects:
- An aspect of one or more embodiments may be the use of simple PCB (printed circuit board) manufacturing processes and/or materials to manufacture a chip (or die) arrangement.
- An aspect of one or more embodiments may be the use of a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
- An aspect of one or more embodiments may be replacement of at least a part of a layup (e.g. the
layup 105ashown inFIG. 1D ) with a stabilizing structure that may not shrink during a lamination process. - An effect of one or more embodiments may be prevention or substantially reduction of warping in at least a part of a leadframe.
- An effect of one or more embodiments may be prevention or substantial reduction of the formation of compounds (e.g. copper silicides) that may damage a chip.
- An effect of one or more embodiments may be prevention or substantial reduction of CTE mismatch and/or high residual stress.
- An effect of one or more embodiments may be manufacture of an interconnection (e.g. metallurgical interconnection) between a chip and a conductive layer in relatively low temperature.
- An effect of one or more embodiments may be prevention or substantial reduction of warpage in a conductive layer and/or a chip.
- An effect of one or more embodiments may be accurate alignment of a chip on a carrier, which may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process.
FIG. 2 shows amethod 200 for manufacturing a chip arrangement.- The
method 200 may, for example, be used to manufacture an embedded chip (or die) arrangement. - The
method 200 for manufacturing the chip arrangement may include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier (in202); encapsulating the chip and the stabilizing structure by means of an encapsulating structure (in204); and forming an electrically conductive connection to the at least one contact of the chip (in206). - An effect provided by the
method 200 may be prevention or substantially reduction of warping of at least a part of a leadframe. - An effect provided by the
method 200 may be prevention or substantial reduction of the formation of compounds (e.g. copper silicides) that may damage a chip. - An effect provided by the
method 200 may be prevention or substantial reduction of CTE mismatch and/or high residual stress. - An effect provided by the
method 200 may be manufacture of an interconnection (e.g. metallurgical interconnection) between a chip and a conductive layer in relatively low temperature. - An effect provided by the
method 200 may be prevention or substantial reduction of warpage in a conductive layer and/or a chip. - An effect provided by the
method 200 may be accurate alignment of a chip on a carrier, which may include, or may be, a panel that may be commonly used as a PCB (printed circuit board) material and/or in a PCB process. FIG. 3A toFIG. 3K show a process-flow illustrating an example of themethod 200 shown inFIG. 2 .FIG. 3A toFIG. 3C show that manufacturing a chip arrangement may include disposing a stabilizingstructure 304 and achip 306 next to each other and over acarrier 302.- In the example shown in
FIG. 3A toFIG. 3C , the stabilizingstructure 304 may be disposed over the carrier302 (e.g. as shown inFIG. 3B ), and thechip 306 may subsequently be disposed next to the stabilizingstructure 304 and over the carrier302 (e.g. as shown inFIG. 3C ). In other words, the stabilizingstructure 304 may be disposed over thecarrier 302 prior to the chip306 (e.g. as shown inFIG. 3B andFIG. 3C ). - However, in another example, the
chip 306 may be disposed over thecarrier 302, and the stabilizingstructure 304 may subsequently be disposed next to thechip 306 and over thecarrier 302. In other words, in another example, thechip 306 may be disposed over thecarrier 302 prior to the stabilizing structure304 (e.g. see description below in respect ofFIG. 7B andFIG. 7C ). FIG. 3A shows across-sectional view 300 of thecarrier 302.- The
carrier 302 may include, or may consist of, aplate 302aand anadhesive layer 302b. As shown inFIG. 3A , theadhesive layer 302bmay be disposed over (e.g. disposed on) theplate 302a. Theadhesive layer 302bof thecarrier 302 may, for example, be formed over theplate 302aof thecarrier 302 by means of a lamination process (e.g. vacuum lamination process) and/or a deposition process, although other processes may be possible as well. - The carrier302 (e.g. the
plate 302aof the carrier302) may include, or may be, a panel. The carrier302 (e.g. theplate 302aof the carrier302) may include, or may be, a foil (e.g. a conductive foil), e.g. that may be available commercially (e.g. a foil available from Metfoils AB). - The carrier302 (e.g. the
plate 302aof the carrier302) may include, or may be, a panel measuring about 300×400 mm2that may be commonly used as a PCB (printed circuit board) material. By way of another example, the carrier302 (e.g. theplate 302aof the carrier302) may include, or may be, a panel that may have a large panel size (e.g. a panel measuring about 300×400 mm2or larger, for example about 500×600 mm2or larger, although other values may be possible as well). - Since the carrier302 (e.g. the
plate 302aof the carrier302) may be a large panel (e.g. measuring about 300×400 mm2), the contraction and/or expansion of thecarrier 302 may be more predictable over a whole panel area, as compared to, e.g., theleadframe 102 shown inFIG. 1A toFIG. 1G , which may be of a smaller size, e.g. 165×68 mm2. - The carrier302 (e.g. the
plate 302aof the carrier302) may include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: aluminium, iron, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the carrier302 (e.g. theplate 302aof the carrier302) may include, or may consist of, an alloy including, or consisting of, iron and at least one other element (e.g. carbon). For example, the carrier302 (e.g. theplate 302aof the carrier302) may include, or may consist of, steel. - The carrier302 (e.g. the
adhesive layer 302bof the carrier302) may include, or may consist of, a non-conductive material. The carrier302 (e.g. theadhesive layer 302bof the carrier302) may include, or may consist of, a release tape (e.g. a thermal release tape, e.g. a temporary thermal release tape). - The carrier302 (e.g. the
adhesive layer 302bof the carrier302) may include, or may consist of, a double-sided sticky tape with thermo-release properties (namely, elements and/or components may be separated and/or released from the double-sided sticky tape by means of heating and/or curing the double-sided sticky tape). - The
carrier 302 may include at least one alignment mark302AL, which may be configured to align a structure and/or a component and/or a layer, which may be subsequently formed and/or disposed over thecarrier 302. FIG. 3B shows across-sectional view 301 of a stabilizingstructure 304 disposed over thecarrier 302.- The stabilizing
structure 304 may be disposed over thecarrier 302 by means of a lamination process (e.g. vacuum lamination process), although other processes may be possible as well. For example, the stabilizingstructure 304 may be laminated to theadhesive layer 302bof thecarrier 302. - The stabilizing
structure 304 may include at least one alignment mark304AL, which may be configured to align the stabilizingstructure 304 to thecarrier 302. For example, the at least one alignment mark304AL of the stabilizingstructure 304 may be aligned to the at least one alignment mark302AL of thecarrier 302, thus aligning the stabilizingstructure 304 to thecarrier 302. In other words, disposing the stabilizingstructure 304 over the carrier may include aligning the stabilizingstructure 304 to thecarrier 302, e.g. by means of the at least one alignment mark304AL of the stabilizingstructure 304 and the at least one alignment mark302AL of thecarrier 302. - The stabilizing
structure 304 may include a thru-opening304O (e.g. one or more thru-openings), which may be formed by means of at least one of a punching process, a routing process, a drilling process, an etching process (e.g. a wet and/or dry etch process), and a laser structuring process, although other processes may be possible as well. The thru-opening304O may be formed prior to disposing the stabilizingstructure 304 over thecarrier 302. - The stabilizing
structure 304 may include asubstrate layer 304A and a bonding layer304BL disposed over thesubstrate layer 304A. The bonding layer304BL may be formed over thesubstrate layer 304A by means of a lamination process (e.g. vacuum lamination process), although other processes may be possible as well. The bonding layer304BL may be formed over thesubstrate layer 304A prior to disposing the stabilizingstructure 304 over thecarrier 302. - The bonding layer304BL of the stabilizing
structure 304 may be configured to attach thesubstrate layer 304A of the stabilizingstructure 304 to thecarrier 302. In this regard, disposing the stabilizingstructure 304 over thecarrier 302 may include attaching thesubstrate layer 304A of the stabilizingstructure 304 to the carrier302 (e.g. theadhesive layer 302bof the carrier302) by means of the bonding layer304BL of the stabilizingstructure 304, as shown inFIG. 3B . For example, the bonding layer304BL of the stabilizingstructure 304 may be disposed between thesubstrate layer 304A of the stabilizingstructure 304 and the carrier302 (e.g. theadhesive layer 302bof the carrier302), as shown inFIG. 3B . - The bonding layer304BL may include, or may be, a resin film (e.g. a B-stage resin film). By way of another example, the bonding layer304BL may include, or may consist of, a material that may be used for laminating PCB layers together, although other materials may be possible as well.
FIG. 4A andFIG. 4B show an example of a method for forming the bonding layer304BL and the thru-opening304O of the stabilizingstructure 304 prior to disposing the stabilizingstructure 304 over thecarrier 302.- As shown in
FIG. 4A in aview 400, the bonding layer304BL may be disposed over thesubstrate layer 304A. As described above, the bonding layer304BL may be formed over thesubstrate layer 304A by means of a lamination process. - A thickness T1 of the bonding layer304BL may depend on a material of the bonding layer304BL. The thickness T1 of the bonding layer304BL may be in the range from about 5 μm to about 150 μm, e.g. in the range from about 10 μm to about 100 μm, e.g. in the range from about 20 μm to about 90 μm, e.g. in the range from about 20 μm to about 60 μm, e.g. in the range from about 20 μm to about 40 μm, e.g. about 30 μm.
- As shown in
FIG. 4B in aview 401, the thru-opening304O (e.g. at least one thru-opening) may be formed (e.g. through thesubstrate layer 304A and the bonding layer304BL) subsequent to forming the bonding layer304BL over thesubstrate layer 304A. As described above, the thru-opening304O may be formed by means of at least one of a punching process, a routing process, a drilling process, an etching process (e.g. a wet and/or dry etch process), and a laser structuring process, although other processes may be possible as well. - The thickness T1 of the bonding layer304BL may be determined such that there may be at least enough material of the bonding layer304BL that may fill an opening (e.g. a cavity) of the
carrier 302, in case thecarrier 302 includes an opening (e.g. cavity). This is illustrated by way of an example inFIG. 5A andFIG. 5B . FIG. 5A andFIG. 5B show thecarrier 302 including at least one opening302O, which may be filled with material of the bonding layer304BL of the stabilizingstructure 304.- As shown in
FIG. 5A in aview 500, the carrier302 (e.g. theplate 302aof the carrier302) may include at least one opening302O.FIG. 5A may, for example, be a magnified view of a portion of thecarrier 302 shown inFIG. 3A . - As shown in
FIG. 5B in aview 501, the at least one opening302O of thecarrier 302 may be filled with the bonding layer304BL of the stabilizingstructure 304.FIG. 5B may, for example, be a magnified view of a portion of thecarrier 302 and the bonding layer304BL of the stabilizingstructure 304 shown inFIG. 3B . - As shown in
FIG. 5B , a first portion304BL-1 of the bonding layer304BL may fill the at least one opening302O of thecarrier 302, and a second portion304BL-2 of the bonding layer304BL may be disposed over at least a part of a surface of thecarrier 302 outside the at least one opening302O. Accordingly, the thickness T1 of the bonding layer304BL may be determined such that there may be enough material to fill the at least one opening302O of the carrier and to line (e.g. coat) the part of the surface of thecarrier 302 outside the at least one opening302O, as shown inFIG. 5B . - Accordingly, by determining the thickness T1 of the bonding layer304BL, the at least one opening302O of the
carrier 302 may be filled with material of the bonding layer304BL, without having to depend on material of a subsequent layer and/or structure (e.g. an encapsulating structure) to fill the at least one opening302O of thecarrier 302. Consequently, material of a subsequent layer and/or structure (e.g. encapsulating structure) may only need to fill at least a part of the thru-opening304O of the stabilizingstructure 304, without having to fill the at least one opening302O of thecarrier 302. - In relation to
FIG. 3B , disposing the stabilizingstructure 304 over thecarrier 302 may include disposing the stabilizing structure over the at least one opening302O of thecarrier 302, wherein the first portion304BL-1 of the bonding layer304BL may fill the at least one opening302O of thecarrier 302, and wherein the a second portion304BL-2 of the bonding layer304BL may be disposed over at least a part of the surface of thecarrier 302 outside the at least one opening302O. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may be configured to prevent or substantially reduce warpage in a chip arrangement manufactured by means of themethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may be configured to prevent or substantially reduce CTE mismatch and/or high residual stress in a chip arrangement manufactured by means of themethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may be configured to prevent or substantially reduce shrinkage in a chip arrangement manufactured by means of themethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of themethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means of themethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may be configured to cool a chip that may be included in a chip arrangement manufactured by means of themethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include, or may consist of, a laminate material (e.g. a cured laminate material). For example, the stabilizing structure304 (e.g. thesubstrate layer 304A of the stabilizing structure304) may include, or may consist of, a PCB laminate material (e.g. a cured PCB laminate material). By way of another example, the stabilizing structure304 (e.g. thesubstrate layer 304A of the stabilizing structure304) may include, or may consist of, an FR4 laminate material (e.g. a cured FR4 laminate material). - The stabilizing
structure 304 including, or consisting of, the laminate material may, for example, be configured to prevent or substantially reduce warpage and/or CTE mismatch and/or high residual stress and/or shrinkage in a chip arrangement manufactured by means of themethod 200. The stabilizingstructure 304 including, or consisting of, the laminate material may, for example, be configured to improve (e.g. optimize) mechanical properties of a chip arrangement manufactured by means of themethod 200. - The stabilizing
structure 304 may include at least one chip (or die) that may, for example, be embedded in thesubstrate layer 304A of the stabilizingstructure 304. The at least one chip (or die) may, for example, be configured to operate in conjunction with a chip, which may be included in the stabilizing structure304 (e.g. embedded in thesubstrate layer 304A of the stabilizing structure) and/or which may be external to the stabilizingstructure 304. The stabilizingstructure 304 including the at least one chip (or die) may, for example, be configured to improve (e.g. optimize) electrical properties of a chip arrangement manufactured by means of themethod 200. - The stabilizing
structure 304 may include at least one via (e.g. a through-via, e.g. a matrix of through-vias) that may, for example, be embedded in thesubstrate layer 304A of the stabilizingstructure 304. The stabilizingstructure 304 including the at least one via (e.g. a matrix of through-vias) may, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means ofmethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include at least one electrically conductive layer (e.g. a copper layer), which may be suitable for routing and/or redistribution of electrical signals. - In an example where the stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include one electrically conductive layer, the stabilizing structure304 (e.g. thesubstrate layer 304A of the stabilizing structure304) may include, or may be, a single layer RDL (redistribution layer). - In another example where the stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include a plurality of electrically conductive layers, the stabilizingstructure 304 may include, or may be, a multi-layer RDL. In such an example, the stabilizing structure304 (e.g. thesubstrate layer 304A of the stabilizing structure304) may include at least one via extending through at least a portion of the stabilizing structure304 (e.g. thesubstrate layer 304A of the stabilizing structure304). The at least one via may, for example, electrically connect a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers. In other words, at least two electrically conductive layers of the plurality of electrically conductive layers may be electrically connected to each other. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include, or may consist of, a polymer material (e.g. a polyimide material). The stabilizingstructure 304 including, or consisting of, the polymer material may, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means of themethod 200. The stabilizingstructure 304 including, or consisting of, the polymer material may, for example, be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means ofmethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the stabilizing structure304 (e.g. thesubstrate layer 304A of the stabilizing structure304) may include, or may consist of, copper. The stabilizingstructure 304 including, or consisting of, the metal or metal alloy may be configured to cool a chip that may be included in a chip arrangement manufactured by means ofmethod 200. The stabilizingstructure 304 including, or consisting of, the metal or metal alloy may, for example, be configured to improve (e.g. optimize) mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means ofmethod 200. - The stabilizing structure304 (e.g. the
substrate layer 304A of the stabilizing structure304) may include, or may consist of, a ceramic material. The stabilizingstructure 304 including, or consisting of, the ceramic material may, for example, be configured to electrically and/or thermally isolate a chip that may be included in a chip arrangement manufactured by means ofmethod 200. The stabilizingstructure 304 including, or consisting of, the ceramic material may, for example, be configured to seal a chip that may be included in a chip arrangement manufactured by means ofmethod 200. The stabilizingstructure 304 including, or consisting of, the ceramic material may, for example, be configured to optimize mechanical and/or thermal and/or electrical properties of a chip arrangement manufactured by means ofmethod 200. FIG. 3C shows across-sectional view 303 of achip 306 disposed next to the stabilizingstructure 304 and over thecarrier 302.- Only two
chips 306 are shown as an example, however the number of chips may be less than two (e.g. one) or greater than two, and may, for example, be three, four, five, six, seven, eight, nine, or on the order of tens, or even more chips. - The
chip 306 may, for example, be a chip used for MEMS and/or logic and/or memory and/or power applications, although chips used for other applications may be possible as well. - As shown in
FIG. 3C ,chip 306 may include afirst side 306aand asecond side 306bopposite thefirst side 306a. Thefirst side 306aand thesecond side 306bof thechip 306 may include, or may be, a frontside and a backside of thechip 306, respectively. By way of another example, thefirst side 306aof thechip 306 may include, or may be, an active side of thechip 306. - The
chip 306 may include at least onecontact 306c. The at least onecontact 306cof thechip 306 may, for example, provide an interface (e.g. an electrical and/or thermal interface) for thechip 306. For example, signals (e.g. electrical signals, power supply potentials, ground potentials, etc.) may be exchanged with thechip 306 via the at least onecontact 306c. By way of another example, heat may be conducted away from thechip 306 by means of the at least onecontact 306c. - The at least one
contact 306cof thechip 306 may, for example, be disposed at thefirst side 306a(e.g. active side), thesecond side 306b(e.g. backside), or both. For example, the at least onecontact 306cmay include, or may be, a metallization layer which may, for example, be disposed over thesecond side 306b(backside) of thechip 306. In the example shown in FIG.3C, the at least onecontact 306cmay be disposed at thefirst side 306a(e.g. active side) and thesecond side 306b(e.g. backside) of the chip306 (the at least onecontact 306cdisposed at thesecond side 306bis not shown inFIG. 3C ). In another example, the at least onecontact 306cmay be disposed at one of thefirst side 306aand thesecond side 306bof thechip 306 - In the example shown in
FIG. 3C , thefirst side 306a(e.g. active side) of thechip 306 may face thecarrier 302 and/or may be in contact (e.g. physical contact) with thecarrier 302. Such an arrangement of thechip 306 may, for example, be referred to as a face-down arrangement of thechip 306. - In another example, the
second side 306b(e.g. backside) of thechip 306 may face thecarrier 302 and/or may be in contact (e.g. physical contact) with the carrier302 (e.g. see description below in respect ofFIG. 6C ). In this example, such an arrangement of thechip 306 may be referred to as a face-up arrangement of thechip 306. - As shown in
FIG. 3C , thechip 306 may be disposed over theadhesive layer 302bof thecarrier 302. Accordingly, disposing the stabilizingstructure 304 and thechip 306 next to each other and over thecarrier 302 may include disposing the stabilizingstructure 304 and thechip 306 next to each other and over theadhesive layer 302bof thecarrier 302. - As described above, the stabilizing
structure 304 may include the at least one alignment mark304AL and thecarrier 302 may include the at least one alignment mark302AL. In this regard, disposing thechip 306 and the stabilizingstructure 304 next to each other and over thecarrier 302 may include aligning thechip 306 to the stabilizingstructure 304 by means of the at least one alignment mark304AL and/or the at least one alignment mark302AL, and disposing thechip 306 next to the stabilizingstructure 304 and over thecarrier 302. In other words, thechip 306 may be aligned (e.g. accurately aligned) by means of the at least one alignment mark304AL of the stabilizingstructure 304 and/or the at least one alignment mark302AL of thecarrier 302. - In the example shown in
FIG. 3C , each of the one ormore chips 306 may be mounted on a large carrier302 (e.g. 300×400 mm2) and aligned using same aligning marks (e.g. of the stabilizingstructure 304 and/or the carrier302). Accordingly, the aligning accuracy may be good all over an entire area of the carrier302 (e.g. the whole panel area). - As described above,
FIG. 3A toFIG. 3C show an example in which the stabilizingstructure 304 may be disposed over the carrier302 (e.g. as shown inFIG. 3B ), and thechip 306 may subsequently be disposed next to the stabilizingstructure 304 and over the carrier302 (e.g. as shown inFIG. 3C ). However, in another example, thechip 306 may be disposed over thecarrier 302, and the stabilizingstructure 304 may subsequently be disposed next to thechip 306 and over thecarrier 302. In such an example, thechip 306 may be aligned to thecarrier 302 by means of the at least one alignment mark302AL of thecarrier 302. The stabilizingstructure 304 may subsequently be aligned to thechip 306 and/or thecarrier 302 by means of the at least one alignment mark302AL of thecarrier 302 and/or the at least one alignment mark304AL of the stabilizingstructure 304. - As described above, the stabilizing
structure 304 may include the thru-opening304O. In this regard, disposing thechip 306 and the stabilizingstructure 304 next to each other and over thecarrier 302 may include disposing thechip 306 within the thru-opening304O of the stabilizingstructure 304 and over thecarrier 302, as shown inFIG. 3C . - The examples shown in
FIG. 3A toFIG. 3C may, for example, be identified with “disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier” disclosed in202 ofmethod 200. FIG. 3D andFIG. 3E showcross-sectional views chip 306 and the stabilizingstructure 304 encapsulated by means of an encapsulatingstructure 308.- The examples shown in
FIG. 3D andFIG. 3E may, for example, be identified with “encapsulating the chip and the stabilizing structure by means of an encapsulating structure” disclosed in204 ofmethod 200. - As shown in
FIG. 3D in aview 305, encapsulating thechip 306 and the stabilizingstructure 304 may include laying-up the encapsulatingstructure 308 over thechip 306, the stabilizingstructure 304, and thecarrier 302. - The encapsulating
structure 308 may include an insulatinglayer 308a. The encapsulatingstructure 308 shown inFIG. 3D may additionally include aconductive layer 308b. However, in another example, the encapsulatingstructure 308 may include the insulatinglayer 308aonly. As illustrated in the example shown inFIG. 3D , the insulatinglayer 308amay be disposed between thechip 306 and theconductive layer 308b. - The encapsulating structure308 (e.g. the insulating
layer 308aof the encapsulating structure308) may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material (e.g. an uncured laminate material), although other materials may be possible as well. - The encapsulating structure308 (e.g. the
conductive layer 308bof the encapsulating structure308) may include, or may consist of, an electrically conductive material and/or a thermally conductive material. For example, the encapsulating structure308 (e.g. theconductive layer 308bof the encapsulating structure308) may include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the encapsulating structure308 (e.g. theconductive layer 308bof the encapsulating structure308) may include, or may consist of, copper or a copper alloy. - As described above in relation to the
chip 306 shown inFIG. 3C , the at least onecontact 306cmay be disposed at thefirst side 306a(e.g. active side) and/or thesecond side 306b(e.g. backside) of thechip 306. Theconductive layer 308bof the encapsulatingstructure 308 may be suitable for forming a subsequent electrical and/or thermal connection with the stabilizingstructure 304 and/or thechip 306. For example, theconductive layer 308bof the encapsulatingstructure 308 may be at least a part of an electrical and/or thermal connection to the at least onecontact 306cdisposed at thesecond side 306bof thechip 306. - As shown in
FIG. 3E in aview 307, encapsulating thechip 306 and the stabilizingstructure 304 by means of the encapsulatingstructure 308 may include applying heat and pressure (indicated by arrows310) to fuse the encapsulatingstructure 308, thechip 306, and the stabilizingstructure 304 together. Applying heat and pressure (indicated by arrows310) may include, or may be, a lamination process. In other words, encapsulating thechip 306 and the stabilizingstructure 304 by means of the encapsulatingstructure 308 may include, or may consist of, a lamination process. - The applied heat and/or pressure (indicated by arrows310) may soften (e.g. melt) the encapsulating structure308 (e.g. the insulating
layer 308aof the encapsulating structure308) such that the encapsulating structure308 (e.g. the insulatinglayer 308aof the encapsulating structure308) flows into and fills the thru-opening304O of the stabilizingstructure 304. At least a portion of the encapsulating structure308 (e.g. at least a portion of the insulatinglayer 308aand/or theconductive layer 308bof the encapsulating structure308) may be additionally disposed over thechip 306 and the stabilizingstructure 304 after the application of heat and/or pressure, as shown inFIG. 3E . FIG. 3F toFIG. 3K show cross-sectional views illustrating the forming of at least one electrically conductive connection to the at least onecontact 306cof thechip 306.- The examples shown in
FIG. 3F toFIG. 3K may, for example, be identified with “forming an electrically conductive connection to the at least one contact of the chip” disclosed in206 ofmethod 200. - As shown in
FIG. 3F in aview 309, forming the at least one electrically conductive connection to the at least onecontact 306cof thechip 306 may include removing thecarrier 302 e.g. to expose the at least onecontact 306cof thechip 306. For example, the at least onecontact 306cof thechip 306 may be visible and/or exposed with the removal of thecarrier 302. In the example shown inFIG. 3F , the at least onecontact 306cdisposed at thefirst side 306a(e.g. active side) of thechip 306 may be visible and/or exposed by the removal of thecarrier 302. In the example shown inFIG. 3F , the bonding layer304BL may be removed with the carrier302 (e.g. by means of at least one of dissolving, peeling off, and curing). - As described above, the
carrier 302 may include theplate 302aand theadhesive layer 302b. Accordingly, removing thecarrier 302 may include removing theplate 302aand theadhesive layer 302bof thecarrier 302, e.g. to expose the at least onecontact 306cof thechip 306. Removing theadhesive layer 302bof thecarrier 302 may include at least one of dissolving theadhesive layer 302b(e.g. by means of a solvent), peeling off theadhesive layer 302b, and curing theadhesive layer 302b. For example, as described above, the carrier302 (e.g. theadhesive layer 302bof the carrier302) may include, or may consist of, a double-sided sticky tape with thermo-release properties (namely, elements may be separated and/or released from the double-sided sticky tape by means of heating and/or curing the double-sided sticky tape). In such an example, theadhesive layer 302bmay be cured, thus separating thechip 306 and the stabilizingstructure 304 from thecarrier 302. The stabilizingstructure 304 and thechip 306 may be held in place by means of the encapsulating structure308 (e.g. the insulatinglayer 308aof the encapsulating structure308). - As shown in
FIG. 3G in aview 311, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include disposing a secondconductive layer 312bover the at least onecontact 306cof the chip306 (e.g. the at least one exposedcontact 306cof the chip306). In the example shown inFIG. 3G , the secondconductive layer 312bmay be disposed over the at least onecontact 306cdisposed at thefirst side 306aof thechip 306, which may be exposed and/or visible (e.g. due to the removal of the carrier302). Since the stabilizingstructure 304 is disposed next to thechip 306, the secondconductive layer 312bmay be disposed over the stabilizingstructure 304 as well. - The second
conductive layer 312bmay include, or may consist of, an electrically conductive material and/or a thermally conductive material. For example, the secondconductive layer 312bmay include, or may consist of, a metal or metal alloy. The metal may include at least one metal selected from a group of metals, the group consisting of: copper, aluminum, titanium, tungsten, nickel, palladium, gold, or an alloy containing at least one of the aforementioned metals, although other metals may be possible as well. For example, the secondconductive layer 312bmay include, or may consist of, copper or a copper alloy. - As shown in
FIG. 3G , disposing the secondconductive layer 312bover the at least onecontact 306cof thechip 306 may include disposing a second insulatinglayer 312abetween the secondconductive layer 312band the at least onecontact 306cof the chip306 (e.g. the exposed contact of the chip, e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306). - The second
insulating layer 312amay include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material (e.g. an uncured laminate material), although other materials may be possible as well. - As described above in relation to the
chip 306 shown inFIG. 3C , the at least onecontact 306cmay be disposed at thefirst side 306a(e.g. active side) and/or thesecond side 306b(e.g. backside) of thechip 306. In the example shown inFIG. 3C , the secondconductive layer 312bmay be suitable for forming the electrically conductive connection with the stabilizingstructure 304 and/or the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306). - As shown in
FIG. 3H in aview 313, disposing the secondconductive layer 312bover the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306) may include applying heat and pressure (indicated by arrows314) to fuse the secondconductive layer 312b, the second insulatinglayer 312a, the encapsulatingstructure 308, thechip 306, and the stabilizingstructure 304 together. Applying heat and pressure (indicated by arrows314) may include, or may be, a lamination process. In other words, disposing the secondconductive layer 312bover the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306) may include, or may consist of, a lamination process. - A distance D between the at least one
contact 306cof the chip306 (e.g. the at least one exposedcontact 306cof thechip 306c) and thesecond conducting layer 312bmay be at least substantially equal over a lateral extent of the chip arrangement shown inFIG. 3H . The distance D may be easily controlled by controlling a thickness of the second insulatinglayer 312a. - As described above, an electrically conductive connection may be formed with the at least one
contact 306cof thechip 306. As described above, the at least onecontact 306cof thechip 306 shown inFIG. 3C toFIG. 3K may be disposed at thefirst side 306aand thesecond side 306bof thechip 306. Accordingly, the electrically conductive connection may be formed with thefirst side 306aand thesecond side 306bof thechip 306. In another example, the electrically conductive connection may be formed to thefirst side 306aor thesecond side 306bof thechip 306, depending on where the at least onecontact 306cof thechip 306 may be disposed. - As shown in
FIG. 3I in aview 315 andFIG. 3J in aview 317, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include forming at least oneopening 316 in the encapsulatingstructure 308 to expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thesecond side 306bof the chip306). For example, the at least oneopening 316 may be formed in theconductive layer 308bof the encapsulatingstructure 308, as shown inFIG. 3I . The at least oneopening 316 may be formed in the encapsulatingstructure 308 by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process). - The at least one
opening 316 may be subsequently deepened (e.g. extended through the insulatinglayer 308aof the encapsulating structure308) to expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thesecond side 306bof the chip306), as shown inFIG. 3J . The at least oneopening 316 may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process). - As shown in
FIG. 3I in aview 315 andFIG. 3J in aview 317, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include forming at least oneopening 318 in the secondconductive layer 312band the second insulatinglayer 312ato expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306). For example, the at least oneopening 318 may be formed in the secondconductive layer 312b, as shown inFIG. 3I . The at least oneopening 318 may be formed in the secondconductive layer 312bby means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process). - The at least one
opening 318 may be subsequently deepened (e.g. extended through the second insulatinglayer 312a) to expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306), as shown inFIG. 3J . The at least oneopening 318 may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process). - In the examples shown in
FIG. 3I andFIG. 3J , at least oneopening 323 may be formed to expose at least a part of the stabilizingstructure 304. The at least oneopening 323 may be formed and/or deepened by means of similar processes used in relation to the at least oneopening 316 and the at least oneopening 318. In another example, however, there may not be an opening that may expose at least a part of the stabilizingstructure 304. - Forming the at least one
opening 316 and/or318 and/or323 (e.g. by means of an etching process and/or micro-via cleaning and/or drilling process) may include using the at least one alignment mark304AL of the stabilizing structure, which may improve accuracy and/or precision of the etching process and/or micro-via cleaning and/or drilling process. - As shown in
FIG. 3K in aview 319, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include a plating process (indicated by arrows320). In one or more examples, a seed metal or seed metal alloy (e.g. seed copper) may be sputtered prior to or as part of the plating process (indicated by arrows320). The plating process (indicated by arrows320) may, for example, fill the at least oneopening - In the example shown in
FIG. 3K , the electrically conductive connection between the secondconductive layer 312band the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306) may be formed by means of the plating process (indicated by arrows320). By way of another example, the electrically conductive connection between theconductive layer 308bof the encapsulatingstructure 308 and the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thesecond side 306bof the chip306) may be formed by means of the plating process (indicated by arrows320). - In the example shown in
FIG. 3K , an electrically conductive connection may also be formed between theconductive layer 308bof the encapsulatingstructure 308 and the stabilizingstructure 304 by means of the plating process (indicated by arrows320). - The plating process (indicated by arrows320) for forming the electrically conductive connection to the at least one
contact 306cof thechip 306 may include an electroless plating process or an electrochemical plating process or a direct metallization process. - Forming the electrically conductive connection to the at least one
contact 306cof thechip 306 may include patterning theconductive layer 308aof the encapsulatingstructure 308 and/or the secondconductive layer 312b, e.g. subsequent to the plating process shown inFIG. 3K . Patterning theconductive layer 308aof the encapsulatingstructure 308 and/or the secondconductive layer 312bmay include, or may consist of, an etching process (e.g. a dry and/or wet etch process). The patterning process may, for example, make use of at least one alignment mark, which may improve accuracy and/or precision of the patterning process. The at least one alignment mark may, for example, be disposed at theconductive layer 308band/or the secondconductive layer 312b. This alignment mark may, for example, be formed by means of reproducing the at least one alignment mark304AL of the stabilizingstructure 304 and/or the at least one alignment mark302AL of thecarrier 302, e.g. prior to the removal of thecarrier 302. - As described above, the patterning process may be performed subsequent to the plating process shown in
FIG. 3K . However, in another example, the at least oneopening 316 and/or318 and/or323 may be filled with electrically conductive material by means of a structured deposition process and/or a selective plating process. For example, a patterned resist material (e.g. a photo-resist material) may be formed over theconductive layer 308bof the encapsulatingstructure 308 and/or the secondconductive layer 312b, wherein the at least oneopening 316 and/or318 and/or323 may be left exposed (namely, not covered by the patterned resist material). Subsequently, a plating process may be performed, which may form the electrically conductive connection to the at least onecontact 306cof thechip 306. In such an example, the electrically conductive connection may be formed (e.g. by means of selective deposition and/or selective plating) over a part of thechip 306 and/or the stabilizingstructure 304 that is not covered by the patterned resist material. FIG. 6A toFIG. 6I show a process-flow illustrating another example of themethod 200 shown inFIG. 2 .- Reference signs in
FIG. 6A toFIG. 6I that are the same as inFIG. 3A toFIG. 3K denote the same or similar elements as inFIG. 3A toFIG. 3K . Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 6A toFIG. 6I andFIG. 3A toFIG. 3K are described below. - As shown in
FIG. 6C in aview 603, thechip 306 may be arranged in a face-up arrangement. In other words, thesecond side 306b(e.g. backside) of thechip 306 may face and/or may be in contact (e.g. physical contact) with thecarrier 302. - As shown in
FIG. 6F in aview 609, forming the at least one electrically conductive connection to the at least onecontact 306cof thechip 306 may include removing thecarrier 302 e.g. to expose the at least onecontact 306cof thechip 306. In the example shown inFIG. 6F , the at least onecontact 306cdisposed at thesecond side 306b(e.g. backside) of thechip 306 may be exposed with the removal of thecarrier 302. - As described above, the at least one
contact 306cdisposed at thesecond side 306b(e.g. backside) of thechip 306 may include, or may be, a metallization layer. Accordingly, in the example shown inFIG. 6F , the metallization layer of thechip 306 may be exposed with the removal of thecarrier 302. - As shown in
FIG. 6G in aview 611 andFIG. 6H in aview 613, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include forming at least oneopening 316 in the encapsulatingstructure 308 to expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306). For example, the at least oneopening 316 may be formed in theconductive layer 308bof the encapsulatingstructure 308, as shown inFIG. 6G . The at least oneopening 316 may be formed in the encapsulatingstructure 308 by means of an etching process (e.g. a micro-etching process, e.g. a micro-via etching process) and/or a drilling process (e.g. a micro-drilling process). - The at least one
opening 316 may be subsequently deepened (e.g. extended through the insulatinglayer 308aof the encapsulating structure308) to expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306), as shown inFIG. 6H . The at least oneopening 316 may be deepened by means of a cleaning process and/or a drilling process (e.g. via cleaning and/or drilling process, e.g. a micro-via cleaning and/or drilling process). - In the example shown in
FIG. 6G andFIG. 6H , there may not be an opening formed to expose at least a part of the stabilizingstructure 304. However, in another example, the at least oneopening 323 may be formed to expose at least a part of the stabilizingstructure 304. - As shown in
FIG. 6I in aview 615, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include the plating process (indicated by arrows320). For example, the electrically conductive connection between theconductive layer 308bof the encapsulatingstructure 308 and the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306) may be formed by means of the plating process (indicated by arrows320). By way of another example, the electrically conductive connection to the at least onecontact 306cdisposed at thesecond side 306bof thechip 306 may be formed by means of the plating process (indicated by arrows320). - The plating process (indicated by arrows320) for forming the electrically conductive connection to the at least one
contact 306cof thechip 306 may include an electroless plating process or an electrochemical plating process or a direct metallization process. - As described above in relation to the example shown in
FIG. 3A toFIG. 3K , forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include patterning the plated electrically conductive connection. The features of the patterning process described above may be analogously applicable to the example shown inFIG. 6A toFIG. 6I . FIG. 7A toFIG. 7K show a process-flow illustrating yet another example of themethod 200 shown inFIG. 2 .- Reference signs in
FIG. 7A toFIG. 7K that are the same as inFIG. 3A toFIG. 3K denote the same or similar elements as inFIG. 3A toFIG. 3K . Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 7A toFIG. 7K andFIG. 3A toFIG. 3K are described below. - As shown in
FIG. 7B in aview 701, the chip arrangement may include a plurality ofchips 306. At least onechip 306 may be arranged in a face-up arrangement (namely, thesecond side 306bmay face and/or be in contact (e.g. physical contact) with the carrier302), and at least oneother chip 306 may be arranged in a face-down arrangement (namely, thefirst side 306amay face and/or be in contact (e.g. physical contact) with the carrier302). - As shown in
FIG. 7B , thechip 306 may be disposed over thecarrier 302 prior to the stabilizingstructure 304. In such an example, the at least one alignment mark302AL of the carrier may be used to align thechip 306 to thecarrier 302. - As shown in
FIG. 7C in aview 703, the stabilizingstructure 304 may be disposed subsequent to disposing thechip 306. In such an example, the least one alignment mark302AL of the carrier may be used to align the stabilizingstructure 304. For example, the at least one alignment mark304AL of the stabilizingstructure 304 and the at least one alignment mark302AL of thecarrier 302 may be used to align the stabilizingstructure 304. FIG. 7D toFIG. 7K show a process-flow, which may be performed using processes described above in respect ofFIG. 3D toFIG. 3K .FIG. 8A toFIG. 8K show a process-flow illustrating an example of themethod 200 shown inFIG. 2 applied to a manufacture of a three-dimensional (3D) chip arrangement.- Reference signs in
FIG. 8A toFIG. 8K that are the same as inFIG. 7A toFIG. 7K denote the same or similar elements as inFIG. 7A toFIG. 7K . Thus, those elements will not be described in detail again here; reference is made to the description above. Differences betweenFIG. 8A toFIG. 8K andFIG. 7A toFIG. 7K are described below. - As shown in
FIG. 8F , afirst module 802 may be arranged over asecond module 804. A third insulatinglayer 806 may be disposed between thefirst module 802 and thesecond module 804. - The first and
second modules FIG. 8E . Namely, each of the first andsecond modules carrier 302, thechip 306, the stabilizingstructure 304, and the encapsulating structure308 (e.g. which may include the insulatinglayer 308a, and which may be free from theconducting layer 308b). - As shown in
FIG. 8F , thefirst module 802, thesecond module 804, and the third insulatinglayer 806 may be disposed over aworkpiece 808. Thefirst module 802, thesecond module 804, and the third insulatinglayer 806 may be aligned to each other by means of the at least one alignment mark302AL of thecarrier 302 of thefirst module 802 and/or thesecond module 804. - As shown in
FIG. 8G in aview 811, thefirst module 802, thesecond module 804, and the third insulatinglayer 806 may be pressed together (indicated by arrows812) to form a 3D chip arrangement. - As shown in
FIG. 8H in aview 813, the respective carriers of the first andsecond modules contact 306cof thechip 306 of thefirst module 802 and thesecond module 804. - As shown in
FIG. 8I in aview 815, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include disposing the secondconductive layer 312bover the at least onecontact 306cof thechip 306 of the first andsecond modules FIG. 8I , the secondconductive layer 312bmay be disposed over the at least onecontact 306cdisposed at thefirst side 306aof thechip 306 of the first andsecond modules FIG. 8I , disposing the secondconductive layer 312bover the at least onecontact 306cof thechip 306 may include disposing the second insulatinglayer 312abetween the secondconductive layer 312band the at least onecontact 306cof thechip 306. - As shown in
FIG. 8J in aview 817, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include forming at least oneopening 318 in the secondconductive layer 312band the second insulatinglayer 312ato expose the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306). The at least oneopening 318 may be formed and/or deepened by means of the processes described above in respect ofFIG. 3I andFIG. 3J . - Forming the electrically conductive connection to the at least one
contact 306cof thechip 306 may include forming at least one through-via814 in the 3D chip arrangement. The at least one through-via814 may be formed by means of similar or identical processes as those described above in respect of the at least oneopening - As shown in
FIG. 8K in aview 819, forming the electrically conductive connection to the at least onecontact 306cof thechip 306 may include a plating process (indicated by arrows320). For example, the electrically conductive connection between theconductive layer 308bof the encapsulatingstructure 308 and the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306) of the first andsecond modules opening 318 with an electrically conductive material. - The plated electrically conductive connection may be patterned, as described above in relation to
FIG. 3K . - As described above, a conventional method for manufacturing a chip arrangement may include embedding a chip inside a prepreg, and may include bonding chips that may be disposed face-down on a copper foil with non-conductive adhesives. Compared with such an example, the
method 200 may avoid the disadvantages of such a conventional method (e.g. HAST problems, delamination, etc.) since the second insulatinglayer 312abetween the secondconductive layer 312band the at least onecontact 306cof the chip306 (e.g. the at least onecontact 306cdisposed at thefirst side 306aof the chip306) is formed after using vacuum lamination. - As described above, a conventional method for manufacturing a chip arrangement may include an eWLB manufacturing process. Compared with the eWLB manufacturing process, the
method 200 may allow manufacturing double sided arrangements where thechip 306 may be arranged in a face-up and/or face-down arrangement. Compared with the eWLB manufacturing process, themethod 200 may allow the forming of a plated electrical connection with thefirst side 306aand/or thesecond side 306bof thechip 306. Compared with the eWLB manufacturing process, themethod 200 may allow the forming of an electrical connection with thesecond side 306b(e.g. backside) of thechip 306 by means of a plating process. Compared with the eWLB manufacturing process, themethod 200 may allow the use of standard PCB material (e.g. standard reinforced PCB material), large panel size and low cost PCB manufacturing processes, instead of wafer level processes. This may be easy to incorporate and/or include in a standard PCB production. - As described above, a conventional method for manufacturing a chip arrangement may include the example shown in
FIG. 1A toFIG. 1G . Compared with this example, themethod 200 may allow manufacturing double sided arrangements where thechip 306 may be arranged in a face-up and/or face-down arrangement. Compared with the example shown inFIG. 1A toFIG. 1G , themethod 200 may allow the forming of a plated electrical connection with thefirst side 306aand/or thesecond side 306bof thechip 306. Compared with the example shown inFIG. 1A toFIG. 1G , themethod 200 may allow the forming of an electrical connection with thesecond side 306b(e.g. backside) of thechip 306 by means of a plating process. Compared with the example shown inFIG. 1A toFIG. 1G , thechip 306 may be aligned to thecarrier 302 that may have a large size (e.g. same size as a production panel) using the at least one alignment mark302AL of thecarrier 302. Compared with theleadframe 102 shown inFIG. 1A toFIG. 1G which may, for example, be smaller (e.g. about 165×68 mm2), themethod 200 may provide accurate alignment of thechip 306 to thecarrier 302. Since a plurality ofleadframes 102 may not be needed compared with the example shown inFIG. 1A toFIG. 1G , an effect of themethod 200 may be reduction or prevention of additional tolerances between a plurality of leadframes102 (which may also be referred to as sub-panels). - As described above, the
chip 306 may be disposed in a face-down arrangement. In such an arrangement, a distance between the at least onecontact 306cof thechip 306 and thesecond conducting layer 312bmay be at least substantially equal over a lateral extent of the chip arrangement. The distance may be easily controlled by controlling a thickness of the second insulatinglayer 312a. This may allow for easier forming of the at least oneopening - As compared with a conventional method for manufacturing a chip arrangement, the
method 200 may allow arrangement of thechip 306 in a face-up or face-down arrangement, or both, and forming of an electrically conductive connection to thechip 306 from thefirst side 306aand/or thesecond side 306b, thus enabling a manufacture of a 3D chip arrangement. FIG. 9A toFIG. 9C show flow diagrams illustrating other examples of themethod 200 shown inFIG. 2 .- As an example, the flow diagram900 shown in
FIG. 9A shows aprocess 902, which may, for example, be identified with the process shown inFIG. 4A andFIG. 4B . - The
process 904 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the process shown inFIG. 6B . - The
process 906 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the process shown inFIG. 6C . - The
process 908 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the process shown inFIG. 6D . - The
process 910 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the process shown inFIG. 6E . - The
process 912 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the process shown inFIG. 6F . - The
process 914 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the processes shown inFIG. 6G andFIG. 6H . - The
process 916 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the seed metal or seed metal alloy (e.g. seed copper) described above, which may be sputtered prior to or as part of the plating process (indicated by arrows320). - The
process 918 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the process shown inFIG. 6I . - The
process 920 shown in the flow diagram900 ofFIG. 9A may, for example, be identified with the patterning process described above. - As another example, the flow diagram901 shown in
FIG. 9B shows aprocess 901, which may, for example, be identified with the process shown inFIG. 4A andFIG. 4B . - The
process 922 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the process shown inFIG. 7B . - The
process 924 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the processes shown inFIG. 7C andFIG. 7D . - The
process 926 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the process shown inFIG. 7E . - The
process 928 shown in the flow diagram901 ofFIG. 9B may, for example, indicate that the at least one alignment mark302AL of thecarrier 302 and/or the at least one alignment mark304AL of the stabilizingstructure 304 may be reproduced at (e.g. reproduced over a surface of) the encapsulatingstructure 308. - The
process 930 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the process shown inFIG. 7F . - The
process 932 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the processes shown inFIG. 7G andFIG. 7H . - The
process 934 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the processes shown inFIG. 7I andFIG. 7J . - The
process 936 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the process shown inFIG. 7K . - The
process 938 shown in the flow diagram901 ofFIG. 9B may, for example, be identified with the patterning process described above. - As yet another example, the flow diagram903 shown in
FIG. 9C shows aprocess 902, which may, for example, be identified with the process shown inFIG. 4A andFIG. 4B . - The
process 940 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the process shown inFIG. 3B . - The
process 942 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the process shown inFIG. 3C . - The
process 944 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the process shown inFIG. 3D . - The
process 946 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the process shown inFIG. 3E . - The
process 948 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the process shown inFIG. 3F . - The
process 950 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the processes shown inFIG. 3G andFIG. 3H . - The
process 952 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the processes shown inFIG. 3I andFIG. 3J . - The
process 954 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the process shown inFIG. 3K . - The
process 956 shown in the flow diagram903 ofFIG. 9C may, for example, be identified with the patterning process described above. FIG. 10 shows achip arrangement 1000.- Reference signs in
FIG. 10 that are the same as inFIG. 3A toFIG. 3K denote the same or similar elements as inFIG. 3A toFIG. 3K . Thus, those elements will not be described in detail again here; reference is made to the description above. - The
chip arrangement 1000 may, for example, be manufactured by means of themethod 200 shown inFIG. 2 . - The
chip arrangement 1000 may include: achip 306, a stabilizingstructure 304 disposed next to thechip 306; and an encapsulatingstructure 308 encapsulating thechip 306 and the stabilizingstructure 304. - According to various examples presented herein, a chip arrangement may be manufactured using large panel sizes and standard PCB materials and/or processes.
- According to various examples presented herein, a chip may be bonded to a temporary thermal release tape of a carrier in a face-up and/or face-down arrangement. After bonding the chip to the temporary release tape, an insulating layer may be manufactured with standard PCB prepreg foils or prepregs and laminates. The insulating layer may be laminated over the chip bonded to the temporary release tape e.g. by means of a lamination process.
- After laminating the insulating layer, the carrier and the release tape may be removed and the whole top or bottom side of the chip may be visible. After removal of the carrier and the release tape, an insulation layer may be laminated over of the chip, and microvias may be manufactured on both side of the panel to contact the chip to conductor layers that may be laminated on the chip. Plating and patterning may be performed either with direct metallization and subtractive process or normal pattern plating process (e.g. standard PCB processes). Because the process uses standard low cost, high volume PCB materials and manufacturing equipment, the manufacturing process may be low cost and can be performed on large panels.
- The manufacturing process may allow exposure of the whole front side and/or or backside of the chip. Furthermore, a distance between a side of the chip and a conducting layer (e.g. copper surface) can be accurately fixed and manufactured without any voids. By replacing the center prepreg with PCB laminate (cured FR4), the warpage of the chip arrangement is smaller. Furthermore, dimensional stability of the chip arrangement may be improved (e.g. since cured laminate has remarkable smaller shrinkage than prepreg). This PCB laminate can also be patterned (conductors and vias) to improve the routing capability. A foil (e.g. copper foil) with thick carrier (e.g. aluminium or copper) carrier instead of a thin foil can be used to reduce warpage that may occur during lamination. In case a laminate is used for the stabilizing structure instead of prepregs, the manufacture of at least one thru-opening of the stabilizing structure may be easier and cheaper because instead of slow and expensive laser cutting, a routing or punching process can be used. This may also reduce a potential risk caused by the carbon that may be formed on the prepregs during laser cutting. The properties of this core layer can also be selected to suit for application (e.g. low CTE, ultralow CTE).
- According to various examples presented herein, a method for manufacturing a chip arrangement may be provided. The method may include disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip.
- The stabilizing structure may include, or may consist of, at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.
- The laminate material may include, or may consist of, a cured laminate material.
- The stabilizing structure may include at least one electrically conductive layer.
- The at least one electrically conductive layer may include a plurality of electrically conductive layers, and wherein the stabilizing structure may include at least one via extending through at least a portion of the stabilizing structure and electrically connecting a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers.
- The stabilizing structure may include a bonding layer configured to attach the stabilizing structure to the carrier, wherein disposing the stabilizing structure and the chip may include the at least one contact next to each other and over the carrier may include attaching the stabilizing structure to the carrier by means of the bonding layer.
- A thickness of the bonding layer of the stabilizing structure may be in the range from about 5 μm to about 150 μm.
- The carrier may include at least one opening, wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier includes disposing the stabilizing structure over the at least one opening of the carrier, wherein a first portion of the bonding layer fills the at least one opening of the carrier, and wherein a second portion of the bonding layer is disposed over at least a part of a surface of the carrier outside the at least one opening.
- Encapsulating the chip and the stabilizing structure may include a lamination process.
- The encapsulating structure may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, a laminate material, an electrically conductive material, and a thermally conductive material.
- The laminate material may include, or may consist of, an uncured laminate material.
- The stabilizing structure may include a thru-opening, wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include disposing the chip within the thru-opening of the stabilizing structure and over the carrier.
- The thru-opening may be formed by means of at least one of a punching process, a routing process, a drilling, an etching process, and a laser structuring process.
- The chip may include a first side facing the carrier and a second side opposite the first side, and wherein the at least one contact of the chip is disposed at the first side of the chip or the second side of the chip, or both.
- Forming the electrically conductive connection to the at least one contact of the chip may include forming at least one opening in the encapsulating structure to expose the at least one contact of the chip.
- Forming the electrically conductive connection to the at least one contact of the chip may include removing the carrier to expose the at least one contact of the chip.
- Forming the electrically conductive connection to the at least one contact of the chip may include a plating process.
- Forming the electrically conductive connection to the at least one contact of the chip may include: disposing a conductive layer over the at least one contact of the chip; forming the electrically conductive connection between the conductive layer and the at least one contact of the chip; and patterning the conductive layer.
- Patterning the conductive layer may include an etching process.
- Forming the electrically conductive connection between the conductive layer and the at least one contact of the chip may include a plating process.
- Disposing the conductive layer over the at least one contact of the chip may include a lamination process.
- Disposing the conductive layer over the at least one contact of the chip may include: disposing an insulating layer between the conductive layer and the at least one contact of the chip.
- Forming the electrically conductive connection between the conductive layer and the at least one contact of the chip may include forming at least one opening in the conductive layer and the insulating layer to expose the at least one contact of the chip.
- The carrier may include a plate and an adhesive layer disposed over the plate, wherein the adhesive layer faces the stabilizing structure and the chip, and wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include disposing the stabilizing structure and the chip over the adhesive layer of the carrier.
- Forming the electrically conductive connection to the at least one contact of the chip may include removing the plate and the adhesive layer of the carrier to expose the at least one contact of the chip.
- Removing the adhesive layer of the carrier may include at least one of dissolving the adhesive layer, peeling off the adhesive layer, and curing the adhesive layer.
- The adhesive layer may include, or may be, a release tape.
- The stabilizing structure may include at least one alignment mark, and wherein disposing the stabilizing structure and the chip including the at least one contact next to each other and over the carrier may include: disposing the stabilizing structure over the carrier; aligning the chip to the stabilizing structure by means of the at least one alignment mark; and disposing the chip next to the stabilizing structure and over the carrier.
- According to various examples presented herein, a chip arrangement may be provided. The chip arrangement may include: a chip; a stabilizing structure disposed next to the chip; and an encapsulating structure encapsulating the chip and the stabilizing structure.
- The stabilizing structure may include at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.
- The laminate material may include a cured laminate material.
- The stabilizing structure may include at least one electrically conductive layer.
- The at least one electrically conductive layer may include a plurality of electrically conductive layers, and wherein the stabilizing structure may include at least one via extending through at least a part of the stabilizing structure and electrically connecting an electrically conductive layer of the plurality of electrically conductive layers to another electrically conductive layer of the plurality of electrically conductive layers.
- The encapsulating structure may include, or may consist of, at least one of a molding material, a prepreg material, a resin material, and a laminate material.
- The laminate material may include, or may consist of, an uncured laminate material.
- Various examples and aspects described in the context of one of the chip arrangements or methods described herein may be analogously valid for the other chip arrangements or methods described herein.
- While various aspects of this disclosure have been particularly shown and described with reference to these aspects of this disclosure, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims. The scope of the disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
Claims (23)
1. A method for manufacturing a chip arrangement, the method comprising:
disposing a stabilizing structure and a chip comprising at least one contact next to each other and over a carrier,
wherein the stabilizing structure comprises a cured laminate material;
encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and
forming an electrically conductive connection to the at least one contact of the chip.
2. The method ofclaim 1 , wherein the stabilizing structure further comprises at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.
3. (canceled)
4. The method ofclaim 1 , wherein the stabilizing structure comprises at least one electrically conductive layer.
5. The method ofclaim 4 , wherein the at least one electrically conductive layer comprises a plurality of electrically conductive layers, and wherein the stabilizing structure comprises at least one via extending through at least a portion of the stabilizing structure and electrically connecting a first electrically conductive layer of the plurality of electrically conductive layers to a second electrically conductive layer of the plurality of electrically conductive layers.
6. The method ofclaim 1 , wherein the stabilizing structure comprises a bonding layer configured to attach the stabilizing structure to the carrier, and wherein disposing the stabilizing structure and the chip comprising the at least one contact next to each other and over the carrier comprises attaching the stabilizing structure to the carrier by means of the bonding layer.
7. The method ofclaim 6 , wherein the carrier comprises at least one opening, and wherein disposing the stabilizing structure and the chip comprising the at least one contact next to each other and over the carrier comprises disposing the stabilizing structure over the at least one opening of the carrier, wherein a first portion of the bonding layer fills the at least one opening of the carrier, and wherein a second portion of the bonding layer is disposed over at least a part of a surface of the carrier outside the at least one opening.
8. The method ofclaim 1 , wherein encapsulating the chip and the stabilizing structure comprises a lamination process.
9. The method ofclaim 1 , wherein the encapsulating structure comprises at least one of a molding material, a prepreg material, a resin material, a laminate material, an electrically conductive material, and a thermally conductive material.
10. The method ofclaim 1 , wherein the stabilizing structure comprises a thru-opening, and wherein disposing the stabilizing structure and the chip comprising the at least one contact next to each other and over the carrier comprises disposing the chip within the thru-opening of the stabilizing structure and over the carrier.
11. The method ofclaim 1 , wherein the chip comprises a first side facing the carrier and a second side opposite the first side, and wherein the at least one contact of the chip is disposed at the first side of the chip or the second side of the chip, or both.
12. The method ofclaim 1 , wherein forming the electrically conductive connection to the at least one contact of the chip comprises forming at least one opening in the encapsulating structure to expose the at least one contact of the chip.
13. The method ofclaim 1 , wherein forming the electrically conductive connection to the at least one contact of the chip comprises removing the carrier to expose the at least one contact of the chip.
14. The method ofclaim 1 , wherein forming the electrically conductive connection to the at least one contact of the chip comprises a plating process.
15. The method ofclaim 1 , wherein forming the electrically conductive connection to the at least one contact of the chip comprises:
disposing a conductive layer over the at least one contact of the chip;
forming the electrically conductive connection between the conductive layer and the at least one contact of the chip; and
patterning the conductive layer.
16. The method ofclaim 15 , wherein forming the electrically conductive connection between the conductive layer and the at least one contact of the chip comprises a plating process.
17. The method ofclaim 15 , wherein disposing the conductive layer over the at least one contact of the chip comprises:
disposing an insulating layer between the conductive layer and the at least one contact of the chip.
18. The method ofclaim 17 , wherein forming the electrically conductive connection between the conductive layer and the at least one contact of the chip comprises forming at least one opening in the conductive layer and the insulating layer to expose the at least one contact of the chip.
19. The method ofclaim 1 , wherein the carrier comprises a plate and an adhesive layer disposed over the plate, wherein the adhesive layer faces the stabilizing structure and the chip, and wherein disposing the stabilizing structure and the chip comprising the at least one contact next to each other and over the carrier comprises disposing the stabilizing structure and the chip over the adhesive layer of the carrier.
20. The method ofclaim 19 , wherein forming the electrically conductive connection to the at least one contact of the chip comprises removing the plate and the adhesive layer of the carrier to expose the at least one contact of the chip.
21. A chip arrangement, comprising:
a chip;
a stabilizing structure disposed next to the chip,
wherein the stabilizing structure comprises a cured laminate material; and
an encapsulating structure encapsulating the chip and the stabilizing structure.
22. The chip arrangement ofclaim 21 , wherein the stabilizing structure further comprises at least one material selected from a group of materials, the group consisting of: a laminate material, a polymer material, a ceramic material, a metal, and a metal alloy.
23. The chip arrangement ofclaim 21 , wherein the stabilizing structure comprises at least one electrically conductive layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/959,795US20150041993A1 (en) | 2013-08-06 | 2013-08-06 | Method for manufacturing a chip arrangement, and a chip arrangement |
| CN201410383467.9ACN104347434B (en) | 2013-08-06 | 2014-08-06 | For manufacturing the method and chip layout of chip layout |
| DE102014111195.8ADE102014111195B4 (en) | 2013-08-06 | 2014-08-06 | Method for producing a chip arrangement and a chip arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/959,795US20150041993A1 (en) | 2013-08-06 | 2013-08-06 | Method for manufacturing a chip arrangement, and a chip arrangement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20150041993A1true US20150041993A1 (en) | 2015-02-12 |
Family
ID=52388986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US13/959,795AbandonedUS20150041993A1 (en) | 2013-08-06 | 2013-08-06 | Method for manufacturing a chip arrangement, and a chip arrangement |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20150041993A1 (en) |
| CN (1) | CN104347434B (en) |
| DE (1) | DE102014111195B4 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150115458A1 (en)* | 2013-10-25 | 2015-04-30 | Infineon Technologies Ag | Semiconductor device and method for manufacturing a semiconductor device |
| US20170018448A1 (en)* | 2015-07-15 | 2017-01-19 | Chip Solutions, LLC | Semiconductor device and method |
| US20170148761A1 (en)* | 2013-08-02 | 2017-05-25 | Siliconware Precision Industries Co., Ltd. | Method of fabricating semiconductor package |
| US10584028B2 (en)* | 2017-05-10 | 2020-03-10 | Infineon Technologies Ag | Method for producing packaged MEMS assemblies at the wafer level, and packaged MEMS assembly |
| US10586746B2 (en) | 2016-01-14 | 2020-03-10 | Chip Solutions, LLC | Semiconductor device and method |
| EP3540765A4 (en)* | 2016-11-11 | 2020-05-13 | SHIN-ETSU ENGINEERING Co., Ltd. | RESIN SEALING DEVICE AND RESIN SEALING METHOD |
| US10714488B2 (en)* | 2017-08-31 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6741419B2 (en)* | 2015-12-11 | 2020-08-19 | 株式会社アムコー・テクノロジー・ジャパン | Semiconductor package and manufacturing method thereof |
| CN105914157A (en)* | 2016-04-28 | 2016-08-31 | 合肥祖安投资合伙企业(有限合伙) | Chip package technology and chip package structure |
| CN106601634B (en)* | 2016-08-25 | 2021-04-02 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging process and chip packaging structure |
| CN106601635B (en)* | 2016-08-25 | 2019-07-09 | 合肥祖安投资合伙企业(有限合伙) | Chip package process and chip-packaging structure |
Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5497033A (en)* | 1993-02-08 | 1996-03-05 | Martin Marietta Corporation | Embedded substrate for integrated circuit modules |
| US5882957A (en)* | 1997-06-09 | 1999-03-16 | Compeq Manufacturing Company Limited | Ball grid array packaging method for an integrated circuit and structure realized by the method |
| US20040020040A1 (en)* | 2002-08-02 | 2004-02-05 | Matrics, Inc. | Method and system for forming a die frame for transferring dies therewith |
| US20050224988A1 (en)* | 2002-01-31 | 2005-10-13 | Imbera Electronics Oy | Method for embedding a component in a base |
| US7070590B1 (en)* | 1996-07-02 | 2006-07-04 | Massachusetts Institute Of Technology | Microchip drug delivery devices |
| US20060278967A1 (en)* | 2003-04-01 | 2006-12-14 | Tuominen Risto | Method for manufacturing an electronic module and an electronic module |
| US20070126122A1 (en)* | 2004-05-06 | 2007-06-07 | Michael Bauer | Semiconductor device with a wiring substrate and method for producing the same |
| US20080116569A1 (en)* | 2006-11-16 | 2008-05-22 | Cheng-Hung Huang | Embedded chip package with improved heat dissipation performance and method of making the same |
| US20080224293A1 (en)* | 2007-03-12 | 2008-09-18 | Keong Bun Hin | Method And Apparatus For Fabricating A Plurality Of Semiconductor Devices |
| US20080261338A1 (en)* | 2004-06-15 | 2008-10-23 | Imbera Electronics Oy | Method For Manufacturing an Electronics Module Comprising a Component Electrically Connected to a Conductor-Pattern Layer |
| US20090273075A1 (en)* | 2008-05-05 | 2009-11-05 | Infineon Technologies Ag | Semiconductor device and manufacturing of the semiconductor device |
| US20100013081A1 (en)* | 2008-07-18 | 2010-01-21 | United Test And Assembly Center Ltd. | Packaging structural member |
| US20110198762A1 (en)* | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
| US20120112355A1 (en)* | 2010-08-27 | 2012-05-10 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die |
| US20120127689A1 (en)* | 2006-08-31 | 2012-05-24 | Ati Technologies Ulc | Integrated package circuit with stiffener |
| US20120181073A1 (en)* | 2011-01-14 | 2012-07-19 | Harris Corporation | Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods |
| US20120217627A1 (en)* | 2011-02-24 | 2012-08-30 | Unimicron Technology Corporation | Package structure and method of fabricating the same |
| US20130187174A1 (en)* | 2012-01-24 | 2013-07-25 | Michael A. Tischler | Light-emitting dies incorporating wavelength-conversion materials and related methods |
| US8617927B1 (en)* | 2011-11-29 | 2013-12-31 | Hrl Laboratories, Llc | Method of mounting electronic chips |
| US20150060872A1 (en)* | 2013-08-29 | 2015-03-05 | Infineon Technologies Austria Ag | Encapsulated Semiconductor Device |
| US20150131247A1 (en)* | 2013-11-11 | 2015-05-14 | Infineon Technologies Ag | Electrically conductive frame on substrate for accommodating electronic chips |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010042567B3 (en)* | 2010-10-18 | 2012-03-29 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for manufacturing a chip package and chip package |
- 2013
- 2013-08-06USUS13/959,795patent/US20150041993A1/ennot_activeAbandoned
- 2014
- 2014-08-06DEDE102014111195.8Apatent/DE102014111195B4/enactiveActive
- 2014-08-06CNCN201410383467.9Apatent/CN104347434B/enactiveActive
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5497033A (en)* | 1993-02-08 | 1996-03-05 | Martin Marietta Corporation | Embedded substrate for integrated circuit modules |
| US7070590B1 (en)* | 1996-07-02 | 2006-07-04 | Massachusetts Institute Of Technology | Microchip drug delivery devices |
| US5882957A (en)* | 1997-06-09 | 1999-03-16 | Compeq Manufacturing Company Limited | Ball grid array packaging method for an integrated circuit and structure realized by the method |
| US20050224988A1 (en)* | 2002-01-31 | 2005-10-13 | Imbera Electronics Oy | Method for embedding a component in a base |
| US20040020040A1 (en)* | 2002-08-02 | 2004-02-05 | Matrics, Inc. | Method and system for forming a die frame for transferring dies therewith |
| US20060278967A1 (en)* | 2003-04-01 | 2006-12-14 | Tuominen Risto | Method for manufacturing an electronic module and an electronic module |
| US20070126122A1 (en)* | 2004-05-06 | 2007-06-07 | Michael Bauer | Semiconductor device with a wiring substrate and method for producing the same |
| US20080261338A1 (en)* | 2004-06-15 | 2008-10-23 | Imbera Electronics Oy | Method For Manufacturing an Electronics Module Comprising a Component Electrically Connected to a Conductor-Pattern Layer |
| US20120127689A1 (en)* | 2006-08-31 | 2012-05-24 | Ati Technologies Ulc | Integrated package circuit with stiffener |
| US20080116569A1 (en)* | 2006-11-16 | 2008-05-22 | Cheng-Hung Huang | Embedded chip package with improved heat dissipation performance and method of making the same |
| US20080224293A1 (en)* | 2007-03-12 | 2008-09-18 | Keong Bun Hin | Method And Apparatus For Fabricating A Plurality Of Semiconductor Devices |
| US20090273075A1 (en)* | 2008-05-05 | 2009-11-05 | Infineon Technologies Ag | Semiconductor device and manufacturing of the semiconductor device |
| US20100013081A1 (en)* | 2008-07-18 | 2010-01-21 | United Test And Assembly Center Ltd. | Packaging structural member |
| US20110198762A1 (en)* | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
| US20120112355A1 (en)* | 2010-08-27 | 2012-05-10 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die |
| US20120181073A1 (en)* | 2011-01-14 | 2012-07-19 | Harris Corporation | Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods |
| US20120217627A1 (en)* | 2011-02-24 | 2012-08-30 | Unimicron Technology Corporation | Package structure and method of fabricating the same |
| US8617927B1 (en)* | 2011-11-29 | 2013-12-31 | Hrl Laboratories, Llc | Method of mounting electronic chips |
| US20130187174A1 (en)* | 2012-01-24 | 2013-07-25 | Michael A. Tischler | Light-emitting dies incorporating wavelength-conversion materials and related methods |
| US20150060872A1 (en)* | 2013-08-29 | 2015-03-05 | Infineon Technologies Austria Ag | Encapsulated Semiconductor Device |
| US20150131247A1 (en)* | 2013-11-11 | 2015-05-14 | Infineon Technologies Ag | Electrically conductive frame on substrate for accommodating electronic chips |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170148761A1 (en)* | 2013-08-02 | 2017-05-25 | Siliconware Precision Industries Co., Ltd. | Method of fabricating semiconductor package |
| US20150115458A1 (en)* | 2013-10-25 | 2015-04-30 | Infineon Technologies Ag | Semiconductor device and method for manufacturing a semiconductor device |
| US9613930B2 (en)* | 2013-10-25 | 2017-04-04 | Infineon Technologies Ag | Semiconductor device and method for manufacturing a semiconductor device |
| US20170018448A1 (en)* | 2015-07-15 | 2017-01-19 | Chip Solutions, LLC | Semiconductor device and method |
| US10332775B2 (en) | 2015-07-15 | 2019-06-25 | Chip Solutions, LLC | Releasable carrier and method |
| US10354907B2 (en) | 2015-07-15 | 2019-07-16 | Chip Solutions, LLC | Releasable carrier method |
| US10586746B2 (en) | 2016-01-14 | 2020-03-10 | Chip Solutions, LLC | Semiconductor device and method |
| EP3540765A4 (en)* | 2016-11-11 | 2020-05-13 | SHIN-ETSU ENGINEERING Co., Ltd. | RESIN SEALING DEVICE AND RESIN SEALING METHOD |
| US10584028B2 (en)* | 2017-05-10 | 2020-03-10 | Infineon Technologies Ag | Method for producing packaged MEMS assemblies at the wafer level, and packaged MEMS assembly |
| US10793429B2 (en) | 2017-05-10 | 2020-10-06 | Infineon Technologies Ag | Method for producing packaged MEMS assemblies at the wafer level, and packaged MEMS assembly |
| US10714488B2 (en)* | 2017-08-31 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102014111195B4 (en) | 2023-11-02 |
| DE102014111195A1 (en) | 2015-02-12 |
| CN104347434A (en) | 2015-02-11 |
| CN104347434B (en) | 2018-01-19 |
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Legal Events
| Date | Code | Title | Description |
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| AS | Assignment | Owner name:INFINEON TECHNOLOGIES AG, GERMANY Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PALM, PETTERI;REEL/FRAME:030946/0128 Effective date:20130806 | |
| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |