US20140306286A1 - Tapered fin field effect transistor - Google Patents

Abstract

A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

Description

BACKGROUND
• The present disclosure relates to a semiconductor structure, and particularly to fin field effect transistors including a tapered vertical cross-sectional area and a method of manufacturing the same.
• As scaling of complementary metal oxide semiconductor (CMOS) devices continues, control of the channel through conventional means such as doping profile control and gate dielectric scaling becomes increasingly challenging. A few categories of devices such as fin field effect transistors, trigate transistors, and nanowire transistors circumvent the short channel behavior due to scaling.
BRIEF SUMMARY
• A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.
• According to an aspect of the present disclosure, a semiconductor structure includes a semiconductor fin located on a substrate and laterally extending along a lengthwise direction. The semiconductor fin has a substantially same vertical cross-sectional shape that includes a vertically tapered portion in which a width of sidewalls increases with a vertical distance between a horizontal interface between the substrate and the semiconductor fin.
• According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. A fin-defining mask structure is formed over a semiconductor layer that is located on a substrate. A semiconductor fin is formed, which laterally extends along a lengthwise direction with a substantially rectangular vertical cross-sectional shape that adjoins a horizontal interface with a top surface of the substrate. An etch residue material with a non-uniform thickness profile covers sidewalls of the semiconductor fin. The substantially rectangular vertical cross-sectional shape is modified into a substantially same vertical cross-sectional shape that includes a vertically tapered portion. In the vertically tapered portion, a width of sidewalls increases with a vertical distance between a horizontal interface between the substrate and the semiconductor fin. The modification of the substantially rectangular vertical cross-sectional shape can be performed by a lateral etch of the semiconductor fin while a thickness profile of the etch residue material is non-uniform.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
• FIG. 1A is a top-down view of a first exemplary semiconductor structure after formation of an optional dielectric liner layer and a plurality of fin-defining mask structures according to a first embodiment of the present disclosure.
• FIG. 1B is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 1A.
• FIG. 1C is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 1A.
• FIG. 2A is a top-down view of the first exemplary semiconductor structure after formation of semiconductor fins having substantially vertical sidewalls after a first anisotropic etch according to the first embodiment of the present disclosure.
• FIG. 2B is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 2A.
• FIG. 2C is a vertical cross-sectional view of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 2A.
• FIG. 3A is a top-down view of the first exemplary semiconductor structure during a second anisotropic etch process, in which lower portions of the sidewalls of the semiconductor fins are physically exposed according to the first embodiment of the present disclosure.
• FIG. 3B is a vertical cross-sectional view of the selected region of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 3A.
• FIG. 3C is a vertical cross-sectional view of the selected region of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 3A.
• FIG. 4A is a top-down view of the first exemplary semiconductor structure after the second anisotropic etch that laterally etches the lower portions of the sidewalls of the semiconductor fins according to the first embodiment of the present disclosure.
• FIG. 4B is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 4A.
• FIG. 4C is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 4A.
• FIG. 5A is a top-down view of the first device region of the first exemplary semiconductor structure after formation of a gate dielectric, a gate electrode, and a gate spacer according to the first embodiment of the present disclosure.
• FIG. 5B is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 5A.
• FIG. 5C is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 5A.
• FIG. 6A is a top-down view of the first exemplary semiconductor structure after formation of a raised source region and a raised drain region according to the first embodiment of the present disclosure.
• FIG. 6B is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 6A.
• FIG. 6C is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 6A.
• FIG. 7A is a top-down view of the first device region of the first exemplary semiconductor structure after formation of a contact level dielectric layer and contact via structures according to the first embodiment of the present disclosure.
• FIG. 7B is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 7A.
• FIG. 7C is a vertical cross-sectional view of the first device region of the first exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 7A.
• FIG. 8 is a vertical cross-sectional view of a variation of the first exemplary semiconductor structure according to the first embodiment of the present disclosure.
• FIG. 9A is a top-down view of a second exemplary semiconductor structure after formation of a contact level dielectric layer and contact via structures according to a second embodiment of the present disclosure.
• FIG. 9B is a vertical cross-sectional view of the first device region of the second exemplary semiconductor structure along the vertical plane B-B′ ofFIG. 9A.
• FIG. 9C is a vertical cross-sectional view of the first device region of the second exemplary semiconductor structure along the vertical plane C-C′ ofFIG. 9A.
• FIG. 10 is a vertical cross-sectional view of a variation of the second exemplary semiconductor structure according to the second embodiment of the present disclosure.
DETAILED DESCRIPTION
• As stated above, the present disclosure relates to fin field effect transistors including a tapered vertical cross-sectional area and a method of manufacturing the same. Aspects of the present disclosure are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. The drawings are not necessarily drawn to scale.
• Referring toFIGS. 1A-1C, a first exemplary semiconductor structure according to a first embodiment of the present disclosure includes a vertical stack of ahandle substrate10, and aninsulator layer20, and asemiconductor layer30L.
• Thehandle substrate10 can include a semiconductor material, an insulator material, or a conductive material. Thehandle substrate10 provides mechanical support to theinsulator layer20 and thesemiconductor layer30L. Thehandle substrate10 can be single crystalline, polycrystalline, or amorphous. The thickness of thehandle substrate10 can be from 50 microns to 2 mm, although lesser and greater thicknesses can also be employed.
• Theinsulator layer20 includes a dielectric material. Non-limiting examples of theinsulator layer20 include silicon oxide, silicon nitride, sapphire, and combinations or stacks thereof. The thickness of theinsulator layer20 can be, for example, from 100 nm to 100 microns, although lesser and greater thicknesses can also be employed. Thehandle substrate10 and theinsulator layer20 collectively functions as a substrate on which thesemiconductor layer30L is located.
• Thesemiconductor layer30L includes a semiconductor material. The semiconductor material of thesemiconductor layer30L can be an elemental semiconductor material, an alloy of at least two elemental semiconductor materials, a compound semiconductor material, or a combination thereof. Thesemiconductor layer30L can be intrinsic or doped with electrical dopants of p-type or n-type. The semiconductor material of thesemiconductor layer30L can be single crystalline or polycrystalline. In one embodiment, thesemiconductor layer30L can be a single crystalline semiconductor layer. In one embodiment, the semiconductor material of thesemiconductor layer30L can be single crystalline silicon. The thickness of thesemiconductor layer30L can be, for example, from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed.
• An optionaldielectric liner layer40L can be formed on the top surface of thesemiconductor layer30L. The optionaldielectric liner layer40L includes a dielectric material, which can be, for example, silicon oxide, silicon oxynitride, a dielectric metal oxide, or a combination thereof. The optionaldielectric liner layer40L can be formed, for example, by chemical vapor deposition (CVD) or conversion of a topmost portion of thesemiconductor layer30L by thermal oxidation, thermal nitridation, plasma oxidation, plasma nitridation, or a combination thereof. In one embodiment, theoptional dielectric liner40L can be thermal oxide of the semiconductor material of thesemiconductor layer30L. The thickness of the optionaldielectric liner layer40L can be from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed.
• A plurality of fin-definingmask structures42 is formed over thesemiconductor layer30L. Each plurality of fin-definingmask structures42 can be formed directly on the optionaldielectric liner layer40L, if present. The plurality of fin-definingmask structures42 is a set of mask structures that cover the regions of thesemiconductor layer30L that are subsequently converted into semiconductor fins. Thus, the plurality of fin-definingmask structures42 is subsequently employed to define the area of the semiconductor fins. The plurality of fin-definingmask structures42 can include a dielectric material such as silicon nitride, silicon oxide, and silicon oxynitride. In one embodiment, the plurality of fin-definingmask structures42 can includes a material selected from an undoped silicate glass (USG), a fluorosilicate glass (FSG), a phosphosilicate glass (PSG), a borosilicate glass (BSG), and a borophosphosilicate glass (BPSG).
• The plurality of fin-definingmask structures42 can be formed, for example, by depositing a planar dielectric material layer and lithographically patterning the dielectric material layer. The planar dielectric material layer can be deposited, for example, by chemical vapor deposition (CVD). The thickness of the planar dielectric material layer can be from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed.
• The planar dielectric material layer can be subsequently patterned to form the plurality of fin-definingmask structures42. In one embodiment, each fin-definingmask structure42 can laterally extend along a lengthwise direction. Further, each fin-definingmask structure42 can have a pair of sidewalls that are separated along a widthwise direction, which is perpendicular to the lengthwise direction. In one embodiment, each fin-definingmask structure42 can have a rectangular horizontal cross-sectional area. In one embodiment, each fin-definingmask structures42 can have the same width w.
• Referring toFIGS. 2A-2C, thesemiconductor layer30L is patterned to form a plurality ofsemiconductor fins30. The formation of the plurality ofsemiconductor fins30 can be performed employing a first anisotropic etch process, which can be a reactive ion etch. The plurality ofsemiconductor fins30 has substantially same horizontal cross-sectional shapes as the fin-definingmask structures42. As used herein, two shapes are “substantially same” if the differences between the two shapes is due to atomic level roughness and does not exceed 2 nm. Thesemiconductor layer30L is etched employing the first anisotropic etch process in which the plurality of fin-definingmask structures42 is employed as an etch mask. The plurality ofsemiconductor fins30 is formed on theinsulator layer20. In one embodiment, the plurality ofsemiconductor fins30 can include a single crystalline semiconductor material, and can have the same width w.
• The optionaldielectric liner layer40L, if present, is patterned into at least one optionaldielectric liner portion40. The sidewalls of each optionaldielectric liner portion40 can be vertically coincident with sidewalls of an overlying fin-definingmask structure42 and with sidewalls of anunderlying semiconductor fin30. As used herein, a first surface and a second surface are vertically coincident if the first surface and the second surface are within a same vertical plane.
• The plurality ofsemiconductor fins30 has substantially vertical sidewalls. As used herein, a surface is “substantially vertical” if the difference between the surface and a vertical surface is due to atomic level roughness and does not exceed 2 nm. Each of the plurality ofsemiconductor fins30 can be a single crystalline semiconductor fin that laterally extends along a lengthwise direction. As used herein, a “lengthwise direction” is a horizontal direction along which an object extends the most. A “widthwise direction” is a horizontal direction that is perpendicular to the lengthwise direction.
• Each of the plurality ofsemiconductor fins30 extends along the lengthwise direction with a substantially rectangular vertical cross-sectional shape. As used herein, a “substantially rectangular shape” is a shape that differs from a rectangular shape only due to atomic level roughness that does not exceed 2 nm. The substantially rectangular vertical cross-sectional shape is a shape within a plane including a vertical direction and a widthwise direction. Thehandle substrate10 and theinsulator layer20 collectively functions as a substrate on which the plurality ofsemiconductor fins30 is located. The substantially rectangular vertical cross-sectional shape adjoins a horizontal interface with a top surface of the combination of theinsulator layer20 and thehandle substrate10, i.e., the substrate (10,20).
• An etch residue material with a non-uniform thickness profile covers sidewalls of eachsemiconductor fin30. Specifically, an etchresidue material portion43 having a non-uniform thickness profile is formed on each sidewall (shown inFIG. 2C) that extends along the lengthwise direction and on each end wall (shown inFIG. 2B) that extends along the widthwise direction. As used herein, the sidewalls of the plurality ofsemiconductor fins30 that extend along the widthwise direction are referred to as “end walls.” The end walls of the plurality ofsemiconductor fins30 are located at the lengthwise end of eachsemiconductor fin30. In one embodiment, the non-uniform thickness profile can provide an increasing thickness of the etch residue material with a vertical distance from a horizontal interface between the plurality ofsemiconductor fins30 and theinsulator layer20.
• In one embodiment, an etch chemistry including O₂, HBr, CH₂F₂, and SF₆can be employed during the first anisotropic etch that forms the plurality ofsemiconductor fins30 and the etchresidue material portions43. In a non-limiting example, if the substrate (10,20) is a circular substrate having a diameter of 300 mm, the first anisotropic etch can be performed in a process chamber by a two-step anisotropic etch process.
• In the first step of the first anisotropic etch process, a combination of gases including CH₂F₂gas at a flow rate in a range from 15 sccm to 60 sccm, SF₆gas at a flow rate in a range from 5 sccm to 20 sccm, Cl₂gas at a flow rate in a range from 22.5 sccm to 90 sccm, N₂gas at a flow rate in a range from 22.5 sccm to 90 sccm, and He gas at a flow rate in a range from 100 sccm to 400 sccm can be flowed into a reactive ion etch process chamber. The pressure of the process chamber can be in a range from 2.5 mTorr to 10 mTorr, and the radio frequency (RF) power applied by the RF source can be in a range from 225 W to 900 W, and the RF bias power can be in a range from 30 W to 120 W.
• In the second step of the first anisotropic etch process, a combination of gases including O₂and a bromine-including gas such as Br₂, HBr, CH₃Br, CH₂Br₂, CHBr₃, and other hydrobromocarbon gases can be employed.
• In a non-limiting example, if the substrate (10,20) is a circular substrate having a diameter of 300 mm, the second step of the first anisotropic etch can be performed in a process chamber by flowing a combination of gases including HBr gas at a flow rate in a range from 150 sccm to 600 sccm and O₂gas at a flow rate in a range from 7.5 sccm to 30 sccm. The pressure of the process chamber can be in a range from 2 mTorr to 8 mTorr, and the radio frequency (RF) power applied by the RF source can be in a range from 200 W to 800 W, and the RF bias power can be in a range from 45 W to 180 W. The second step of the first anisotropic etch can have a fixed duration, which can be in a range from 7.5 second to 30 seconds. Various adjustments can be made to the etch chemistry, the pressure, and the RF powers as needed. The second step of the first anisotropic etch process can be an endpointed etch that terminate within a predetermined overetch time after detection of the top surface of theinsulator layer20. If the plurality ofsemiconductor fins30 includes single crystalline silicon, the average etch rate of the first anisotropic etch process can be in a range from 12.5 nm/sec to 50 nm/sec. Various adjustments can be made to the etch chemistry, the pressure, and the RF powers as needed.
• In one embodiment, the etch residue material can include a compound formed by a chemical reaction of an etchant gas employed in the first anisotropic etch process and the dielectric material of the plurality of fin-definingmask structures42. The etch residue is formed by interaction of the difluoromethane gas and the semiconductor material on the sidewalls of the plurality ofsemiconductor fins30. The etch residue can include a compound including silicon atoms, carbon atoms, hydrogen atoms, and fluorine atoms, and passivates the sidewalls of the plurality ofsemiconductor fins30, thereby preventing a lateral etch of the plurality ofsemiconductor fins30 during the first anisotropic etch step. The thickness of the etch residue is non-uniform, and increases with a vertical distance from the top surface of the substrate (10,20) because the upper portions of the plurality ofsemiconductor fins30 are exposed to the etch gases for a longer duration of time than the lower portions of the plurality ofsemiconductor fins30. The maximum thickness of the etch residue, which typically occurs at the topmost portions of the plurality ofsemiconductor fins30, can be from 1.0 nm to 5.0 nm, and can be typically in a range from 1.5 nm to 3.0 nm. The minimum thickness of the etch residue occurs at the bottommost portions of the plurality ofsemiconductor fins30, and can be in a range from 0.5 nm to 1.5 nm, although lesser and greater thicknesses can also be employed.
• Referring toFIGS. 3A-3C, first exemplary semiconductor structure is shown after partially performing a second anisotropic etch process, i.e., during the second anisotropic etch process. The second anisotropic etch is performed to physically expose lower portions of the sidewalls and end walls of the plurality ofsemiconductor fins30. The second anisotropic etch process is less anisotropic than the first anisotropic etch process, and includes an isotropic etch component. The isotropic etch component of the second anisotropic etch laterally thins the etchresidue material portions43. Portions of sidewalls of the plurality ofsemiconductor fins30 become physically exposed in regions at which the thickness of the etchresidue material portions43 is less than the cumulative etch distance of the second anisotropic etch, while remaining portions of the etchresidue material portions43 cover underlying portions of the sidewalls of the plurality ofsemiconductor fins30. Specifically, the second anisotropic etch can partially remove the etchresidue material portions43 such that sidewall surfaces (and end wall surfaces) of the plurality ofsemiconductor fins30 are physically exposed at a lower portion of eachsemiconductor fin30, while a remaining portion of each etchresidue material portion43 covers an upper portion of eachsemiconductor fins30.
• In one embodiment, the second anisotropic etch process can be a dry etch process employing at least one bromine-containing gas and oxygen gas. In a non-limiting example, if the substrate (10,20) is a circular substrate having a diameter of 300 mm, the second anisotropic etch can be performed in a process chamber by flowing a combination of gases including HBr gas at a flow rate in a range from 175 sccm to 700 sccm, O₂gas at a flow rate in a range from 6 sccm to 24 sccm, helium gas at a flow rate in a range from 100 sccm to 400 sccm. The pressure of the process chamber can be in a range from 37.5 mTorr to 150 mTorr, and the radio frequency (RF) power applied by the RF source can be in a range from 200 W to 800 W, and the RF bias power can be in a range from 45 W to 180 W. The second anisotropic etch can have a fixed duration, which can be in a range from 20 second to 80 seconds. Various adjustments can be made to the etch chemistry, the pressure, and the RF powers as needed.
• Referring toFIGS. 4A-4C, the second anisotropic etch is continued to laterally etch the physically exposed lower portions of the sidewalls (and end walls) of the plurality ofsemiconductor fins30. The substantially rectangular vertical cross-sectional shape of each of the plurality ofsemiconductor fins30 is modified into a substantially same vertical cross-sectional shape. The substantially same vertical cross-sectional shape includes a vertically tapered portion in which a width of sidewalls increases with a vertical distance between the horizontal interface between the substrate (10,20) and the plurality ofsemiconductor fins30. The lateral etch of the plurality ofsemiconductor fins30 is performed while the thickness profile of the etchresidue material portions43 remains non-uniform. In one embodiment, an upper portion of eachsemiconductor fin30 can be protected from the lateral etch by a remainder of an etchresidue material portion43 throughout the lateral etch.
• The substantially same vertical cross-sectional shape can have a mirror symmetry around a vertical axis SA passing through the geometrical center of the substantially same vertical cross-sectional shape. The vertical axis SA is the symmetry axis of the minor symmetry.
• The substantially same vertical cross-sectional shape can further include a rectangular portion having the same width as the maximum width of the vertically tapered portion and adjoining an upper end of the vertically tapered portion. In addition, the substantially same vertical cross-sectional shape can further include another rectangular portion having a same width as the minimum width of the vertically tapered portion and adjoining a lower end of the vertically tapered portion. In one embodiment, the sidewalls of the vertically tapered portion of eachsemiconductor fin30 can be concave sidewalls.
• During the lateral etch, i.e., the second anisotropic etch, end walls of the plurality ofsemiconductor fins30 having the substantially rectangular vertical cross-sectional shape within vertical planes perpendicular to the lengthwise direction are laterally etched in the same manner as the substantially vertical sidewalls of the plurality ofsemiconductor fins30 that extend along the lengthwise direction. In this case, a vertical cross-sectional shape of eachsemiconductor fin30 after the lateral etch along a vertical plane including the lengthwise direction can include a pair of tapered edges such that each of the tapered edges is congruent with a tapered edge of the substantially same vertical cross-sectional shape that is a cross-sectional shape of asemiconductor fin30 along a plane perpendicular to the lengthwise direction.
• The first exemplary semiconductor structure includes at least onesemiconductor fin30 that is located on the substrate (10,20). Each of the at least onesemiconductor fin30 laterally extends along the lengthwise direction with the substantially same vertical cross-sectional shape. A vertical cross-sectional shape of eachsemiconductor fin30 along a vertical plane including the lengthwise direction (e.g., as inFIG. 4B) includes a pair of tapered edges. Each of the tapered edges within a vertical cross-sectional shape along a vertical plane including the lengthwise direction is congruent with a tapered edge of the substantially same vertical cross-sectional shape, which is a cross-sectional shape along a plane including the widthwise direction (e.g., as inFIG. 4C). As used herein, a two-dimensional shape is congruent with another two-dimensional shape if a combination of rotation and translation that matches the two two-dimensional shapes exists.
• With the plurality ofsemiconductor fins30, eachsemiconductor fin30 is laterally spaced from anothersemiconductor fin30, extends in directions that are parallel to the lengthwise direction, and has the substantially same vertical cross-sectional shape.
• Referring toFIGS. 5A-5C, the optionaldielectric liner portions40 and the fin-definingmask structures42 can be removed selective to the plurality ofsemiconductor fins30. The removal of the optionaldielectric liner portions40 and the fin-definingmask structures42 can be effected by an etch, which can be a wet etch or a dry etch. The optionaldielectric liner portions40 and the fin-definingmask structures42 can be removed by a wet etch that removes dielectric materials selective to semiconductor materials. For example, a wet etch employing hot phosphoric acid can be employed to remove silicon nitride and/or a wet etch employing hydrofluoric acid can be employed to remove silicon oxide.
• A stack of agate dielectric50, agate electrode52, and a gate cap dielectric58 can be formed across the plurality ofsemiconductor fins30 such that the stack (50,52,58) straddles each of the plurality ofsemiconductor fins30. Thegate dielectric50 is in contact with a top surface and sidewall surfaces of eachsemiconductor fin30. Thegate electrode52 is in contact with thegate dielectric50.
• The formation of thegate dielectric50 and thegate electrode52 can be effected, for example, by deposition of a stack of a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer, and by subsequent patterning of the gate cap dielectric layer, the gate electrode layer, and the gate dielectric layer. The patterning of the gate cap dielectric layer and the gate electrode layer can be performed employing a combination of lithographic methods and at least one anisotropic etch. The patterning of the gate dielectric layer can be performed by an isotropic etch that is selective to the semiconductor material of the plurality ofsemiconductor fins30.
• Referring toFIGS. 6A-6C, a raisedsource region144 and a raiseddrain region146 can be formed, for example, by selective deposition of a semiconductor material. The raisedsource region144 and the raiseddrain region146 are doped with electrical dopants, which can be p-type dopants or n-type dopants. If the plurality ofsemiconductor fins30 is doped with dopants of a first conductivity type, the raisedsource region144 and the raiseddrain region146 are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.
• The doping of the raisedsource region144 and the raiseddrain region146 can be performed by in-situ doping, i.e., during deposition of the raisedsource region144 and the raiseddrain region146, or by ex-situ doping, i.e., after deposition of the raisedsource region144 and the raiseddrain region146. Exemplary methods for performing the ex-situ doping include, but are not limited to, ion implantation, plasma doping, and outdiffusion of dopants from a disposable dopant-including material that is temporarily deposited and subsequently removed.
• A portion of eachsemiconductor fin30 that underlies the raisedsource region144 is converted into asource region44, and a portion of eachsemiconductor fin30 that underlies the raiseddrain region146 is converted into adrain region46. Thesource regions44 and thedrain regions46 have the same type of doping as the raisedsource region144 and the raiseddrain region146. The doping of thesource regions44 and thedrain regions46 can be performed by ion implantation prior to, or after, formation of the raisedsource region144 and the raiseddrain region146, and/or by outdiffusion of dopants from the raisedsource region144 and the raiseddrain region146.
• The portion of eachsemiconductor fin30 that is not converted into asource region44 or adrain region46 constitutes abody region30B. Thebody regions30B collectively function as a body of a field effect transistor. Thesource regions44 and the raisedsource region144 collectively function as a source of the field effect transistor. Thedrain regions46 and the raiseddrain region146 collectively function as a drain of the field effect transistor.
• The raisedsource region144 is in contact with thesource regions44 and is located outside the plurality of semiconductor fins (30B,44,46). The raiseddrain region146 is in contact with thedrain regions46 and is located outside the semiconductor fins (30B,44,46).
• In one embodiment, the plurality ofsemiconductor fins30 can be a plurality of single crystalline semiconductor fins, and the raisedsource region144 and the raiseddrain region146 can be formed by selective epitaxy such that the raisedsource region144 and the raiseddrain region146 are in epitaxial alignment with the plurality of single crystalline semiconductor fins.
• Referring toFIGS. 7A-7C, a contact leveldielectric layer80 and various contact via structures (82,84,86) can be formed to provide electrical contact to the combination of thesource regions44 and the raisedsource region144, the combination of thedrain regions46 and the raiseddrain region146, and thegate electrode52 of the field effect transistor.
• Referring toFIG. 8, a variation of the first exemplary semiconductor structure can be derived from the first exemplary semiconductor structure by employing a replacement gate integration scheme. For example, a disposable gate stack can be formed in lieu of the stack of thegate dielectric50, thegate electrode52, and thegate cap dielectric58. After formation of agate spacer56,source regions44,drain regions46,body region30B, a raisedsource region144, and a raiseddrain region146 are formed. Subsequently, aplanarization dielectric layer170 is deposited and planarized. The disposable gate stack is removed to form a gate cavity, in which areplacement gate dielectric150 having a U-shaped vertical cross-sectional shape and areplacement gate electrode152 are formed. A contact leveldielectric layer180 can be subsequently formed above theplanarization dielectric layer170, and various contact via structures (82,84,86) are formed therethrough to provide electrical contact to the combination of thesource regions44 and the raisedsource region144, the combination of thedrain regions46 and the raiseddrain region146, and thegate electrode52 of the field effect transistor.
• Referring toFIGS. 9A-9C, a second exemplary semiconductor structure according to a second embodiment of the present disclosure can be derived from the first exemplary semiconductor structure by altering the second anisotropic etch. Specifically, a lateral etch that simultaneously removes the material of the etchresidue material portions43 and the semiconductor material of the plurality ofsemiconductor fins30 can be employed in lieu of the second anisotropic etch processes employed at the processing steps ofFIGS. 3A-3C and4A-4C. The lateral etch can be an anisotropic etch including an isotropic etch component or an isotropic etch.
• In one embodiment, the removal of the material of the etchresidue material portions43 can be performed such that the sidewall surfaces (and end surfaces) of the plurality ofsemiconductor fins30 is performed gradually from bottom to top of the plurality ofsemiconductor fins30, and each of the plurality ofsemiconductor fins30 has a substantially rectangular vertical cross-sectional shape of a trapezoid in vertical planes that are perpendicular to the lengthwise direction of the plurality ofsemiconductor fins30, i.e., in vertical planes that include a vertical direction and a widthwise direction. In one embodiment, a bottom side of the trapezoid can coincide with the horizontal interface between theinsulator layer20 and thesemiconductor fins30, and a top side of the trapezoid can coincide with a topmost surface of asemiconductor fin30.
• Each substantially same vertical cross-sectional shape can have a mirror symmetry around a vertical axis passing through the geometrical center of the substantially same vertical cross-sectional shape. In one embodiment, end walls of eachsemiconductor fin30 can have the substantially rectangular vertical cross-sectional shape within vertical planes perpendicular to the lengthwise direction are laterally etched during the lateral etch. A vertical cross-sectional shape of the semiconductor fin after the lateral etch along a vertical plane including the lengthwise direction can include a pair of tapered edges, wherein each of the tapered edges is congruent with a tapered edge of the substantially same vertical cross-sectional shape.
• Referring toFIG. 10, a variation of the second exemplary semiconductor structure can be derived from the second exemplary semiconductor structure by employing a replacement gate integration scheme. For example, a disposable gate stack can be formed in lieu of the stack of thegate dielectric50, thegate electrode52, and thegate cap dielectric58. After formation of agate spacer56,source regions44,drain regions46,body region30B, a raisedsource region144, and a raiseddrain region146 are formed. Subsequently, aplanarization dielectric layer170 is deposited and planarized. The disposable gate stack is removed to form a gate cavity, in which areplacement gate dielectric150 having a U-shaped vertical cross-sectional shape and areplacement gate electrode152 are formed. A contact leveldielectric layer180 can be subsequently formed above theplanarization dielectric layer170, and various contact via structures (82,84,86) are formed therethrough to provide electrical contact to the combination of thesource regions44 and the raisedsource region144, the combination of thedrain regions46 and the raiseddrain region146, and thegate electrode52 of the field effect transistor.
• While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the embodiments described herein can be implemented individually or in combination with any other embodiment unless expressly stated otherwise or clearly incompatible. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.

Claims (13)

1. A semiconductor structure comprising a semiconductor fin located on a substrate and laterally extending along a lengthwise direction with a substantially same vertical cross-sectional shape that includes a vertically tapered portion in which a width of sidewalls increases with a vertical distance between a horizontal interface between said substrate and said semiconductor fin.

2. The semiconductor structure ofclaim 1, wherein said substantially same vertical cross-sectional shape has a mirror symmetry around a vertical axis passing through a geometrical center of said substantially same vertical cross-sectional shape.

3. The semiconductor structure ofclaim 1, wherein said substantially same vertical cross-sectional shape further includes a rectangular portion having a same width as a maximum width of said vertically tapered portion and adjoining an upper end of said vertically tapered portion.

4. The semiconductor structure ofclaim 3, wherein said substantially same vertical cross-sectional shape further includes another rectangular portion having a same width as a minimum width of said vertically tapered portion and adjoining a lower end of said vertically tapered portion.

5. The semiconductor structure ofclaim 4, wherein sidewalls of said vertically tapered portion are concave sidewalls.

6. The semiconductor structure ofclaim 1, wherein said vertically tapered portion has a cross-sectional shape of a trapezoid.

7. The semiconductor structure ofclaim 6, wherein a bottom side of said trapezoid coincides with said horizontal interface, and a top side of said trapezoid coincides with a topmost surface of said semiconductor fin.

8. The semiconductor structure ofclaim 1, wherein a vertical cross-sectional shape of said semiconductor fin along a vertical plane including said lengthwise direction includes a pair of tapered edges, wherein each of said tapered edges is congruent with a tapered edge of said substantially same vertical cross-sectional shape.

9. The semiconductor structure ofclaim 1, further comprising at least another semiconductor fin located on said substrate, laterally spaced from said semiconductor fin, extending in directions that are parallel to said lengthwise direction, and having said substantially same vertical cross-sectional shape.

10. The semiconductor structure ofclaim 1, wherein said substrate includes an insulator layer, and said horizontal interface is an interface between said insulator layer and said semiconductor fin.

11. The semiconductor structure ofclaim 1, further comprising:

a gate dielectric in contact with a top surface and sidewall surfaces of said semiconductor fin; and

a gate electrode in contact with said gate dielectric.

12. The semiconductor structure ofclaim 11, wherein said semiconductor fin includes a body region, a source region, and a drain region, and said semiconductor structure further comprises:

a raised source region in contact with said source region and located outside said semiconductor fin; and

a raised drain region in contact with said drain region and located outside said semiconductor fin.

13.-25. (canceled)

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