US20140281662A1 - Dynamically adaptive bit-leveling for data interfaces - Google Patents

Abstract

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Description

COPYRIGHT NOTICE
• A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
TECHNICAL FIELD
• The present invention relates generally to interface circuits, typically implemented on integrated circuits such as Processor chips, memory controller chips, and SOC (System On Chip) integrated circuits where such interface are required. One common example of such an interface would receive data read from dynamic memory chips that are located externally to a device containing the receiving interface.
BACKGROUND
• Given today's high clock rates and transmission line effects when signals must travel between integrated circuit chips, skew between different data bits in the same bus becomes a problem. As a system heats and cools during operation, and/or develops hot and cool spots, the skew between data bits can likewise change as data bit signals and strobe signals travel off chip and between chips through various system-level paths. Also, as these phenomenon dynamically change during operation, the skew between data bits can likewise change. Therefore, it would be useful to have a way to perform bit leveling from time to time during system operation, and to do so quickly, and to perform bit leveling independently for each data bit on a data bus.
• One application where a dynamic bit leveling capability is especially useful for compensating for variable system-level delays is that of dynamic memory interfaces where DQ data bits can develop a skew problem with respect to the DQS strobe used to sample them. Jitter can also develop between data bits and strobes, and it would also be useful to resolve jitter issues while performing a bit-leveling function.
SUMMARY
• A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving data interface on a receiving device. In the receiving interface, a programmable delay line incrementally delays or advances each individual data bit relative to a sampling point in time, and delays are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the bit leveling calibration process and the advancing and/or delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of a data value midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of jitter.
• To perform a calibration operation according to the invention a pattern of alternating “1s” and “0s” is read into a receiving data interface circuit and is processed according to the methods described herein. A strobe signal is delayed such that it will be nominally placed in the center of the delay line delay used to delay one or more data bit signals. As such, a particular data value, shown as a “0” for example in the description that follows, is expected when the strobe signal first samples a data bit signal. If the opposite value is recorded, according to a first embodiment of the invention this is considered an exception and is followed by special exception processing. When such an exception occurs, circuits and methods are disclosed that accommodate the exception and provide an optimum sampling point in time and the corresponding appropriate delay line delay for the sampled data bit.
• In a first embodiment of the invention a programmable delay line for delaying the sampled data bit is used to both advance and delay the data bit in time relative to a sampling strobe. In the case of data coming from a dynamic memory, the sampled data bit would typically be a programmably delayed version of DQ, while the sampling strobe is a delayed version of DQS.
• In a second embodiment of the invention, a programmable delay line for delaying the sampled data bit is used to incrementally sweep the delay of a sampled data bit in time relative to a sampling strobe, with sampled values recorded and/or analyzed at each increment, with an analysis also performed after completing the sweep to determine the best point in time to sample the data bit. The second embodiment may require a longer delay line for delaying the sampled data bit, additional time for the calibration operation, and additional controller storage capacity and control logic compared with the first embodiment. At the same time, the second embodiment includes an analysis process where criteria for analyzing strings of consecutive sampled data bits having the same value is performed such that jitter detection is performed at the same time, and there is no specific need for exception handling.
BRIEF DESCRIPTION OF THE DRAWINGS
• The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.
• FIGS. 1A and 1B show exemplary and non-limiting embodiments for generalized circuit descriptions describing different aspects of the invention.
• FIG. 2 shows an exemplary and non-limiting embodiment for a generalized circuit description describing aspects of the invention.
• FIG. 3 shows an exemplary flowchart for bit leveling according to the invention where an expected data value is initially sampled, and where no exception processing or jitter detection is required.
• FIG. 4 shows exemplary timing diagrams for bit leveling in accordance with the flowchart ofFIG. 3, whereFIG. 4ashows timing relationships before bit leveling andFIG. 4bshows timing relationships after bit leveling.
• FIG. 5 shows an exemplary and non-limiting circuit block diagram for a generalized bit leveling controller circuit according to the invention.
• FIG. 6 shows an overall flowchart for an embodiment for bit leveling according to the invention including exception processing when a first sampled data bit is not an expected value, as well as jitter detection and correction.
• FIG. 7 shows an exemplary flowchart for the first steps in a process for exception processing, also including jitter detection and correction.
• FIG. 8 shows diagrams describing timing relationships before and after exception processing plus a flow chart inFIG. 8bshowing steps to complete exception processing under a first condition, whereFIG. 8ashows timing relationships before bit leveling andFIG. 8cshows timing relationships after bit leveling.
• FIG. 9 shows diagrams describing timing relationships before and after exception processing plus a flow chart inFIG. 9bshowing steps to complete exception processing under a second condition, whereFIG. 9ashows timing relationships before bit leveling andFIG. 9cshows timing relationships after bit leveling.
• FIG. 10 shows timing diagrams for jitter detection and correction when the sampling point is in the vicinity of a rising edge of the sampled data bit, and jitter is present.
• FIG. 11 shows timing diagrams for jitter detection and correction when the sampling point is in the vicinity of a falling edge of the sampled data bit, and jitter is present.
• FIG. 12 shows exemplary timing diagrams for two scenarios where a data bit is sampled by incrementally sweeping a sampling point in time, and the results are analyzed to determine the best final sampling point, whereFIG. 12ashows timing relationships before bit leveling,FIG. 12bshows a jitter zone, andFIG. 12cshows timing relationships after bit leveling.
• FIG. 13 shows an exemplary flow chart for a generalized scenario where a data bit is sampled by incrementally sweeping a sampling point in time, and the results are analyzed to determine the best final sampling point.
DETAILED DESCRIPTION
• The embodiments disclosed by the invention are only examples of the many possible advantageous uses and implementations of the innovative teachings presented herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.
• Bit leveling operations, according to the exemplary and non-limiting embodiments described herein, may be run at any time. However in some applications, bit leveling may be run after write leveling is performed and before a core clock capture synchronization operation is run when such a function is utilized. Examples of such core clock capture synchronization circuits and methods are described in U.S. Pat. No. 7,975,164 where such a function is termed SCL (Self-Configuring Logic), and also in US Patent Application Pub No2011/0258475 where such a function is termed DSCL (Dynamic SCL).
• Bit leveling according to the invention is able to be run dynamically at any point in time, preferably when the particular data interface is not being utilized such as for a dynamic memory data interface during a memory refresh operation. For the exemplary and non-limiting examples described herein for different embodiments of the invention, and in view of the fact that many common applications for the invention include dynamic memory controllers and data interfaces receiving data bits and strobes from dynamic memories, reference will typically be made to “DQ” for data bits being sampled and bit leveled, and to “DQS” as the corresponding sampling strobe. It should be understood however that the circuits and methods described herein are applicable to any data interface receiving data bits where skew and/or jitter develops and it is desirable to mitigate these problems in order to produce a more reliable data interface implementation.
• To ensure that the rising edge of DQS is sampling the respective DQ data accurately, bit-leveling aligns the rising edge with the center of the DQ data bit value. This is done in order to compensate for the unpredictable amount of delay on DQ and DQS that results in an undesirable skew between the DQ and DQS signals. The algorithm is implemented by reading a continuous pattern of alternating 1s and 0s from the DRAM on DQ and DQS. The alternating pattern may be either “1-0-1-0” or “0-1-0-1”, however for simplicity and consistency the pattern is described herein as 0-1-0-1. For exemplary embodiments described herein, DQS is typically delayed by 90 degrees to align sampling edges of DQS with centers of DQ data bits. Therefore ideally, the rising edge of DQS is always sampling a “0” on DQ. Prior to sampling, the DQ data bit is programmably delayed to allow advancing or delaying with respect to an edge of the DQS strobe. Therefore, in addition to the 90° delay of DQS mentioned above, DQS is additionally delayed by a programmable amount which is nominally equivalent to the amount DQ is initially programmably delayed. From this starting point, calibration processes determine further adjustment to the DQ the programmable delay line in order to place the center of each DQ data bit value in time aligned with the appropriate edge of the DQS strobe.
• FIG. 1 shows two generalized circuit diagrams for data interfaces according to the invention. InFIG. 1a,data bit DQ102 is programmably delayed indelay line108 and thereafter is sampled at flip-flop110 by a version of theDQS strobe104 which has been delayed106 by 90° to align its edge nominally with the center of a DQ data bit, and has also had a programmable delay added to position a delayed DQS strobe nominally centered relative to the delayed DQ data bit.FIG. 1ashows a more detailed exemplary implementation where bit levelingcontrol circuit112 is clocked by acore clock116, and a buffered version of the output of flip-flop110 is synchronized with thesame core clock116 by synchronizing flip-flops114.
• Exemplary implementations shown herein focus in general on synchronizing with the positive edge of the sampling strobe (flip-flop110 is has a positive edge clock input), with the assumption that if bit leveling is performed relative to the positive edge of a sampling strobe such asDQS104, the negative edge of such a sampling strobe will effectively align approximately in the center of the other half cycle of the data bit being sampled.FIG. 2 shows a more comprehensive example where the positive edge ofDQS104, having been delayed106, samples delayed DQ data bit in flip-flop110, while the negative edge of the delayed DQS strobe samples the same delayed DQ data bit in flip-flop202. It should be noted that in another implementation, not shown, a similar bit leveling calibration and synchronization function can be applied such that bit leveling for the delayed DQ data bit relative to the negative edge of the delayed DQS strobe is also performed. This would typically require additional instances of bit levelingcontrol circuit112 and an additional programmable delay line for each DQ data bit being bit leveled.
• In an example demonstrating one exemplary embodiment, bit-leveling operates by sampling DQ at the rising edge of DQS and then delays and advances DQ with respect to DQS so as to measure the distance (in delay line delay increments) to each edge of DQ. These distances, referred to as windows, are used to determine how far, or close, the rising edge of DQS is from the center of DQ and how much DQ needs to be delayed or advanced to center it. The example ofFIGS. 3 and 4 demonstrate a scenario where DQ is being sampled too early, and the bit-leveling process therefore determines that a delay of (Ta−Tb)/2 QUOTE is to be added to DQ to align the center of a DQ data bit “0” value as close as possible with the rising edge of DQS.
• In general, by determining the size of these delay measurement windows, the bit leveling process determines if DQ is being sampled too early or too late, and therefore adjusts the delay on DQ to sample it correctly.
• Anexemplary flowchart300 for this process is shown inFIG. 3. Instep302, a 0-1-0-1 pattern is installed such that it can be received by a data interface according to the invention during a calibration operation. In this example, such a pattern is installed in a DRAM. According to step304 while continuously receiving the 0-1-0-1 pattern, a programmably delayed version of a DQ data bit is sampled on the rising edge of DQS—where DQS has been delayed by 90° plus a suitable programmable delay as described previously. It is expected that given the data pattern received for this scenario, that when first sampled, a value of “0” will be sampled given the initial setting of the DQ programmable delay line. In an alternate embodiment, a value of “1” might instead be the expected value. Perstep306, from the initial delay line setting for DQ, DQ is subsequently delayed in time by some number of delay line increments until a “1” is sampled, and the total number of delay line increments required to achieve this point is recorded relative to the initial setting as Ta. Perstep308, DQ is advanced in time by incrementally adjusting the programmable delay line for DQ until a “1” is sampled, and the total number of increments advanced relative to the initial delay line setting is recorded as Tb. Subsequently perstep310, if Ta is greater than Tb, bit leveling is achieved by setting the programmable delay line delay value for DQ to be a delay value of (Ta−Tb)/2 from the initial sampling point. If however perstep312, Tb is greater than Ta, bit leveling is achieved by setting the programmable delay line delay value for DQ to be an advance value of (Tb−Ta)/2 from the initial sampling point. If Ta is equal to Tb, then the strobe is centered within the data bit value for DQ, and no further adjustment beyond the initial setting of the delay line is required to achieve bit leveling.
• It should be noted that diagram300 ofFIG. 3 shows a simplified flow where when first sampled, the expected value is recorded as such no exception processing is required. Diagram300 also includes no detection or compensation for jitter.
• Timing diagrams400 for the scenario ofFIG. 3 are shown inFIG. 4. Here,FIG. 4ashows the timing relationship between theDQS strobe402 and the programmably delayed DQ data bitvalue404 before bit leveling, whereinitial sampling point406 is not properly centered within that portion of DQ having a “0”value408. The desired final sampling point is shown here as410. Timingmeasurement windows Ta412 andTb414 are also shown where Ta is greater than Tb.FIG. 4bshows the timing relationships after bit leveling where DQ has been additionally delayed by a value of (Ta−Tb)/2 from the initial sampling point such thatsampling point410 is now properly aligned to be at the center of that portion ofDQ404 where the data value is a “0”. After alignment, Ta equals Tb as shown.
• A generalized circuit block diagram500 for an exemplary and non-limiting embodiment of a bit leveling invention is shown inFIG. 5. In this example,DQ102 is delayed inprogrammable delay line108 and sampled in flip-flop110 by a strobe signal, in this case a delayed version502 of DQS. For this generalized description, a state machine504 controls bit leveling calibration operations including counters506 and508 for advancing and delaying DQ as well as for storing counter values. According to different embodiments of the invention delay measurements may be added or subtracted in block512, and compared in block510 to determine “greater than”, “less than”, or “equal to” results. It should be noted that one skilled in the art could devise many different circuit implementations to implement the functionalities described herein, and that no one particular circuit implementation is defined according to the appended claims. Counters, comparators, and adder/subtractors may be used as described inFIG. 5, however an equivalent functionality could be arrived at by simply having a much larger and more complex version of bit leveling state machine504.
• Note that for the alternative embodiment ofFIGS. 12 and 13, an implementation of the bit leveling controller circuit may require more storage capability for storing sampled data bit values at different delay increments, and/or for storing more counter values in order to facilitate the analysis process that is performed after and/or during the sweep process.
• Flowchart600 ofFIG. 6 shows an overall exemplary flow for an embodiment of the invention, including when exception handling is required and jitter detection and correction are performed. In step602 a 0-1-0-1 pattern has been installed such that it can be received by a data interface according to the invention during a calibration operation. In this example, such a pattern is installed in a DRAM. According to step604, while continuously receiving the 0-1-0-1 pattern, a programmably delayed version of a DQ data bit is sampled on the rising edge of DQS—where DQS has been delayed by 90° plus a suitable programmable delay as described previously. It is expected in this scenario that when first sampled, a value of “0” will be sampled at the initial setting of the DQ programmable delay line. Instep606 this determination is made, and if a value of “1” is detected, then exception handling is begun perstep608. During exception handling operations as described inFIGS. 7,8, and9, either bit leveling is completed or the process returns to step604 as shown inFIG. 6.
• If a “0” is sampled as expected per 606, the process proceeds to step610 where DQ is delayed in time by increments from an initial starting point until a “1” is sampled, and the total delay relative to an initial starting point is recorded as Ta. Subsequently perstep612, DQ is advanced in time by increments from the initial starting point until a “1” is sampled, and the total delay relative to the initial starting point is recorded as Tb. Next, jitter detection is performed perstep614 where (Ta+Tb) is compared with a jitter threshold value. If (Ta+Tb) is less than the jitter threshold value, then jitter compensation is performed616 according toFIGS. 10 and 11, after which the process returns to step604. Subsequently perstep618, Ta and Tb are compared. Perstep620, if Ta is greater than Tb, bit leveling is achieved by setting the programmable delay line for DQ to be a delay value of (Ta−Tb)/2 from the initial sampling point. If however perstep622, Tb is greater than Ta, bit leveling is achieved by setting the programmable delay line for DQ to be an advance value of (Tb−Ta)/2 from the initial sampling point. If Ta is equal to Tb, then according to the initial delay line setting the strobe is already centered within the data bit value for DQ, and no further adjustment beyond the initial setting of the delay line is required to achieve bit leveling.
Exception Processing
• For the exemplary embodiment for data interface as applied to the dynamic memory controller application, it is typically expected that when first sampled at an initial DQ delay line setting, the sample data bit value will be a “0”. It is possible however that skews can develop in the system such that initial sampled value is instead a “1”. For these circumstances, a similar method as described above is used with some additional steps that provide for a third window measurement in order to position the delayed DQ data bit correctly with respect to sampling strobe DQS.
• A first stage of exception processing is shown in flow-chart700 ofFIG. 7 where the process begins instep702 having been preceded bystep608 ofFIG. 6. When a “1” is initially sampled instead of a “0”, there are two possible scenarios that may exist —either DQ delay is too high or DQ delay is too small. To determine which might be the case, the following steps are performed by the invention as shown inFIG. 7. First perstep704, DQ is delayed from an initial starting point until a “0” is detected at the sample point, and this delay is recorded as Tc. Then perstep706, DQ is advanced from the initial starting point until a “0” is detected at the sample point, and this delay is recorded as Td. At this point in the exception processing flow, it is appropriate to check for the presence of jitter according tostep708. If the value (Tc+Td) is less than a Jitter Threshold value, then the process proceeds to step710 for jitter correction where a Jitter Correction Offset value is added to the initial delay line setting, and the process moves 712 to step604 ofFIG. 6 where bit leveling starts again. Note that the appropriate Jitter Threshold value and the Jitter Correction Offset value may vary from implementation to implementation, and proper and effective values will be chosen by the designer who understands all parameters involved in the decision.
• If the value (Tc+Td) is not less than a Jitter Threshold value, then it is determined that jitter is not interfering with the bit leveling process and the flow proceeds to step714 where Tc and Td are compared. If perstep714, Tc is not less than Td, the process proceeds718 to step810 ofFIG. 8b. If however perstep714, Tc is less than Td, the process proceeds716 to step910 ofFIG. 9b.FIGS. 8 and 9 show timing diagrams and flow charts for completing the bit leveling process when exception handling is required.
• Diagrams andflow charts800 ofFIG. 8 show the completion of bit leveling whenTc804 is greater thanTd806. InFIG. 8a, delayed DQ data bit404 is sampled bystrobe DQS402 at aninitial sampling point802 where a “1” is detected which previously had initiated exception processing. In the flowchart ofFIG. 8b, the process continues instep810 as a result of Tc being determined to be greater than Td according to step716 ofFIG. 7. Instep812, DQ is advanced from the initial delay line starting point until a “0” is detected (previously recorded as Td), and then further advanced until a “1” is detected, whereby the delay when the “1” is detected is recorded as Te. Then instep814, bit leveling is completed by setting the DQ delay line to advance DQ from the initial delay line starting point by a value of (Td+Te)/2, whereby a desiredsampling point808 is achieved. The timing diagram ofFIG. 8C shows the timing relationships after bit leveling is completed.Delay value Te816 is shown along with the final correction whereby DQ is advanced (delay is decremented) by a value equal to (Td+Te)/2818 relative to the initial delay line starting point value.
• Diagrams andflow charts900 ofFIG. 9 show the completion of bit leveling whenTc904 is less thanTd906. InFIG. 9a, delayed DQ data bit404 is sampled bystrobe DQS402 at aninitial sampling point902 where a “1” is detected which previously had initiated exception processing. In the flowchart ofFIG. 9b, the process continues instep910 as a result of Tc being determined to be less than Td according to step718 ofFIG. 7. Instep912, DQ is delayed from the initial delay line starting point until a “0” is detected (previously recorded as Tc), and then further delayed until a “1” is detected, whereby the delay when the “1” is detected is recorded as Tf. Then instep914, bit leveling is completed by setting the DQ delay line to delay DQ from the initial delay line starting point by a value of (Tc+Tf)/2, whereby a desiredsampling point908 is achieved. The timing diagram ofFIG. 9C shows the timing relationships after bit leveling is completed.Delay value Tf916 is shown along with the final correction whereby DQ is delayed (delay is incremented) by a value equal to (Tc+Tf)/2918 relative to the initial delay line starting point value.
Jitter Detection and Correction
• Jitter on the DQS signal, and/or DQ signal, may cause the sampled value of DQ to be taken incorrectly. This may happen when the initial sampling point is near a rising or falling edge of DQ. In the exemplary and non-limiting embodiments that follow for jitter detection and correction, jitter has been shown on the DQS signal and not on the DQ signal. In reality jitter may exist on either signal or both, however to simplify the explanation and the drawings jitter is shown herein only on the DQS signal.
• Since a jitter scenario may arise when sampling DQ near either its rising or falling edge, examples are shown for both edges with sampling near the rising edge of DQ shown inFIG. 10 and sampling near the falling edge of DQ shown inFIG. 11. InFIG. 10, the rising edge of the DQS is shown with a jitter region betweensample #1edge1002 andsample #2 & #3edge1004. When the sequence ofFIG. 6 is executed and jitter is present, the initial sample,sample #1, may record a “0”1006. This is the expected value for an initial sample so the procedure ofFIG. 6 continues initially as if no jitter is present. Subsequently due to jitter,sample #2 records a “1”1008 definingTa1012. The procedure then continues and again due to jitter the next sample,sample #3, records a “1”1010 definingTb1014. Consequently these measurements determine the size of the (Ta+Tb) window to be very small, or zero, when it should in fact be large, nearly a half cycle. To avoid utilizing this incorrect window value, a value of (Ta+Tb) is compared with a Jitter Correction Threshold value, and if the value (Ta+Tb) is less than this threshold value, a Jitter Correction Offset1016 is added to the initial sampling point. Subsequently when the bit leveling process is restarted, and assuming a positive jitter correction offset is used to delay DQ from the initial sampling point, either jitter edge of DQS (1002 or1004) will be positioned such that a “0” value will be detected when DQ is sampled.
• Note that if jitter is present and the initial sampling point is near a rising or falling edge of DQ, but however the first sampled value is a “1”, then exception processing perFIGS. 7-9 will be initiated and the jitter problem will be resolved through that procedure.
• InFIG. 11, the rising edge of the DQS is shown with a jitter region betweensample #1edge1102 andsample #2 & #3edge1104. When the sequence ofFIG. 6 is executed and jitter is present, the initial sample,sample #1, may record a “0”1106. This is the expected value for an initial sample so the procedure ofFIG. 6 continues initially as if no jitter is present. Subsequently, due to jitter,sample #2 records a “1”1108 definingTa1112. The procedure then continues and again due to jitter the next sample,sample #3, records a “1”1110 definingTb1114. Consequently these measurements determine the size of the (Ta+Tb) window value to be very small, or zero, when it should in fact be large, nearly a half cycle. To avoid utilizing this incorrect window value, the value (Ta+Tb) is compared with a Jitter Correction Threshold value, and if the value (Ta+Tb) is less than this threshold value, a Jitter Correction Offset1016 is added to the initial sampling point. Subsequently when the bit leveling process is restarted, and assuming a positive jitter correction offset is used to delay DQ from the initial sampling point, either jitter edge of DQS (1102 or1104) will be positioned such that a “1” value will be detected when DQ is sampled. The detection of a “1” will initiate the exception processing sequence ofFIGS. 7-9 and bit leveling will be thus resolved.
Bit Leveling Via Delay Sweep and Analysis
• The methods of the exemplary embodiments described by the methods ofFIGS. 6-11 utilize a relatively short delay line for delaying each DQ data bit, with exception processing and jitter detection/correction performed as required. These methods ofFIGS. 6-11 also require very little storage circuitry to implement a bit-leveling controller function. An alternative approach is shown in the exemplary and non-limiting embodiments ofFIGS. 12 and 13, where the delay value of DQ is swept for a larger number of delay increments, either in two directions perFIG. 12aor in a single direction perFIG. 12c. As shown inFIG. 12a, an initial sampling point might be timed to sample a “0” onDQ404, however for the operational methods for the embodiments ofFIGS. 12 and 13, it doesn't matter whether the initial sampled value for DQ is a “0” or a “1”. As shown inFIG. 12a, DQ is first delayed from an initial position by number of increments which are swept as shown bysequence1204, and then subsequently swept in the opposite direction (advanced) by a number of increments shown assequence1206. Each of these sweeps may continue for a predetermined number of delay line increments, or may continue until the end of the delay line is reached or until some other condition is satisfied. In one exemplary and non-limiting embodiment, at each increment the value of DQ that is sampled is recorded. Subsequently aftersweeps1204 and1206 have been completed, the recorded values of DQ for each delay line increments are analyzed to determine an optimumfinal sampling point1208. In an alternative implementation for the embodiment ofFIGS. 12 and 13, at least a portion of the analysis of the strings of sampled data bits is performed while the sweep of the delay line is executed, thereby requiring fewer data and counter values to be saved along the way for post-sweep analysis. For instance, only delay line increments where a sampled data bit value changes relative to its value at the previous delay line increment would be stored. In yet another alternative embodiment for a sweep-based controller function, to avoid storing counter values a string of data bit values can be stored in successive memory or register locations within the bit-leveling controller circuit, with each location corresponding to an increment of the sweep. Then after the sweep is complete, these locations can be analyzed with the understanding that each successive bit location represents the data bit value at the next delay line increment. For all embodiments of a sweep-based methodology, the optimum sampling point is determined by locating consecutive strings of sampled data bits having the same value, typically a “0”, and placing thefinal sampling point1208 in the center of one of these consecutive strings.
• For embodiments perFIGS. 12 and 13, jitter is resolved in a different manner than described inFIGS. 10 and 11. When jitter occurs it becomes evident at the rising and falling edges of DQ such as fallingedge1210 shown for example in the enlarged diagram1212 ofFIG. 12bwherejitter zone1214 is highlighted. According to an analysis method used with the sweep methodologies ofFIGS. 12 and 13, when sweeping through a jitter zone sampled data values on successive samples may be different, and thus can be differentiated from a successive string of sample data bits having the same value, and where the string of sampled data values has a width of an appropriate size. Therefore in analyzing successive strings of sampled data bits having the same value, to be considered for placement of a final sampling point, a string of sample data bits having the same value must have a width greater than a jitter threshold value.
• The diagram ofFIG. 12cshowsinitial sampling point1216 and describes a scenario where asingle sweep1218 is performed from one delay position of the DQ delay line to another delay position of the DQ delay line. These positions may be the extreme settings of the delay line, or arbitrary start and finish positions as determined by the application. As described above forFIG. 12a, sampled data bits may be recorded for every increment while the sweep is performed, and successive strings of data bits having a “0” value are considered for possible placement of thefinal sampling point1220. Jitter is resolved in the same manner described above forFIG. 12a. Alternately, at least a portion of the analysis of the strings of sampled data bits may be performed while the sweep of the delay line is executed, thereby requiring fewer data and counter values to be saved along the way for post-sweep analysis.
• Flowchart1300 ofFIG. 13 shows a generalized description of a process encompassing the embodiments ofFIG. 12. Instep1302, a pattern of alternating “1”s and “0”s is received on a data bits signal, nominally DQ ofFIGS. 12aand12c. In step1304 a programmable delay line is provided for delaying data received on the data bit signal, typically DQ for a dynamic memory interface, and a delayed data bit signal is produced. Instep1306 the delayed data bit signal is strobed by a data strobe signal, nominally a delayed version of DQS for dynamic memory interfaces. Strobing is performed at a regular interval to produce a sampled data bit signal value. The regular interval is typically at substantially the same frequency as the pattern of alternating “1”s and “0”s. Instep1308, from an initial delay setting for the delay line that delays the data bit (DQ), the delay line delays are incrementally changed or swept until a condition is satisfied that indicates the changing should cease. This condition could be that a predetermined point along the delay line has been reached, or that the end of the delay line has been reached, or some other termination condition determined according to a specific application. As the delay line is swept, at each increment the sampled data bits signal is recorded. Alternately, at least a portion of the analysis of the strings of sampled data bits is performed while the sweep of the delay line is executed, thereby requiring fewer data bit and counter values to be saved along the way for post-sweep analysis.
• Instep1310 the recorded sampled data bit signal values are analyzed in order to determine the width and position of strings of consecutive sample data bits having the same signal values. Note thatSteps1308 and1310 can be combined in an alternative implementation such that at least a portion of the analysis of the strings of sampled data bits is performed while the sweep of the delay line is executed, thereby requiring fewer data and counter values to be saved along the way for post-sweep analysis.
• In step1312 a center point of one of the strings of consecutive sample data bits is chosen to be a desired sampling point. Instep1314 the programmable delay line for the data bit is set to a value that causes the data strobe signal to be aligned with the desired sampling point. If jitter is present, jitter is resolved by only considering consecutive strings of sampled data bits having the same value where the length of the string is greater than a jitter detection threshold.
• At this point in the method ofFIG. 13, bit leveling has been completed for a particular data bit. Typically, a similar bit leveling capability is included for each data bit where system timing skews can affect the reliability of the data interface in question. This requires a reasonable amount of circuitry and if silicon real estate is an issue, bit leveling could be performed on a byte or nibble basis where a delay setting for one data bit of a byte or nibble is utilized for the other bits. On the other hand, if silicon real estate is not an issue, bit leveling capabilities such as those described herein can be utilized for sampling data bits on the negative edge of a sampling strobe such as DQS in addition to the positive edge as focused on herein.
• Thus, a circuit and operating method for adaptive bit-leveling for data interfaces has been described.
• It should be appreciated by a person skilled in the art that methods, processes and systems described herein can be implemented in software, hardware, firmware, or any combination thereof. The implementation may include the use of a computer system having a processor and a memory under the control of the processor, the memory storing instructions adapted to enable the processor to carry out operations as described hereinabove. The implementation may be realized, in a concrete manner, as a computer program product that includes a non-transient and tangible computer readable medium holding instructions adapted to enable a computer system to perform the operations as described above.

Claims (36)

1. A method for performing bit leveling for a data interface, comprising:

receiving a pattern of alternating 1's and 0's on a data bit signal;

providing a programmable delay line for delaying the data received on the data bit signal;

strobing the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;

incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Ta;

incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tb;

as a function of Ta and Tb, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.

2. The method ofclaim 1, further comprising:

determining the sum of Ta and Tb wherein if the sum of Ta and Tb is less than a jitter detection threshold value, adding a jitter correction offset value, and performing the method ofclaim 1 again.

3. The method ofclaim 1, further comprising:

comparing Ta and Tb wherein if Ta is greater than Tb, setting the delay line delay to a value equal to the initial delay line delay with the addition of an averaging factor wherein the averaging factor is (Ta−Tb)/2.

4. The method ofclaim 1, further comprising:

comparing Ta and Tb wherein if Ta is less than Tb, setting the delay line delay to a value equal to the initial delay line delay decremented by an averaging factor wherein the averaging factor is (Tb−Ta)/2.

5. A method for performing bit leveling for a data interface, comprising:

receiving a pattern of alternating 1's and 0's on a data bit signal;

providing a programmable delay line for delaying the data received on the data bit signal;

sampling the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;

if a sampled data bit signal differs from an expected value when first sampled from the pattern of alternating 1's and 0's, then proceeding with the following method:

from an initial delay line delay setting, incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tc;

from the initial delay line delay setting, incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Td;

as a function of at least Tc and Td, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.

6. The method ofclaim 5, further comprising:

summing Tc and Td wherein if (Tc+Td) is less than a jitter detection threshold value, adding a jitter correction offset value to the initial delay line setting, and then performing a method for performing bit leveling for a data interface, comprising:

receiving a pattern of alternating 1's and 0's on a data bit signal;

strobing the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;

incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Ta;

incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tb;

as a function of Ta and Tb, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.

7. The method ofclaim 5, further comprising:

summing Tc and Td wherein if (Tc+Td) is less than a jitter detection threshold value, adding a jitter correction offset value to the initial delay line setting, and then re-performing the method ofclaim 5.

8. The method ofclaim 5, further comprising:

comparing the values of Tc and Td wherein if the value Tc is greater than Td, incrementally advancing DQ from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Td, and then further advancing DQ until a 1 is detected, whereby the delay line delay is recorded as Te;

setting the DQ delay line delay to advance DQ from the initial point by the value (Td+Te)/2.

9. The method ofclaim 5, further comprising:

Comparing the values of Tc and Td wherein if the value Tc is less than Td, incrementally delaying DQ from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Tc, and then further delaying DQ until a 1 is detected, whereby the delay line delay is recorded as Te;

setting the DQ delay line delay to delay DQ from the initial point by the value (Tc+Tf)/2.

10. A method for performing bit leveling for a data interface, comprising:

receiving a pattern of alternating 1's and 0's on a data bit signal;

providing a programmable delay line for delaying data received on the data bit signal to produce a delayed data bit signal;

strobing the delayed data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal value, the regular interval being at substantially the same frequency as the pattern of alternating 1's and 0's;

from an initial delay line delay setting, incrementally changing the delay line delay by a plurality of increments, and recording at each increment the sampled data bit signal value;

analyzing the recorded sampled data bit signal values to determine the width and position of strings of consecutive sampled data bits having the same signal values;

choosing a center point of one of the strings of consecutive sampled data bits to be a desired sampling point; and

setting the programmable delay line to a delay setting that causes the data strobe signal to be aligned with the desired sampling point.

11. The method ofclaim 10 wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the initial delay line setting.

12. The method ofclaim 10 wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the position of the data strobe signal.

13. The method ofclaim 10 wherein incrementally changing the delay line delay by a plurality of increments further comprises:

from the initial delay line delay setting, incrementally changing the delay line delay until a criteria has been satisfied indicating the changing should terminate, and recording at each increment the sampled data bit signal value.

14. The method ofclaim 13 wherein during a first operation a first portion of the total available delay line delay is utilized, and if a suitable position for the data strobe signal to be aligned with the desired sampling point is not found, performing the operation ofclaim 13 again while utilizing a portion of the total available delay line delay that is larger than the first portion.

15. The method ofclaim 10 wherein incrementally changing the delay line delay by a plurality of increments further comprises:

from the initial delay line delay setting, incrementally changing the delay line delay until a maximum delay or a minimum delay provided by the delay line has been reached, and recording at each increment the sampled data bit signal value.

16. The method ofclaim 10 wherein incrementally changing the delay line delay by a plurality of increments further comprises:

from the initial delay line delay setting, incrementally increasing the delay line delay by a first predetermined number of increments, and recording at each increment the sampled data bit signal value; and

from the initial delay line delay setting, incrementally decreasing the delay line delay by a second predetermined number of increments, and recording at each increment the sampled data bit signal value.

17. The method ofclaim 10 wherein choosing a center point of one of the strings of consecutive sampled data bits, further comprises choosing from strings of consecutive sampled data bits having a string length greater than a predetermined number of increments.

18. The method ofclaim 10 wherein at least a portion of the analyzing the recorded sampled data bit signal values is performed while incrementally changing the delay line delay.

19. A circuit for implementing a dynamically configurable bit-leveling function for a data interface, comprising:

a circuit for providing a data strobe signal;

a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;

at least one flip-flop for sampling the delayed data bit signal;

a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and

wherein a pattern of alternating 1's and 0's is received on a data bit signal;

wherein the delayed data bit signal is sampled with the data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;

wherein the delay line delay is incrementally increased until the value of the sampled data bit signal changes, and a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at an initial delay line delay setting is stored as value Ta;

wherein the delay line delay is incrementally decreased until the value of the sampled data bit signal changes, and a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting is stored as value Tb; and

wherein as a function of Ta and Tb, the delay line setting is adjusted to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.

20. The circuit ofclaim 19, wherein the circuit determines the sum of Ta and Tb, and wherein if the sum of Ta and Tb is less than a jitter detection threshold value, a jitter correction offset value is added, and the operation of the circuit perclaim 1 is performed again.

21. The circuit ofclaim 19, wherein Ta and Tb are compared, and wherein if Ta is greater than Tb, the delay line delay is set to a value equal to the initial delay line delay with the addition of an averaging factor wherein the averaging factor is (Ta−Tb)/2.

22. The circuit ofclaim 19, wherein Ta and Tb are compared, and wherein if Ta is less than Tb, the delay line delay is set to a value equal to the initial delay line delay decremented by an averaging factor wherein the averaging factor is (Tb−Ta)/2.

23. A circuit for performing bit leveling for a data interface, comprising:

a circuit for providing a data strobe signal;

a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;

at least one flip-flop for sampling the delayed data bit signal;

a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and

wherein a pattern of alternating 1's and 0's is received on a data bit signal;

wherein the data bit signal is sampled with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;

wherein, if a sampled data bit signal differs from an expected value when first sampled from the pattern of alternating 1's and 0's, the circuit is operated according to the following method:

from an initial delay line delay setting, incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tc;

from the initial delay line delay setting, incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Td;

as a function of at least Tc and Td, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.

24. The circuit ofclaim 23 wherein Tc and Td are summed, and wherein if (Tc+Td) is less than a jitter detection threshold value, a jitter correction offset value is added to the initial delay line setting, and the circuit is further operated according to a method for performing bit leveling for a data interface, comprising:

receiving a pattern of alternating 1's and 0's on a data bit signal;

strobing the data bit signal with a data strobe signal at a regular interval to produce a sampled data bit signal, the regular interval being at substantially the same frequency that the pattern of 1's and 0's is changing;

incrementally increasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Ta;

incrementally decreasing the delay line delay, until the value of the sampled data bit signal changes, and storing a number of increments necessary to reach the point where the sampled data bit signal changed relative to its value at the initial delay line delay setting as value Tb;

as a function of Ta and Tb, adjusting the delay line setting to advance or delay the data bit signal, such that the data bit signal is sampled at substantially the midpoint of a half-cycle.

25. The circuit ofclaim 23 wherein Tc and Td are summed, and wherein if (Tc+Td) is less than a jitter detection threshold value, a jitter correction offset value is added to the initial delay line setting, and the method ofclaim 5 is performed again.

26. The circuit ofclaim 23, wherein the values of Tc and Td are compared, and wherein if the value Tc is greater than Td, DQ is incrementally advanced from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Td, and then DQ is further advanced until a 1 is detected, whereby the delay line delay is recorded as Te; and

wherein the DQ delay line delay is set to advance DQ from the initial point by the value (Td+Te)/2.

27. The circuit ofclaim 23, wherein the values of Tc and Td are compared and wherein if the value Tc is less than Td, DQ is incrementally delayed from the initial point until a 0 is detected, the increment for the detected 0 having been previously recorded as Tc, and then DQ is further delayed until a 1 is detected, whereby the delay line delay is recorded as Te; and

wherein the DQ delay line delay is set to delay DQ from the initial point by the value (Tc+Tf)/2.

28. A circuit for performing bit leveling for a data interface, comprising:

a circuit for providing a data strobe signal;

a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;

at least one flip-flop for sampling the delayed data bit signal;

a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and

wherein a pattern of alternating 1's and 0's is received on a data bit signal;

wherein the delayed data bit signal is sampled with a data strobe signal at a regular interval to produce a sampled data bit signal value, the regular interval being at substantially the same frequency as the pattern of alternating 1's and 0's;

wherein from an initial delay line delay setting, the delay line delay is incrementally changed by a plurality of increments, and at each increment the sampled data bit signal value is recorded;

wherein the recorded sampled data bit signal values are analyzed to determine the width and position of strings of consecutive sampled data bits having the same signal values;

wherein a center point of one of the strings of consecutive sampled data bits is chosen to be a desired sampling point; and

wherein the programmable delay line is set to a delay setting that causes the data strobe signal to be aligned with the desired sampling point.

29. The circuit ofclaim 28 wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the initial delay line setting.

30. The circuit ofclaim 28 wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the position of the data strobe signal.

31. The circuit ofclaim 28 wherein incrementally changing the delay line delay by a plurality of increments further comprises:

from the initial delay line delay setting, incrementally changing the delay line delay until a criteria has been satisfied indicating the changing should terminate, and recording at each increment the sampled data bit signal value.

32. The circuit ofclaim 31 wherein during a first operation a first portion of the total available delay line delay is utilized, and if a suitable position for the data strobe signal to be aligned with the desired sampling point is not found, the operation ofclaim 31 is performed again while utilizing a portion of the total available delay line delay that is larger than the first portion.

33. The circuit ofclaim 28 wherein incrementally changing the delay line delay by a plurality of increments further comprises:

from the initial delay line delay setting, incrementally changing the delay line delay until a maximum delay or a minimum delay provided by the delay line has been reached, and recording at each increment the sampled data bit signal value.

34. The circuit ofclaim 28 wherein incrementally changing the delay line delay by a plurality of increments further comprises:

from the initial delay line delay setting, incrementally increasing the delay line delay by a first predetermined number of increments, and recording at each increment the sampled data bit signal value; and

from the initial delay line delay setting, incrementally decreasing the delay line delay by a second predetermined number of increments, and recording at each increment the sampled data bit signal value.

35. The circuit ofclaim 28 wherein choosing a center point of one of the strings of consecutive sampled data bits, further comprises choosing from strings of consecutive sampled data bits having a string length greater than a predetermined number of increments.

36. The circuit ofclaim 28 wherein at least a portion of the analyzing the recorded sampled data bit signal values is performed while incrementally changing the delay line delay.

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