US20140246773A1 - Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate - Google Patents

Abstract

An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.

Description

TECHNICAL FIELD
• This disclosure is related to flip chip attachment of Mother die and Daughter Integrated Passive Device die, and more particularly, to methods of flip chip attachment of Mother die and Daughter Integrated Passive Device die in an inverted pyramid die stack, using a laser drilled cavity laminate Ball Grid Array/Land Grid Array substrate to accommodate the protruding Daughter die.
BACKGROUND
• Passive device integration is typically done by:
• • 1) Back side on active side die stacking with wire bond interconnection,
  • 2) Surface Mount of the passive to the top layer of a laminate substrate, or
  • 3) Embedding large passive components into a printed circuit board.
• The limitations of these methods prevent direct electrical connection between mother and daughter die, followed by the flip chip attach of the resulting inverted die stack onto a Ball Grid Array (BGA) or Land Grid Array (LGA) laminate substrate. Direct connection would allow for better electrical performance and printed circuit board (PCB) real estate reduction by integrating passives off the PCB and into the package.
• In the past, substrate technologies were limited with respect to the ability to laser or mechanically drill a cavity into a laminate substrate having a Bismaleimide Triazine (BT) core while maintaining mechanical and reliability integrity. With the advancements in substrate manufacturing technology, it is now possible to manufacture substrates with mechanically drilled or lasered cavities.
• U.S. Pat. No. 7,915,084 (Hong), U.S. Pat. No. 8,222,717 (Shim et al), and U.S. Pat. No. 7,835,157 (Tilmans) discuss integrated passive devices, but these are completely different die stacking and die to substrate interconnection and package types from those in the present disclosure.
SUMMARY
• It is the primary objective of the present disclosure to provide a new integration method for inverted pyramid die stack using flip chip attachment to a BGA or LGA laminate cavity substrate.
• Yet another objective is to use a die on die attachment to produce direct contact of a Mother die to a Daughter die.
• In accordance with the objectives of the present disclosure, a method of fabricating a mother and daughter integrated circuit is achieved. A mother die and a daughter die, wherein the daughter die is smaller than the mother die, are directly connected, active surface to active surface, resulting in a die stack. The die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the daughter die fits into the cavity.
• Also in accordance with the objectives of the present disclosure, a method of fabricating an integrated passive device is achieved. An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a die stack. The die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the smaller die fits into the cavity.
• Also in accordance with the objectives of the present disclosure, an mother and daughter integrated circuit is achieved. A mother die and a daughter die, wherein the daughter die is smaller than the mother die, are directly connected, active surface to active surface, resulting in a pyramid die stack. The pyramid die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the daughter die fits into the cavity.
BRIEF DESCRIPTION OF THE DRAWINGS
• In the accompanying drawings forming a material part of this description, there is shown:
• FIG. 1 is a top view of a substrate having a cavity therein.
• FIG. 2 is a cross-sectional representation of the substrate inFIG. 1, having the cavity therein.
• FIG. 3 is a cross-sectional representation of a die stack showing die to die interconnection.
• FIG. 4 is a cross-sectional representation of a flip chip attachment of the substrate and the die stack ofFIGS. 2 and 3, respectively.
• FIG. 5 is an enlarged cross-sectional representation of a portion ofFIG. 4.
DETAILED DESCRIPTION
• The present disclosure is a process integration method of fabricating chip on chip using flip chip attachment and a cavity substrate. For example, this method can be used for passive and power management integrated circuit (PMIC) devices. The Daughter die, such as an integrated passive device (IPD) chip, is attached under the Mother die, such as a power management chip, resulting in an inverted pyramid die stack once flipped onto the cavity substrate. Since the daughter chip protrudes below the interconnects of the mother chip, it needs a cavity substrate for flip chip attachment. The die on die attach capability produces direct contact between the mother and daughter chips.
• This package technology has recently become viable due to:
• • 1) Availability of the IPD die, and
  • 2) Laminate cavity substrate
    as opposed to the use of standard surface mount passives.
• Higher accuracy drilling capabilities of substrate suppliers are essential to this technology. Higher drilling accuracy minimizes cavity sizes to prevent potential package XY dimension increase for integration into existing products. Package XY dimension is critical in order to reduce end printed circuit board (PCB) space which is at a premium and very cost sensitive.
• Advancements in substrate drilling systems and tools prevent mechanical vibration resulting in mechanical damage and substrate layer separation which can lead to package delamination and reliability failures and permits the laser drilling of cavities in laminate substrates.
• Referring now more particularly toFIGS. 1-5, a preferred integration method will be described.
• The present disclosure provides a new process integration for fabricating chip on chip using flip chip attachment and a cavity substrate. For example, these may be passive and power management integrated circuit (PMIC) devices, but the method is not limited to only these types of devices. For illustration purposes, the mother chip will be a power management chip and the daughter chip will be an integrated passive device, for example.
• Referring now toFIG. 3, there is shown
• • 1)Mother chip10, which may be a power management chip.
  • 2)Daughter chip14, which may be an IPD chip.
  • 3) Active surface of theIPD chip16 being attached to the active surface of thepower management chip12 usingmicro bump33.
  • 4) The copper pillar interconnect35 for the power management chip to attach the pyramid die stack to the laminate substrate20 (FIG. 2).
• The IPD chip could be a capacitor array or other passives such as resistors, inductors, baluns, or filters, or the like. The direct electrical connections between the active surfaces of the twodies10 and14, usingmicro bump33, result in better electrical performance than non-direct connections, such as wire bonding or passive surface mount and connection via laminate substrate copper trace. The die on die attach results in the flip chip attach of the pyramid die stack as shown inFIG. 4.
• The IPD die is smaller than the PMIC die in all dimensions, i.e. length, width, and height directions. The IPD die size can vary depending upon the number of passives required. The smaller IPD die, when attached to the PMIC die, then results in a pyramid die stack configuration.
• FIG. 2. illustrates alaminate substrate20 havingsolder balls30 on the underside of the substrate. Solder balls are required for BGA packages, but this cavity substrate technology is also applicable for LGA packages where solder balls are not attached. Thesubstrate20 has been laser drilled to formcavity25.
• Advancements in substrate drilling techniques and tools allow for the laser drilling of thissmall cavity25 without increasing the package dimension and without causing mechanical damage or substrate layer separation.
• FIG. 1 illustrates a top view of the substrate shown in cross-section view A-A′ inFIG. 2.Cavity25 is shown.
• The die on die attached chips shown inFIG. 3 are flipped resulting in an inverted pyramid diestack22 as shown inFIG. 4. Now thedie stack22 is connected to theBGA substrate20 via thecopper pillars35 using a flip chip attach method. The passive IPD die14 protrudes below theinterconnects35 of the mother die10, but it fits into thecavity25 drilled into thesubstrate20.
• This method can be applied for some existing products by re-routing substrate metal traces in the laminate substrate to make space available for the cavity. This is only a slight change as compared to the standard substrate. Alternatively, the cavity can be designed into new laminate substrates.
• FIG. 5 is an enlarged portion of the cross-section ofFIG. 4. There is shown:
• • 1)Laminate substrate20
  • 2)Power management chip10.
  • 3)IPD chip14.
  • 4) Power management to substrate interconnect via flip chip attach35.
  • 5) IPD to power management interconnect micro bumps33.
  • 6) Flip Chip attachunderfill32.
  • 7)Epoxy Molding Compound34.
  • 8)Substrate cavity25.
  • 9)BGA solder balls30.
• Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims.

Claims (20)

What is claimed is:

1. A method of fabricating a mother and daughter integrated circuit device comprising:

providing a mother die having an active surface;

providing a daughter die having an active surface wherein said daughter die is smaller than said mother die in all dimensions;

directly connecting said active surface of said daughter die to said active surface of said mother die resulting in a pyramid die stack;

providing a substrate having a cavity drilled therein wherein said cavity corresponds to a size and position of said daughter die in relation to said mother die; and

attaching said pyramid die stack to said substrate using a flip chip method wherein said daughter die fits into said cavity.

2. The method according toclaim 1 wherein said mother die is a power management circuit chip.

3. The method according toclaim 1 wherein said daughter die is an integrated passive device containing at least one passive device.

4. The method according toclaim 3 wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter.

5. The method according toclaim 1 wherein said directly connecting said active surface of said daughter die to said active surface of said mother die comprises micro bumps.

6. The method according toclaim 1 wherein said cavity is drilled by a mechanical drilling process or a laser drilling process.

7. The method according toclaim 1 wherein said substrate is a ball grid array or a land grid array substrate.

8. The method according toclaim 1 wherein said attaching said pyramid die stack to said substrate comprises copper pillar interconnects.

9. A method of fabricating an integrated passive device comprising:

providing a first die containing at least one power management device;

providing a second die containing at least one passive device wherein said second die is smaller than said first die;

directly connecting an active surface of said second die to an active surface of said first die resulting in a die stack;

providing a substrate having a cavity drilled therein wherein said cavity corresponds to a size and position of said second die in relation to said first die; and

attaching said die stack to said substrate using a flip chip method wherein said second die fits into said cavity.

10. The method according toclaim 9 wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter.

11. The method according toclaim 9 wherein said directly connecting said active surface of said second die to said active surface of said first die comprises micro bumps.

12. The method according toclaim 9 wherein said cavity is drilled by a mechanical drilling process or by a laser drilling process.

13. The method according toclaim 9 wherein said substrate is a ball grid array or a land grid array substrate.

14. The method according toclaim 9 wherein said attaching said die stack to said substrate comprises copper pillar interconnects.

15. A mother and daughter integrated circuit comprising:

a mother die having an active surface;

a daughter die having an active surface wherein said daughter die is smaller than said mother die and wherein an active surface of said daughter die is directly connected to an active surface of said mother die resulting in a pyramid die stack; and

a substrate having a cavity drilled therein wherein said pyramid die stack is flip-chip attached to said substrate wherein said daughter die fits into said cavity.

16. The device according toclaim 15 wherein said mother die is a power management circuit chip.

17. The device according toclaim 15 wherein said daughter die is an integrated passive device containing at least one passive device.

18. The device according toclaim 17 wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter.

19. The device according toclaim 15 wherein said substrate is laminate substrate.

20. The device according toclaim 15 wherein said substrate is a ball grid array or a land grid array substrate.

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