US20140117550A1 - Semiconductor device including an insulating layer, and method of forming the semiconductor device - Google Patents

Abstract

A method of forming a semiconductor device, includes depositing first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer, heating the first copper material to reflow the first copper material into the trench, depositing a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material, and heating the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than 1ppm.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This Application claims priority to U.S. Provisional Patent Application No. 61/719,571 which was filed on Oct. 29, 2012, and is incorporated by reference herein.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates generally to a semiconductor device and, more particularly, to a semiconductor device including an insulating layer, and a method of forming the semiconductor device.
• 2. Description of the Related Art
• In conventional methods, a barrier material is formed in a trench (e.g., trench, via, narrow line, etc.) in an insulating layer of a semiconductor device, and a copper material (e.g., pure copper or copper alloys) is formed on the barrier material in the trench by electrochemical plating. The copper material is then planarized by chemical-mechanical polishing (CMP).
• However, in such conventional methods, nodular defects are formed at an interface between the copper material and barrier material (e.g., a metal such as tantalum) after CMP. Nodular defects are corrosion products formed by an electrochemical reaction at the interface between barrier and copper material after CMP. The nodular defects may degrade line-to-line leakage performance, especially for narrow spacing (e.g., 32 nm or less) between narrow lines (e.g., 32 nm or less).
• Conventionally, there are three methods of solving the problem of nodular defect formation after CMP. First, the manufacturer of the semiconductor device may minimize the time (e.g., q-time, or time between processes) between the CMP, and the subsequent dielectric cap deposition. This is one of the best conventional ways to avoid nodular defect formation. Second, the manufacturer may apply post-plating anneal with high temperature. This is also effective to suppress nodular defect formation. Third, the manufacturer may to apply a post-CMP chemical treatment.
• However, there are drawbacks to the three conventional methods of solving the problem of nodular defect formation. In particular, with respect to the first method, for mass production, a process which needs q-time control is not preferable because it may affect lot movement significantly. With respect to the second method, a high temperature anneal may cause via-chain yield degradation. With respect to the third method, applying a post-CMP chemical treatment raises process costs and increases process steps.
SUMMARY
• In view of the foregoing and other exemplary problems, disadvantages, and drawbacks of the aforementioned conventional methods, an exemplary aspect of the present invention is directed to method, device and system which may reduce a formation of nodular defects and, therefore, have a reduced line-to-line leakage current over conventional methods.
• An exemplary aspect of the present invention is directed to a method of forming a semiconductor device. The method includes depositing first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer, heating the first copper material to reflow the first copper material into the trench, depositing a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material, and heating the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than 1 ppm.
• Another exemplary aspect of the present invention is directed to a method of forming a semiconductor device. The method includes depositing a copper material by physical vapor deposition (PVD) on an insulating layer including a trench, and on a barrier material formed on a sidewall and a bottom of the trench, and during the depositing of the copper material, heating the copper material and applying an AC bias to the substrate to reflow the copper material into the trench, the copper material forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than 1 ppm.
• Another exemplary aspect of the present invention is directed to a semiconductor device which includes an insulating layer including a trench formed in a surface of the insulating layer, a barrier layer formed on a sidewall and a bottom of the trench, and a copper layer formed in the trench on the barrier layer and including an upper surface which is coplanar with the surface of the insulating layer, an amount of sulfur and chlorine in the copper layer being less than 1 ppm.
• With its unique and novel features, the present invention may provide a method of forming a semiconductor device which may reduce a formation of nodular defects and, therefore, have a reduced line-to-line leakage current over conventional methods.
BRIEF DESCRIPTION OF THE DRAWINGS
• The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of the embodiments of the invention with reference to the drawings, in which:
• FIG. 1 illustrates amethod100 of forming a semiconductor device, according to an exemplary aspect of the present invention;
• FIG. 2 illustrates amethod200 of forming a semiconductor device, according to an exemplary aspect of the claimed invention;
• FIGS. 3A-3H illustrate amethod300 of forming a semiconductor, according to an exemplary aspect of the present invention;
• FIG. 3I illustrates an upper surface (S_Cu4) of thefourth copper material230dwhich is planarized (e.g., by using chemical mechanical polishing (CMP) with the upper surface (S_ins) of theinsulating layer210, according to an exemplary aspect of the present invention;
• FIG. 4 illustrates asystem400 for forming a semiconductor device, according to an exemplary aspect of the present invention;
• FIG. 5 illustrates amethod500 of forming a semiconductor device, according to another exemplary aspect of the present invention;
• FIG. 6 illustrates an exemplary manner of implementing themethod500, according to an exemplary aspect of the present invention;
• FIG. 7A illustrates a schematic diagram of a pair of post-CMP lines700 (e.g., narrow lines having a width which is less than40nm) filled by electrochemical plating, according to a conventional method;
• FIG. 7B illustrates a schematic diagram of a pair of post-CMP lines750 (e.g., narrow lines having a width which is less than40nm) filled according to an exemplary aspect of the present invention (e.g.,method100,500,system400, etc.);
• FIG. 8A illustrates a top-down scanning electron microscope (SEM) image ofpost-CMP copper lines800 formed in a trench by conventional electrochemical plating;
• FIG. 8B illustrates a top-down SEM image ofpost-CMP copper lines850 formed in a trench by the exemplary aspects of the present invention (e.g., a PVD reflow process);
• FIG. 9 illustrates a graph which plots test data from experiments conducted by the inventors;
• FIG. 10 illustrates atypical hardware configuration1000 that may be used to implement the system and method of the present invention, in accordance with an exemplary aspect of the present invention; and
• FIG. 11 illustrates a magneticdata storage diskette1100 and compact disc (CD)1102 that may be used to store instructions for performing the inventive method of the present invention, in accordance with an exemplary aspect of the present invention.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS OF THE INVENTION
• Referring now to the drawings,FIGS. 1-6,7B,8B and9-11 illustrate some of the exemplary aspects of the present invention.
• The exemplary aspects of the present invention may solve the problem of nodular defect formation after CMP without the drawbacks of the conventional methods. In particular, the exemplary aspects of the present invention may not require strict q-time control (so lot movement is not adversely affected), may not require a high temperature anneal (so via-chain yield degradation is avoided), and may not require post-CMP chemical treatment (so an increase in process costs and process steps are avoided).
• As noted above, in conventional methods, copper is formed in a trench by electrochemical plating. The electrochemical plating uses a plating electrolyte which includes sulfur and chlorine, which appear as impurities (e.g., more than 10 ppm, respectively) in the copper.
• Based on their experimentation, the inventors have concluded that nodular defects are formed at the interface between copper and barrier material (e.g., tantalum) by an electrochemical reaction (e.g., corrosion) after the CMP, and since sulfur and chlorine enhance the corrosive reaction of copper, if sulfur and chlorine are incorporated in copper line, then nodular defects can form more easily at the interface. Therefore, the inventors concluded that nodular defect formation at the interface of the copper and barrier material may be suppressed by reducing an amount of sulfur and chlorine in the copper.
• FIG. 1 illustrates amethod100 of forming a semiconductor device, according to an exemplary aspect of the present invention.
• As illustrated inFIG. 1, themethod100 includes depositing (110) first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer, heating (120) the first copper material to reflow the first copper material into the trench, depositing (130) a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material, and heating (140) the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than1ppm.
• Themethod100 may also include performing chemical mechanical polishing (CMP) to planarize an upper surface of the copper layer and an upper surface of the insulating layer.
• Further, after the heating of the second copper material an elevation of an upper surface of the second copper material may be less than an elevation of the upper surface of the insulating layer (e.g., the trench being formed in the upper surface of the insulating layer). Thus, themethod100 may also include repeating the depositing of the second copper material and the heating of the second copper material until an elevation of an upper surface of the second copper material (after the heating of the second copper material) is greater than an elevation of the upper surface of the insulating layer.
• Further, themethod100 may also include selecting an optimum deposition rate for depositing the first copper material and the second copper material, the repeating of the depositing of the second copper material and the heating of the second copper material being performed a number of times which is based on the selected optimum deposition rate. Alternatively, themethod100 may include selecting an optimum number of times for performing the repeating of the depositing of the second copper material and the heating of the second copper material, the deposition rate for depositing of the first copper material and the second copper material, being based on the selected optimum number of times.
• After the CMP, an interface between the copper layer (e.g., embedded copper layer) and the barrier material (e.g., an inner sidewall of the barrier layer formed on a sidewall of the trench) may be substantially devoid of a nodular defect formation. That is, the sidewall of the copper layer may be uniform (e.g., flat) at the interface. Therefore, a line-to-line leakage current may be reduced as compared to a conventional device having a sidewall which includes a nodular defect formation.
• Thus, in an exemplary aspect of the present invention, a trench may be filled with a copper material (e.g., pure copper, copper alloy, etc.) by using PVD (e.g., only PVD), and without necessarily using electrochemical plating. That is, an entire volume of the trench which is bounded by the sidewalls of the barrier material (e.g., the inner sidewalls of the barrier layer which is formed on the sidewalls of the trench) and the bottom surface of the barrier material (e.g., the inner surface of the barrier layer which is formed on the bottom of the trench) may be filled with a copper material which is formed by PVD.
• In the PVD, a thin film of copper material (e.g., pure copper, copper alloy, etc.) is deposited on the insulating layer. Generally, the PVD may be performed in a deposition chamber, where the copper material to be deposited is converted into vapor by physical means, the vapor is transported across a region of low pressure from its source (e.g., a copper rod, bar, sheet, etc.) to the insulating layer (e.g., the barrier material in the trenches of the insulating layer), and the vapor undergoes condensation on the insulating layer to form the thin film of copper material.
• In particular, the PVD may include sputtering of the copper material in which atoms are dislodged from the surface of a material as a result of collision with high-energy particles. In particular, in the deposition chamber, ions (e.g., ions of an inert gas such as argon) are generated and directed at a target (e.g., a copper rod, bar, sheet, etc.), the ions sputter atoms or molecules of the copper material from the target, the sputtered atoms or molecules get transported to a surface of the insulating layer (e.g., the barrier material in the trenches of the insulating layer) through a region of reduced pressure, and the sputtered atoms condense on the insulating layer, forming a thin film.
• FIG. 2 illustrates amethod200 of forming a semiconductor device, according to an exemplary aspect of the claimed invention. As illustrate inFIG. 2, themethod200 may include a PVD copper thermal reflow process.
• Themethod200 illustrated inFIG. 2 may correspond, for example, to the depositing (110) of the first copper material, and the heating (120) of the first copper material, in themethod100. By using themethod200, a plurality of trenches (e.g., small features) may be filled completely with PVD copper material.
• In themethod200, a substrate (e.g., a semiconductor wafer) having an insulating layer210 (e.g., a patterned structure) formed thereon (atrench215 being formed in the insulatinglayer210 and a barrier material220 (e.g., Ta, TaN, TaN/Ta, Ti, TiN/Ti, TaN/Ru, TaN/Ta/Ru, TaN/Co, and TaN/Ta/Co) being formed on a bottom and a sidewall of the trench215), is placed in adeposition chamber250. As illustrated inFIG. 2, acopper material230 is deposited by physical vapor deposition (PVD) (e.g., conformally formed) on the insulatinglayer210 and on thebarrier material220, while the substrate is in the deposition chamber.
• For example, thetrenches215 inFIG. 2 may include a pair of lines (e.g., elongated trenches which form narrow lines) having a width in a range of 10 nm to 40 nm, and which may be separated by a distance of 50 nm or less.
• It should be noted that a thickness of thecopper material230 which is deposited by PVD (e.g., sputtering) may be substantially uniform across the surface of the insulating layer210 (e.g., across an entire surface of the insulating layer210). That is, a thickness of thecopper material230 deposited on thesidewalls220a,220band the bottom of thebarrier material220 in thetrench215, is the substantially equal to a thickness of thecopper material230 deposited on the upper surface (S_ins) of the insulatinglayer210.
• For purposes of the exemplary aspect of the present invention, thecopper material230 may have a thickness in a range of 10 nm to 50 nm, or more particularly, in a range from 15 nm to 25 nm. The thickness of thecopper material230 to be deposited may depend on several factors such as the width and depth of the trenches in the insulating layer, the aspect ratio of the trenches, the overall surface area of the insulating layer, and the number of cycles (e.g., deposition-reflow cycles) to be used to fill the trenches (e.g., the more cycles that are to be used, the less thickness to be deposited).
• After the depositing of thecopper material230, the substrate may be transferred (indicated by the arrow inFIG. 2) out of thedeposition chamber250 and into agas chamber270. As illustrated inFIG. 2, thecopper material230 is heated to reflow thecopper material230 into thetrench215, while the substrate is in thegas chamber270.
• That is, in the second step, the heating of the substrate (e.g., heating of the copper material) may cause thecopper material230 on an upper surface (S_ins) of the insulatinglayer210 to flow along the upper surface (S_ins) in a horizontal direction and into thetrench215 so that there is substantially nocopper material230 remaining on the upper surface (S_ins). Further, after the heating of the substrate, thecopper material230 in thetrench215 has a substantially horizontal and uniform upper surface (S_Cu) which extends from asidewall220aof thebarrier material220 to theother sidewall220bof the barrier material220 (e.g., a sidewall of thebarrier material220 which is opposite thesidewall220a). That is, there is substantially nocopper material230 remaining on thesidewalls220a,220bof thebarrier material220 above the upper surface (S_Cu) of thecopper material230.
• It should be noted that althoughFIG. 2 illustrates the first and second steps being performed inseparate chambers250,270, it is possible for the first and second steps to be performed in one chamber which may be used for both deposition of thecopper material230, and for heating (e.g., reflow) of thecopper material230.
• FIGS. 3A-3H illustrate amethod300 of forming a semiconductor, according to an exemplary aspect of the present invention. As illustrated inFIGS. 3A-3H, themethod300 may include a process sequence of trench filling with PVD copper by multi-cycle thermal reflow.
• In particular,FIGS. 3A-3B illustrate a first cycle in a multi-cycle process. InFIG. 3A, afirst copper material230ais deposited by physical vapor deposition (PVD) on the insulating layer210 (e.g., on the upper surface (S_ins) of the insulating layer210) and on the barrier material220 (e.g., a sidewall of the barrier layer formed on the sidewall of the trench215). InFIG. 3B, thefirst copper material230ais heated to reflow thefirst copper material230ainto thetrench215.
• As illustrated inFIG. 3B, the heating of the substrate causes thefirst copper material230aon the upper surface (S_ins) of the insulatinglayer210 to flow along the upper surface (S_ins) in a horizontal direction and into thetrench215 so that there is substantially nofirst copper material230aremaining on the upper surface (S_ins). Further, at the completion of the first cycle (e.g., at completion of the reflow), thefirst copper material230ain thetrench215 has a substantially horizontal and uniform upper surface (S_Cu1) which extends from asidewall220aof thebarrier material220 to theother sidewall220bof thebarrier material220. That is, there is substantially nofirst copper material230aremaining on thesidewalls220a,220bof thetrench220 above the upper surface (S_Cu1) of thecopper material230a.
• Further, as illustrated inFIG. 3B, after reflow, the upper surface S_Cu1of thefirst copper material230ais formed below the upper surface S_insof the insulatinglayer210. That is, only a portion of a volume of thetrench215 is filled by thefirst copper material230a.In particular, an amount of the volume of thetrench215 filled by thefirst copper material230amay range from 5% to 70% of the total volume of thetrench215.
• FIGS. 3C-3D illustrate a second cycle in the multi-cycle process. InFIG. 3C, asecond copper material230bis deposited by physical vapor deposition (PVD) on the insulatinglayer210, on thefirst copper material230a, and on the barrier material220 (e.g., a sidewall of the barrier layer formed on the sidewall of the trench215). InFIG. 3D, thesecond copper material230bis heated to reflow thesecond copper material230binto thetrench215.
• As illustrated inFIG. 3D, the heating of the substrate causes thesecond copper material230bon the upper surface (S_ins) of the insulatinglayer210 to flow along the upper surface (S_ins) in a horizontal direction and into thetrench215 so that there is substantially nosecond copper material230bremaining on the upper surface (S_ins). Further, at the completion of the second cycle (e.g., at completion of the reflow), thesecond copper material230bin thetrench215 has a substantially horizontal and uniform upper surface (S_Cu2) which extends from asidewall220aof thebarrier material220 to theother sidewall220bof thebarrier material220. That is, there is substantially nosecond copper material230bremaining on thesidewalls220a,220bof thetrench220 above the upper surface (S_Cu2) of thesecond copper material230b.
• Further, as illustrated inFIG. 3D, after reflow, the upper surface S_Cu2of thesecond copper material230bis formed below the upper surface S_insof the insulatinglayer210. That is, only a portion of a volume of thetrench215 is filled by thesecond copper material230b. In particular, a volume of thetrench215 filled by thesecond copper material230bmay range from 5% to 50% of the total volume of thetrench215.
• Further, as illustrated inFIG. 3D, the volume of thetrench215 which is filled by thesecond copper material230bmay be less than the volume of thetrench215 which is filled by thefirst copper material230a.However, in another aspect of the present invention, the volume of thetrench215 which is filled by thesecond copper material230bmay be equal to or greater than the volume of thetrench215 which is filled by thefirst copper material230a.
• FIGS. 3E-3F illustrate a third cycle in the multi-cycle process. InFIG. 3E, athird copper material230cis deposited by physical vapor deposition (PVD) on the insulatinglayer210, on the first andsecond copper materials230a,230b, and on the barrier material220 (e.g., a sidewall of the barrier layer formed on the sidewall of the trench215). InFIG. 3F, thethird copper material230cis heated to reflow thethird copper material230cinto thetrench215.
• As illustrated inFIG. 3F, the heating of the substrate causes thethird copper material230con the upper surface (S_ins) of the insulatinglayer210 to flow along the upper surface (S_ins) in a horizontal direction and into thetrench215 so that there is substantially nothird copper material230cremaining on the upper surface (S_ins). Further, at the completion of the third cycle (e.g., at completion of the reflow), thethird copper material230cin thetrench215 has a substantially horizontal and uniform upper surface (S_Cu3) which extends from asidewall220aof thebarrier material220 to theother sidewall220bof thebarrier material220. That is, there is substantially nothird copper material230cremaining on thesidewalls220a,220bof thetrench220 above the upper surface (S_Cu3) of thethird copper material230b.
• Further, as illustrated inFIG. 3F, after reflow, the upper surface S_Cu3of thethird copper material230cis formed below the upper surface S_insof the insulatinglayer210. That is, only a portion of a volume of thetrench215 is filled by thethird copper material230c.In particular, an amount of the volume of thetrench215 filled by thethird copper material230cmay range from 5% to 50% of the total volume of thetrench215.
• Further, as illustrated inFIG. 3F, the volume of thetrench215 which is filled by thethird copper material230cmay be less than the volume of thetrench215 which is filled by thefirst copper material230aand/or the volume of thetrench215 which is filled by the by thesecond copper material230b.However, in another aspect of the present invention, the volume of thetrench215 which is filled by thethird copper material230cmay be equal to or greater than the volume of thetrench215 which is filled by thefirst copper material230aand/or the volume of thetrench215 which is filled by the by thesecond copper material230b.
• FIGS. 3G-3H illustrate a fourth cycle in the multi-cycle process. InFIG. 3E, afourth copper material230cis deposited by physical vapor deposition (PVD) on the insulatinglayer210, on the first, second andthird copper materials230a,230b,230cand on the barrier material220 (e.g., a sidewall of the barrier layer formed on the sidewall of the trench215). InFIG. 3H, thefourth copper material230dis heated to reflow thefourth copper material230dinto thetrench215.
• As illustrated inFIG. 3H, the heating of the substrate causes thefourth copper material230don the upper surface (S_ins) of the insulatinglayer210 to flow along the upper surface (S_ins) in a horizontal direction and into thetrench215. However, unlike after the first, second and third cycles, after the fourth cycle there is some of thefourth copper material230dremaining on the upper surface (S_ins).
• That is, as illustrated inFIG. 3H, after reflow, the volume of the trench within thebarrier material220 is filled with a plurality of copper layers including a first layer formed by thefirst copper material230a, a second layer formed by thesecond copper material230b, a third layer formed by thethird copper material230c, and a fourth layer formed by thefourth copper material230d.Further, the upper surface S_Cu4of thefourth copper material230dis formed below the upper surface S_i, of the insulatinglayer210. The thickness of thefourth copper material230dremaining on the upper surface (S_ins) should be in a range from 1 nm to 20 nm, in order to ensure that thetrench215 is sufficiently filled by the first, second, third andfourth copper materials230a,230b,230c,230d.
• Further, the volume of thetrench215 which is filled by thefourth copper material230dmay be less than, equal to, or greater than the volume of thetrench215 which is filled by thefirst copper material230aand/or the volume of thetrench215 which is filled by the by thesecond copper material230b, and/or the volume of thetrench215 which is filled by the by thethird copper material230c.
• It should be noted that althoughFIGS. 3A-3H illustrate a multi-cycle process which includes four cycles (i.e., four deposition-reflow cycles), any number of cycles may be used. In the interest of time, the minimum number of cycles may be used. To fill the gap with fewer cycles would require that an increase in the thickness of the deposited copper material. However, if the thickness of the deposited copper material is too great, then a “pinching off” of the copper material may occur, in which the deposited copper material on thesidewalls220a,220bare joined together which may result in a void forming in the copper material. Thus, the minimum number of cycles may be determined by the maximum thickness of the deposited copper material, which may be determined by the risk of “pinch off”.
• As illustrated inFIG. 3I, upon completion of the fourth cycle, the upper surface (S_Cu4) of thefourth copper material230dmay be planarized (e.g., by using chemical mechanical polishing (CMP)) with the upper surface (S_ins) of the insulatinglayer210.
• FIG. 4 illustrates asystem400 for forming a semiconductor device, according to an exemplary aspect of the present invention.
• As illustrated inFIG. 4, thesystem400 includes adeposition chamber450 in which a deposition of a copper material is performed on asemiconductor wafer401, and a control device460 (e.g., controller, microprocessor, etc.) which controls an operation of thedeposition chamber450. Thesystem400 also includes agas chamber470 which in which a reflow of the copper material is performed on thesemiconductor wafer401, to produce a plurality of layers of copper material in a trench of an insulatinglayer410 on thesemiconductor wafer401, the uppermost layer of copper material430 (e.g.,fourth copper material230dinFIG. 3H) of the plurality of layers being formed on an upper surface (e.g., S_insinFIG. 3A) of the insulatinglayer410.
• Thecontrol device460 may also control an operation of thegas chamber470. Alternatively, there could be another control device which separately controls an operation of thegas chamber470. In addition, thesystem400 may include one processing chamber which performs both the deposition of the copper material and the reflow of the copper material (e.g., seeFIG. 6).
• As illustrated inFIG. 4, thedeposition chamber460 andgas chamber470 may also generate data which thecontrol device460 may use to control an operation of thechambers460,470. For example, thedeposition chamber460 may include a sensor for detecting a weight of thewafer401 in thechamber460, so that thedeposition chamber460 may generate weight data which is fed back to thecontrol device460. In this case, thecontrol device460 may control an operation of an ion generator in thedeposition chamber460 based on the weight data generated by the gas chamber.
• Similarly, thegas chamber470 may include a sensor for detecting a temperature of thewafer401 in thechamber470, so that thegas chamber470 may generate temperature data which is fed back to thecontrol device460. In this case, thecontrol device460 may control an operation of a heater in thegas chamber470 based on the temperature data generated by thegas chamber470.
• Thesystem400 may also include a memory device465 (e.g., random access memory (RAM), read-only memory (ROM), etc.) for storing programs and data. For example, thememory device465 may store data input by the user, and data generated by thedeposition chamber450 and thegas chamber470. Thememory device465 may be accessed by thecontrol device460, and may store data and programs for allowing thecontrol device460 to control the features and functions of thesystem400.
• Further, the programs which stored in thememory device465 and used by thecontrol device460 to control the features of thesystem400, may be updated by the data fed back to thecontrol device460 from thedeposition chamber450 and thegas chamber470. For example, if thememory device465 stores a program which calculates an optimum temperature for performing a reflow of the copper material, and a user manually sets a reflow temperature to be less than the calculated optimum temperature, then controldevice460 may adjust the program based on the temperature feedback data, so that in a subsequent operation of thesystem400, the optimum temperature calculated by the program may be reduced to reflect the user preference.
• Thesystem400 may also include an input device480 (e.g., keyboard, mouse, touchscreen, etc.) for inputting control parameters to thecontrol device460. In particular, theinput device480 and thecontrol device460 may be integrally formed as a single unit.
• For example, a user may use theinput device480 to input the number of deposition-reflow cycles to be performed by thesystem400, the desired thickness of the copper material to be deposited, a duration of the deposition of the copper material, a temperature of the wafer during the reflow of copper material, a duration of the reflow of the copper material, etc.
• Thecontrol device460 may also be programmed to set some control parameters based on a user input. For example, thecontrol device460 may include a control panel which displays a graphic user interface (GUI) which a user may manipulate by using theinput device480. The user may view the GUI while inputting data which is used by thecontrol device460 to set some of the control parameters.
• For example, a user may input a trench profile such as a width of a trench, a depth of a trench and whether there is any taper to the trench (e.g., if the trench is tapered to be more narrow at the top than at the bottom, then a thickness of the deposited copper material may be less than if there was no taper), a degree of taper to the trench, a desired thickness of the copper material to be deposited, a duration of the deposition, a number of cycles to be performed, a line spacing between the trenches, a surface area of the insulating layer, a type of copper material being used (e.g., pure copper, copper alloy, etc.), a temperature of the wafer during the reflow, duration of the reflow, and a flow rate of an inert gas during the deposition and during the reflow. This list is merely exemplary and is not exhaustive, and should not be considered as limiting the present invention in any manner.
• Based on the data input by the user using theinput device480, thecontrol device460 may execute a program stored in thememory device465 to generate a preferred set of operating parameters, which may be displayed on the GUI and viewed by the user. For example, thecontrol device460 may set (e.g., automatically set) a duration of copper material deposition and/or a duration of the reflow based on trench profile data (e.g., width of the trench, depth of the trench, taper of the trench) input by the user. Thecontrol device460 may also set a number of deposition-reflow cycles based on such trench profile data and/or the type of copper material being used.
• FIG. 5 illustrates amethod500 of forming a semiconductor device, according to another exemplary aspect of the present invention. As illustrated inFIG. 5, themethod500 includes depositing (510) a copper material by physical vapor deposition (PVD) on an insulating layer including a trench (e.g., a trench formed in an upper surface of the insulating layer), and on a barrier material formed on a sidewall and a bottom of the trench, and during the depositing of the copper material, heating (520) the copper material and applying an AC bias to the substrate to reflow the copper material into the trench, the copper material forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than1ppm.
• Further, the depositing of the copper material and the heating of the copper material may be performed until an elevation of an upper surface of the copper material is greater than an elevation of the upper surface of the insulating layer.
• Themethod500 may also include selecting an optimum deposition rate for the depositing the copper material. In this case, the depositing of the copper material and the heating of the copper material may be performed for a duration which is based on the selected optimum deposition rate.
• Themethod500 may also include selecting an optimum duration for performing the depositing of the copper material and the heating of the copper material. In this case, a deposition rate for the depositing of the copper material may be based on the selected optimum duration.
• FIG. 6 illustrates an exemplary manner of implementing themethod500. As illustrated inFIG. 6, themethod500 may include a process sequence of trench filling with PVD copper by thermal and ion assisted reflow.
• As illustrated inFIG. 6, in themethod500, a substrate (e.g., a semiconductor wafer) having an insulatinglayer610 formed thereon (atrench615 being formed in the insulatinglayer610 and a barrier material620(e.g., Ta, TaN, TaN/Ta, Ti, TiN/Ti, TaN/Ru, TaN/Ta/Ru, TaN/Co, and TaN/Ta/Co) being formed on a bottom and a sidewall of the trench615), is placed in aprocessing chamber650. Thechamber650 may be a combination of thedeposition chamber250 and the reflow chamber295 inFIG. 2, and may include all of the features of thechambers250,270 (and thechambers450,470 inFIG. 4).
• As illustrated inFIG. 6, in thechamber650, acopper material630 is deposited by physical vapor deposition (PVD) (e.g., conformally formed) on the insulatinglayer610 and on thebarrier material620. During the depositing of the copper material, the substrate is heated and a electrical bias (e.g., an AC bias) is applied to the substrate to reflow the copper material into thetrench615. Thus, during the depositing, the electrical bias may cause ions of inert gas (e.g., Argon ions) which are present in theprocessing chamber650 to assist the reflow of the copper material into thetrench615.
• That is, in themethod500 the copper material may be continuously (i.e., without interruption) deposited on the upper surface (S_ins) of the insulatinglayer610 and reflown into thetrench615. As a result, as illustrated inFIG. 6, over time (e.g., time progressing from left to right inFIG. 6, as illustrated by the arrows), the upper surface (S_Cu) of thecopper material630 rises in thetrench615. When the upper surface (S_Cu) of thecopper material630 rises above the upper surface (_Sins) of the insulatinglayer610, the heating of the substrate and the electrical bias may be stopped. The thickness of thecopper material630 remaining on the upper surface (S_ins) should be in a range from 1 nm to 20 nm, in order to ensure that thetrench215 is sufficiently filled by thecopper material630.
• The upper surface (S_Cu) of thecopper material630 may then be planarized (e.g., by CMP) so that the upper surface of thecopper material630 in the trench is coplanar with the upper surface of the insulating layer610 (e.g., seeFIG. 3I).
• Themethod500 may eliminate the need for transferring the substrate (e.g., semiconductor wafer) including the insulatinglayer610 back and forth to and from thedeposition chamber250 and thegas chamber270. Therefore, the time needed to fill thetrench615 may be less than the time needed to fill thetrench215 inFIGS. 3A-3H.
• In addition, the process time of themethod500 can be modulated depending on feature size (e.g., width of the trench, depth of the trench, etc.). For example, a process time for wider and deeper trenches may be greater than a process time for narrower and shallower trenches. Similarly, a deposition rate and/or a reflow rate may be modulated depending on the feature size. For example, a deposition rate and/or a reflow rate for a wider and deeper trench may be greater than a deposition rate and/or a reflow rate for narrow and shallow trenches.
• Similarly, the process time of themethod500 can be modulated depending on the number of trenches which are to be filled. For example, a process time for more trenches may be greater than a process time for fewer trenches. Similarly, a deposition rate and/or a reflow rate may be modulated depending on the number of trenches which are to be filled. For example, a deposition rate and/or a reflow rate for more trenches may be greater than a deposition rate and/or a reflow rate for fewer trenches.
• An advantage of themethod100 over themethod500 is that in themethod100, different types of copper materials may be used in different cycles. This may be useful where one type of copper material is, for example, less expensive, more conducive to processing by CMP or is better for bonding to the barrier material (e.g., tantalum) than other types of copper material. For example, if a copper alloy is more conducive to processing by CMP, but pure copper provides a better bond with the barrier material, then the copper alloy may be used for thecopper material230d,whereas pure copper may be used forcopper materials230a,230band230c.
• It should be noted that thesystem400 may also be used to implement themethod500. In this case, thedeposition chamber450 andgas chamber470 may be replaced by theprocessing chamber650 inFIG. 6. The features and functions of thesystem400 described above may also be applicable to a system which includes theprocessing chamber650.
• FIG. 7A illustrates a schematic diagram of a pair of post-CMP lines700 (e.g., narrow lines having a width which is less than 40 nm) filled by electrochemical plating, according to a conventional method.FIG. 7B illustrates a schematic diagram of a pair of post-CMP lines750 (e.g., narrow lines having a width which is less than 40 nm) filled according to an exemplary aspect of the present invention (e.g.,method100,500,system400, etc.). A distance between thelines700 may be 50 nm or less, and a distance between thelines750 may be 50 nm or less.
• As illustrated inFIG. 7A, thecopper material730 of the lines700 (e.g., elongated trenches) filled by electrochemical plating include sulfur and chlorine impurities. In particular, the amount of sulfur and chlorine impurities in thecopper material730 in thelines700 may be 10 ppm or more. As a result, nodular defects will likely form at an interface between the barrier metal and thecopper material730 in thelines700, resulting in a line-to-line leakage current between thelines700.
• As illustrated inFIG. 7B, thecopper material730 of thelines750 filled by the method of the exemplary aspects of the present invention is substantially devoid of sulfur and chlorine impurities. In particular, an amount of sulfur and chlorine in thecopper material730 in thelines750 may be less than1ppm. As a result, nodular defects will not likely form at an interface between the barrier metal and thecopper material730 in thelines750, so that a line-to-line leakage current between thelines700 may be avoided.
• FIG. 8A illustrates a top-down scanning electron microscope (SEM) image ofpost-CMP copper lines800 formed in a trench by conventional electrochemical plating , andFIG. 8B illustrates a top-down SEM image ofpost-CMP copper lines850 formed in a trench by the exemplary aspects of the present invention (e.g., a PVD reflow process). Both images inFIGS. 8A and 8B were taken 10 days after CMP, to enhance nodular defect growth.
• As illustrated inFIG. 8A, a plurality of nodular defects (D) are formed at an interface between the copper material and the barrier material in thecopper lines800 formed by conventional electrochemical plating. As illustrated inFIG. 8B, nodular defects are not formed at an interface between the copper material and the barrier material in thecopper lines850 formed according to the exemplary aspects of the present invention.
• The inventors have noted that the leakage current caused by nodular defects resulting from conventional electrochemical plating is especially problematic where the distance between the pair of lines is 50 nm or less. Thus, thepost-CMP copper lines800 would likely suffer from a leakage current between thecopper lines800 especially where the distance between thecopper lines800 is 50 nm or less. However, thepost-CMP copper lines850 would not likely suffer from a leakage current, even where the distance between thecopper lines850 is 50 nm or less.
• In particular, the inventors have performed secondary ion mass spectrometer (SIMS) analysis to compare devices formed by electrochemical plating with devices formed according to an exemplary aspect of the present invention (e.g., formed by PVD reflow). Based on the SIMS analysis, in the conventional electrochemical plating method, the sulfur(S) concentration was in a range of 3×10⁴- 4×10⁴counts per second (C/S), and the chlorine(Cl) concentration was in a range of more than 1×10⁵(C/S). In contrast, in the PVD reflow method, the sulfur(S) concentration was in a range of less than 3×10³(C/S), and the chlorine (Cl) concentration was in a range of less than 3×10³(C/S).
• As it is clear from these results, Cu layer formed according to an exemplary aspect of the present invention (e.g., PVD-reflow method) may have a significantly lower concentration of S and Cl than the Cu layer formed by the convention method (e.g., electrochemical plating method). This reduced concentration of S and Cl in the Cu layer formed by PVD may contribute to a reduction of a generation of nodular defects, as compared with the higher concentration of S and Cl in the Cu layer formed by the conventional method which may promote a generation of nodular defects.
• FIG. 9 illustrates a graph which plots test data from experiments conducted by the inventors. In the experiments, the inventors measured a line-to-line leakage current in copper lines filled by conventional electrochemical plating (e.g.,copper lines800 inFIG. 8A) and copper lines filled according to the exemplary aspects of the present invention (e.g., copper lines850). The graph inFIG. 9 plots the cumulative probability (%) vs. the line-to-line leakage current (A) for both the copper lines filled by conventional electrochemical plating and the copper lines filled according to the exemplary aspects of the present invention.
• As illustrated inFIG. 9, the line-to-line leakage current in the copper lines filled by conventional electrochemical plating was in a range from about 10⁻¹¹A to more than10⁻⁷A, whereas the line-to-line leakage current in the copper lines filled according to the exemplary aspects of the present invention was in a range from about 10⁻¹¹A to about 10⁻¹⁰A. That is, because of the nodular defects formed at the interface between the copper material and the barrier material in the copper lines filled by electrochemical plating, the leakage current of the copper lines filled by electrochemical plating is much higher than the leakage current of the copper lines filled according to the exemplary aspects of the present invention (e.g., PVD reflow process).
• Thus, the exemplary aspects of the present invention may fabricate narrow copper lines and/or vias which are substantially devoid of sulfur and chlorine (e.g., include less than1ppm of sulfur and chlorine, respectively) which are the root causes of nodular defect formation. This may allow the exemplary aspects of the present invention to achieve good line-to-line leakage performance (including TDDB performance).
• FIG. 10 illustrates asystem1000 including a typical hardware configuration which may be used for implementing a system (e.g., system400) for forming a semiconductor device, and method (e.g.,method100,300,500) of forming a semiconductor device, according to an exemplary aspect of the present invention.
• The configuration of thesystem1000 has preferably at least one processor or central processing unit (CPU)1010. TheCPUs1010 are interconnected via asystem bus1012 to a random access memory (RAM)1014, read-only memory (ROM)1016, input/output (I/O) adapter1018 (for connecting peripheral devices such asdisk units1021 andtape drives1040 to the bus1012), user interface adapter1022 (for connecting akeyboard1024,mouse1026,speaker1028,microphone1032 and/or other user interface device to the bus1012), acommunication adapter1034 for connecting an information handling system to a data processing network, the Internet, an Intranet, a personal area network (PAN), etc., and adisplay adapter1036 for connecting thebus1012 to adisplay device1038 and/orprinter1039. Further, an automated reader/scanner1041 may be included. Such readers/scanners are commercially available from many sources.
• In addition to the system described above, a different aspect of the invention includes a computer-implemented method for performing the above method. As an example, this method may be implemented in the particular environment discussed above.
• Such a method may be implemented, for example, by operating a computer, as embodied by a digital data processing apparatus, to execute a sequence of machine-readable instructions. These instructions may reside in various types of signal-bearing media.
• Thus, this aspect of the present invention is directed to a programmed product, including non-transitory, signal-bearing media tangibly embodying a program of machine-readable instructions executable by a digital data processor to perform the above method.
• Such a method may be implemented, for example, by operating theCPU1010 to execute a sequence of machine-readable instructions. These instructions may reside in various types of non-transitory, signal bearing media.
• Thus, this aspect of the present invention is directed to a programmed product, including non-transistory, signal-bearing media tangibly embodying a program of machine-readable instructions executable by a digital data processor incorporating the CPU1011 and hardware above, to perform the method of the invention.
• This non-transitory, signal-bearing media may include, for example, a RAM contained within theCPU1010, as represented by the fast-access storage for example. Alternatively, the instructions may be contained in another non-transitory, signal-bearing media, such as a magneticdata storage diskette1100 or compact disc1102 (FIG. 11), directly or indirectly accessible by theCPU1010.
• Whether contained in the computer server/CPU1010, or elsewhere, the instructions may be stored on a variety of machine-readable data storage media, such as DASD storage (e.g., a conventional “hard drive” or a RAID array), magnetic tape, electronic read-only memory (e.g., ROM, EPROM, or EEPROM), an optical storage device (e.g., CD-ROM, WORM, DVD, digital optical tape, etc.), paper “punch” cards, or other suitable signal-bearing media including transmission media such as digital and analog and communication links and wireless. In an illustrative embodiment of the invention, the machine-readable instructions may comprise software object code, compiled from a language such as C, C++, etc.
• Thus, an exemplary aspect of the present invention is directed to a programmable storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform a method of forming a semiconductor device (e.g.,method100,300,500).
• With its unique and novel features, the present invention may provide a method of forming a semiconductor device which may have a reduced line-to-line leakage current over conventional methods.
• While the invention has been described in terms of one or more exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Specifically, one of ordinary skill in the art will understand that the drawings herein are meant to be illustrative, and the design of the inventive method and system is not limited to that disclosed herein but may be modified within the spirit and scope of the present invention.
• Further, Applicant's intent is to encompass the equivalents of all claim elements, and no amendment to any claim the present application should be construed as a disclaimer of any interest in or right to an equivalent of any element or feature of the amended claim.

Claims (20)

What is claimed is:

1. A method of forming a semiconductor device, comprising;

depositing first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer;

heating the first copper material to reflow the first copper material into the trench;

depositing a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material; and

heating the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than1ppm.

2. The method ofclaim 1, further comprising:

performing chemical mechanical polishing (CMP) to planarize an upper surface of the copper layer and an upper surface of the insulating layer.

3. The method ofclaim 1, wherein after the heating of the second copper material, an elevation of an upper surface of the second copper material is less than an elevation of the upper surface of the insulating layer.

4. The method ofclaim 1, further comprising:

repeating the depositing of the second copper material and the heating of the second copper material until an elevation of an upper surface of the second copper material after the heating of the second copper material is greater than an elevation of the upper surface of the insulating layer.

5. The method ofclaim 1, further comprising:

selecting an optimum deposition rate for the depositing of the first copper material and the second copper material,

wherein the repeating of the depositing of the second copper material and the heating of the second copper material is performed a number of times which is based on the selected deposition rate.

6. The method ofclaim 1, further comprising:

selecting an optimum number of times for performing the repeating of the depositing of the second copper material and the heating of the second copper material,

wherein the depositing of the first copper material and the second copper material, is based on the selected number of times.

7. The method ofclaim 2, wherein after the performing of the CMP, an interface between the copper layer and the barrier material is devoid of a nodular defect formation.

8. The method ofclaim 1, wherein the copper layer comprises one of an interconnect, a narrow line and a via.

9. The method ofclaim 1, wherein the trench comprises a plurality of elongated trenches, a distance between the plurality of elongated trenches being less than50nm.

10. The method ofclaim 1, wherein a width of the trench is less than40nm.

11. The method ofclaim 1, wherein the barrier material is selected from a group consisting of Ta, TaN, TaN/Ta, Ti, TiN/Ti, TaN/Ru, TaN/Ta/Ru, TaN/Co, and TaN/Ta/Co.

12. The method ofclaim 1, wherein the first and second copper materials comprise one of copper and a copper alloy.

13. The method ofclaim 1, wherein the depositing of the first copper material and the depositing of the second copper material are performed in a deposition chamber, and the heating the first copper material and the heating of the second copper material are performed in a gas chamber which is different from the deposition chamber.

14. The method ofclaim 1, wherein the depositing of the first copper material, the depositing of the second copper material, the heating the first copper material and the heating of the second copper material are performed in the same chamber.

15. A method of forming a semiconductor device, comprising:

depositing a copper material by physical vapor deposition (PVD) on an insulating layer including a trench, and on a barrier material formed on a sidewall and a bottom of the trench; and

during the depositing of the copper material, heating the copper material and applying an AC bias to the substrate to reflow the copper material into the trench, the copper material forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than 1 ppm.

16. The method ofclaim 15, wherein the trench is formed in an upper surface of the insulating layer, and the depositing of the copper material and the heating of the copper material are performed until an elevation of an upper surface of the copper material is greater than an elevation of the upper surface of the insulating layer.

17. The method ofclaim 15, further comprising:

selecting an optimum deposition rate for the depositing the copper material,

wherein the depositing of the copper material and the heating of the copper material are performed for a duration which is based on the selected optimum deposition rate.

18. The method ofclaim 15, further comprising:

selecting an optimum duration for performing the depositing of the copper material and the heating of the copper material,

wherein a deposition rate for the depositing of the copper material is based on the selected optimum duration.

19. A semiconductor device, comprising;

an insulating layer including a trench formed in a surface of the insulating layer;

a barrier layer formed on a sidewall and a bottom of the trench; and

a copper layer formed in the trench on the barrier layer and including an upper surface which is coplanar with the surface of the insulating layer, an amount of sulfur and chlorine in the copper layer being less than1ppm.

20. The semiconductor device ofclaim 19, wherein the copper layer comprises:

a first copper layer formed in the trench and on the barrier layer; and

a second copper layer formed in the trench and on the first copper layer, the upper surface of the copper layer comprising an upper surface of the second copper layer.

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