US20140117501A1 - Differential moscap device - Google Patents

Abstract

A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments.

Description

TECHNICAL FIELD
• The disclosure relates to differential MOS capacitor devices and methods for forming the same.
BACKGROUND
• Differential capacitor devices such as differential MOSCAP devices are widely used in various applications and in various devices in the electronics industry. These semiconductor devices are fabricated using MOS, metal oxide semiconductor, manufacturing techniques, materials and principles. Differential capacitor devices include multiple capacitor sections or multiple capacitor plates or regions, and the different capacitor sections or different capacitor plates or regions can include different capacitances. Capacitance can be increased in one capacitor section of the MOS capacitor and decreased in another capacitor section of the MOS capacitor during operation, for example. Variable capacitances can be applied and the MOS capacitor devices therefore also serve as MOSVAR devices, i.e. MOS devices with variable reactance, i.e. variable capacitance.
• MOSCAP devices are formed on or over semiconductor substrates using MOS processing operations. One problem that plagues differential capacitors is parasitic capacitance. Parasitic capacitance is present between electronic components or parts because of their proximity to each other. Parasitic capacitance can result between different capacitor electrodes coupled to different gates. Parasitic capacitance can also result between a capacitor electrode and the drain/source pickup devices used to couple various components such as a lower capacitor plate, to ground. Parasitic capacitance can alter the intrinsic capacitance of a capacitor and can also adversely affect the effective capacitance of the operating capacitor of the differential capacitor device. Parasitic capacitance negatively affects device speed and device performance.
• It would therefore be desirable to provide methods and designs for differential MOS capacitor devices that eliminate or prevent parasitic capacitance.
BRIEF DESCRIPTION OF THE DRAWING
• The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.
• FIG. 1A is a top, plan view of an arrangement of a differential capacitor according to the disclosure andFIG. 1B is a cross-sectional view of a portion of the differential MOS capacitor ofFIG. 1A;
• FIGS. 2A and 2B are a plan view and a cross-sectional view of another embodiment of a differential MOS capacitor according to the disclosure;
• FIGS. 3A and 3B are a plan view and a cross-sectional view of another embodiment of a differential MOS capacitor according to the disclosure;
• FIG. 4 is a plan, top view of another embodiment of a differential MOS capacitor according to the disclosure; and
• FIG. 5 is a plan, top view of another embodiment of a differential MOS capacitor according to the disclosure.
DETAILED DESCRIPTION
• The disclosure provides a differential MOS capacitor (MOSCAP) with capacitor plates coupled to different gates. The gates can be biased differently. Different signals can be delivered to the gates and in one embodiment, out-of-phase signals are delivered to the gates. The differential MOSCAP includes multiple upper capacitor electrodes disposed over a common lower capacitor electrode which serves as a common node. In some embodiments, the common lower capacitor electrode is a conductive plate such as an N-well formed in a semiconductor substrate. The upper capacitor electrodes are formed over the common lower capacitor electrode in a capacitor region and, in some embodiments, no other electrical components are disposed in the capacitor region and no electrical connections are made to the capacitor region. In some embodiments, the MOSCAP device includes two capacitors or two capacitor sections coupled to two separate gates, with each of the capacitors or capacitor sections including multiple upper capacitor electrodes. In some embodiments, the multiple upper capacitor electrodes of each capacitor gate are adjacent one another, and in some embodiments, the multiple upper capacitor electrodes of both capacitors are disposed adjacent one another. In some embodiments, a guard ring is used and at least partially surrounds the lower conductive plate. In some embodiments, one or more drain/source pickup devices are used to couple the conductive plate serving as a common lower capacitor electrode, to ground.
• FIGS. 1A and 1B show an exemplary arrangement of a differential MOS capacitor according to the disclosure. The differential MOS capacitor includescapacitors2 and4 coupled togates6 and8, respectively. Each ofcapacitor2 andcapacitor4 may be alternatively referred to and considered to be a capacitor section of a differential MOS capacitor but will be referred to ascapacitors2 and4 throughout the disclosure. Capacitor2 includes twoupper capacitor plates12 andcapacitor4 includes twoupper capacitor plates14.Upper capacitor plates12 and14 are electrodes that are disposed withincapacitor region18 which is indicated by dashed lines.
• Capacitor region18 is rectangular in the illustrated embodiment and takes on other shapes in other embodiments.Capacitor region18 can generally be described as a convex polygon ascapacitor region18 does not include void areas or indentations within the region.Upper capacitor plates12 and14 are disposed overlower capacitor plate10.Lower capacitor plate10 is a conductive structure, and in one embodiment,lower capacitor plate10 is an N-well, or other active area or other conductive area formed within a semiconductor substrate such as withinsurface16, which is an upper surface ofsemiconductor substrate48. In other embodiments,lower capacitor plate10 is formed of different materials and may be formed withinsurface16 ofsemiconductor substrate48 or over a semiconductor substrate such assemiconductor substrate48.Capacitors2 and4 each include capacitor dielectric20 disposed betweenlower capacitor plate10 and eachupper capacitor plate12 and14. Various oxides or other suitable dielectric materials are used for capacitor dielectric20 and various dielectric thicknesses are used.Lower capacitor plate10 represents a common node between the twoupper capacitor plates12, a common node between the twoupper capacitor plates14, and also a common node betweenupper capacitor plates12 and14, i.e.lower capacitor plate10 is a common node forcapacitors2 and4.
• Upper capacitor plates12 and14 include different shapes and different structures in various embodiments. In the embodiment illustrated inFIG. 1A, eachupper capacitor plate12,14 is formed of three semiconductive or conductive layers disposed over one another and coupled by vias. In one embodiment, each of lowerconductive layer22, middleconductive layer24, and upperconductive layer26 is a metal and in another embodiment, lowerconductive layer22 is formed of doped or undoped polysilicon, with middleconductive layer24 and upperconductive layer26 formed of metal. Vias28 couple lowerconductive layer22 to middleconductive layer24 and also couple middleconductive layer24 to upperconductive layer26. Other arrangements are used in other embodiments and in some embodiments, eachupper capacitor plate12,14 is formed of fewer than three semiconductive or conductive layers shown inFIGS. 1A and 1B.Upper capacitor plates12 and14 are rectangular inFIG. 1A, but other shapes are used in other embodiments. Becauselower capacitor plate10 is a common node as indicated above,regions34 are largely void of any parasitic capacitance between the respectiveupper capacitor plates12 and between theupper capacitor plates14. Because there are no further electrical components inregions34, parasitic capacitance betweenupper capacitor plates12,14 and a further electrical component, is avoided. The components shown inFIGS. 1A and 1B are formed using various semiconductor manufacturing processes and materials in various embodiments.
• Arrow36 indicates thatcapacitors2 and4 serve as a differential MOS capacitor, with different signals delivered torespective capacitors2 and4. In one embodiment,gates6 and8 are coupled to signalsource38 as shown inFIG. 1A. Signalsource38 delivers AC signals in one embodiment. In one embodiment, signal42 delivered togate6 andcapacitor2, is out of phase withsignal44 delivered togate8 andcapacitor4. In one embodiment, signals42 and44 are 180° out of phase. In one embodiment, signals42 and44 are sinusoidal signals that are delivered such that a voltage of +1V is delivered to one ofgates6,8 at the same time a negative voltage of −1V is delivered to the other ofgates6,8. Various amplitudes and frequencies are used in various embodiments. In some embodiments, signals42 and44 are delivered in phase. In some embodiments, signals42,44 delivered togates6 and8 include the capacitance increasing incapacitor2 while the capacitance decreases incapacitor4, or vice versa. Although asingle signal source38 is shown inFIG. 1A, in other embodiments, two separate dedicated signal sources are used with a separate signal source dedicated to eachgate6,8. Either or both ofsignals42,44 may be signals that vary in strength and frequency andcapacitors2 and4 are varactors in various embodiments.
• In some embodiments, such as will be shown inFIGS. 2A and 2B, a guard ring is used to at least partially surroundlower capacitor plate10. In other embodiments, such as shown inFIGS. 1A and 1B, one ormore pickup devices30 are used.Pickup devices30 are drain/source pickup devices and are used to provide a direct connection betweenlower capacitor plate10 and ground. In one embodiment, allpickup devices30 are disposed outsidecapacitor region18. In other embodiments,pickup devices30 are situated such that they are not interposed betweenupper capacitor plates12 and such that they are not interposed betweenupper capacitor plates14. In still other embodiments, pickup devices are not used.Pickup devices30 are directly coupled tolower capacitor plate10 bycontacts40 and are formed of one or more layers of stacked conductive or semiconductor materials such as polysilicon and metal.Pickup devices30 are coupled to ground using various wires and other conductive interconnect features not shown inFIGS. 1A and 1B.
• FIGS. 2A,2B show another arrangement of a differential MOS capacitor according to the disclosure. The differential MOS capacitor includescapacitors52 and54. InFIG. 2A,capacitor52 includes twoupper capacitor plates56 andcapacitor54 includes twoupper capacitor plates58.Upper capacitor plates56 and58 are disposed withincapacitor region18.Upper capacitor plates56 and58 are arranged in an alternating matter and adjacent one another withincapacitor region18 andcapacitor region18 includes no other electrical components therein. In particular,capacitor region18 includes nopickup devices30 situated over and contactinglower capacitor plate10. Twopickup devices30 are disposed over and contactinglower capacitor plate10 in regions outsidecapacitor region18.Capacitors52 and54 are coupled to respective gates (not shown) and the gates are coupled to a signal source or multiple signal sources that provide separate signals to the respective gates as described above and therefore separate signals tocapacitors52,54.
• In the cross-sectional view ofFIG. 2B, eachupper capacitor plate56,58 includes only two conductive or semiconductive layers.Upper capacitor plates56 include two conductive orsemiconductive layers60 coupled byvias62 andupper capacitor plates58 each include two conductive orsemiconductive layers66 coupled byvias68. Conductive orsemiconductive layers60 may be the same as conductive or semiconductive layers66. In other embodiments such as was shown inFIG. 1A,1B, each upper capacitor plate is formed of three stacked conductive plates with interconnecting vias.FIGS. 2A and 2B showpickup devices30 disposed on and directly coupled tolower capacitor plate10 bycontacts40 and disposedoutside capacitor region18. In the illustrated embodiment ofFIG. 2B,pickup device30 is formed of only a single conductive layer which may be polysilicon or various suitable metals butpickup device30 is formed of various levels of conductive materials in various embodiments.FIG. 2B also showsguard ring70 formed withinsurface16 ofsemiconductor substrate48 andguard ring70 completely or at least partially surroundslower capacitor plate10.Guard ring70 is formed of vias and stacked metal layers in some embodiments. The depiction of bothpickup device30 andguard ring70 inFIG. 2B represents one embodiment only and in other embodiments, only one ofpickup device30 andguard ring70 is used and in still other embodiments, neither ofpickup device30 andguard ring70 is used. In some embodiments,lower capacitor plate10 is an N-well region. In some embodiments,lower capacitor plate10 is a P-well formed within an N-well or deep N-well region50 insemiconductor substrate48.Lower capacitor plate10 is formed of other materials in other embodiments.
• FIGS. 3A and 3B illustrate another arrangement of a differential MOS capacitor according to the disclosure.FIGS. 3A and3B show capacitors76 and78 that combine to form the differential MOS capacitor.Capacitor76 includesupper capacitor plates80 andcapacitor78 includesupper capacitors plates82.Upper capacitor plates80 and82 are all withinrectangular capacitor region18.Capacitor region18 does not includepickup devices30 or any other electrical components therein. In the arrangements shown inFIGS. 3A,3B, theupper capacitor plates80 fromcapacitor76 are immediately adjacent one another and internally adjacentupper capacitor plates82 ofcapacitor78.FIGS. 3A and 3B also show an embodiment in which theupper capacitor plates80,82 are disposed sequentially adjacent one another along a direction within capacitor region18 (extending left to right in the illustrated embodiment) which includes no further electrical components therein.
• FIG. 4 shows another embodiment of a differential MOS capacitor according to the disclosure. InFIG. 4,capacitors86,88 each include more than two upper capacitor plates. As in the other embodiments,capacitors86,88 may alternatively be considered to represent respective capacitor sections of a differential MOS capacitor.Capacitor86 includes fourupper capacitor plates90 andcapacitor88 includes fourupper capacitor plates92. Eachcapacitor86,88 is coupled to a gate and a signal source, not shown inFIG. 4.FIG. 4 also illustrates an embodiment in whichupper capacitor plates90,92 are disposed sequentially adjacent one another withincapacitor region18 that includes no other electrical components therein. In particular,capacitor region18 is void ofpickup devices30 which are, instead, disposed external tocapacitor region18. The arrangements shown inFIGS. 1A,1B,2A,2B,3A,3B andFIG. 4 are examples of the various arrangements according to the disclosure in which two or more capacitors, each having two or more upper capacitor plates disposed over a common node, are formed in a capacitor region in which no further electrical components are situated. Various other arrangements in which two capacitors, each having two or more upper capacitor plates disposed over a common node, i.e., over a common lower capacitor plate, are used in other embodiments in which the capacitors combine to form a differential MOS capacitor. In many embodiments, the upper capacitor electrodes are disposed adjacent one another in a region, i.e.,capacitor region18, that does not include pickup devices or other electrical components within acapacitor region18. In some embodiments, pickup devices are disposed outside the capacitor region and in other embodiments, a guard ring at least partially surrounds the lower capacitor plate.
• FIG. 5 shows another embodiment of a differential MOS capacitor according to the disclosure.
• FIG. 5 shows another exemplary arrangement and shows two differential MOS capacitors. Each differential MOS capacitor includes onecapacitor96 havingupper capacitor plates100 and onecapacitor98 havingupper capacitor plates102. Eachcapacitor96,98 is coupled to a gate and a common or dedicated signal source, as in the embodiment illustrated inFIG. 1A. In each case, the upper capacitor plates,100 or102 of a particular capacitor are disposed adjacent one another with no other electrical components such aspickup devices30, between the upper capacitor plates. In the embodiment ofFIG. 5,pickup devices30 are regularly spaced betweencapacitors96 and98 withinlower capacitor plate10. Pickup devices couplelower capacitor plate10 to ground. In other embodiments,pickup devices30 are not used and a guard ring such asguard ring70 is used. In some embodiments, bothpickup devices30 andguard ring70 are used.
• According to one aspect, a differential MOS capacitor semiconductor device is provided. The differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes coupled to the first gate; a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes coupled to the first gate; a conductive plate that serves as a common bottom capacitor plate for each of the first and second capacitor sections and is formed in or on a substrate surface, wherein the plurality of first capacitor upper electrodes and the plurality of second capacitor upper electrodes are each disposed over the common bottom capacitor plate. In some embodiments, no further electrical components are interposed between the capacitor upper electrodes.
• According to another aspect, a differential MOS capacitor semiconductor device is provided. The differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes; a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes; and a conductive plate that serves as a common bottom capacitor plate for each of the first and second capacitor sections, is disposed in or on a substrate surface, and includes an enclosed capacitor region thereover. The capacitor region includes the plurality of first capacitor upper electrodes and the plurality of second capacitor upper electrodes. In some embodiments, no further electrical components are within the capacitor region.
• According to yet another aspect, a differential MOS capacitor semiconductor device is provided. The differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes disposed over a common bottom capacitor plate; a second capacitor section coupled to a second gate and including a duality of second capacitor upper electrodes disposed over the common bottom capacitor plate; the common bottom capacitor plate comprising a conductive plate disposed in a semiconductor substrate. The first gate is coupled to a first AC signal source; and the second gate is coupled to a second AC signal source. The first signal source delivers first signals that are in phase or out of phase with second signals delivered from the second AC signal source.
• The preceding merely illustrates the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
• This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise
• Although the disclosure has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the disclosure, which may be made by those of ordinary skill in the art without departing from the scope and range of equivalents of the disclosure.

Claims (23)

What is claimed is:

1. A differential MOS capacitor semiconductor device comprising:

a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes coupled to said first gate;

a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes coupled to said first gate; and

a conductive plate that serves as a common bottom capacitor plate for each of said first and second capacitor sections and is formed in or on a substrate surface,

wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are each disposed over said common bottom capacitor plate.

2. The differential MOS capacitor semiconductor device as inclaim 1, wherein no electrical components are interposed between said first capacitor upper electrodes of said plurality of first capacitor upper electrodes; no electrical components are interposed between said second capacitor upper electrodes of said plurality of second capacitor upper electrodes, and no electrical components are interposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes

3. The differential MOS capacitor semiconductor device as inclaim 2, wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are arranged adjacent one another.

4. The differential MOS capacitor semiconductor device as inclaim 1, wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are arranged adjacent one another.

5. The differential MOS capacitor semiconductor device as inclaim 4, wherein said plurality of first capacitor upper electrodes comprise a duality of said first capacitor upper electrodes and said plurality of second capacitor upper electrodes comprise a duality of said second capacitor upper electrodes and wherein said first capacitor upper electrodes are juxtaposed and disposed adjacent said duality of second capacitor upper electrodes which are also juxtaposed.

6. The differential MOS capacitor semiconductor device as inclaim 4, wherein said first capacitor upper electrodes and said second capacitor upper electrodes are arranged sequentially adjacent one another along a first direction and one of said plurality of first capacitor upper electrodes is interposed between adjacent second capacitor upper electrodes of said plurality of second capacitor upper electrodes.

7. The differential MOS capacitor semiconductor device as inclaim 1, wherein:

said substrate comprises a semiconductor substrate;

said conductive plate comprises an N-well formed in said substrate surface; and

no electrical components and no electrical connections to said conductive plate are disposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.

8. The differential MOS capacitor semiconductor device as inclaim 1, wherein said substrate comprises a semiconductor substrate and said conductive plate comprises an N-well formed in said semiconductor substrate.

9. The differential MOS capacitor semiconductor device as inclaim 8, wherein no electrical components are disposed within a convex polygonal region that includes said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes and further comprising a pickup device formed on said conductive plate laterally outside said convex polygonal region, said pickup device coupling said conductive plate to ground.

10. The differential MOS capacitor semiconductor device as inclaim 9, wherein said pickup device couples said conductive plate to ground through at least one electrical wire disposed over said conductive plate.

11. The differential MOS capacitor semiconductor device as inclaim 1, wherein said first gate is coupled to a first AC signal source and said second gate is coupled to a second AC signal source, wherein said first and second signal sources deliver signals that are out of phase.

12. The differential MOS capacitor semiconductor device as inclaim 1, wherein each said first capacitor upper electrode and each said second capacitor upper electrode is formed of polysilicon or a first metal layer of a plurality of metal layers, and

further comprising a guard ring disposed in said substrate surface and at least partially surrounding said conductive plate.

13. The differential MOS capacitor semiconductor device as inclaim 1, wherein each of said first capacitor section and said second capacitor section is a variable capacitance MOS capacitor.

14. The differential MOS capacitor semiconductor device as inclaim 1, wherein each said first capacitor upper electrode and each said second capacitor upper electrode is formed of a plurality of stacked metal layers coupled together with vias.

15. The differential MOS capacitor semiconductor device as inclaim 1, wherein each of said first capacitor upper electrodes and second capacitor upper electrodes are disposed within a capacitor portion of said conductive plate, said capacitor portion having a convex polygonal shape, and wherein no further electrical components are disposed within said capacitor portion.

16. A differential MOS capacitor semiconductor device comprising:

a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes;

a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes; and

a conductive plate that serves as a common bottom capacitor plate for each of said first and second capacitor sections, is disposed in or on a substrate surface, and includes an enclosed capacitor region thereover, said enclosed capacitor region including said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.

17. The differential MOS capacitor semiconductor device as inclaim 16, wherein said enclosed capacitor region is a convex polygon and includes no further electrical components therein.

18. The differential MOS capacitor semiconductor device as inclaim 16, wherein said substrate comprises a semiconductor substrate, no further electrical components are disposed within said enclosed capacitor region, said conductive plate comprises an N-well formed in said semiconductor substrate, and

further comprising a pickup device formed on said conductive plate laterally outside said capacitor region, said pickup device coupling said conductive plate to ground.

19. The differential MOS capacitor semiconductor device as inclaim 16, wherein:

said first gate is coupled to a first AC signal source and said second gate is coupled to a second AC signal source, said first and second signal sources delivering signals that are out of phase;

each said first and second capacitor upper electrode is formed of a plurality of stacked metal layers coupled together with vias; and

each of said first capacitor section and said second capacitor section is a variable capacitance MOS capacitor.

20. A differential MOS capacitor semiconductor device comprising:

a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes disposed over a common bottom capacitor plate;

a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes disposed over said common bottom capacitor plate;

said common bottom capacitor plate comprising a conductive plate disposed in a semiconductor substrate;

said first gate coupled to a first AC signal source; and

said second gate coupled to a second AC signal source,

wherein said first AC signal source delivers first signals that are in phase or out of phase with second signals delivered from said second AC signal source.

21. The differential MOS capacitor semiconductor device as inclaim 20, wherein no electrical components are interposed between said first capacitor upper electrodes of said plurality of first capacitor upper electrodes; no electrical components are interposed between said second capacitor upper electrodes of said plurality of second capacitor upper electrodes, and no electrical components are interposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.

22. The differential MOS capacitor semiconductor device as inclaim 21, wherein said first capacitor upper electrodes and said second capacitor upper electrodes are arranged sequentially adjacent one another along a first direction in a capacitor region that includes no further electrical components therein.

23. The differential MOS capacitor semiconductor device as inclaim 20, further comprising a guard ring disposed in said semiconductor substrate and at least partially surrounding said conductive plate, and wherein said first capacitor upper electrodes and said second capacitor upper electrodes each include a plurality of stacked metal layers.

Images