US20140103294A1 - Techniques and configurations to impart strain to integrated circuit devices - Google Patents

Abstract

Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application claims priority to U.S. patent application Ser. No. 12/646,697, entitled “TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES,” filed Dec. 23, 2009. The application is hereby incorporated by reference herein in its entirety for all purposes.
FIELD
• Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to techniques and configurations to impart strain to integrated circuit devices such as horizontal field-effect transistors.
BACKGROUND
• Generally, integrated circuit devices such as transistors are being formed in emerging semiconductor thin films such as, for example, group III-V semiconductor materials for electronic or optoelectronic devices. Increasing carrier mobility of such group III-V materials may increase a speed of integrated circuit devices formed therein.
BRIEF DESCRIPTION OF THE DRAWINGS
• Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
• FIG. 1 schematically illustrates an example integrated circuit device in accordance with some embodiments.
• FIG. 2 provides a diagram of band gap energy and lattice constant for some example semiconductor materials in accordance with some embodiments.
• FIG. 3 provides a graph of stress and corresponding resistance for a group III-V semiconductor material.
• FIG. 4 provides a band gap energy diagram through a vertical direction of an integrated circuit device in accordance with some embodiments.
• FIG. 5 schematically illustrates formation of a source structure and drain structure in a semiconductor heterostructure after various process operations in accordance with some embodiments.
• FIG. 6 schematically illustrates formation of electrode structures and a strain-inducing film on a semiconductor heterostructure after various process operations in accordance with some embodiments.
• FIG. 7 is a flow diagram of a method for fabricating an integrated circuit in accordance with some embodiments.
• FIG. 8 schematically illustrates an example processor based system that may include an integrated circuit device as described herein in accordance with some embodiments.
DETAILED DESCRIPTION
• Embodiments of the present disclosure provide techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments in accordance with the present disclosure is defined by the appended claims and their equivalents.
• Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
• The description may use perspective-based descriptions such as horizontal/vertical, up/down, back/front, over/under, and top/bottom. Such descriptions may not restrict the application of embodiments described herein to a particular orientation.
• For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
• The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
• The term “coupled” may be used to describe various relationships between components herein. For example, the term “coupled to” may generally refer to a more direct physical connection between components, unless otherwise expressed (e.g., “electrically coupled,” “communicatively coupled,” or “coupled to [perform a function]”). The term “coupled with” generally refers to a physical connection where other intervening components may or may not be present between such coupled components.
• FIG. 1 schematically illustrates an example integrated circuit device in accordance with some embodiments. In an embodiment, theintegrated circuit device100 includes asemiconductor substrate102, one ormore buffer films104, afirst barrier film106, aquantum well channel108, asecond barrier film110, anetch stop film112, acontact film114, asource structure116, adrain structure118, asource electrode120, adrain electrode122, agate electrode124, and a strain-inducingfilm126, coupled as shown.
• Thesemiconductor substrate102 may include N-type or P-type (100) off-oriented silicon, the crystalline directions of thesemiconductor substrate102 being symbolized by the convention (xyz), where x, y, and z represent respective crystallographic planes in three dimensions that are perpendicular to one another. Thesemiconductor substrate102 may, for example, include material of a (100) direction off-cut in a range between about 2 degrees to about 8 degrees towards a (110) direction. Other off-cut orientations or asubstrate102 without an off-cut orientation may be used. Off-cutting may eliminate anti-phase boundaries.
• Thesemiconductor substrate102 may have a high resistivity between about1 Ω-cm to about50 kΩ-cm. High resistivity may allow for device isolation of one or more integrated circuit devices (e.g., integrated circuit device100) formed on anactive surface125 of thesemiconductor substrate102. Theactive surface125 may be a substantially planar surface upon which integrated circuit devices (e.g., integrated circuit device100) such as transistors are formed.
• One ormore buffer films104 may be coupled to thesemiconductor substrate102. In an embodiment, the one ormore buffer films104 include a nucleation buffer film (not shown) and a graded buffer film (not shown). The nucleation buffer film may be used, for example, to fillsemiconductor substrate102 terraces with atomic bi-layers of a semiconductor material including, for example, one or more group III-V semiconductor materials and/or one or more group II-VI semiconductor materials, or combinations thereof. A nucleation portion (not shown) of the nucleation buffer film may create a virtualpolar semiconductor substrate102. Such nucleation portion may, for example, have a thickness of about 3 nanometers (nm) to about 50 nm. A buffer film portion (not shown) of the nucleation buffer film may serve as a buffer against dislocation threading and/or provide control of a lattice mismatch of about 4% to about 8% between thesemiconductor substrate102 and thefirst barrier film106. The buffer film portion of nucleation buffer film may, for example, have a thickness of about 0.3 microns to about 5 microns. The nucleation buffer film (e.g., the one or more buffer films104) may include group III-V semiconductors and/or group II-VI semiconductors, such as gallium arsenide (GaAs). Other material systems may be used to form the nucleation buffer film including N-type or P-type material systems.
• The one ormore buffer films104 may further include a graded buffer film (not shown) formed on the nucleation buffer film (not shown). The graded buffer film may include, for example, group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof. For example, the graded buffer film may include indium aluminum arsenide (In_xAl_1−xAs), where x has a value between 0 and 1, representing the relative composition of the elements. In one embodiment, x has a value between about 0 and about 0.52. In another embodiment, the graded buffer film includes indium aluminum antimonide (InAlSb).
• Other material systems including N-type or P-type materials may be used for the graded buffer film in other embodiments. For example, the graded buffer film may include inverse graded InAlAs or indium gallium aluminum arsenide (InGaAlAs) to provide a larger bandgap for device isolation. Increasing the relative percentage of aluminum (Al) in the graded buffer film in such a material system may strategically increase strain (e.g., compressive strain) to thequantum well channel108 to increase performance of theintegrated circuit device100.
• The graded buffer film may also provide stress relaxation between thesemiconductor substrate102 and other lattice mismatched films, such as, for example, thefirst barrier film106, to reduce threading dislocation defects in theintegrated circuit device100. The graded buffer film may, for example, have a thickness of about0.5 microns to2 microns. Other thicknesses may be used in other embodiments. The one ormore buffer films104 may include other buffer films, or techniques that provide similar function as described herein in other embodiments.
• The one ormore buffer films104 may be epitaxially deposited. In an embodiment, the one or more buffer films are deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments.
• Afirst barrier film106 may be coupled with thesemiconductor substrate102. For example, thefirst barrier film106 may be coupled to the one ormore buffer films104 formed on thesemiconductor substrate102, as illustrated. Thefirst barrier film106 may include group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof. In an embodiment, thefirst barrier film106 includes indium aluminum arsenide (In_xAl_1−xAs), where x has a value between 0 and 1, representing the relative composition of the elements. According to various embodiments, x has a value between about 0.5 and about 0.8. In another embodiment, thefirst barrier film106 includes indium aluminum antimonide (InAlSb). In yet another embodiment, thefirst barrier film106 includes indium phosphide (InP). Other material systems including N-type materials and/or P-type materials may be used for thefirst barrier film106 in other embodiments.
• Thefirst barrier film106 may include a material that has a higher bandgap than a material used for thequantum well channel108. A thickness for thefirst barrier film106 may be selected to provide a sufficient barrier to charge carriers in thequantum well channel108. In an embodiment, thefirst barrier film106 has a thickness of about 10 nm to about 200 nm. Other thicknesses for thefirst barrier film106 may be used in other embodiments.
• Thefirst barrier film106 may be epitaxially deposited. In an embodiment, thefirst barrier film106 is deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments.
• Aquantum well channel108 may be coupled to thefirst barrier film106. Thequantum well channel108 may include group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof. In an embodiment, thequantum well channel108 includes indium gallium arsenide (In_xGa_1−xAs), where x has a value between 0 and 1, representing the relative composition of the elements. In an embodiment, x includes values between about 0.5 and about 0.8. In another embodiment, thequantum well channel108 includes indium antimonide (InSb). Thequantum well channel108 may include various other material systems including N-type or P-type materials in other embodiments. Thequantum well channel108 provides a pathway for mobile charge carriers such as electrons or holes to move between asource structure116 and adrain structure118. According to various embodiments, thequantum well channel108 provides electron mobility for N-type devices and/or provides hole mobility for P-type devices.
• According to various embodiments, thequantum well channel108 has a band gap energy that is relatively smaller than a band gap for thefirst barrier film106 and thesecond barrier film110. Thequantum well channel108 may have a thickness that provides channel conductance for theintegrated circuit device100. According to various embodiments, thequantum well channel108 has a thickness of about 2 nm to about 15 nm. Thequantum well channel108 may have other thicknesses in other embodiments.
• Thequantum well channel108 may be epitaxially deposited. In an embodiment, thequantum well channel108 is deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments.
• Asource structure116 is coupled to provide mobile charge carriers (e.g., electrons or holes) for thequantum well channel108. According to various embodiments, thesource structure116 includes a material having a lattice constant that is different (e.g., greater or smaller) than a lattice constant of a material used to form thequantum well channel108 to impart a strain on thequantum well channel108. Thesource structure116 may be epitaxially coupled to thequantum well channel108 to form a heterojunction such that the different lattice constant between the materials for thesource structure116 and thequantum well channel108 creates a compressive or tensile strain on thequantum well channel108. A material for thesource structure116 may be selected to provide a desired or sufficient conductivity and/or epitaxial connection with thequantum well channel108 according to well-known band-gap engineering principles.
• Thesource structure116 may be coupled to horizontally inject the mobile charge carriers into thequantum well channel108. For example, a strain imparted by thesource structure116 may increase an injection velocity of the mobile charge carriers in a direction that is substantially parallel with a direction (e.g., arrow150) of current flow in thequantum well channel108. The direction indicated byarrow150 may be a longitudinal direction of thequantum well channel108. A horizontal direction may refer to a direction (e.g., arrow150) that is substantially parallel with the active surface (e.g.,125) of thesemiconductor substrate102 and/or substantially parallel with the longitudinal direction of thequantum well channel108. That is, strain imparted by thesource structure116 may be a uniaxial strain in a direction that is substantially parallel with the active surface (e.g.,125) of the semiconductor substrate and/or substantially parallel with the longitudinal direction of thequantum well channel108. According to various embodiments, theintegrated circuit device100 is a horizontal field-effect transistor, or a high electron mobility transistor, or combinations thereof. Theintegrated circuit device100 may include other types of transistors that benefit from embodiments described herein, including non-planar transistors such as multi-gate transistors. Theintegrated circuit device100 may be a transistor having a gate length of about 15 nm. Other gate lengths may be used in other embodiments.
• Applying a strain to thequantum well channel108 as described herein may reduce an effective mass and/or resistance of thequantum well channel108, thereby increasing a velocity of mobile charge carriers in thequantum well channel108. Increasing the velocity of the mobile charge carriers may improve direct current (DC) and radio frequency (RF) characteristics of theintegrated circuit device100.
• Thesource structure116 may be formed using a variety of materials including group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof. In an embodiment, thesource structure116 includes gallium arsenide (GaAs). In another embodiment, thesource structure116 includes indium aluminum arsenide (InAlAs). According to various embodiments, thesource structure116 has a thickness of less than about 60 nm. Thesource structure116 may have other thicknesses in other embodiments. In an embodiment, thesource structure116 is deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments.
• Adrain structure118 may be coupled to receive the mobile charge carriers from thequantum well channel108. According to various embodiments, thedrain structure118 includes a material having a lattice constant that is different (e.g., greater or smaller) than a lattice constant of a material used to form thequantum well channel108 to impart a strain on thequantum well channel108. Thedrain structure118 may be epitaxially coupled to thequantum well channel108 to form a heterojunction such that the different lattice constant between the materials for thedrain structure118 and thequantum well channel108 creates a compressive or tensile strain on thequantum well channel108. A material for thedrain structure118 may be selected to provide a desired or sufficient conductivity and/or epitaxial connection with thequantum well channel108 according to well-known band-gap engineering principles.
• According to various embodiments, thedrain structure118 includes the same material as thesource structure116 to conjunctively increase or enhance the compressive or tensile strain applied to thequantum well channel108 by thesource structure116. In an embodiment, a lattice constant for a material used to form thesource structure116 and/or thedrain structure118 is smaller than a lattice constant for a material used to form thequantum well channel108 to impart a tensile strain that increases a velocity of electrons in an N-type integrated circuit device. In another embodiment, a lattice constant for a material used to form thesource structure116 and/or thedrain structure118 is larger than a lattice constant for a material used to form thequantum well channel108 to impart a compressive strain that increases a velocity of holes in a P-type integrated circuit device.
• Thedrain structure118 may be formed using a variety of materials including group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof. In an embodiment, thedrain structure118 includes gallium arsenide (GaAs). In another embodiment, thedrain structure118 includes indium aluminum arsenide (InAlAs). According to various embodiments, thedrain structure118 has a thickness of less than about 60 nm. Thedrain structure118 may have other thicknesses in other embodiments. In an embodiment, thedrain structure118 is deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments.
• Thesource structure116 and/or thedrain structure118 may be doped with an impurity, according to various embodiments. For example, thesource structure116 and/or thedrain structure118 may be delta-doped, modulation doped and/or combinations thereof. For an N-type device, thesource structure116 and/or thedrain structure118 may be doped with silicon (Si), sulfur (S), tellurium (Te), or combinations thereof. For a P-type device, thesource structure116 and/or thedrain structure118 may be doped with beryllium (Be), carbon (C), or combinations thereof. Other impurities may be used to dope thesource structure116 and/or thedrain structure118 in other embodiments. According to one or more embodiments, thequantum well channel108 may be un-doped while thesource structure116 and/or thedrain structure118 are doped to create an N-type or P-type device. In such embodiment, the undoped quantum well-channel108 may be a channel of the N-type or P-type device.
• Asecond barrier film110 may be coupled to thequantum well channel108 to provide confinement for mobile charge carriers when they travel in thequantum well channel108. Thesecond barrier film110 may comport with embodiments already described in connection with thefirst barrier film110 including material types, thicknesses, and/or deposition techniques. According to various embodiments, thesecond barrier film110 is a Schottky barrier layer for control of thequantum well channel108 using thegate electrode124. In an embodiment, thequantum well channel108 is disposed between thefirst barrier film110 and thesecond barrier film110, as illustrated.
• Anetch stop film112 may be coupled with thesecond barrier film110. Theetch stop film112 may be used to facilitate formation of thegate electrode124. Theetch stop film112 may include group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof, including, for example, indium phosphide (InP), InAlSb, or suitable combinations thereof. Other material systems including N-type materials and/or P-type materials may be used for theetch stop film112 in other embodiments.
• In an embodiment, theetch stop film112 has a thickness of about 2 nm to 15 nm. Other thicknesses for theetch stop film112 may be used in other embodiments. In an embodiment, theetch stop film112 is deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments.
• Acontact film114 may be coupled with theetch stop film112. Thecontact film114 may include group III-V semiconductor materials and/or group II-VI semiconductor materials, or combinations thereof, including, for example, InGaAs. Other material systems including N-type materials and/or P-type materials may be used for thecontact film114 in other embodiments. Thecontact film114 may be doped to increase electrical conductivity of thecontact film114. For example, thecontact film114 may be delta-doped, modulation doped and/or combinations thereof. For an N-type device, thecontact film114 may be doped with silicon (Si), sulfur (S), tellurium (Te), or combinations thereof. For a P-type device, thecontact film114 may be doped with beryllium (Be), carbon (C), or combinations thereof. Other impurities may be used to dope thecontact film114 in other embodiments. Other structures described herein may be doped according to similar principles to affect conductivity or other physical or electrical properties.
• In an embodiment, thecontact film114 has a thickness of about 5 to 50 nm. Other thicknesses of thecontact film114 may be used in other embodiments. In an embodiment, thecontact film114 is deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), epitaxial growth, chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof. Other suitable deposition methods may be used in other embodiments. Theintegrated circuit device100 may include other films and structures such as, for example, spacer films, doped films, other barrier films, and/or strain-inducing films, which may intervene between structures and features described herein, according to various embodiments.
• Asource electrode120 and adrain electrode122 may be coupled to therespective source structure116 and thedrain structure122. Agate electrode124 may be coupled to control the flow of mobile charge carriers in thequantum well channel108. According to various embodiments, a gate dielectric (not shown) may be formed between thegate electrode124 and thequantum well channel108. The gate dielectric may include, for example silicon oxide (SiO₂), silicon oxynitride (SiO_xN_y), silicon nitride (Si_xN_y) aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium aluminum oxide (HfAl_xO_y), hafnium silicon oxide (HfSi_xO_y), zirconium oxide (ZrO₂), zirconium silicon oxide (ZrSi_xO_y), lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), lanthanum aluminum oxide (LaAl_xO_y), tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), barium strontium titanium oxide (BaSrTi_xO_y), barium titanium oxide (BaTi_xO_y), strontium titanium oxide (SrTi_xO_y), lead scandium tantalum oxide (PbSc_xTa_yO_z), or lead zinc niobate (PbZn_xNb_yO_z), or combinations thereof, where x, y, and z represent suitable quantities of the respective elements. Other materials may be used in other embodiments for the gate dielectric.
• Thecontact film114 may be electrically insulated or isolated from thegate electrode124 by a variety of techniques, including, for example, recessing thecontact film114 to form an air gap or depositing a spacer dielectric material between thegate electrode124 and thecontact film114. In an embodiment, thesecond barrier film110 is a Schottky barrier layer for thegate electrode124 to provide a Schottky junction through which thegate electrode124 may control thequantum well channel108.
• Thegate electrode124, thesource electrode120, and thedrain electrode122 may include a wide variety of suitable electrically conductive materials. For example, theelectrodes120,122,124 may include copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof. Theelectrodes120,122,124 may include a metal nitride such as, for example, titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof. Theelectrodes120,122,124 may include a metal silicide such as, for example, titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof. Theelectrodes120,122,124 may include a metal silicon nitride such as, for example, titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof. Theelectrodes120,122,124 may include a metal carbide such as, for example, titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AIC), or combinations thereof. Theelectrodes120,122,124 may include a metal carbon nitride such as, for example, tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. Other suitable materials may be used in other embodiments for theelectrodes120,122,124 such as conductive metal oxides (e.g., ruthenium oxide).
• A strain-inducingfilm126 may be formed on or over theelectrodes120,122,124 and/or thecontact film114, thesource structure116, and thedrain structure118. According to various embodiments, the strain-inducingfilm126 is an amorphous material that is blanket-deposited (e.g., deposited over and on all exposed structures of the integrated circuit device100) by any of a variety of well-known deposition techniques to stress the deposited material such as plasma-enhanced chemical vapor deposition (PECVD) and/or low pressure chemical vapor deposition (LPCVD). Portions of the strain-inducingfilm126 may be recessed or selectively removed to allow formation of conductive interconnects to be coupled with theelectrodes120,122,124. In the process of relaxing, the strain-inducingfilm126 may transfer strain to underlying structures such as thequantum channel108 of theintegrated circuit device100. According to various embodiments, the strain may be compressive for P-type integrated circuit devices or tensile for N-type integrated circuit devices. The strain-inducingfilm126 may incorporate a variety of materials including, for example, silicon nitride or silicon oxide materials. In an embodiment, the strain-inducingfilm126 has a thickness of about10 nm. Other thicknesses may be used in other embodiments.
• FIG. 2 provides a diagram200 of band gap energy and lattice constant for some example semiconductor materials in accordance with some embodiments. The band gap energy (eV) is depicted on avertical axis202 and a lattice constant (Angstroms) is depicted on ahorizontal axis204. The diagram200 depicts some example semiconductor materials that may be used to fabricate theintegrated circuit device100 for visual comparison of respective band gap energies and lattice constants. For example, points are illustrated on the diagram200 for indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), germanium (Ge), gallium antimonide (GaSb), silicon (Si), indium phosphide (InP), gallium arsenide (GaAs), aluminum antimonide (AlSb), aluminum arsenide (AlAs), gallium phosphide (GaP), and aluminum phosphide (AlP). Materials for structures and features described herein may be selected to provide a desired or sufficient conductivity and/or epitaxial connection relative to adjacent structures and features according to well-known band-gap engineering principles.
• The example semiconductor materials depicted in the diagram200 are not intended to be an exhaustive representation of materials that can be used to form structures described herein. A wide variety of suitable materials, many of which may not be illustrated in the diagram200, can be used to form structures described herein, including other combinations of the elements and compounds depicted in diagram200.
• FIG. 3 provides agraph300 of stress and corresponding resistance for a group III-V semiconductor material. Ahorizontal axis302 depicts stress in megapascals (MPa) and avertical axis304 depicts a change of resistance (Rs) in percentage (%) for an applied stress. Thepoints306 correspond with data collected from bending a wafer including indium gallium arsenide (InGaAs) to impart stress (e.g., longitudinal tension to spread atoms apart in a direction of current flow) on the InGaAs. Thetrend line308 is a best fit line through the data points306. Thetrend line308 shows a general decrease in resistance (e.g., sheet resistance) with increasing stress, which may provide increased mobility of charge carriers in an N-type device.
• FIG. 4 provides a band gap energy diagram400 through a vertical direction (e.g., from A to A′) of theintegrated circuit device100. Ahorizontal axis402 represents vertical position through theintegrated circuit device100 in nanometers (nm) andvertical axis404 represents increasing energy in electron-volts (eV) in the direction of the vertical axis arrow. Avalence band energy406 and aconduction band energy408 for materials between position A and position A′ of theintegrated circuit device100 are depicted. As illustrated, aband gap energy410 of the second barrier film (e.g.,110) is greater than aband gap energy412 of the quantum well channel (e.g.,108) and aband gap energy414 of the first barrier film (e.g.,106) is greater than theband gap energy412 of the quantum well channel (e.g.,108). The first barrier film (e.g.,106) and the second barrier film (e.g.,110) may be doped with an impurity to provide confinement of mobile charge carriers to the quantum well channel (e.g.,108).
• FIG. 5 schematically illustrates formation of asource structure516 anddrain structure518 in asemiconductor heterostructure500aafter various process operations in accordance with some embodiments. Asemiconductor heterostructure500amay be formed according to various techniques described herein. Afirst barrier film506 may be formed and coupled with asemiconductor substrate502. For example, thefirst barrier film506 may be deposited on thesemiconductor substrate502 or on one or more buffer films (e.g.,104) formed on thesemiconductor substrate502.
• A material forquantum well channel508 may be deposited on or over thefirst barrier film506, followed by deposition of a material for thesecond barrier film510 on or over thequantum well channel508. Acontact film514 may be deposited on or over thesecond barrier film510 to form thesemiconductor heterostructure500a.Thesemiconductor heterostructure500amay include other films and/or structures, including films described herein (e.g.,etch stop film112 of the integrated circuit device100), that are omitted inFIG. 5 for the sake of clarity. Thefilms506,510,514, and thequantum well channel508 may be epitaxially deposited.
• Inmanufacturing product500b,portions of thesemiconductor heterostructure500aare selectively removed to form a first recessedregion515 and a second recessedregion517. In an embodiment, portions of at least thecontact film514, thesecond barrier film510, and thequantum well channel508 are removed to form the first recessedregion515 and the second recessedregion517. In another embodiment, portions of thesemiconductor heterostructure500aare selectively removed prior to deposition of thecontact film514. In such embodiment, portions of at least thesecond barrier film510 and thequantum channel508 are removed to form the first recessedregion515. Thecontact film514 may be subsequently deposited subsequent to formation of the first recessedregion515 and/or the second recessedregion517 according to various embodiments.
• In an embodiment, the first recessedregion515 and the second recessedregion517 are simultaneously formed by an etching process. The first recessedregion515 and the second recessedregion517 may be separately formed in other embodiments. Other processes such as lithography or other patterning processes may be used to selectively remove portions of thesemiconductor heterostructure500ato form the first recessedregion515 and the second recessedregion517 in themanufacturing product500b.
• Inmanufacturing product500c,a material is deposited to form asource structure516 in the first recessedregion515 and adrain structure518 in the second recessedregion517. The material of thesource structure516 and thedrain structure518 may have a lattice constant that is larger or smaller than a lattice constant of the material used to form thequantum well channel508. According to various embodiments, material for thesource structure516 and thedrain structure518 is simultaneously deposited. Thesource structure516 and thedrain structure518 may be separately formed in other embodiments. Material for thesource structure516 and/or the drain structure may be epitaxially deposited. Thesource structure516 and thedrain structure518 may apply uniaxial strain (e.g., compressive or tensile) to thequantum well channel508 according to techniques described herein to increase velocity of mobile charge carriers in an integrated circuit device (e.g.,100).
• FIG. 6 schematically illustrates formation of electrode structures (e.g.,620,622,624) and a strain-inducing film (e.g.,626) on a semiconductor heterostructure (e.g.,500a) after various process operations in accordance with some embodiments.Manufacturing product600arepresents themanufacturing product500cofFIG. 5 after formation of asource electrode620, adrain electrode622, and agate electrode624.
• Inmanufacturing product600a,thegate electrode624 may be formed by selective removal (e.g., by etching and/or lithography) of portions of at least thecontact film514 and thesecond barrier film510 to form a third recessed region (not shown). An etch stop film (e.g.,112) may be used to facilitate control of etching processes to form the third recessed region. A gate dielectric (not shown) may be deposited into the third recessed region, and a material to form thegate electrode624 may be deposited on the gate dielectric. Thecontact film514 may be recessed to electrically insulate thegate electrode624 from thecontact film514 or to reduce leakage from thegate electrode624 to thecontact film514.Gate electrode624 may be electrically insulated from conductive elements (e.g., the contact film514) in a variety of ways including by an air spacer, an insulating material such as silicon oxide or silicon nitride, or a high-k dielectric to line the sidewalls of thecontact film514. Other gate control techniques and structures may be used in other embodiments. For example, thesecond barrier film510 may operate as a Schottky junction for control of thequantum well channel508.
• An electrode material may be deposited to form thesource electrode620 and thedrain electrode622. A variety of suitable deposition techniques including chemical vapor deposition, sputtering, and/or epitaxial deposition techniques may be used to deposit theelectrodes620,622,624. Patterning techniques such as lithography and/or etch processes may be used to selectively deposit the electrode material. In an embodiment, electrode material for thesource electrode620, thedrain electrode622, and thegate electrode624 is deposited during the same deposition operation. In other embodiments, one or more of theelectrodes620,622,624 are formed during separate deposition operations.
• Inmanufacturing product600b,a strain-inducingfilm626 is formed on or over themanufacturing product600a.The strain-inducingfilm626 may be deposited according to a variety of techniques to impart strain on the underlying structures, such as thequantum well channel508, including, for example, plasma-enhanced chemical vapor deposition (PECVD) and/or low pressure chemical vapor deposition (LPCVD) methods to stress the material deposited to form the strain-inducingfilm626. Portions of the strain-inducingfilm626 may be recessed or selectively removed to allow formation of conductive interconnects to be coupled with theelectrodes620,622,624. According to various embodiments, the strain may be compressive for P-type integrated circuit devices or tensile for N-type integrated circuit devices. The strain-inducingfilm626 may incorporate a variety of materials including, for example, silicon nitride or silicon oxide materials. In an embodiment, the strain-inducingfilm626 has a thickness of about 10 nm. Other thicknesses may be used in other embodiments. Other well-known semiconductor structures and/or process operations may be used in fabricating themanufacturing product600b.
• FIG. 7 is a flow diagram of amethod700 for fabricating an integrated circuit (e.g.,100) in accordance with some embodiments. Themethod700 includes forming a semiconductor heterostructure atblock702. The semiconductor heterostructure (e.g.,500a) can be formed according to a variety of techniques described herein. In an embodiment, the semiconductor heterostructure is formed by depositing a first barrier film on or over a semiconductor substrate, depositing a quantum well channel film on or over the first barrier film, depositing a second barrier film on or over the quantum well channel film, and/or depositing a contact film on or over the second barrier film. Other intervening films and/or structures may be deposited to form the semiconductor heterostructure. The films may be epitaxially deposited according to various embodiments.
• Atblock704, themethod700 further includes selectively removing portions of the semiconductor heterostructure to form a first recessed region and a second recessed region in the semiconductor heterostructure. For example, portions of the contact film, the second barrier film and/or the quantum well channel may be selectively removed. The selective removal may be performed by etch and/or lithography processes.
• Atblock706, themethod700 further includes depositing a material to form a source and a drain structure in the first recessed region and the second recessed region. The material used to form the source structure and the drain structure may be the same. In such case, the material may be deposited during the same deposition operation to form the source structure and the drain structure.
• Atblock708, themethod700 further includes forming electrode structures (e.g.,620,622,624) for the source structure, the drain structure, and a gate structure to form a transistor device (e.g.,100 or600a). At block710, themethod700 further includes depositing a strain-inducing film (e.g.,126 or626) on the transistor device to reduce resistance in a quantum well channel (e.g.,108 or508) of the transistor device.Method700 may include other techniques and configurations described in connection withFIGS. 1-6.
• FIG. 8 schematically illustrates an example processor basedsystem2000 that may include an integrated circuit device (e.g.,100) as described herein in accordance with some embodiments. Theprocessor system2000 may be a desktop computer, a laptop computer, a handheld computer, a tablet computer, a PDA, a server, an Internet appliance, and/or any other type of computing device.
• Theprocessor system2000 illustrated inFIG. 8 includes achipset2010, which includes amemory controller2012 and an input/output (I/O)controller2014. Thechipset2010 may provide memory and I/O management functions as well as a plurality of general purpose and/or special purpose registers, timers, etc. that are accessible or used by aprocessor2020. Theprocessor2020 may be implemented using one or more processors, WLAN components, WMAN components, WWAN components, and/or other suitable processing components. Theprocessor2020 may include acache2022, which may be implemented using a first-level unified cache (L1), a second-level unified cache (L2), a third-level unified cache (L3), and/or any other suitable structures to store data.
• Thememory controller2012 may perform functions that enable theprocessor2020 to access and communicate with amain memory2030 including avolatile memory2032 and anon-volatile memory2034 via abus2040. WhileFIG. 8 shows abus2040 to communicatively couple various components to one another, other embodiments may include additional/alternative interfaces.
• Thevolatile memory2032 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and/or any other type of random access memory device. Thenon-volatile memory2034 may be implemented using flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), and/or any other desired type of memory device.
• Theprocessor system2000 may also include aninterface circuit2050 that is coupled to thebus2040. Theinterface circuit2050 may be implemented using any type of interface standard such as an Ethernet interface, a universal serial bus (USB), a third generation input/output interface (3GIO) interface, and/or any other suitable type of interface.
• One ormore input devices2060 may be connected to theinterface circuit2050. The input device(s)2060 permit an individual to enter data and commands into theprocessor2020. For example, the input device(s)2060 may be implemented by a keyboard, a mouse, a touch-sensitive display, a track pad, a track ball, an isopoint, and/or a voice recognition system.
• One ormore output devices2070 may also be connected to theinterface circuit2050. For example, the output device(s)2070 may be implemented by display devices (e.g., a light emitting display (LED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, a printer and/or speakers). Theinterface circuit2050 may include, among other things, a graphics driver card.
• Theprocessor system2000 may also include one or moremass storage devices2080 to store software and data. Examples of such mass storage device(s)2080 include floppy disks and drives, hard disk drives, compact disks and drives, and digital versatile disks (DVD) and drives.
• Theinterface circuit2050 may also include a communication device such as a modem or a network interface card to facilitate exchange of data with external computers via a network. The communication link between theprocessor system2000 and the network may be any type of network connection such as an Ethernet connection, a digital subscriber line (DSL), a telephone line, a cellular telephone system, a coaxial cable, etc.
• In some embodiments, theprocessor system2000 may be coupled to an antenna structure (not shown in the figure) to provide access to other devices of a network. In some embodiments, the antenna structure may include one or more directional antennas, which radiate or receive primarily in one direction (e.g., for 120 degrees), cooperatively coupled to one another to provide substantially omnidirectional coverage; or one or more omnidirectional antennas, which radiate or receive equally well in all directions. In some embodiments, the antenna structure may include one or more directional and/or omnidirectional antennas, including, e.g., a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a microstrip antenna or any other type of antennas suitable for OTA transmission/reception of RF signals.
• Access to the input device(s)2060, the output device(s)2070, the mass storage device(s)2080 and/or the network may be controlled by the I/O controller2014. In particular, the I/O controller2014 may perform functions that enable theprocessor2020 to communicate with the input device(s)2060, the output device(s)2070, the mass storage device(s)2080 and/or the network via thebus2040 and theinterface circuit2050.
• While the components shown inFIG. 8 are depicted as separate blocks within theprocessor system2000, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although thememory controller2012 and the I/O controller2014 are depicted as separate blocks within thechipset2010, thememory controller2012 and the I/O controller2014 may be integrated within a single semiconductor circuit.
• According to various embodiments, theprocessor2020, themain memory2030, or thechipset2010, or combinations thereof, may include one or more integrated circuit devices (e.g.,100) or transistors that include features described herein. The one or more integrated circuit devices may include, for example, horizontal field-effect transistors, or high electron mobility transistors (HEMT), or combinations thereof. Theprocessor2020, themain memory2030, or thechipset2010 may include a P-type metal-oxide-semiconductor (PMOS) device and/or an N-type metal-oxide-semiconductor (NMOS) device.
• Although certain embodiments have been illustrated and described herein for purposes of description, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.

Claims (19)

What is claimed is:

1. An apparatus comprising:

a semiconductor substrate;

a quantum well channel coupled with the semiconductor substrate;

a source structure coupled with the quantum well channel;

a drain structure coupled with the quantum well channel; and

a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate.

2. The apparatus ofclaim 1, wherein the strain-inducing film is planar.

3. The apparatus ofclaim 2, wherein the strain-inducing film comprises an amorphous material.

4. The apparatus ofclaim 3, wherein the strain-inducing film comprises silicon oxide or silicon nitride.

5. The apparatus ofclaim 1, wherein:

the strain-inducing film is configured to impart a tensile strain on the quantum well channel to increase a velocity of mobile charge carriers in the quantum well channel, the mobile charge carriers being electrons; and

the quantum well channel is a channel of an N-type device.

6. The apparatus ofclaim 1, wherein:

the strain-inducing film is configured to impart a compressive strain on the quantum well channel to increase a velocity of mobile charge carriers in the quantum well channel, the mobile charge carriers being holes; and

the quantum well channel is a channel of a P-type device.

7. The apparatus ofclaim 1, wherein:

the quantum well channel comprises a first material having a first lattice constant;

the source structure and the drain structure comprise a second material having a second lattice constant that is different than the first lattice constant; and

material of the quantum well channel does not extend into the source structure.

8. The apparatus ofclaim 7, wherein:

the source structure is epitaxially coupled to the quantum well channel to form a heterojunction;

the drain structure is epitaxially coupled to the quantum well channel to form another heterojunction; and the quantum well channel, the source structure, and the drain structure comprise a group III-V semiconductor, or a group II-VI semiconductor, or combinations thereof.

9. The apparatus ofclaim 1, wherein the quantum well channel is a channel of a horizontal field-effect transistor; and

wherein the horizontal field-effect transistor is a high electron mobility transistor (HEMT).

10. The apparatus ofclaim 1, further comprising:

a contact layer coupled with the quantum well channel, wherein the quantum well channel is disposed between the contact layer and the semiconductor substrate and the strain-inducing layer is in direct contact with the contact layer.

11. The apparatus ofclaim 10, further comprising:

a first barrier layer disposed between the quantum well channel and the semiconductor substrate; and

a second barrier layer disposed between the contact layer and the quantum well channel, wherein the first barrier layer comprises a material having a bandgap energy that is greater than a bandgap energy of the quantum well channel; and the second barrier layer comprises a material having a bandgap energy that is greater than the bandgap energy of the quantum well channel.

12. The apparatus ofclaim 11, further comprising one or more buffer layers epitaxially coupled to the semiconductor substrate, the first barrier layer being epitaxially coupled to the one or more buffer layers.

13. The apparatus ofclaim 11, wherein:

the semiconductor substrate comprises silicon (Si),

the first barrier layer comprises indium aluminum arsenide (InAlAs), or indium phosphide (InP), or combinations thereof,

the quantum well channel comprises indium gallium arsenide (InGaAs),

the source structure and the drain structure comprise gallium arsenide (GaAs),

the second barrier layer comprises indium aluminum arsenide (InAlAs), or indium phosphide (InP), or combinations thereof, and

the contact layer comprises indium gallium arsenide (InGaAs).

14. A method comprising:

forming a semiconductor heterostructure comprising:

a semiconductor substrate, and

a quantum well channel coupled with the semiconductor substrate;

forming a source structure coupled with the quantum well channel and a drain structure coupled with the quantum well channel; and

depositing a strain-inducing film on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate.

15. The method ofclaim 14, wherein depositing the strain-inducing film comprises depositing an amorphous material.

16. The method ofclaim 14, wherein depositing the strain-inducing film provides a planar strain-inducing film.

17. The method ofclaim 14, wherein depositing the strain-inducing film comprises blanket-depositing silicon oxide or silicon nitride by plasma-enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

18. The method ofclaim 14, wherein subsequent to depositing the strain-inducing film, the strain-inducing film transfers strain to the quantum channel in a process of relaxing.

19. The method ofclaim 14, wherein:

forming the semiconductor heterostructure further comprises depositing a contact layer on the quantum well channel; and

the strain-inducing layer is in direct contact with the contact layer.

Images