US20140053979A1 - Reduced number of masks for ic device with stacked contact levels - Google Patents

Abstract

A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2^Nlevels of interconnect contact regions at the stack of contact levels. According to some examples, 2^x-1contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.

Description

REFERENCE TO RELATED APPLICATIONS
• This application is a divisional of U.S. patent application Ser. No. 13/049,303 filed 16 Mar. 2013, attorney docket MXIC 1965-2; which claims the benefit of U.S. provisional patent application No. 61/434,086 filed 19 Jan. 2011, attorney docket MXIC 1965-1.
• This application is related to the following: U.S. provisional patent application No. 61/434,423 filed 19 Jan. 2011, attorney docket MXIC 1971-1; U.S. patent application Ser. No. 12/579,192 filed 14 Oct. 2009, now U.S. Pat. No. 8,154,128, attorney docket MXIC 1901-1.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates generally to high density integrated circuit devices, and more particularly to interconnect structures for multi-level three-dimensional stacked devices.
• 2. Description of Related Art
• In the manufacturing of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Thus, as the critical dimensions of the memory devices approach lithographic technology limits, techniques for stacking multiple levels of memory cells have been proposed in order to achieve greater storage density and lower costs per bit.
• For example, thin film transistor techniques are applied to charge trapping memory in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
• Also, cross-point array techniques have been applied for anti-fuse memory in Johnson et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells,” IEEE J. of Solid-State Circuits, Vol. 38, No. 11, November 2003. See, also U.S. Pat. No. 7,081,377 to Cleeves entitled “Three-Dimensional Memory.”
• Another structure that provides vertical NAND cells in a charge trapping memory technology is described in “Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE,” by Kim et al., 2008 Symposium on VLSI Technology Digest of Technical Papers;” 17-19 Jun. 2008; pages 122-123.
• In three-dimensional stacked memory devices, conductive interconnects used to couple the lower levels of memory cells to decoding circuitry and the like pass through the upper levels. The cost to implement the interconnections increases with the number of lithographic steps needed. One approach to reduce the number of lithographic steps is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007; pages 14-15.
• However, one of the drawbacks with conventional 3-D stacked memory devices is that a separate mask is typically used for each contact level. Therefore, if there are, for example, 20 contact levels, 20 different masks are commonly required, each contact level requiring the creation of a mask for that level and an etching step for that level.
SUMMARY OF THE INVENTION
• According to some examples of the present invention, it only requires N masks to provide access to a landing area at 2^Ncontact levels. According to some examples, 2^x-1contact levels are etched for each mask sequence number x.
• A first example of a method, for use with a three-dimensional stacked IC device having a stack of contact levels at an interconnect region, is used to create interconnect contact regions aligned with and exposing landing areas at the contact levels. A set of N etch masks is used to create up to and including 2^Nlevels of interconnect contact regions at the stack of contact levels. Each mask comprises mask and etch regions. N is an integer equal to at least 2. x is a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. At least a portion of any upper layer overlying the stack of contact levels at the interconnect region is removed. The interconnect region is etched N times using said masks in a chosen order. Doing so creates contact openings extending from a surface layer to each contact level. The contact openings are aligned with and provide access to landing areas at each of the 2^Ncontact levels. 2^x-1contact levels are etched during the etching step for each mask of sequence number x. Electrical conductors can then be formed through the contact openings to contact the landing areas at the contact levels. Some examples include the following steps: a fill material is applied over the openings to define a via pattern surface; vias are opened through the fill material to expose the landing areas in each contact level; and a conductive material is deposited within the vias. In some examples, the accessing step is carried out with N equal to at least 4. In some examples, the removing step is carried out using an additional mask exposing the interconnect region while in other examples, the removing step is carried out using a blanket etching step at the interconnect region. In some examples, sidewall material acts as one of the N etch masks.
• Another example of a method provides electrical connections to landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device. The IC device is of a type comprising an interconnect region, the interconnect region including an upper layer with a stack of at least first, second, third and fourth contact levels beneath the upper layer. At least first and second openings are formed in the upper layer, each opening exposing a surface portion of a first contact level, the first and second openings partially bounded by upper layer sidewalls. A sidewall material is deposited on the sidewalls of each of the first and second openings and on a first part of each of the surface portions while leaving a second part of the surface portions without sidewall material thereon. The first and second openings are extended through the second parts of the surface portions to expose a surface of the second contact level for each of the first and second openings. At least some of the sidewall material at each opening is removed to expose at least some of the first part of the surface portion at each opening, thereby forming interconnect contact regions at the second openings. The interconnect contact regions at the second opening are aligned with landing areas at the first and second contact levels. The first opening is further extended from (1) the exposed first part of the surface portion, through the first and second contact levels to expose a surface of a third contact level, and (2) an exposed surface of the second contact level through the second and third contact levels to expose a surface of the fourth contact level. Doing so forms interconnect contact regions at the first opening aligned with landing areas at the third and fourth contact levels. Electrical conductors are formed to the landing areas at the first, second, third and fourth contact levels. In some examples, the electrical conductors forming step comprises: applying a fill material over the openings to define a via pattern surface; opening vias through the fill material to expose the landing areas in each contact level; and depositing a conductive material within the vias.
• An example of a set of masks is used to create interconnect contact regions aligned with landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device, the stack of contact levels covered by an upper layer. Each mask of a set of N etch masks comprises mask and etch regions, the etch regions used to create interconnect contact regions alignable with landing areas at up to and including 2^N-1contact levels of an interconnect region for a three-dimensional stacked IC device. N is an integer equal to at least 3. x is the sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. In some examples, sidewall material acts as one of the N etch masks. In some examples, the etch masks comprise a dummy mask region on at least one of said etch masks. In some examples, the etch masks comprise dummy mask regions at corresponding locations on at least some of said etch masks. In some examples, the etch masks comprise at least one dummy mask region at corresponding locations on each of said etch masks. In some examples, N is greater than or equal to 4.
• Another example of a set of masks is used to create interconnect contact regions aligned with landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device. Each mask of a set of N masks comprises mask and etch regions, the etch regions used to create interconnect contact regions alignable with landing areas at up to and including 2^Ncontact levels of an interconnect region for a three-dimensional stacked IC device. N is an integer equal to at least 2. x is the sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N.
• Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description, and the claims which follow.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1-16 and the associated description are taken from U.S. patent application Ser. No. 12/579,192 filed 14 Oct. 2009 and entitled 3D Integrated Circuit Layer Interconnect having the same assignee as this application, the disclosure of which is incorporated by reference.
• FIG. 1 illustrates a cross-sectional view of a device including a three-dimensional structure having aninterconnect structure190 with a small footprint whereconductors180 extend to various levels160-1 to160-4 in the device.
• FIG. 2A illustrates a plan view of level160-1 showing the landing areas.
• FIG. 2B illustrates a plan view of level160-2 showing openings adjacent the landing areas.
• FIG. 2C illustrates a plan view of level160-3 showing openings adjacent the landing areas.
• FIG. 2D illustrates a plan view of level160-4 showing openings adjacent the landing area.
• FIGS. 3A and 3B illustrate respective orthogonal views of a portion of a three-dimensional stacked integrated circuit device including a 3D interconnect structure with a small footprint.
• FIG. 4 illustrates a top view layout of an embodiment of the device which includes interconnect structures in the periphery on two sides of a memory array.
• FIG. 5 illustrates a top view layout of an embodiment of the device which includes interconnect structures in the periphery on four sides of a memory array.
• FIG. 6 is a schematic diagram of a portion of the memory device including an interconnect structure as described herein.
• FIG. 7 is a simplified block diagram of an integrated circuit device including a 3D memory array having an interconnect structure as described herein.
• FIGS. 8A-8C to15 illustrate steps in a fabrication sequence for manufacturing an interconnect structure as described herein.
• FIG. 16 illustrates a plan view of an opening in a mask having a width varying in the longitudinal direction in a step-like manner, to accommodate varying widths of landing areas on the levels.
• The present invention is described primarily with reference toFIGS. 17-47.
• FIG. 17 is a simplified flowchart for a method for creating interconnect contact regions according to the present invention.
• FIGS. 18-27 illustrate a first example of a method for creating interconnect contact regions at a number of contact levels at an interconnect region of a three-dimensional stacked IC device.
• FIG. 18 is a simplified cross-sectional view of a stack of contact levels with an additional mask formed above an upper layer.
• FIG. 19 shows the result of etching through an open region in the additional mask ofFIG. 18 through the upper layer.
• FIG. 20 shows a first mask applied to the stack of contact levels ofFIG. 19.
• FIG. 21 shows the result of etching a single contact level using the first mask.
• FIG. 22 shows a second mask applied to the stack of contact levels ofFIG. 21.
• FIG. 23 shows the results of etching through two contact levels ofFIG. 22.
• FIG. 24 shows the structure ofFIG. 23 with the second mask removed thereby exposing interconnect contact regions at four different contact levels.
• FIG. 25 shows the structure ofFIG. 24 with an etch stop layer applied over the exposed surfaces of the structure ofFIG. 24.
• FIG. 26 shows the structure ofFIG. 25 covered by interlayer dielectric.
• FIG. 27 shows the structure ofFIG. 26 after electrical conductors have been formed through the interlayer dielectric and the etch stop layer to make contact with landing areas at the interconnect contact regions of each of the four contact levels.
• FIGS. 28-34 illustrate a second example of a method for creating interconnect contact regions at a number of contact levels at an interconnect region of a three-dimensional stacked IC device.
• FIGS. 35-44 illustrate a third example of a method for creating interconnect contact regions at a number of contact levels at an interconnect region of a three-dimensional stacked IC device.
• FIGS. 45 and 46 illustrate a process example for a stack of 16 contact levels withFIG. 46 illustrating the etching results.
• FIG. 47 illustrates the etching results when the masks have dummy contact regions so to create dummy stacks between the interconnect contact regions.
DETAILED DESCRIPTION
• FIG. 1 illustrates a cross-sectional view of a device including three-dimensional structure having aninterconnect structure190 with a small footprint whereconductors180 extend to various levels160-1 to160-4 in the device. In the illustrated example, four levels160-1 to160-4 are shown. More generally, thesmall interconnect structure190 described herein can be implemented in astructure having levels0 to N, where N is at least 2.
• Theconductors180 are arranged within theinterconnect structure190 to contact landing areas on the various levels160-1 to160-4. As described in more detail below, theconductors180 for each particular level extend through openings in the overlying levels to contact the landing areas161-1a,161-1b,161-2a,161-2b,161-3a,161-3b,161-4. Theconductors180 are used in this example for coupling the contact levels160-1 to160-4 to interconnectlines185 in a wiring layer overlying the levels160-1 to160-4.
• The landing areas are the portions of contact levels160-1 to160-4 used for contact withconductors180. The sizes of the landing areas are large enough to provide room for theconductors180 to adequately couple the electrically conductive landing areas within the landing areas of the various contact levels160-1 to160-4 to theoverlying interconnect lines185, as well as to address issues such as misalignment between theconductors180 and the overlying openings in one level for landing areas in different levels.
• The size of a landing area thus depends on a number of factors, including the size and number of conductors used, and will vary from embodiment to embodiment. In addition, the number of theconductors180 can be different for each of the landing areas.
• In the illustrated example, the levels160-1 to160-4 consist of respective planar conductive layers of material such as doped polysilicon, with layers of insulatingmaterial165 separating the levels160-1 to160-4. Alternatively, the levels160-1 to160-4 need not be planar stacked material layers, and instead the layers of material can vary in the vertical dimension.
• Theconductors180 contacting the different levels160-1 to160-4 are arranged in a direction extending along the cross-section illustrated inFIG. 1. This direction defined by the arrangement of theconductors180 contacting different levels160-1 to160-4 is referred to herein as the “longitudinal” direction. The “transverse” direction is perpendicular to the longitudinal direction, and is into and out of the cross-section illustrated inFIG. 1. Both the longitudinal and transverse directions are considered to be “lateral dimensions”, meaning a direction that is in a two-dimensional area of a plan view of the levels160-1 to160-4. The “length” of structures or features is its length in the longitudinal direction, and its “width” is its width in the transverse direction.
• Level160-1 is the lowest level in the plurality of levels160-1 to160-4. The level160-1 is on insulatinglayer164.
• The level160-1 includes first and second landing areas161-1a,161-1bfor contact withconductors180.
• InFIG. 1 the level160-1 includes two landing areas161-1a,161-1bon opposite ends of theinterconnect structure190. In some alternative embodiments one of the landing areas161-1a,161-1bis omitted.
• FIG. 2A is a plan view of a portion of level160-1, including the landing areas161-1a,161-1bwithin the footprint of theinterconnect structure190. The footprint of theinterconnect structure190 can be close to the width of the via size for the conductors, and have a length that can be much longer than the width. As shown inFIG. 2A, landing area161-1ahas awidth200 in the transverse direction and alength201 in the longitudinal direction. Landing area161-1bhas awidth202 in the transverse direction and alength203 in the longitudinal direction. In the embodiment ofFIG. 2A the landing areas161-1a,161-1beach have a rectangular cross-section. In embodiments, the landing areas161-1a,161-1bmay each have a cross-section that is circular, elliptical, square, rectangular, or somewhat irregularly shaped.
• Because level160-1 is the lowest level, theconductors180 need not pass through the level160-1 to underlying levels. Thus, in this example, level160-1 does not have openings within theinterconnect structure190.
• Referring back toFIG. 1, level160-2 overlies level160-1. Level160-2 includes anopening250 overlying the landing area161-1aon level160-1. Theopening250 has a distallongitudinal sidewall251aand a proximallongitudinal sidewall251bdefining thelength252 of theopening250. Thelength252 of theopening250 is at least as large as thelength201 of the underlying landing area161-1a, so that theconductors180 for the landing area161-1acan pass through the level160-2.
• The level160-2 also includesopening255 overlying the landing area161-1b. Theopening255 has distal and proximallongitudinal sidewalls256a,256bdefining thelength257 of theopening255. Thelength257 of theopening255 is at least as large as thelength203 of the underlying landing area161-1b, so that theconductors180 for the landing area161-1bcan pass through the level160-2.
• The level160-2 also includes first and second landing areas161-2a,161-2badjacent theopenings250,255 respectively. The first and second landing areas161-2a,161-2bare the portions of level160-2 used for contact with theconductors180.
• FIG. 2B is a plan view of a portion of level160-2, including the first and second landing areas161-2a,161-2band theopenings250,255 within theinterconnect structure190.
• As shown inFIG. 2B, opening250 haslongitudinal sidewalls251a,251bdefining thelength252, and hastransverse sidewalls253a,253bdefining thewidth254 of theopening250. Thewidth254 is at least as large as thewidth200 of the underlying landing area161-1a, so that theconductors180 can pass through theopening250.
• Opening255 haslongitudinal sidewalls256a,256bdefining thelength257, and hastransverse sidewalls258a,258bdefining thewidth259. Thewidth259 is at least as large as thewidth202 of the underlying landing area161-1b, so that theconductors180 can pass through theopening255.
• In the plan view ofFIG. 2B theopenings250,255 each have a rectangular cross-section. In embodiments, theopenings250,255 may each have a cross-section that is circular, elliptical, square, rectangular, or somewhat irregularly shaped, depending on the shape of the mask used to form them.
• As shown inFIG. 2B, landing area161-2ais adjacent theopening250 and has awidth204 in the transverse direction and alength205 in the longitudinal direction. Landing area161-2bis adjacent theopening255 and has awidth206 in the transverse direction and alength207 in the longitudinal direction.
• Referring back toFIG. 1, level160-3 overlies level160-2. Level160-3 includes anopening260 overlying landing area161-1aon level160-1 and landing area161-2aon level160-2. Theopening260 has distal and proximallongitudinal sidewalls261a,261bdefining thelength262 of theopening260. Thelength262 of theopening260 is at least as large as the sum of thelengths201 and205 of the underlying landing areas161-1aand161-2a, so that theconductors180 for the landing areas161-1aand161-2acan pass through the level160-3.
• As can be seen inFIG. 1, the distallongitudinal sidewall261aofopening260 is vertically aligned with the distallongitudinal sidewall251aof theunderlying opening250. In the manufacturing embodiment described in more detail below, the openings can be formed using the opening in a single etch mask and one additional mask formed over the opening in the single etch mask, as well as processes for etching the addition mask without a critical alignment step, resulting in the formation of openings having distal longitudinal sidewalls (261a,251a, . . . ) along the perimeter of the single etch mask that are vertically aligned.
• The level160-3 also includesopening265 overlying the landing area161-1bon level160-1 and landing area161-2bon level160-2. Theopening265 has outside and insidelongitudinal sidewalls266a,266bdefining thelength267 of theopening265. The outsidelongitudinal sidewall266aofopening265 is vertically aligned with the outsidelongitudinal sidewall256aof theunderlying opening255.
• Thelength267 of theopening265 is at least as large as sum of thelengths203 and207 of the underlying landing areas161-1band161-2b, so that theconductors180 for the landing areas161-1band161-2bcan pass through the level160-3.
• The level160-3 also includes first and second landing areas161-3a,161-3badjacent theopenings260,265 respectively. The first and second landing areas161-3a,161-3bare the portions of level160-3 used for contact with theconductors180.
• FIG. 2C is a plan view of a portion of level160-3, including the first and second landing areas161-3a,161-3band theopenings260,265 within theinterconnect structure190.
• As shown inFIG. 2C, opening260 has outside and insidelongitudinal sidewalls261a,261bdefining thelength262, and hastransverse sidewalls263a,263bdefining thewidth264a,264bof theopening260. Thewidth264ais at least as large as thewidth200 of the underlying landing area161-1a, andwidth264bis at least as large as thewidth204 of the underlying landing area161-2a, so that theconductors180 can pass through theopening260.
• In the illustrated embodiments,widths264aand264bare substantially the same. Alternatively, thewidths264aand264bcan be different, in order to accommodate landing areas having different widths.
• Opening265 haslongitudinal sidewalls266a,266bdefining thelength267, and hastransverse sidewalls268a,268bdefining thewidth269a,269b. Thewidth269ais at least as large as thewidth202 of the underlying landing area161-1b, and thewidth269bis at least as large as thewidth206 of the underling landing area161-2b, so that theconductors180 can pass through theopening265.
• As shown inFIG. 2C, landing area161-3ais adjacent theopening260 and has awidth214 in the transverse direction and alength215 in the longitudinal direction. Landing area161-3bis adjacent theopening265 has awidth216 in the transverse direction and alength217 in the longitudinal direction.
• Referring back toFIG. 1, level160-4 overlies level160-3. Level160-4 includes anopening270 overlying the landing area161-1aon level160-1, the landing area161-2aon level160-2, and the landing area161-3aon level160-3. Theopening270 haslongitudinal sidewalls271a,271bdefining thelength272 of theopening270. Thelength272 of theopening270 is at least as large as the sum of thelengths201,205, and215 of the underlying landing areas161-1a,161-2a,161-3aso that theconductors180 for the landing areas161-1a,161-2a,161-3acan pass through the level160-4. As shown inFIG. 1, thelongitudinal sidewall271aofopening270 is vertically aligned with thelongitudinal sidewall261aof theunderlying opening260.
• The level160-4 also includesopening275 overlying the landing area161-1bon level160-1, the landing area161-2bon level160-2, and the landing area161-3bon level160-3. Theopening275 haslongitudinal sidewalls276a,276bdefining thelength277 of theopening275. Thelongitudinal sidewall276aofopening275 is vertically aligned with thelongitudinal sidewall266aof theunderlying opening265.
• Thelength277 of theopening275 is at least as large as sum of thelengths203,207, and217 of the underlying landing areas161-1b,161-2band161-3b, so that theconductors180 for the landing areas161-1b,161-2b, and161-3bcan pass through the level160-4.
• The level160-4 also includes a landing area161-4 between theopenings270,275. The landing area161-4 is the portion of level160-4 used for contact with theconductors180. InFIG. 1, the level160-4 has one landing area161-4. Alternatively, the level160-4 may include more than one landing area.
• FIG. 2D is a plan view of a portion of level160-4, including landing area161-4 and theopenings270,275 within theinterconnect structure190.
• As shown inFIG. 2D, opening270 haslongitudinal sidewalls271a,271bdefining thelength272, and hastransverse sidewalls273a,273bdefining thewidth274a,274b,274cof theopening270. Thewidths274a,274b,274care at least as large as thewidths200,204, and214 of the underlying landing areas161-1a,161-2aand161-3a, so that theconductors180 can pass through theopening270.
• Opening275 haslongitudinal sidewalls276a,276bdefining thelength277, and hastransverse sidewalls278a,278bdefining thewidth279a,279b,279c. Thewidths279a,279b,279care at least as large as thewidths202,206, and216 of the underlying landing areas161-1b,161-2band161-3b, so that theconductors180 can pass through theopening275.
• As shown inFIG. 2D, landing area161-4 is between theopenings270,275 and has awidth224 in the transverse direction and alength225 in the longitudinal direction.
• Referring back toFIG. 1, the distallongitudinal sidewalls271a,261a, and251aofopenings270,260, and250 are vertically aligned, so that the difference in the length of theopenings270,260, and250 is due to the horizontal offset of thesidewalls271b,261b, and251b. As used herein, elements or features “vertically aligned” are substantially flush with an imaginary plane perpendicular to both the transverse and longitudinal directions. As used herein, the term “substantially flush” is intended to accommodate manufacturing tolerances in the formation of the openings using the opening in a single etch mask and multiple etch processes which may cause variations in the planarity of the sidewalls.
• As shown inFIG. 1, thelongitudinal sidewalls276a,266a, and256aofopenings275,265, and255 also are vertically aligned.
• Similarly, the transverse sidewalls of the openings in the levels are also vertically aligned. Referring toFIGS. 2A-2D, thetransverse sidewalls273a,263a, and253aofopenings270,260, and250 are vertically aligned. In addition thetransverse sidewalls273b,263b, and253bare vertically aligned. Foropenings275,265, and255 thelongitudinal sidewalls276a,266a, and256aare vertically aligned, and thetransverse sidewalls278b,268b, and258bare vertically aligned.
• In the illustrated embodiment, the openings in the various levels160-1 to160-4 have substantially the same width in the transverse direction. Alternatively, the width of the openings can vary along the longitudinal direction, for example, in a step-like manner, in order to accommodate landing areas having different widths.
• This technique for implementing theinterconnect structure190 as described herein significantly reduces the area or footprint needed for making contact to the plurality of levels160-1 to160-4, compared to prior art techniques. As a result, more space is available for implementing memory circuits in the various levels160-1 to160-4. This allows for higher memory density and a smaller cost per bit in the upper levels compared to prior art techniques.
• In the cross-section ofFIG. 1, the openings within theinterconnect structure190 result in the levels having a staircase-like pattern on both sides of the landing area161-4 on level160-4. That is, the two openings in each level are symmetrical about an axis perpendicular to both the longitudinal and transverse directions, and the two landing areas of each level are also symmetrical about that axis. As used herein, the term “symmetrical” is intended to accommodate manufacturing tolerances in the formation of the openings using the opening in a single etch mask and multiple etch processes which may cause variations in the dimensions of the openings.
• In alternative embodiments in which each level includes a single opening and a single landing area, the levels have a staircase-like pattern on only one side.
• In the illustrated example, four levels160-1 through160-4 are shown. More generally, the small interconnect structure described herein can be implemented inlevels0 to N, where N is at least 2. Generally, level (i), for (i) equal to 1 through N, overlies level (i−1), and has an opening (i) adjacent the landing area (i) on level (i). The opening (i) extends over the landing area (i−1) on level (i−1), and for (i) greater than 1, over the adjacent opening (i−1) in level (i−1). The opening (i) has a distal longitudinal sidewall aligned with the distal longitudinal sidewall of opening (i−1) in level (i), and a proximal longitudinal sidewall defining a length of the opening (i). The length of the opening (i) is at least as large as the length of the landing area (i−1) plus the length of the opening (i−1), if any. For (i) greater than 1, the opening (i) has transverse sidewalls aligned with the transverse sidewalls of opening (i−1) in level (i−1) and defines a width of the opening (i) at least as large as the width of the landing area (i−1).
• Other types of memory cells and configurations can be used in alternative embodiments. Examples of the other types of memory cells which may be used include dielectric charge trapping and floating gate memory cells. For example, in an alternative the levels of the device may be implemented as planar memory cell arrays separated by insulating material, with the access devices and access lines formed within the levels using thin film transistors or related technologies. In addition, the interconnect structure described herein can be implemented in other types of three-dimensional stacked integrated circuit devices, where having conductors extending to various levels in the device within a small footprint is useful.
• FIG. 3A is a cross-section of a portion of a three-dimensional stackedintegrated circuit device100 including amemory array region110 and aperiphery region120 with aninterconnect structure190 as described herein.
• InFIG. 3A, thememory array region110 is implemented as one-time programmable multi-level memory cells as described in U.S. patent application Ser. No. 12/430,290 by Lung, which is commonly owned by the assignee of the present application and incorporated by reference herein. It is described here as a representative integrated circuit structure in which the 3D interconnect structure described herein can be implemented.
• Thememory array region110 includes amemory access layer112 including horizontal field effecttransistor access devices131a,131bhavingsource regions132a,132banddrain regions134a,134bin a semiconductor substrate130. The substrate130 can comprise bulk silicon or a layer of silicon on an insulating layer or other structures known in the art for supporting integrated circuits.Trench isolation structures135a,135bisolate regions in the substrate130.Word lines140a,140bact as gates for theaccess devices131a,131b. Contact plugs142a,142bextend throughinter-layer dielectric144 to couple thedrain regions134a,134bto bitlines150a,150b.
• Contactpads152a,152bare coupled to underlying contacts146a,146b, providing connection to thesource regions132a,132bof the access transistors. Thecontact pads152a,152band bitlines150a,150bare within aninter-layer dielectric154.
• In the illustrated example, the levels consist of respective planar conductive layers of material such as doped polysilicon. Alternatively, the levels need not be planar stacked material layers, and instead the layers of material can vary in the vertical dimension.
• Insulating layers165-1 to165-3 separate the levels160-1 to160-4 from one another. An insulatinglayer166 overlies the levels160-1 to160-4 and insulating layers165-1 to165-3.
• A plurality ofelectrode pillars171a,171bare arranged on top of the memorycell access layer112 and extend through the levels. In this drawing, afirst electrode pillar171aincludes a centralconductive core170amade, for example, of tungsten or other suitable electrode material, surrounded by apolysilicon sheath172a. Alayer174aof anti-fuse material, or other programmable memory material, is formed between thepolysilicon sheath172aand the plurality of levels160-1 through160-4. The levels160-1 through160-4 comprise a relatively highly doped, n-type polysilicon in this example, while thepolysilicon sheath172acomprises a relatively lightly doped, p-type polysilicon. Preferably, the thickness of thepolysilicon sheath172ais greater than the depth of the depletion region formed by the p-n junction. The depth of the depletion region is determined in part by the relative doping concentrations of the n-type and p-type polysilicon used to form it. The levels160-1 through160-4 and thesheath172acan be implemented using amorphous silicon as well. Also, other semiconductor materials could be utilized.
• Thefirst electrode pillar171ais coupled to thepad152a. Asecond electrode pillar171bincludingconductive core170b,polysilicon sheath172b, andanti-fuse material layer174bis coupled to the pad152b.
• Interface regions between the plurality of levels160-1 through160-4 and thepillars171a,171binclude memory elements comprising a programmable element in series with a rectifier, as explained in more detail below.
• In the native state, thelayer174aof anti-fuse material ofpillar171a, which can be a silicon dioxide, silicon oxynitride, or other silicon oxide, has a high resistance. Other anti-fuse materials may be used, such as silicon nitride. After programming by applying appropriate voltages to the word lines140,bit lines150, and the plurality of levels160-1 to160-4, thelayer174aof anti-fuse material breaks down and an active area within the anti-fuse material adjacent a corresponding level assumes a low resistance state.
• As shown inFIG. 3A, the plurality of conductive layers of levels160-1 to160-4 extend into theperiphery region120 where supporting circuitry andconductors180 are made to the plurality levels160-1 to160-4. A wide variety of devices are implemented in theperiphery120 to support decoding logic and other circuits on theintegrated circuit100.
• Theconductors180 are arranged within theinterconnect structure190 to contact landing areas on the various levels160-1 to160-4. As discussed in more detail below, theconductors180 for each particular level160-1 to160-4 extend through openings in the overlying levels to a wiring layer including conductive interconnect lines185. Theconductive interconnect lines185 provide for interconnection between the levels160-1 to160-4 and decoding circuitry in theperiphery120.
• As represented by the dashed line inFIG. 3A, theconductors180 contacting the different levels160-1 to160-4 are arranged in the longitudinal direction extending into and out of the cross-section illustrated inFIG. 3A.
• FIG. 3B is a cross-sectional view in the longitudinal direction taken along lineFIG. 3B-FIG.3B through theinterconnect structure190 ofFIG. 3A, showing a view of theinterconnect structure190 like that shown inFIG. 1. As can be seen inFIG. 3B, theconductors180 for each particular level extend through openings in the overlying levels to contact the landing areas.
• In the illustrated example, four levels160-1 through160-4 are shown. More generally, the small interconnect structure described herein can be implemented inlevels0 to N, where N is at least 2.
• Other types of memory cells and configurations can be used in alternative embodiments. For example, in an alternative the levels of the device may be implemented as planar memory cell arrays separated by insulating material, with the access devices and access lines formed within the levels using thin film transistors or related technologies. In addition, the interconnect structure described herein can be implemented in other types of three-dimensional stacked integrated circuit devices, where having conductors extending to various levels in the device within a small footprint is useful.
• InFIGS. 3A-3B, asingle interconnect structure190 is shown. A plurality of interconnect structures can be arranged at various locations in the device, such as surrounding thememory array region110, so as to provide more even power distribution.FIG. 4 illustrates a top view layout of an embodiment of thedevice100 which includes a two series of interconnect structures, including series in the regions190-1 and190-2 in theperiphery120 on respective sides of an array.FIG. 5 illustrates a top view layout of an embodiment which includes four series of interconnect structures, including series190-1,190-2,190-3, and190-4, in theperiphery120 on all four sides of an array. For an example array size including 1000 columns and 1000 rows of cells, and having 10 levels, with a feature size F defining the word line width and the bit line width, and in which the size of the landing areas on the levels is about F, then one can see that the length of the area occupied by one interconnect structure is about 2F times the number of levels or 20F, while the pitch per word line is about 2F or more making the width of the array about 2000F. Thus, following this example, about 100 interconnect structures could be formed in a series such as series190-3 along the array width, and a similar number could be formed in a series such as series190-1 along the array length.
• In yet other alternative embodiments, one or more interconnect structures can be implemented within thememory array region110 in addition to, or as a replacement of, having an interconnect structure in theperiphery120. In addition, the interconnect structures can extend diagonally or in any other direction, rather than being parallel to an edge of thememory array region110.
• FIG. 6 is a schematic illustration of a portion of the memory device including an interconnect structure as described herein.First electrode pillar171ais coupled to theaccess transistor131awhich is selected using thebit line150aandword line140a. A plurality of memory elements544-1 through544-4 are connected to thepillar171a. Each of the memory elements includes aprogrammable element548 in series with arectifier549. This series arrangement represents the structure shown inFIGS. 3A-3B, even though the layer of anti-fuse material is placed at the p-n junction. Theprogrammable element548 is represented by a symbol often used to indicate anti-fuses. However, it will be understood that other types of programmable resistance materials and structures can be utilized.
• Also, therectifier549 implemented by the p-n junction between the conductive plane and the polysilicon in the electrode pillar can be replaced by other rectifiers. For example, a rectifier based on a solid electrolyte like germanium silicide, or other suitable material, could be used to provide a rectifier. See U.S. Pat. No. 7,382,647 for other representative solid electrolyte materials.
• Each of the memory elements544-1 through544-4 is coupled to corresponding conductive levels160-1 through160-4. The levels160-1 to160-4 are coupled viaconductors180 andinterconnect lines185 to aplane decoder546. Theplane decoder546 is responsive to addresses to apply a voltage, such asground547, to a selected level so that the rectifier in the memory element is forward biased and conducting, and to apply a voltage to or float unselected levels so that the rectifier in the memory element is reversed biased or non-conducting.
• FIG. 7 is a simplified block diagram of anintegrated circuit device300 including a3D memory array360 having an interconnect structure as described herein. Arow decoder361 is coupled to a plurality ofword lines140 arranged along rows in thememory array360. Acolumn decoder363 is coupled to a plurality ofbit lines150 arranged along columns in thememory array360 for reading and programming data from the memory cells in thearray360. Theplane decoder546 is coupled to a plurality of levels160-1 to160-4 in thememory array360 viaconductors180 andinterconnect lines185. Addresses are supplied onbus365 tocolumn decoder363,row decoder361, andplane decoder546. Sense amplifiers and data-in structures inblock366 are coupled to thecolumn decoder363 in this example viadata bus367. Data is supplied via the data-inline371 from input/output ports on theintegrated circuit300, to the data-in structures inblock366. In the illustrated embodiment,other circuitry374 is included on theintegrated circuit300, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality. Data is supplied via data-outline372 from the sense amplifiers inblock366 to input/output ports on theintegrated circuit300, or to other data destinations internal or external to theintegrated circuit300.
• A controller implemented in this example using biasarrangement state machine369 controls the application of bias arrangement supply voltages generated or provided through the voltage supply or supplies inblock368, such as read and program voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.
• FIGS. 8A-8C to15 illustrate steps in an embodiment of a fabrication sequence for manufacturing an interconnect structure having a very small footprint as described herein.
• FIGS. 8A and 8C illustrate cross-sectional views, andFIG. 8B illustrates a top view, of a first step of the fabrication sequence. For the purposes of this application, the first step involves forming a plurality of levels160-1 to160-4 overlying the provided memorycell access layer112. In the illustrated embodiment the structure illustrated inFIGS. 8A-8C is formed using processes described in commonly owned U.S. patent application Ser. No. 12/430,290 by Lung, which was incorporated by reference above.
• In alternative embodiments, the levels can be formed by standard processes as known in the art and may include access devices such as transistors and diodes, word lines, bit lines and source lines, conductive plugs, and doped regions within a substrate, depending upon the device in which the interconnect structure described herein is to be implemented.
• As noted above, other types of memory cells and configurations for thememory array region110 can also be used in alternative embodiments.
• Next, afirst mask800 having anopening810 is formed on the structure illustrated inFIGS. 8A-8C, resulting in the structure illustrated in the top and cross-sectional views ofFIGS. 9A and 9B respectively. Thefirst mask800 can be formed by depositing the layer for thefirst mask800, and patterning the layer using lithographic techniques to form theopening810. Thefirst mask800 may comprise, for example, a hard mask material such as silicon nitride, silicon oxide, or silicon oxynitride.
• Theopening810 in thefirst mask800 surrounds the perimeter of the combination of landing areas on the levels160-1 to160-4. Thus, thewidth192 of theopening810 is at least as large as the widths of the landing areas on the levels160-1 to160-4, so that the subsequently formedconductors180 can pass through the openings in the levels. Thelength194 of theopening810 is at least as large as the sum of the lengths of the landing areas on the levels160-1 to160-4, so that the subsequently formedconductors180 can pass through the openings in the levels.
• Next, asecond etch mask900 is formed on the structure illustrated inFIGS. 9A-9B, including within theopening810, resulting in the structure illustrated in the top and cross-sectional views ofFIGS. 10A and 10B respectively. As shown in the figures, thesecond etch mask900 has alength910 less than thelength194 of theopening810, and has a width at least as large as thewidth192 of theopening810.
• In the illustrated embodiment, thesecond etch mask900 comprises a material that can be selectively etched relative to the material of thefirst mask800, so that the length of thesecond mask900 within theopening810 can be selectively reduced in subsequent process steps described below. In other words, the material of thesecond mask900 has an etching rate greater than an etching rate of the material of thefirst mask800 for the process used to reduce the length of thesecond mask900. For example, in embodiments in which thefirst mask800 comprises a hard mask material, the second mask can comprise photoresist.
• Next, an etching process is performed on the structure illustrated inFIGS. 10A-10B using the first andsecond masks800,900 as etch masks, resulting in the structure illustrated in the top and cross-sectional views ofFIGS. 11A and 11B respectively. The etching process can be carried out using a single etch chemistry using, for example, timing mode etching. Alternatively, the etching process can be carried out using different etch chemistries to individually etch through insulatinglayer166, level160-4, insulating material165-3, and level160-3.
• The etching forms anopening1000 through the level160-4 to expose a portion of level160-3. Theopening1000 overlies the landing area161-1aon level160-1. Theopening1000 has alength1002 at least as large as the length of the landing area161-1a, and has awidth1004 at least as large as the width of the landing area161-1a.
• The etching also forms opening1010 through the level160-4 to expose a portion of level160-3. Theopening1010 overlies the landing area161-1bon level160-1. Theopening1010 has alength1012 at least as large as the length of the landing area161-1b, and has awidth1004 at least as large as the width of the landing area161-1b
• Next, thelength910 of themask900 is reduced to form reducedlength mask1100 withlength1110, resulting in the structure illustrated in the top and cross-sectional views ofFIGS. 12A and 12B respectively. In the illustrated embodiment themask900 comprises photoresist, and can be trimmed, for example, using reactive ion etching with CL2 or HBr based chemistries.
• Next, an etching process is performed on the structure illustrated inFIGS. 12A-12B using thefirst mask800 and the reducedlength mask1100 as etch masks, resulting in the structure illustrated in the top and cross-sectional views ofFIGS. 13A and 13B.
• The etching process extends theopenings1000,1010 through level160-3 to expose underlying portions of the level160-2.
• The etching also formsopenings1200,1210 through the portions of the level160-4 no longer covered by themask1100 due to the reduction in the length ofmask1100, thereby exposing portions of level160-3. Theopening1200 is formedadjacent opening1000, and overlies the landing area161-2aon level160-2. Theopening1200 has alength1202 at least as large as the length of the landing area161-2a, and has awidth1204 at least as large as the width of the landing area161-2a.
• Theopening1210 is formedadjacent opening1010, and overlies the landing area161-2bon level160-2. Theopening1210 has alength1212 at least as large as the length of the landing area161-2b, and has awidth1204 at least as large as the width of the landing area161-2b.
• Next, thelength1110 of themask1100 is reduced to form reducedlength mask1300 withlength1305. An etching process performed using thefirst mask800 and themask1300 as etch masks, resulting in the structure illustrated in the top and cross-sectional views ofFIGS. 14A and 14B.
• The etching process extends theopenings1000,1010 through level160-2 to expose the landing areas161-1a,161-1bon level160-1. The etching process also extends theopenings1200,1210 through level160-3 to expose the landing areas161-2a,161-2bon level160-2.
• The etching also formsopenings1310,1320 through the portions of the level160-4 no longer covered due to the reduction in the length ofmask1300, thereby exposing the landing areas161-3a,161-3bon level160-3.
• Theopening1310 is formedadjacent opening1200. Theopening1310 has alength1312 at least as large as the length of the landing area161-3a, and has awidth1314 at least as large as the width of the landing area161-3a.
• Theopening1320 is formedadjacent opening1210. Theopening1320 has alength1322 at least as large as the length of the landing area161-3b, and has awidth1324 at least as large as the width of the landing area161-3b.
• Next, insulatingfill material1400 is deposited on the structure illustrated inFIGS. 14A-14B and a planarization process such as Chemical Mechanical Polishing (CMP) is performed to remove themasks800,1300, resulting in the structure illustrated in the cross-sectional view ofFIG. 15.
• Next, a lithographic pattern is formed to define vias to the landing areas for theconductors180. Reactive ion etching can be applied to form deep, high aspect ratio vias through the insulatingfill material1400 to provide vias for theconductors180. After opening the vias, the vias are filled with tungsten or other conductive material to form theconductors180. Metallization processes are then applied to forminterconnect lines185 to provide interconnection between theconductors180 and plane decoding circuitry on the device. Finally, back end of line BEOL processes are applied to complete the integrated circuit, resulting in the structure illustrated inFIGS. 3A-3B.
• The openings in the various levels used for passing conductors to the landing areas on underlying levels are formed by patterning the levels using theopening810 in thesingle etch mask800, as well as processes for etching the additional mask without a critical alignment step. As a result the openings in the various levels having vertically aligned sidewalls are formed in a self-aligned manner.
• In the illustrated examples described above, theopening810 in themask800 has a rectangular cross-section in plan view. As a result, the openings in the various levels have substantially the same width along the transverse direction. Alternatively, the opening in themask800 can have a cross-section that is circular, elliptical, square, rectangular, or somewhat irregularly shaped, depending on the shape of the landings areas of the various levels.
• For example, the width of the opening in themask800 can vary along the longitudinal direction, in order to accommodate landing areas having different widths.FIG. 16 illustrates a plan view of anopening1510 in themask800 having a width varying in the longitudinal direction in a step-like manner, which results in the widths of the openings in the levels varying accordingly.
• The present invention will now be described primarily with reference toFIGS. 17-47.
• The following description will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals.
• FIG. 17 is a simplified flowchart for amethod10 for creatinginterconnect contact regions14 according to the present invention. The interconnect contactregion creating method10 ofFIG. 17 includes obtaining a set of N masks at obtainingstep12. Further steps in themethod10 shown inFIG. 17 will be discussed below in conjunction withFIGS. 18-27, which illustrate a first example of a method for carrying out the present invention.
• The set of N masks are used to create up to 2N levels ofinterconnect contact regions14, seeFIG. 27, at thestack16 of contact levels18.1,18.2,18.3,18.4, thestack16 being at theinterconnect region17 of a three-dimensional stacked IC device. Theinterconnect region17 will typically be a peripheral interconnect region, such as shown inFIGS. 4 and 5, but may be located elsewhere. In the three examples ofFIGS. 18-44, four contact levels are shown on asubstrate19 for simplicity of illustration; three-dimensional stacked IC devices will commonly have many more contact levels. As will be discussed below, each mask comprises mask and etch regions, N is an integer equal to at least 2, and x is a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. When x=1, the etching step for the associated mask will etch one contact level18, when x=2, the etching step for the associated mask will etch two contact levels, etc.
• Next, aportion removing step20, seeFIG. 17, is carried out to remove aportion22, seeFIG. 19, of anupper layer24 overlying thestack16 of contact levels18. In this example,upper layer24 includes first and second silicon oxide layers26,28 with acharge trapping layer27, typically of silicon nitride, therebetween. In this example, this removal is accomplished using anadditional mask30 having anopen region32, seeFIG. 18, to permit the etching of aportion22 ofupper layer24 as shown inFIG. 19. In this example, contact levels18 each include an upper conductive layer34, typically a polysilicon layer patterned to form conductors such as word lines, and a lower insulating layer36, typically a silicon oxide or silicon nitride compound. For ease of reference layer34 will typically be referred to as polysilicon layer34. However, layer34 may be made of other appropriate materials, such as metals, metal silicides and multilayer combinations of more than one of polysilicon, metal silicides and metals. The etching throughdielectric layer28 ofupper layer24 is typically controlled by the use of material-selective etching processes. For example, whendielectric layer28 is silicon oxide and layer34 is polysilicon, using reactive ion etching to etch throughdielectric layer28, the etching is effectively stopped upon reaching layer34. Similar techniques can be used to control the depth of etching in other situations. Other techniques for controlling the depth of etching may also be used.Additional mask30 may not be considered a part of the set of N masks because it is used to simply open a space for etching of thestack16 of contact levels18. In the example discussed below with regard toFIGS. 28-34, anyadditional layer24 is removed from the interconnect contact region using a blanket etch without the need for an additional mask.
• FIG. 20 illustrates the formation of a first mask38.1 on thestack16 of contact levels18 ofFIG. 19. In this example, first mask38.1 comprises photoresist mask elements40.1,40.2 and40.3 with mask element40.2 covering a central portion42.1 of the first polysilicon layer34.1 and mask element40.3 covering an edge portion42.2 of the first polysilicon layer34.1.FIG. 21 illustrates the result of an etching step in which the portions of contact level18.1 not covered byphotoresist mask elements40 are etched down to contact level18.2. That is, one contact level18 is etched in this first etching step.
• FIG. 22 illustrates the formation of a second photoresist mask38.2 on thestack16 of contact levels18 ofFIG. 21. Mask38.2 covers otherwise exposed portions of polysilicon layers34.1 and34.2 that are subsequently to be used as interconnect contact regions14.1 and14.2 as suggested by the dashed lead lines inFIG. 22.FIG. 23 shows the result of a second etching step in which two contact levels are etched. In particular, exposedsurface portion44 of polysilicon layer34.2 is etched down two layers to expose aportion46 of polysilicon layer34.4. In addition, the exposed portion42.3 of polysilicon layer34.1 is also etched down two contact levels to expose aportion47 polysilicon layer34.3.FIG. 24 shows the result of removing second mask38.2 leaving portions of the polysilicon layers34.1,34.2,34.3 and34.4 to act as interconnect contact regions14.1,14.2,14.3 and14.4. Thethin column portion48 of contact level18.1, sometimes called a dummy stack or a partial height dummy stack, may be formed on purpose or as the result of manufacturing tolerances.
• In the example ofFIGS. 18-24, two masks38.1,38.2 were used to provide access to landing areas at four interconnect contact regions14.1-14.4 at four different contact levels18.1-18.4. According to the present invention, theinterconnect region17 is etched N times using N masks to create aninterconnect contact region14 at each of 2N contact levels18. Theinterconnect contact regions14 are aligned with and provide access to landing areas56, discussed below with reference toFIG. 27, at each of the 2N contact levels. Each etching step comprises etching through 2x−1 contact levels for each mask of sequence number x. See interconnectregion etch step49 ofFIG. 17.
• FIG. 25 illustrates the result of the optional step of applyingetch stop layer50, such as a silicon nitride layer when the interlayer insulator is silicon oxide, over the exposed surfaces of the etchedstack16 of contact levels18. Thereafter, aninterlayer dielectric52 is deposited on the structure ofFIG. 25 as illustrated inFIG. 26 and by the etch regions fillstep53 ofFIG. 17. This is followed by formation of electrical conductors54 through theinterlayer dielectric52 andetch stop layer50 to make electrical contact with the electrically conductive landing areas56 at theinterconnect contact regions14. Conductors54 may be formed using a tungsten plug process, that includes forming vias through the dielectric fill which provide openings to the landing areas on the selected layers, then using a CVD or PVD process, an adhesive liner may be formed in the via followed by deposition of tungsten to fill the vias, forming vertical conductors54. This is illustrated inFIG. 27 and is shown as the electricalconductors forming step60 ofFIG. 17.
• A second example will be discussed with reference toFIGS. 28-34 with like reference numerals referring to like elements of the first example ofFIGS. 17-27. Thestack16 of contact levels18 atinterconnect region17 ofFIG. 28 has the same basic structure as inFIG. 18. In this example,dielectric layer26 andcharge trapping layer27 ofupper layer24 are removed with a blanket etch process thereby eliminating the need foradditional mask30. First mask38.1 is formed ondielectric layer28, mask38.1 with open regions41.1,41.2 between mask elements40.1 and40.2 and between mask elements40.2 and40.3. This is followed by the first etching step shown inFIG. 31 wherebyopenings62,63 are formed throughdielectric layer28 and polysilicon layer34.1 at the openings41.1 and41.2 between the mask elements40.1/40.2 and between the mask elements40.2/40.3. Although such etching step could be continued down to polysilicon layer34.2, it is not necessary for reasons that will be evident when discussingFIGS. 33 and 34. A second mask38.2 is then formed on the etchedstack16 of contact levels18. Second mask38.2 includes mask elements40.4 and40.5 with mask element40.5 coveringopening63 while leavingopening62 and aportion64dielectric layer28 betweenopenings62,63 uncovered.
• FIG. 33 illustrates result of the second etching step in which two contact levels are etched. Specifically, opening62 is etched down to oxide layer36.3 whileportion64 ofdielectric layer28 is etched two contact levels down to oxide layer36.2. Thereafter, second mask38.2 is removed andinterlayer dielectric52 is deposited on the etched structure as shown inFIG. 34. This is then followed by the formation of electrical conductors54.1-54.4 through theinterlayer dielectric52 and the oxide layers28,36.1,36.2,36.3 covering polysilicon layers34.1-34.4 so to make contact with the landing areas56.1-56.4 at the interconnect contact regions14.1-14.4.
• As with the example ofFIGS. 18-24, two masks38.1,38.2 were used in the example ofFIGS. 28-34 to provide access to landing areas56.1-56.4 at four interconnect contact regions14.1-14.4 at four different contact levels18.1-18.4. According to the present invention theinterconnect region17 is etched N times using N masks to create aninterconnect contact region14 at each contact level18. Theinterconnect contact regions14 are aligned with and provide access to landing areas56 at each of the 2N contact levels. Again, the etching step comprising etching through 2x−1 contact levels for each mask of sequence number x.
• FIGS. 35-44 illustrate a third example of a method for carrying out the present invention again with like reference numerals referring to like elements. First mask38.1 is formed overupper layer24 and stack16 of contact levels18 atinterconnect region17. Photoresist mask elements40.1,40.2 and40.3 form open regions66.1 and66.2 between mask elements40.1 and40.2 and between mask elements40.2 and40.3 as shown inFIG. 35. The portions ofupper layer24 underlying open regions66.1 and66.2 are etched down to polysilicon layer34.1 of first contact level18 creating first and second openings68.1,68.2 inupper layer24. Openings68.1 and68.2 expose surface portions70.1,70.2 of first polysilicon layer34.1.
• FIG. 38 shows result of depositing sidewall material72.1 and72.2 on the sidewalls of the first and second openings68.1,68.2. This can be accomplished in different ways, such as by depositing blanket layer of insulating material such as silicon nitride by CVD or sputtering over the wafer, followed by anisotropic etching until the material is removed from horizontal surfaces of the wafer, except regions adjacent vertical sidewalls, at which sidewall spacers are left. Sidewall material72.1 and72.2 covers a first part74.1,74.2 of each of the surface portions70.1,70.2 while leaving a second part76.1,76.2 of each of the surface portions70.1,70.2 uncovered.
• The structure ofFIG. 38 is then etched, such as by an anisotropic reactive ion etch that does not attack the side wall material, but only reduces the size of sidewall material72.1,72.2 and extends the first and second openings68.1,68.2 through one contact level to expose polysilicon layer34.2. SeeFIG. 39. Next, sidewall material72.1,72.2 is removed, seeFIG. 40, to expose first parts74.1,74.2 of surface portions70.1,70.2.FIG. 41 shows second mask38.2 on the structure ofFIG. 40 filling second opening68.2. First opening68.1 is then etched through two contact levels18 to exposeportions78 of third polysilicon layer34.3 beneath first part74.1 andportion80 of forth polysilicon layer34.4 beneath the second part76.1.
• Second mask38.2 is then removed and the structure ofFIG. 42 is covered byinterlayer dielectric52 as shown inFIG. 43.FIG. 44 illustrates result of the formation of conductors54.1-54.4 contacting the landing areas56.1-56.4 at the interconnect contact regions14.1-14.4.
• The method illustrated inFIGS. 35-44 is especially suited when a relatively thickupper layer24 is used above astack16 of contact levels18. ASiN layer50, used with theFIGS. 18-27 example, may be used with the second and third examples.
• FIG. 45 illustrates a process example for a stack of 16 contact levels18. According to the present invention,interconnect contact regions14 for each of the 16 contact levels18 can be accessed using only 4 masks38. In this example, first mask38.1 has 8photoresist mask elements40, labeled1,3,5, etc., followed byopen etch regions41, labeled2,4,6, etc. In this example, eachmask element40 and each edge ofregion41 has a 1 unit longitudinal dimension. One layer is etched for the first mask38.1. Second mask38.2 has 4 photoresist mask elements, labeled1/2,5/6, etc., followed by open etch regions labeled3/4,7/8, etc., each having a 2 unit longitudinal dimension. Two layers are etched with second mask38.2. Third mask38.3 has 2 photoresist mask elements, labeled1-4,9-12, followed by open etch regions, labeled5-8,13,16, each having a 4 unit longitudinal dimension. Four layers are etched with third mask38.3. Fourth mask38.4 has 1 photoresist mask element, labeled1-8, followed by an open etch region, labeled9-16, each having an 8 unit longitudinal dimension. Eight layers are etched with fourth mask38.4.
• As discussed above, when using first mask38.1, with x=1, a single layer18 is etched (2x−1=20=1); when using second mask38.2, 2 layers18 are etched (2x−1=21=2); when using third mask38.3, 4 layers18 are etched (2x−1=22=4); when using fourth mask38.4, 8 layers38 are etched (2x−1=23=8). In this way any contact level18 between 1 and 16 can be accessed by using some combination ofetching 1 level,etching 2 levels,etching 4 levels andetching 8 levels. Another way to think about this is that the 4 masks represent a four digit binary number, that is 0000, 0001, 0010, . . . 1111 corresponding to the decimal numbers 1-16. For example, to access theinterconnect contact regions14 at contact level18 requires etching through 12 contact levels which can be accomplished usingopen regions41 for third mask38.3 (etching through 4 contact levels) and fourth mask38.4 (etching through 8 contact levels). The result of use of masks38.1-38.4 ofFIG. 45 withstack16 of contact levels18 is shown inFIG. 46. Conventional methods would typically require 16 different masks resulting in a much higher processing expense and increased chance of failure due to tolerance buildup.
• The example ofFIGS. 45 and 46 results in a continuous, open step region forinterconnect contact regions14 aligned with landing areas56.FIG. 47 shows an example in which 4 masks38 are configured to create astack16 of 16 contact levels18 having full height dummy stacks82 between eachinterconnect contact region14 and a full height boundary stack84 adjacent to contactregion14. This is achieved by providingdummy mask regions86 for each mask38 wherever a dummy stack82 is to be created. In this example, there is a dummy stack82 between eachinterconnect contact region14. However, in some examples, one or more of the dummy stacks82 could be eliminated. Also, the longitudinal dimension of dummy stacks82 need not be the same.
• It is not necessary that the masks38 be used in the order of the number of contact levels18 etched with each mask. That is, mask38.2 could be used before mask38.1. However, it is preferred that the masks be used in an ascending order of the number of contact levels etched, that is with the mask used with etching of one contact level first, the mask used with etching of two contact levels second, etc. for larger process window.
• In the example ofFIG. 47,dummy mask regions86 are provided at corresponding positions at each mask38 so that the resulting dummy stack82 is a full height dummy stack. Partial height dummy stacks, such asthin column portion48 ofFIG. 24, can be made by providingdummy mask regions86 at corresponding positions for one or more but not all of masks38.
• While the invention has been discussed with reference to N=2 with regard toFIGS. 17-44 and with N=4 with regard toFIGS. 45-47, the number of masks could be other than 3 or N could be greater than 4. While a set of N masks can be used to create 2N levels of interconnect contact regions, it can also be used to create up to and including 2N levels of interconnect contact regions. For example, with N equal to 4, the 4 masks can be used to create fewer than 16 levels of interconnect contact regions, such as 13, 14 or 15 levels of interconnect contact regions.
• While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
• Disclosures of any and all patents, patent applications and printed publications referred to above are incorporated by reference.

Claims (10)

What is claimed is:

1. A set of masks, used to create interconnect contact regions aligned with landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device, the stack of the contact levels covered by an upper layer, comprising:

a set of N etch masks, each mask comprising mask and etch regions, the etch regions used to create the interconnect contact regions alignable with the landing areas at up to and including 2^N-1contact levels of an interconnect region for a three-dimensional stacked IC device, N being an integer equal to at least 3, x being the sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N.

2. The set of masks according toclaim 1, wherein sidewall material acts as one of the N etch masks.

3. The set of masks according toclaim 1, wherein the etch masks comprise a dummy mask region on at least one of said etch masks.

4. The set of masks according toclaim 1, wherein the etch masks comprise dummy mask regions at corresponding locations on at least some of said etch masks.

5. The set of masks according toclaim 1, wherein the etch masks comprise at least one dummy mask region at corresponding locations on each of said etch masks.

6. The set of masks according toclaim 1, wherein longitudinal dimensions for the etch regions for a chosen etch mask are about equal.

7. The set of masks according toclaim 1, wherein:

the mask and etch regions have longitudinal dimensions; and

the longitudinal dimensions for the mask and etch regions for a chosen mask are about equal to one another.

8. The set of masks according toclaim 1, wherein:

the mask and etch regions have longitudinal dimensions; and

the longitudinal dimensions for the mask and etch regions for all of the masks are about equal to one another.

9. The set of masks according toclaim 1, wherein N is greater than or equal to 4.

10. A set of masks, used to create interconnect contact regions aligned with landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device, comprising:

a set of N masks, each mask comprising mask and etch regions, the etch regions used to create the interconnect contact regions alignable with the landing areas at up to and including 2^Ncontact levels of an interconnect region for a three-dimensional stacked IC device, N being an integer equal to at least 2, x being the sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N.

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