US20140043092A1 - Input switches in sampling circuits - Google Patents

Abstract

A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Description

FIELD OF THE INVENTION
• The present invention is generally directed to circuits including switches. In particular, the present invention is directed to an apparatus for improving the linearity of an output and reliability of the switches.
BACKGROUND INFORMATION
• Circuits commonly include MOS-based switches. For example, sampling circuits including input switches are commonly used at the front end of a circuit to receive and sample input signals. Specifically, analog-to-digital converters (ADCs) may include a sample-and-hold (or track-and-hold) circuit as an input switch for receiving analog input signals to be converted into digital codes.FIG. 1 illustrates a track-and-hold circuit as commonly known in the art. Referring toFIG. 1, the track-and-hold circuit10 may include aninput MOS transistor12, a first set ofswitches14,16,18, a second set ofswitches20,22, a voltage level shifter such as a capacitive level shifter (or a capacitor)24, aload capacitor26, asecond MOS transistor28, and animpedance29. WhileMOS transistor12 is illustrated as a NMOS for the convenience of discussion,MOS12 may be a NMOS or PMOS transistor.MOS transistor12 may include a gate (G), a source (S), and a drain (D). Additionally,MOS transistor12 may include a back-gate (B) coupled to the body of theMOS12. TheMOS transistor12 may operate alternatively in a first “track” phase (or, “ON” phase), controlled by a first clock (01), during whichMOS12 is turned on and a second “hold” phase (or, “OFF” phase), controlled by a second clock (φ2), during whichMOS12 is turned off.Voltage level shifter24 is coupled between the gate (G) and source (S) ofMOS12 during the “track” phase viaswitches14,16. Gate (G) ofMOS12 is coupled to the ground (or a very low voltage level) during the “hold” phase viaswitch20. Source (S) ofMOS12 may receive an input signal Vin which, in turn, may be generated from a voltage source Vs including asource impedance29. Drain (D) ofMOS12 is coupled to aload capacitor26 which is coupled toMOS switch28 whose operating state is controlled by clock φ1a. Back-gate (B) ofMOS12 is connected to the source (S) via a switch controlled by the first clock (φ1) during the “track” phase, and is connected to a reference voltage such as ground (GND) via aswitch22 controlled by the second clock (φ2) during the “hold” phase. Additionally, the track-and-hold circuit10 may include parasitic capacitance Cp associated withMOS12 at its source and drain. The parasitic capacitance Cp may also affect the quality of output signal V_sample.
• Operating in the “track” phase whenswitches14,16,18 are engaged according to clock φ1 (φ1 is high) andswitches20,22 are disengaged according to clock φ2 (φ2 is low), MOS12 (which is turned on) is connected to the input signal Vin throughvoltage level shifter24 to bootstrap a voltage at the gate. Thus, if the bootstrapping voltage is V_BSTRAP, the voltage at gate (G) during the “track” phase is V_G=V_BSTRAP+V_in. In this way, the output V_samplemay sample (or track) Vin through the turned-onMOS12. Further,switch18 may also be engaged to couple back-gate (B) to source (S) according to the clock φ1 to provide a back-gate bootstrapping toMOS12. Next during the “hold” phase whenswitches14,16,18 are disengaged according to clock φ1 (φ1 is low) andswitches20,22 are disengaged according to clock φ2 (φ2 is high), the gate ofMOS12 is connected to ground (GND) (or a very low voltage level) to ensureMOS12 is turned off. Thus, voltage at gate (G) during the “hold” phase is V′_G≈0. Further,switch22 may also be engaged to couple back-gate (B) to ground according to the clock φ2.
• While the back-gate bootstrapping may help keep the source-to-bulk voltage approximately constant (subjecting to the limitation of the source impedance Zs), the voltage swing (V_G−V′_G≈V_{BSTRAP S}+V_in) at the gate ofMOS12 between the “track” and “hold” phases is dependent on the input signal Vin. Since the charge injection for the track-and-hold circuit10 relates to voltage at the gate ofMOS12 and is therefore also dependent on input signal Vin. Charge injection is commonly understood as a voltage level change caused by parasitic capacitance (Cp) associated with NMOS or PMOS transistors in the track-and-hold circuit. When the charge injection is dependent on input signal Vin, it may cause further non-linearity in the output V_sample.
• Another issue with the current art is that the gate (G) ofMOS12 is commonly grounded during the hold phase, while the source (S) and/or drain (D) ofMOS12 may reach high voltage values depending on the input signal (e.g., a sine wave). If the input signal causes the high voltages at the source (S) and/or drain (D) ofMOS12 exceed the maximum allowed values forMOS12, the oxide ofMOS12 may break down, and the lifetime of theMOS12 may be shortened.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 illustrates an input switch including a track-and-hold circuit.
• FIG. 2 illustrates an input switch including a track-and-hold circuit according to an exemplary embodiment of the present invention.
• FIG. 3 illustrates clocks supplied to the input switch as shown inFIG. 2 according to an exemplary embodiment of the present invention.
• FIG. 4 illustrates another input switch including a track-and-hold circuit according to an exemplary embodiment of the present invention.
• FIG. 5 illustrates another input switch including a track-and-hold circuit according to an exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
• There is a need for reducing the dependency of gate voltage ofMOS12 on input signal Vin to reduce non-linearity in the output signal V_samplecaused by charge injection. It is an objective of the present invention to reduce the dependency of the voltage swings between the “track” phase (or “ON” phase) and the “hold” phase (or “OFF” phase) of an input switch on the input signal, and therefore to improve linearity of the output signal V_sampleand the reliability of the MOS device.
• Embodiments of the present invention may provide a switch that may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second level shifter may be selectively coupled between a reference and the gate during the OFF phase, in which the second voltage level shifter shifts a voltage at the gate to a level lower than a voltage at the source and lower than a voltage at the drain.
• Embodiments of the present invention may provide a switch that may include a MOS transistor alternatively operating in an ON phase and an OFF phase, and a voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate, in which the gate is selectively coupled to the input signal during the OFF phase.
• Embodiments of the present invention may provide a switch that may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.
• FIG. 2 illustrates an input switch including a track-and-hold circuit according to an exemplary embodiment of the present invention. The track-and-hold circuit30 as shown inFIG. 2 may include similarly constructed and labeled track-and-hold circuit10 as shown inFIG. 1. Additionally, the track-and-hold circuit30 include a second voltage level shifter such as a capacitivevoltage level shifter32 at a first end coupled to gate ofMOS12 viaswitch20 and at a second end to ground (GND). The track-and-hold circuit30 as shown inFIG. 2 may work with clocks (φ1, φ2, φ1a) as shown inFIG. 3 according to an exemplary embodiment of the present invention. When the first clock (φ1) is high and the second clock (φ2) is low, the track-and-hold circuit30 may operate in the “track” phase in which switches14,16,18 are engaged and switches20,20 are disengaged. When the first clock (φ1) is low and the second clock (φ2) is high, the track-and-hold circuit30 may operate in the “hold” phase in which switches14,16,18 are disengaged and switches20,22 are engaged. Thus, during the “track” phase, gate voltage V_GforMOS12 may be the same V_BSTRAP+V_in. However, during the “hold” phase, gate voltage V′_GforMOS12 may be_V′BSTRAPrather than the ground as shown inFIG. 1. In this way, the voltage swing at gate (G) ofMOS12 may be changed by the amount of V_BSTRAP. Further, thus the reliability of the operation ofMOS12 may be improved because the voltage at the gate (G) is shifted to a level that is higher than ground but less than the lowest voltage at either the source (S) or the drain (D). This may ensure thatMOS12 is turned off and the voltage bias between the gate and source (V_SG) And the voltage bias between the gate and drain (V_DG) are both reduced (i.e., reduce voltage over oxides), and thus reduce the chance of breaking down.
• While the track-and-hold circuit30 may improve the reliability of input switch operation, the voltage swing at gate (G) ofMOS12 may still depend on input signal Vin.FIG. 4 illustrates another input switch including a track-and-hold circuit40 according to an exemplary embodiment of the present invention. To reduce the voltage swing at the gate (G) ofMOS12, whenswitch20 is engaged, gate (G) ofMOS12 may be coupled to input signal Vin rather than to the ground (GND) as shown inFIG. 1. Similarly, the track-and-hold circuit30 as shown inFIG. 4 may work with clocks (φ1, φ2, φ1a) as shown inFIG. 3 according to an exemplary embodiment of the present invention. When the first clock (φ1) is high and the second clock (φ2) is low, the track-and-hold circuit40 may operate in the “track” phase in which switches14,16,18 are engaged and switches20,20 are disengaged. When the first clock (φ1) is low and the second clock (φ2) is high, the track-and-hold circuit30 may operate in the “hold” phase in which switches14,16,18 are disengaged and switches20,22 are engaged. Thus, during the “track” phase, gate voltage V_GforMOS12 may be the same V_BSTRAP+V_in. However, during the “hold” phase, gate voltage V′_GforMOS12 may be V. The resulting voltage swing between the “track” and “hold” phases is therefore V_G−V′_G≈V_BSTRAPwhich is substantially constant and independent of input signal V_in. Therefore, the linearity of V_sampleis substantially improved.
• Although coupling gate voltage to input signal Vin may reduce the dependency of the gate voltage swing on Vin, when input voltage Vin overshoots (e.g., to the positive voltage for NMOS),MOS12 as shown inFIG. 4 may not be turned off reliably during the “hold” phase. To improve the operational reliability ofMOS12 and linearity of V_sample, the gate voltage during the “hold” phase (whileMOS12 is off) may be bootstrapped from input signal Vin.FIG. 5 illustrates another input switch including a track-and-hold circuit50 according to an exemplary embodiment of the present invention. The track-and-hold circuit50 as shown inFIG. 5 may include similarly constructed and labeled components as shown inFIGS. 1,2, and4. Additionally, the track-and-hold circuit50 may includeswitches34,36 and avoltage level shifter38 that is, at a first end, coupled to the input signal Vin viaswitch36 and at a second end, coupled to the gate (G) ofMOS12 viaswitch34. Both switches34,36 are controlled by the second clock (φ2) so that they are disengaged during the “track” phase and engaged during the “hold” phase. Thevoltage level shifter38 may be a capacitive voltage level shifter that includes a capacitor C3. Further, thus the reliability of the operation ofMOS12 may be improved because the gate (G) is bootstrapped during the hold phase as well. This may ensure that the voltage bias between the gate and source (V_SG) And the voltage bias between the gate and drain (V_DG) are always fixed voltage values that cannot exceed the maximum allowed voltages for the MOS device.
• In one embodiment, thevoltage level shifter38 may shift the voltage in a same amount but in an opposite direction with respect to thevoltage level shifter24. Thus, ifvoltage level shifter24 shifts the input signal Vin by a positive voltage of V_BSTRAPduring the “track” phase,voltage level shifter38 may shift the input signal Vin by a negative voltage of −V_BSTRAPduring the “hold” phase. In one exemplary embodiment,voltage level shifter24 may shift the input signal Vin by a fixed positive voltage value during the “track” phase, andvoltage level shifter38 may shift the input signal Vin by a fixed negative voltage value during the “hold” phase.
• In an alternative embodiment, thevoltage level shifter38 may shift the voltage in an opposite direction and by a different amount from the voltage shift byvoltage level shifter24. Thus, ifvoltage level shifter24 may shift the input signal Vin by a positive voltage of V_BSTRAP(where V_BSTRAP>0) during the “track” phase,voltage level shifter38 may shift the input signal by a negative voltage of V″_BSTRAP(where V″_BSTRAP<0) so long as the negative voltage shift V″_BSTRAPensuresMOS12 is turned off during the “hold” phase.
• Because bothvoltage level shifters24 and38 shift voltages in reference of input signal Vin to the gate (G) ofMOS12, the voltage swing at the gate between the “track” and “hold” phases may be substantially constant and independent from input signal Vin, or V_G−V′_G=V_BSTRAP−V″_BSTRAP. When V″_BSTRAP=−V_BSTRAP, V_G−V′_G=2 V_BSTRAP. In this way, the both the reliability of the operation of the track-and-hold circuit50 and linearity of output voltage V_sampleare improved.
• While the present invention is discussed in light of the exemplary track-and-hold circuits that include an input switches, the principles of the present invention are not limited to the exemplary input switch and may be applied to other types of switches, which include MOS devices, to improve the linearity of output signals and reliability of the switches. For example, a MOS switch that operates between an “ON” state and an “OFF” state at a stage of a circuit known to a person of ordinary skill in the art may be similarly improved with present invention by providing bootstrapped gate voltages as described inFIGS. 2 to 5.
• Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Claims (22)

1-5. (canceled)

6. A switching device, comprising:

a MOS transistor alternatively operating in an ON phase and an OFF phase, the MOS transistor including a source for receiving an input signal, a drain for connecting to a load, a gate, and a back-gate that is coupled to one of the input signal and a reference; and

a first voltage level shifter switchably coupled between the source and the gate during the ON phase,

wherein during the OFF phase, the gate is switchably coupled to one of the input signal and a second voltage level shifter.

7. The switching device ofclaim 6, wherein the MOS transistor is one of an NMOS transistor and a PMOS transistor.

8. The switching device ofclaim 6, wherein the MOS transistor is turned on by a voltage at the gate during the ON phase and turned off by the voltage at the gate during the OFF phase.

9. The switching device ofclaim 6, wherein a voltage swing between the ON and OFF phases at the gate is substantially independent from the input signal.

10-17. (canceled)

18. The switching device ofclaim 6, wherein the second voltage level shifter is coupled between the gate and a reference during the OFF phase.

19. The switching device ofclaim 18, wherein the second voltage level shifter shifts a voltage at the gate to a level lower than a voltage at the source and lower than a voltage at the drain.

20. The switching device ofclaim 18, wherein the second level shifter shifts the voltage at the gate to a level below the reference.

21. The switching device ofclaim 6, wherein the first voltage level shifter is switchably coupled between the source and the gate during the ON phase via a first set of switches controlled by a first clock, and the second voltage level shifter is switchably coupled between the gate and the source during the OFF phase via a second set of switches controlled by a second clock.

22. The switching device ofclaim 21, wherein the load is switchably coupled to the drain via a third switch controlled by a third clock.

23. The switching device ofclaim 22, wherein the first, second, and third clocks are different clocks.

24. The switching device ofclaim 21, wherein a phase of the first clock is opposite to a phase of the second clock.

25. The switching device ofclaim 21, wherein a phase of the first clock is opposite to a phase of the second clock with an offset.

26. The switching device ofclaim 6, wherein the first voltage level shifter is switchably coupled between the source and the gate during the ON phase via a first set of switches controlled by a first clock, and the gate is switchably coupled to the input signal via a second set of switches controlled by a second clock.

27. The switching device ofclaim 26, wherein the load is switchably coupled to the drain via a third switch controlled by a third clock.

28. The switching device ofclaim 27, wherein the first, second, and third clocks are different clocks.

29. The switching device ofclaim 26, wherein a phase of the first clock is opposite to a phase of the second clock.

30. The switching device ofclaim 26, wherein a phase of the first clock is opposite to a phase of the second clock with an offset.

31. The switching device ofclaim 6, wherein the back-gate tracks the input signal so that the MOS transistor operates in the OFF phase.

32. The switching device ofclaim 6, wherein the back-gate is coupled to the reference.

33. A switching device, comprising:

switching means for alternatively operating in an ON phase and an OFF phase, wherein the switching means includes a source for receiving an input signal, a drain for connecting to a load, a gate, and a back-gate that is coupled to one of the input signal and a reference,

first voltage level shifting means for switchably connecting the source and the gate during the ON phase,

wherein during the OFF phase, the gate is switchably coupled to one of the input signal and a second voltage level shifting means.

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