US20140017900A1 - Plasma etching apparatus and plasma etching method - Google Patents

Abstract

A plasma etching apparatus performs plasma etching on a substrate having a resist pattern formed thereon and an outer edge portion where the substrate surface is exposed. The plasma etching apparatus includes a support part that supports the substrate, a cover member that covers the outer edge portion of the substrate and prevents plasma from coming around the outer edge portion, and a control unit that generates plasma by controlling high frequency power application and supply of a processing gas for etching, and uses the generated plasma to etch the substrate that is supported by the support part and has the outer edge portion covered by the cover member. After etching the substrate, the control unit generates plasma by controlling high frequency power application and supply of a processing gas for ashing, and uses the generated plasma to perform ashing on the resist pattern on the etched substrate.

Description

TECHNICAL FIELD
• The present invention relates to a plasma etching apparatus and a plasma etching method.
BACKGROUND ART
• In the field of semiconductor device manufacturing, numerous efforts have been made to increase the density of semiconductor devices through their miniaturization. Recently, attention is being directed to a semiconductor device stacking technique called three-dimensional (3D) packaging as means for increasing the density per unit area of semiconductor devices.
• Semiconductor devices stacked in the vertical direction may include electrodes that are arranged to penetrate through a substrate made of silicon, for example. In this way, the semiconductor devices may be electrically connected via the electrodes. To create such an electrode that penetrates through a substrate, a resist is applied on the substrate using a coater, the resist is exposed using an exposure apparatus, and a resist pattern is developed using a developing apparatus. The resist is then used as a mask to etch the substrate using a plasma etching apparatus to create a through hole or a via hole. After creating the through hole or via hole in the substrate, the resist remaining on the substrate is removed by ashing.
• When etching the substrate using the plasma etching apparatus in the above process, if the resist applied on the substrate extends to the outer edge portion of the substrate, the resist may come into contact with a substrate carrier or a transfer arm and come off during transfer of the substrate, and this may result in the generation of dust. Accordingly, after applying the resist on the substrate, the resist is removed from the rear surface and the outer edge portion including a bevel portion of the substrate by a back rinse mechanism and a bevel rinse mechanism of the coater using an organic solvent, for example. In this way, dust may be prevented from being generated as a result of the resist coming off of the outer edge portion of the substrate (See e.g., Patent Document 1).
• As another way of preventing the generation of dust as a result of the resist material coming off of the outer edge portion of a substrate, after applying the resist on the substrate and exposing the entire substrate to form a resist pattern, an insolubilization process may be performed on the resist pattern formed at the outer edge portion of the substrate using a developing solution (See e.g., Patent Document 2).
PRIOR ART DOCUMENTSPatent Documents
• Patent Document 1: Japanese Laid-Open Patent Publication No. 2009-295636
• Patent Document 2: Japanese Laid-Open Patent Publication No. 2000-331913
SUMMARY OF THE INVENTIONProblem to be Solved by the Invention
• However, in the above case where the resist on the outer edge portion of a substrate is removed after which the substrate is etched using the resist pattern on the substrate as a mask and the remaining resist is removed by asking, the following problems are encountered, for example.
• When etching the substrate using a plasma etching apparatus, because the substrate surface of a bevel region of the substrate is exposed, the exposed substrate surface may be prone to build-up of black silicon, which refers to the roughening of the silicon substrate surface due to exposure to plasma. For example, when a part of the resist applied on the surface of the substrate is removed from a region extending over a predetermined width from the outer edge of the substrate, black silicon may be formed at both the substrate surface and rear surface within this region.
• To prevent the formation of black silicon, the region extending over a predetermined width from the outer edge of the substrate may be protected by a resist as illustrated inPatent Documents 1 and 2, for example. However, as described above, when the region extending over the predetermined width from the outer edge of the substrate is protected by a resist, the resist may come off during transfer of the substrate to result in the generation of dust, for example.
• Also, the above problem is not limited to cases of etching one substrate. For example, in the case of etching a bonded substrate that is formed by bonding a plurality of substrates via an adhesive, the adhesive is exposed at the outer edge portion of the bonded substrate. Thus, the exposed adhesive may come off upon coming into contact with plasma to cause the generation of dust, or the substrates themselves may be separated from one another. Further, the outer edge portion of the bonded substrate may become brittle or be prone to cracking, for example.
• The present invention has been conceived in view of the foregoing problems associated with the prior art, and it is an object of the present invention to provide a plasma etching apparatus and a plasma etching method that are capable of protecting the outer edge portion of a substrate having a resist pattern formed thereon upon etching the substrate.
Means for Solving The Problem
• According to one embodiment of the present invention, a plasma etching apparatus is provided that performs plasma etching on a substrate having a surface portion on which a resist pattern is formed and an outer edge portion where a substrate surface of the substrate is exposed. The plasma etching apparatus includes a support part that supports the substrate; a cover member that covers the outer edge portion of the substrate that is supported by the support part and prevents plasma from coming around the outer edge portion of the substrate; and a control unit that generates plasma by controlling application of a high frequency power from a high frequency power supply and supply of a processing gas for etching from a first processing gas supply source, and uses the generated plasma to etch the substrate that is supported by the support part and has the outer edge portion covered by the cover member. After etching the substrate, the control unit generates plasma by controlling application of a high frequency power from a high frequency power supply and supply of a processing gas for ashing from a second processing gas supply source, and uses the generated plasma to perform ashing on the resist pattern on the etched substrate.
• According to another embodiment of the present invention, a plasma etching apparatus is provided that performs plasma etching on a bonded substrate, which includes a plurality of substrates that are bonded together via an adhesive, the bonded substrate having a surface portion on which a resist pattern is formed and an outer edge portion where the adhesive is exposed. The plasma etching apparatus includes a support part that supports the bonded substrate; a cover member that covers the outer edge portion of the bonded substrate that is supported by the support part and prevents plasma from coming around the outer edge portion of the bonded substrate; and a control unit that generates plasma by controlling application of a high frequency power from a high frequency power supply and supply of a processing gas for etching from a first processing gas supply source, and uses the generated plasma to etch the bonded substrate that is supported by the support part and has the outer edge portion covered by the cover member. After etching the bonded substrate, the control unit generates plasma by controlling application of a high frequency power from a high frequency power supply and supply of a processing gas for ashing from a second processing gas supply source, and uses the generated plasma to perform ashing on the resist pattern on the etched bonded substrate.
• According to another embodiment of the present invention, a plasma etching method is provided for performing plasma etching on a substrate having a surface portion on which a resist pattern is formed and an outer edge portion where a substrate surface of the substrate is exposed. The plasma etching method includes the steps of supporting the substrate by a support part; arranging a cover member to cover the outer edge portion of the substrate that is supported by the support part to prevent plasma from coming around the outer edge portion of the substrate; generating plasma by controlling application of a high frequency power from a high frequency power supply and controlling supply of a processing gas for etching from a first processing gas supply source, and using the generated plasma to etch the substrate that is supported by the support part and has the outer edge portion covered by the cover member; and after etching the substrate, generating plasma by controlling application of a high frequency power from a high frequency power supply and controlling supply of a processing gas for ashing from a second processing gas supply source, and using the generated plasma to perform ashing on the resist pattern on the etched substrate.
• According to another embodiment of the present invention, a plasma etching method is provided for performing plasma etching on a bonded substrate, which includes a plurality of substrates that are bonded together via an adhesive, the bonded substrate having a surface portion on which a resist pattern is formed and an outer edge portion where the adhesive is exposed. The plasma etching method includes the steps of supporting the bonded substrate by a support part; arranging a cover member to cover the outer edge portion of the bonded substrate that is supported by the support part to prevent plasma from coming around the outer edge portion of the bonded substrate; generating plasma by controlling application of a high frequency power from a high frequency power supply and controlling supply of a processing gas for etching from a first processing gas supply source, and using the generated plasma to etch the bonded substrate that is supported by the support part and has the outer edge portion covered by the cover member; and after etching the bonded substrate, generating plasma by controlling application of a high frequency power from a high frequency power supply and controlling supply of a processing gas for ashing from a second processing gas supply source, and using the generated plasma to perform ashing on the resist pattern on the etched bonded substrate.
Advantageous Effect of the Invention
• According to an aspect of the present invention, when etching a substrate having a resist pattern formed thereon, an outer edge portion of the substrate may be protected.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic cross-sectional view illustrating a configuration of a plasma etching apparatus according to a first embodiment of the present invention;
• FIG. 2 is an enlarged cross-sectional view of a portion surrounding a bevel cover ring;
• FIG. 3 is a schematic cross-sectional view illustrating a first state of an operation for placing a wafer on an electrostatic chuck;
• FIG. 4 is a schematic cross-sectional view illustrating a second state of the operation for placing the wafer on the electrostatic chuck;
• FIG. 5 is a schematic cross-sectional view illustrating a third state of the operation for placing the wafer on the electrostatic chuck;
• FIG. 6 is a schematic cross-sectional view illustrating a fourth state of the operation for placing the wafer on the electrostatic chuck;
• FIG. 7 is an enlarged cross-sectional view illustrating the wafer being supported by the electrostatic chuck while having an outer edge portion covered by a brim part of an upper ring member;
• FIG. 8 is a cross-sectional view illustrating surface roughening of a substrate surface of the wafer at its outer edge portion that may occur in a case where the outer edge portion is not covered by the upper ring member;
• FIG. 9 is a cross-sectional view illustrating an inclination of a via hole formed within the wafer;
• FIG. 10 is a graph indicating measurement results of inclination angles with respect to the vertical direction of via holes formed at various distances from the outer edge of the wafer;
• FIG. 11 is a graph indicating measurement results of resist ashing rates at various points on the wafer at various distances from the outer edge of the wafer in two different examples using different ashing conditions;
• FIG. 12 is a graph indicating measurement results of resist film thicknesses before and after ashing at various points on the wafer at various distances from the outer edge of the wafer;
• FIG. 13 is a schematic cross-sectional view illustrating a configuration of a bonded wafer;
• FIG. 14A is a schematic cross-sectional view illustrating a first state of a wafer in a process step of a semiconductor device manufacturing method including a plasma etching method according to a second embodiment of the present invention;
• FIG. 14B is a schematic cross-sectional view illustrating a second state of the wafer in a process step of the semiconductor device manufacturing method including the plasma etching method according to the second embodiment;
• FIG. 14C is a schematic cross-sectional view illustrating a third state of the wafer in a process step of the semiconductor device manufacturing method including the plasma etching method according to the second embodiment;
• FIG. 15A is a schematic cross-sectional view illustrating a fourth state of the wafer in a process step of the semiconductor device manufacturing method including the plasma etching method according to the second embodiment;
• FIG. 15B is a schematic cross-sectional view illustrating a fifth state of the wafer in a process step of the semiconductor device manufacturing method including the plasma etching method according to the second embodiment;
• FIG. 15C is a schematic cross-sectional view illustrating a sixth state of the wafer in a process step of the semiconductor device manufacturing method including the plasma etching method according to the second embodiment; and
• FIG. 16 is a table indicating measurement results of the angles of via holes with respect to the horizontal direction for via holes formed at various distances from the center of the wafer.
EMBODIMENTS FOR IMPLEMENTING THE INVENTION
• In the following, embodiments of the present invention are described with reference to the accompanying drawings.
First Embodiment
• First, a plasma etching apparatus according to a first embodiment of the present invention is described.
• FIG. 1 is a schematic cross-sectional view illustrating a configuration of the plasma etching apparatus according to the first embodiment of the present invention.
• The plasma etching apparatus includes aprocessing chamber1 that is configured to be airtight and is electrically grounded. Theprocessing chamber1 has a cylindrical structure and may be made of aluminum, for example. Astage2 that holds a semiconductor wafer W (simply referred to as “wafer W” hereinafter) in the horizontal direction is arranged inside theprocessing chamber1. The wafer W is an example of a substrate to be processed. Thestage2 may be made of aluminum, for example, and is configured to act as a lower electrode. Thestage2 is supported by a conductor support4 and is arranged at a bottom of theprocessing chamber1 via an insulatingplate3. A cylindricalinner wall member3athat may be made of quartz, for example, is arranged to surround thestage2 and the support4.
• Abevel cover ring5 is arranged on an upper side outer edge portion of thestage2. The configuration of thebevel cover ring5 is described in detail below. Thebevel cover ring5 is an embodiment of a cover member that prevents plasma from coming around the outer edge portion of a substrate.
• A firstRF power supply10ais connected to thestage2 via afirst matching unit11a, and a secondRF power supply10bis connected to thestage2 via asecond matching unit11b.The firstRF power supply10ais for plasma generation. The firstRF power supply10ais configured to output to the stage2 a high frequency power of a predetermined frequency (at least 27 MHz; e.g., 100 MHz). The secondRF power supply10bis for ion attraction. The secondRF power supply10bis configured to output to the stage2 a high frequency power of a predetermined frequency (no more than 13.56 MHz; e.g., 13.56 MHz) that is lower than the high frequency power output by the firstRF power supply10a.Ashower head16 that acts as an upper electrode is arranged above thestage2 to face thestage2 in parallel. Theshower head16 and thestage2 are configured to function as a pair of electrodes (i.e., upper electrode and lower electrode).
• In theprocessing chamber1, plasma is generated from a processing gas for etching that is introduced from theshower head16, which acts as the upper electrode, using the high frequency power applied to thestage2, which acts as the lower electrode. The generated plasma is used to perform an etching process on the wafer W that has its outer edge portion covered by the cover member (bevel cover ring5). After the etching process, plasma is generated from a processing gas for ashing that is introduced into theprocessing chamber1 by the high frequency power applied to the lower electrode, and the generated plasma is used to perform an ashing process on the wafer W that has its outer edge portion covered by the cover member. The above processes are controlled by acontrol unit90.
• Anelectrostatic chuck6 that is configured to hold the wafer W by an electrostatic attracting force is provided on a top surface of thestage2. Theelectrostatic chuck6 includes anelectrode6aarranged within aninsulator6b.Theelectrode6ais electrically connected to aDC power supply12. A Coulomb force is generated between theelectrode6aand the wafer W by the application of a DC voltage from theDC power supply12 so that the wafer W may be electrostatically attracted to theelectrostatic chuck6 by the Coulomb force. In this way, the wafer W is held by theelectrostatic chuck6.
• In the present example, thestage2 and theelectrostatic chuck6 embody a support part that supports a substrate.
• Acoolant path4ais formed within the support4, and thecoolant path4ais connected to acoolant inlet pipeline4band acoolant outlet pipeline4c.By circulating a suitable coolant such as cooling water through thecoolant path4a,the support4 and thestage2 may be controlled to a predetermined temperature. Further, a rear sidegas supply line30 for supplying a heat transfer gas (rear side gas) such as a helium (He) gas to a rear surface of the wafer W is arranged to penetrate through thestage2, for example. The rear sidegas supply line30 is connected to a rear side gas supply source (not shown). With such an arrangement, the wafer W that is electrostatically attracted to the top surface of thestage2 by theelectrostatic chuck6 may be controlled to a predetermined temperature.
• Theshower head16 is arranged at a ceiling portion of theprocessing chamber1. Theshower head16 includes amain body16aand anupper ceiling plate16b, which acts as an electrode plate. Theshower head16 is mounted to a top part of theprocessing chamber1 via an insulatingmember17. Themain body16amay be made of a conductive material such as aluminum having a surface that is alumite-treated, for example. Theupper ceiling plate16bis detachably mounted to a lower part of themain body16a.
• Themain body16ahas agas diffusion chamber16carranged therein. Multiple gas throughholes16dthat communicate with thegas diffusion chamber16care arranged at a bottom part of themain body16a.Also, gas introduction holes16ethat communicate with the gas throughholes16dare arranged to penetrate through theupper ceiling plate16bin its thickness direction. With such an arrangement, a processing gas supplied to thegas diffusion chamber16cmay be dispersed via the gas throughholes16dand the gas introduction holes16eupon being supplied to theprocessing chamber1. Further, a pipeline (not shown) for circulating a coolant is arranged within themain body16aso that theshower head16 may be cooled to a predetermined temperature while a plasma etching process is performed.
• Themain body16ahas agas introduction port16ffor introducing processing gas for etching into thegas diffusion chamber16c.Thegas introduction port16fis connected to one end of agas supply pipeline14a.The other end of thegas supply pipeline14ais connected to a first processinggas supply source14 for supplying the processing gas for etching. A mass flow controller (MFC)14band an open/close valve V1 are arranged on thegas supply line14ain this order from the upstream side. Processing gas for plasma etching is introduced into thegas diffusion chamber16cfrom the first processinggas supply source14 via thegas supply pipeline14a.The processing gas is then discharged from thegas diffusion chamber16cthrough the gas throughholes16dand the gas introduction holes16eto be dispersed into theprocessing chamber1 like a shower.
• Themain body16aalso has agas introduction port16gfor introducing processing gas for ashing into thegas diffusion chamber16c.Thegas introduction port16gis connected to one end of agas supply pipeline15a. The other end of thegas supply pipeline15ais connected to a second processinggas supply source15 that supplies a processing gas for ashing. A mass flow controller (MFC)15band an open/close valve V2 are arranged on thegas supply line15ain this order from the upstream side. Processing gas for plasma ashing is introduced into thegas diffusion chamber16cfrom the second processinggas supply source15 via thegas supply pipeline15a.The processing gas is then discharged from thegas diffusion chamber16cthrough the gas throughholes16dand the gas introduction holes16eto be dispersed into theprocessing chamber1 like a shower.
• Theshower head16, which acts as the upper electrode as described above, is electrically connected to a low pass filter (LPF)71 via a variableDC power supply72. Power supply operations of the variableDC power supply72 may be turned on/off by an on/offswitch73. The current voltage of the variableDC power supply72 and the on/off operations of the on/offswitch73 are controlled by the control unit90 (described below). As described in detail below, when generating plasma within theprocessing chamber1 by applying a high frequency power from the firstRF power supply10aor the secondRF power supply10bto thestage2, thecontrol unit90 turns on the on/offswitch73 as is necessary so that a predetermined DC voltage may be applied to theshower head16, which acts as the upper electrode.
• Further, a cylindrically-shapedground conductor1ais arranged to extend above the height of theshower head16 from the side wall of theprocessing chamber1. The cylindrically-shapedground conductor1ahas a ceiling wall arranged at its top portion.
• Anexhaust port81 is formed at a bottom portion of theprocessing chamber1, and anexhaust device83 is connected to theexhaust port81 via anexhaust pipe82. Theexhaust device83 includes a vacuum pump, and the pressure within theprocessing chamber1 may be reduced to a predetermined degree of vacuum by operating this vacuum pump. Further, a loading/unloadingport84 is arranged at the side wall of theprocessing chamber1, and agate valve85, which is configured to open and close the loading/unloadingport84, is arranged at the loading/unloadingport84.
• Further, deposition shields86 and87, which are configured to be detachable, are arranged within theprocessing chamber1. Thedeposition shield86 is arranged along the inner wall face of theprocessing chamber1 and is configured to prevent etching by-products (deposition) from adhering to theprocessing chamber1. A conductive member (GND block)89 is connected to thedeposition shield86 at a height position that is substantially the same as that of the wafer W. The conductive member (GND block)89 is connected such that its potential with respect to ground may be controlled, and in this way, an abnormal discharge may be prevented.
• In the following, the configuration of thebevel cover ring5 is described in detail.
• FIG. 2 is an enlarged schematic cross-sectional view of a portion surrounding thebevel cover ring5.
• As illustrated inFIGS. 1 and 2, thebevel cover ring5 includes anupper ring member51, alower ring member52, alift pin53, and adrive mechanism54.
• Theupper ring member51 includes amain part51aand abrim part51b.Themain part51ahas a ring-shaped structure. Thebrim part51bis arranged to protrude inward from the inner circumference of themain part51ain the radial direction of the ring-shapedmain part51a.Thebrim part51bis configured to cover an outer edge portion WE of the wafer W that is held by theelectrostatic chuck6. Theupper ring member51 includes thebrim part51bthat covers the outer edge portion WE in order to prevent plasma from coming around the outer edge portion WE of the wafer W.
• Theupper ring member51 may be made of quartz or yttria (Y₂O₃), for example. Yttria may be preferred considering its excellent plasma resistance. Also, as described in detail below with reference toFIG. 16, in terms of suppressing the inclination angle of a via hole V, yttrium may produce effects that are substantially the same or even more advantageous than that in a case where quartz is used.
• Thelower ring member52 is arranged into a ring-shaped structure corresponding to the ring-shape of theupper ring member51. A ring-shapedgroove52ais formed at the upper face of thelower ring member52. By having themain part51aengage the ring-shapedgroove52bformed on the upper face of thelower ring member52, movement of theupper ring member51 in the horizontal direction may be restricted.
• Multiple (e.g., three) throughholes52bpenetrating through thelower ring member52 in the vertical direction are formed along the circumferential direction of thelower ring member52.Protrusions51care formed along the circumferential direction of theupper ring member51 at positions corresponding to the throughholes52b.By having theprotrusions51cof theupper ring member51 engage the throughholes52bformed at thelower ring member52, movement of theupper ring member51 in the circumferential direction may be restricted. Thelower ring member52 may be made of quartz, for example.
• Further, holes51dare formed at the bottom faces of theprotrusions51cof theupper ring member51.
• Thelift pin53 is arranged within ahole6cformed at theelectrostatic chuck6 at a position corresponding to that of thehole51d,which is formed at theupper ring member51. Thelift pin53 is configured to be movable in the vertical direction by thedrive mechanism54 that drives thelift pin53 to move up and down. When thelift pin53 is raised, the top end of theleft pin53 pushes an upper face of thehole51dof theupper ring member51 in the upward direction so that theupper ring member51 may be raised.
• Theelectrostatic chuck6 includes alift pin61 and adrive mechanism62. Thelift pin61 is arranged within ahole6dformed at theelectrostatic chuck6 and is configured to be movable in the vertical direction by thedrive mechanism62 that drives thelift pin61 to move up and down. When thelift pin61 is raised, the top end of theleft pin61 pushes the wafer W upward so that the wafer W may be raised.
• The overall operations of the plasma etching device having the above configuration are controlled by thecontrol unit90. Thecontrol unit90 includes aprocess controller91, auser interface92, and astorage unit93. Theprocess controller91 includes a CPU and is configured to control operations of various components of the plasma etching device.
• Theuser interface92 may include a keyboard that is operated by a process controller to input various commands for controlling the process of the plasma etching apparatus, and a display that indicates the operation status of the plasma etching apparatus in visual form, for example.
• Thestorage unit93 stores recipes that include control programs (software) for enabling theprocess controller91 to control various process operations of the plasma etching apparatus and process condition data, for example. Theprocess controller91 reads a given recipe from thestorage unit93 according to a command from theuser interface92 to execute a desired process. In this way, the plasma etching apparatus may perform the desired process under control by thecontrol processor91. In certain embodiments, the recipes including the control programs and process condition data may be stored in a computer-readable storage medium (e.g., hard disk, CD, flexible disk, semiconductor memory). In other embodiments, the recipes including the control programs and process condition data may be transmitted from another device via a dedicated line, for example.
• In the following, a plasma etching method according to an embodiment of the present invention is described.
• FIGS. 3-6 are schematic cross-sectional views illustrating various states of an operation for placing the wafer W on theelectrostatic chuck6.
• First, thelift pin53 is raised by thedrive mechanism54 in a state where the wafer W is not held by the electrostatic chuck6 (seeFIG. 3). The raisedlift pin53 pushes theupper ring member51 upward to raise the upper ring member51 (seeFIG. 4).
• Next, thegate valve85 is opened, and the wafer W having a resist pattern formed thereon is transferred by a transfer robot (not shown), for example, to be delivered onto theelectrostatic chuck6 within theprocessing chamber1 from the loading/unloadingport84 via a load lock chamber (not shown). Then, thelift pin61 is raised by thedrive mechanism62, and the wafer W is received by the raisedlift pin61 from the transfer robot (seeFIG. 5).
• Next, the transfer robot is evacuated out of theprocessing chamber1, and thegate valve85 is closed. Then, thelift pin61 is lowered by thedrive mechanism62, and the wafer W is placed on the electrostatic chuck6 (seeFIG. 6). Further, a predetermined DC voltage from theDC power supply12 is applied to theelectrode6aof theelectrostatic chuck6, and as a result the wafer W is electrostatically attracted to theelectrostatic chuck6 by the Coulomb force that is generated between the wafer W and theelectrostatic chuck6.
• Next, as thelift pin53 is lowered by thedrive mechanism54, theupper ring member51 is lowered to its original position to be accommodated within a ring-shapedgroove52a.At this point, the wafer W and thebevel cover ring5 may be in their respective positions illustrated inFIG. 2. In this way, the outer edge portion WE of the wafer W may be covered by thebrim part51bof theupper ring member51.
• Note that in the example described above, the wafer W is electrostatically attracted to theelectrostatic chuck6 before theupper ring member51 is lowered. However, the electrostatic attraction of the wafer W to theelectrostatic chuck6 may alternatively be performed after lowering theupper ring member51, for example.
• FIG. 7 is an enlarged cross-sectional view of the wafer W having its outer edge portion WE covered by thebrim part51bof theupper ring member51 and being supported by theelectrostatic chuck6 in such a state.
• As illustrated inFIG. 7, theupper ring member51 covers a region of the outer edge portion WE of the wafer W extending over a predetermined width L from the outer edge of the wafer W. Also, a resist pattern (resist PR) is formed on the surface of the wafer W. The resist PR is removed from a region of the outer edge portion WE of the wafer W extending over a predetermined width L1 from the outer edge of the wafer W so that the substrate surface of the waver W is exposed at this region. As indicated in formula (1) shown below, the predetermined width L is preferably greater than the predetermined width L1.
• 
  L>L1  (1)
• The predetermined width L1 is an example of a first predetermined width that satisfies formula (1).
• Assuming an inner diameter of theupper ring member51 is denoted as DI, and an outer diameter of the wafer W is denoted as DO (seeFIG. 2), the relationship between DI, DO, and L may satisfy the following formula (2).
• 
  L=(DO−DI)/2  (2)
• Based on the above formulas (1) and (2), the relationship between DI, DO, and L1 preferably satisfies the following formula (3).
• 
  DI<DO−2L1  (3)
• That is, the inner diameter DI of thebrim part51bof theupper ring member51 is preferably determined based on the outer diameter DO of the wafer W and the predetermined width L1.
• Next, air is discharged from theprocessing chamber1 via theexhaust port81 by the vacuum pump of theexhaust device83. Then, a processing gas for etching is introduced into theprocessing chamber1 to generate plasma for etching the wafer W.
• The etching process involves introducing a predetermined processing gas (etching gas) into theprocessing chamber1 from the first processinggas supply source14 in a state where theprocessing chamber1 is depressurized to a predetermined degree of vacuum and maintained at a predetermined pressure. In the case of etching silicon Si as the base material of the wafer W using a resist pattern as a mask, the so-called halogen gas such as Cl₂, Cl₂+HBr, Cl₂+O₂, CF₄+O₂, SF₆, Cl₂+N₂, Cl₂+HCl, or HBr+Cl₂+SF₆may be used as the predetermined processing gas, for example. Alternatively, in a case where one or more layers of a hard mask film made of SiO₂or SiN, for example, is formed on the surface of the wafer W, and the resist pattern is used as a mask to etch such hard mask film, a mixed gas including CF gas (e.g., CF₄, C₄F₈, CHF₃, CH₃F, CH₂F₂) and Ar gas, or a gas having oxygen added to such mixed gas may be used as the predetermined processing gas, for example. In a state where such a predetermined processing gas is introduced into theprocessing chamber1, a high frequency power of 100 MHz, for example, is supplied to thestage2 from the firstRF power supply10a.Also, a high frequency power (for biasing) of 13.56 MHz, for example, is supplied to thestage2 from the secondRF power supply10bto prompt ion attraction.
• When the high frequency powers are applied to thestage2 corresponding to the lower electrode, an electric field is formed between theshower head16 corresponding to the upper electrode and thestage2 corresponding to the lower electrode. Electrical discharge occurs within theprocessing chamber1 that accommodates the wafer W, and this electrical discharge prompts the generation of plasma from the processing gas. Anisotropic etching is performed on the wafer W by the generated plasma using the resist pattern formed on the surface of the wafer W as a mask while the outer edge portion WE of the wafer W is covered by theupper ring member51.
• After the etching process is completed, an ashing process is performed to remove the remaining resist from the wafer W. The ashing process is performed using plasma generated from a processing gas for ashing.
• The ashing process involves introducing a predetermined processing gas (ashing gas) into theprocessing chamber1 from the second processinggas supply source15 in a state where theprocessing chamber1 is depressurized to a predetermined degree of vacuum and maintained at a predetermined pressure. For example, O₂gas, NO gas, N₂O gas, H₂O gas, or O₃gas may be used as the predetermined processing gas for ashing. In a state where such a predetermined processing gas is introduced into theprocessing chamber1, a high frequency power of 100 MHz, for example, is supplied to thestage2 from the firstRF power supply10a.Also, a high frequency power (for biasing) of 13.56 MHz, for example, is supplied to thestage2 from the secondRF power supply10bto prompt ion attraction.
• When the high frequency powers are applied to thestage2 corresponding to the lower electrode, an electric field is formed between theshower head16 corresponding to the upper electrode and thestage2 corresponding to the lower electrode. Electrical discharge occurs within theprocessing chamber1 that accommodates the wafer W, and this electrical discharge prompts the generation of plasma from the processing gas. The resist remaining on the surface of the wafer W is removed by the generated plasma while the outer edge portion WE of the wafer W is covered by theupper ring member51.
• After the etching process and the ashing process are performed in the manner described above, the application of high frequency power, the application of the DC voltage, and the supply of processing gas are stopped. Then, the wafer W is transferred outside theprocessing chamber1 by performing the wafer transfer operations described above in reverse order.
• According to an aspect of the present embodiment, surface roughening of the substrate surface of the wafer W at its outer edge portion WE may be prevented when etching the wafer W having a resist pattern formed thereon. In the following, such an aspect of the present embodiment is described in connection with a comparison example.
• As a comparison example, a case where the outer edge portion WE of the wafer W is not covered by theupper ring member51 is contemplated below. In this case, the outer edge portion WE of the wafer W is exposed and comes into contact with plasma. As described above, the resist PR is removed from the region of the outer edge portion WE of the wafer extending over the predetermined width L1 from the outer edge of the wafer W so that the substrate surface of the wafer W is exposed at this region. As illustrated inFIG. 8, when the exposed substrate surface of the wafer W comes into contact with plasma, the so-called black silicon (roughened silicon) is formed at the exposed substrate surface at the outer edge portion WE of the wafer W.
• On the other hand, as described above, in the present embodiment, the region of the outer edge portion WE of the wafer W extending over the predetermined width L from the outer edge of the wafer W is covered by theupper ring member51. In this way, plasma may be prevented from coming around the outer edge portion WE of the wafer W while an etching process is performed on the wafer W. That is, the region of the outer edge portion WE of the wafer W extending over the predetermined width L1 from the outer edge of the wafer W where the substrate surface of the wafer W is exposed may be covered so that it would not be exposed to plasma. In this way, the substrate surface of the wafer W at the outer edge portion WE of the wafer W may be prevented from roughening. In other words, the outer edge portion WE of the wafer W may be protected.
• Also, according to an aspect of the present embodiment, when etching the wafer W having a resist pattern formed thereon to create a via hole V, an inclination of the via hole V by a certain inclination angle with respect to the vertical direction may be suppressed for via holes V formed near the outer edge portion WE of the wafer W. In the following, such an aspect of the present embodiment is described.
• When the outer edge portion WE of the wafer W is covered by theupper ring member51, a via hole V formed at the wafer W near thebrim part51bof theupper ring member51 may be prone to inclination. That is, as illustrated inFIG. 9, a central axis of the via hole V tends to incline at an inclination angle of (90−θ) with respect to the vertical direction, assuming θ represents an angle of the central axis with respect to the horizontal direction. It is speculated that while thebrim part51bprevents plasma from coming around the outer edge portion WE of the wafer W, it also causes an inclination of the irradiation direction of plasma.
• FIG. 10 is a graph illustrating inclination angles (90−θ) of the central axes of via holes V that are etched at various distances from the outer edge of the wafer W in an exemplary case where DO=300 mm, L=1.7 mm (DI=296.6 mm), or L=1.0 mm (DI=298 mm). In the graph ofFIG. 10, black circles represent the case where L=1.0 mm, and white circles represent the case where L=1.7 mm. Also, inFIGS. 10, (90−θ)=0 represents a case where the central axis of the via hole V is not inclined at all with respect to the vertical direction, and the greater the value of the inclination angle (90−θ), the greater the inclination of the central axis with respect to the vertical direction.
• Whether L=1.7 mm or L=1.0 mm, the inclination angle (90−θ) of a via hole V that is formed at a point that is relatively far away from the edge of the wafer W; namely, a point towards the center of the wafer W, is substantially equal to 0 (zero). That is, the via hole V formed at such a point extends substantially in the vertical direction without inclining. On the other hand, whether L=1.7 mm or L=1.0 mm, the inclination angle (90−θ) of the via hole V is greater at a point where the distance from the edge of the wafer W is shorter; namely, a point toward the outer edge portion WE of the wafer W. That is, the inclination angle (90−θ) of the via hole V increases as the via hole V comes closer to the edge of thebrim part51bof theupper ring member51.
• In comparing the case where L=1.0 mm with the case where L=1.7 mm, when the distance from the outer edge of the wafer W is the same, the inclination angle (90−θ) is smaller when L=1.0 mm. That is, the inclination angle (90−θ) of the via hole V with respect to the vertical direction becomes smaller as the value of the predetermined width L becomes smaller. In other words, based on the above formula (2), this means that the inclination angle (90−θ) of the via hole V with respect to the vertical direction becomes smaller as the inner diameter DI of thebrim part51bof theupper ring member51 becomes larger.
• Assuming the positioning accuracy of the relative position of the wafer W with respect to theupper ring member51 is denoted as ±a0, the positioning accuracy of the wafer W attributed to the transfer system for transferring the wafer W such as the transfer robot and thelift pin61 is denoted as ±a1, and the positioning accuracy of thebevel cover ring5 attributed to the shape accuracy of thelift pin53 or thebevel cover ring5 is denoted as ±a2, the relationship between a0, a1, and a2 may be expressed by the following formula (4).
• 
  a0=a1+a2  (4)
• That is, the absolute value a0 of the positioning accuracy of the relative position of the wafer W with respect to theupper ring member51 ±a0 is equal to the sum of the absolute value a1 of the positioning accuracy of the wafer W and the absolute value a2 of the positioning accuracy of thebevel cover ring5.
• The predetermined width L is preferably designed to be a suitable value such that the actual width of the covered region of the wafer W would not be less than the predetermined width L1 even when the actual width varies from the designed value due to the positioning accuracy (±a0). If the predetermined width L is smaller than the predetermined width L1, the region of the outer edge portion WE of the wafer W that has the resist removed and the substrate surface of the wafer W exposed would come into contact with plasma. Accordingly, when the predetermined width L subject to variations attributed to the positioning accuracy has a range of (L±a0), the minimum value (L−a0) of the predetermined width L may be set equal to the predetermined width L1, for example. In this way, the outer edge portion WE of the wafer W may be protected from surface roughening while minimizing the inclination angle (90−θ) with respect to the vertical direction of a via hole V formed near the outer edge portion WE of the wafer W.
• FIG. 7 illustrates an exemplary case where the predetermined width L1 is set equal to the minimum value (L−a0) of the predetermined width L subject to variations attributed to the positioning accuracy (±a0).
• In another example, the minimum value (L−a0) of the predetermined width L subject to variations attributed to positioning accuracy (±a0) may be set equal to the sum of the predetermined width L1 plus a margin α (L1+α). In this case, the relationship between L and L1 may be expressed by the following formula (5).
• 
  L=L1+(a0+α)  (5)
• That is, the predetermined width L may be set equal to the sum of the predetermined width L1 and a predetermined width (a0+α) that depends on the positioning accuracy a0 of the relative position of the wafer W with respect to theupper ring member51. Based on the above formulas (2) and (5), the relationship between DI and DO preferably satisfies the following formula (6).
• 
  DI=DO−2(L1+a0+α)  (6)
• That is, the inner diameter DI of thebrim part51bof theupper ring member51 is preferably determined based on the outer diameter DO of the wafer W, the predetermined width L1, and the predetermined width (a0+α) that depends on the positioning accuracy a0. In this way, the outer edge portion WE of the wafer W may be protected from surface roughening while minimizing the inclination angle (90−θ) with respect to the vertical direction of a via hole V formed near the outer edge portion WE. Note that the predetermined width (a0+α) is an example of a second predetermined width that depends on the positioning accuracy of the relative position of the substrate with respect to the cover member.
• FIG. 16 is a table indicating measurement results of the angle θ with respect to the horizontal direction of via holes V formed at different distances from the center of the wafer W for three different examples; namely, a first example where L=1.7 mm (DI=296.6) and theupper ring member51 is made of quartz, a second example where L=1.7 mm (DI=296.6) and theupper ring member51 is made of yttria (Y₂O₃), and a third example where L=1.0 mm (DI=298) and theupper ring member51 is made of yttria (Y₂O₃).
• Comparing the measurement results of the first and second examples ofFIG. 16, in the case where theupper ring member51 is made of yttrium (Y₂O₃) and has the same inner diameter (DI=296.6) as that of theupper ring member51 made of quartz, the measurement results of the angle θ are substantially the same as the case where theupper ring member51 is made of quartz. That is, the angle θ is substantially close to 90 degrees in both cases. Considering the superior plasma resistance characteristics of yttria compared to quartz, yttria may preferably be used as the material for theupper ring member51 so that the life of theupper ring member51 may be prolonged in addition to providing protection of the outer edge portion WE of the wafer W.
• Next, comparing the measurement results of the second and third examples ofFIG. 16, in the case where theupper ring member51 is made of yttria (Y₂O₃) and the inner diameter of theupper ring member51 is varied (DI=296.6 or DI=298), the angle θ may be closer to 90 degrees when the inner diameter DI of theupper ring member51 is greater. That is, the greater the inner diameter DI of theupper ring member51, the smaller the inclination angle of the via hole V with respect to the vertical direction.
• According to another aspect of the present embodiment, when ashing the resist remaining on the etched wafer W, the ashing rate at the outer edge portion WE of the wafer W may be prevented from decreasing. In the following, such as aspect of the present embodiment is described.
• FIG. 11 is a graph indicating measurement results of resist ashing rates measured at various distances from the outer edge of the wafer W in Example 1 and Example 2 that perform ashing processes under different ashing conditions. The ashing conditions used in Example 1 and Example 2 are as follows:
Example 1
• Pressure within film formation apparatus:
• • 300 mTorr
• High frequency power supply power
• (upper electrode/lower electrode):
• • 0/1500 W
• Processing gas flow rate:
• • O₂=300 sccm
• Processing time:
• • 30 seconds
Example 2
• Pressure within film formation apparatus:
• • 100 mTorr
• High frequency power supply power
• (upper electrode/lower electrode):
• • 0/2000 W
• Processing gas flow rate:
• • O₂=1300 sccm
• Processing time:
• • 30 seconds
• As illustrated inFIG. 11, the ashing rate tends to decrease as the distance from the outer edge of the wafer W becomes smaller; namely, as the ashing position comes closer to the outer edge of the wafer W. This indicates that while plasma may be prevented from coming around the outer edge portion WE of the wafer W by arranging theupper ring member51, such an arrangement may cause the ashing rate to decrease near theupper ring member51. In Example 1, the ratio of the ashing rate at a position 0.3 mm from the wafer edge with respect to the ashing rate at aposition 3 mm from the wafer edge is approximately 10%.
• In Example 2, the overall ashing rate is increased compared to Example 1. Also, the ratio of the ashing rate at a position 0.3 mm from the wafer edge with respect to the ashing rate at aposition 3 mm from the wafer edge is increased to approximately 50%. As can be appreciated, by optimizing the processing conditions of the ashing process, a decrease in the ashing rate at the outer edge portion WE of the wafer W that is covered by theupper ring member51 may be suppressed.
• FIG. 12 is a graph indicating measurement results of resist film thicknesses before and after ashing measured at various distances from the outer edge of the wafer W in cases where the inner diameter DI of theupper ring member51 is 296.6 mm and 298 mm (DI=296.6 mm and DI=298 mm). Note that in the example illustrated inFIG. 12, the resist film thickness before ashing is assumed to be the same regardless of the value of the inner diameter DI of theupper ring member51.
• At a position 0.5 mm from the edge of the wafer W, the resist film thickness after ashing in the case where DI=298 mm is less than the resist film thickness after ashing in the case where DI=296.6 mm. That is, by increasing the inner diameter DI of theupper ring member51, a decrease in the ashing rate at the outer edge portion WE of the wafer W that is covered by theupper ring member51 may be suppressed.
Second Embodiment
• In the following, a plasma etching method according to a second embodiment of the present invention is described.
• The plasma etching method according to the second embodiment may be implemented using a plasma etching apparatus similar to the plasma etching apparatus used in the first embodiment. Accordingly, descriptions of the plasma etching apparatus used in the second embodiment are omitted.
• The plasma etching method according to the present embodiment is for forming a via hole through a wafer using the so-called TSV (Through-Silicon Via) technology to form a via electrode within a three-dimensionally stacked semiconductor device. That is, the plasma etching method according to the present embodiment differs from that of the first embodiment in that it involves etching a bonded wafer that includes a wafer on which a via hole is formed (also referred to as “device wafer”) and a support wafer to which the device wafer is bonded via an adhesive.
• FIG. 13 is a schematic cross-sectional view illustrating an exemplary configuration of a bonded wafer LW.
• The bonded wafer LW includes a device wafer W and a support wafer SW. The device wafer W is a substrate having a semiconductor device such as a transistor formed on its surface Wa. The support wafer SW is a support substrate for reinforcing the device wafer W when the device wafer W is thinned by a grinding process that is performed on its rear surface Wb. The device wafer W is bonded to the support wafer SW via an adhesive G.
• FIGS. 14A-15C are schematic cross-sectional views illustrating states of the wafer W at various process steps of a semiconductor device manufacturing method including the plasma etching method of the present embodiment.
• First, atransistor101 is formed on the surface of the device wafer W, which may be a silicon wafer, for example. Then, aninterlayer insulating film102 is formed on the device W having thetransistor101 formed thereon (seeFIG. 14A).
• Next, awiring structure103 is formed on theinterlayer insulating film102. Thewiring structure103 is formed on theinterlayer insulating film102 by alternately layering awiring layer104 and an insulatingfilm105 and forming a viahole106, which penetrates through the insulatingfilm105 and establishes electrical connection between the wiring layers104 arranged above and below the insulating film105 (seeFIG. 14B).
• Next, the device wafer W is turned upside down and is bonded to the support wafer SW via an adhesive G to prepare the bonded wafer LW. The support wafer SW may be a silicon wafer, for example. The support wafer SW acts as a support substrate that reinforces the device wafer W and prevents the device wafer W from warping when the device wafer W is reduced in thickness by a grinding process that is performed on its rear surface Wb. The bonded wafer LW is placed on a support member of a grinding apparatus, for example, and the rear surface Wb of the device wafer W is subject to a grinding process so that the device wafer W may be thinned from a thickness T1 before grinding to a predetermined thickness T2 after grinding (seeFIG. 14C). The predetermined thickness T2 may be 50-200 μm, for example.
• Note that inFIGS. 14A-150, theinterlayer insulating film102 and thewiring structure103 are not drawn to scale. That is, for purposes of illustration, the thicknesses of theinterlayer insulating film102 and thewiring structure103 are magnified. However, in actual applications, theinterlayer insulating film102 and thewiring structure103 are much thinner than the device wafer W itself.
• Also, the adhesive G is exposed at the outer edge portion WE of the bonded wafer LW (seeFIG. 13).
• Next, a resist is applied on the rear surface Wb of the device wafer W after which the resist is exposed and developed into a resist pattern (not shown). Then, the bonded wafer LW with the device wafer W having the resist pattern formed on its rear surface Wb is subject to an etching process that is similar to that implemented in the plasma etching method according to the first embodiment to form a via hole V. Then, an asking process similar to that implemented in the plasma etching method of the first embodiment is performed to remove the resist remaining on the rear surface Wb of the bonded wafer LW having the via hole V formed thereon (seeFIG. 15A). The diameter of the via hole V may be 1-10 μm, for example. Also, the depth of the via hole V corresponds to the thickness of the thinned device wafer W after its rear surface Wb has undergone the grinding process. As described above, the thickness of the thinned device wafer W may be 50-200 μm, for example.
• Next, an insulatingfilm107 made of polyimide, for example, is arranged to cover the inner peripheral face of the via hole V, and a viaelectrode108 is formed within the via hole V having its inner peripheral face covered by the insulatingfilm107 through an electrolytic plating process, for example (seeFIG. 15B).
• Next, the support wafer SW is separated from the device wafer W, so that the device wafer W that is thinned and has the viaelectrode108 formed therein may be obtained. For example, the support wafer SW may be separated from the device wafer W by irradiating ultraviolet (UV) light and weakening the adhesion of the adhesive G (seeFIG. 15C).
• As with the first embodiment, in the present embodiment, a region of the outer edge portion WE of the bonded wafer LW extending over a predetermined width from the outer edge of the bonded wafer LW is covered by theupper ring member51. As a result, when the bonded wafer LW is subject to the etching process, plasma may be prevented from coming around the outer edge portion WE of the bonded wafer LW. Thus, the substrate surface of the device wafer W that is exposed at a region of the outer edge portion WE of the bonded wafer LW extending over a predetermined width from the edge of the device wafer W may be prevented from coming into contact with plasma. In this way, surface roughening of the substrate surface of the device wafer W at the outer edge portion WE of the bonded wafer LW may be prevented.
• Also, in the present embodiment, the adhesive G is exposed at the outer edge portion WE of the bonded wafer LW between the device wafer W and the support wafer SW. Accordingly, the adhesive G exposed at the outer edge portion WE of the bonded wafer LW may be prevented from coming into contact with plasma. In this way, the adhesive G may be prevented from coming off to generate dust, and the device wafer W and the support wafer SW may be prevented from separating. Further, the outer edge portion WE of the bonded wafer LW may be prevented from becoming brittle and cracking. In other words, the outer edge portion WE of the bonded wafer LW may be protected.
• Although certain preferred embodiments of the present invention are described above with reference to the accompanying drawings, the present invention is not limited to these embodiments. That is, additional advantages and modifications will readily occur to those skilled in the art in light of the above disclosures. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
• The present application is based on and claims the benefit of priority of Japanese Patent Application No. 2011-73191 filed on Mar. 29, 2011, the entire contents of which are herein incorporated by reference.
DESCRIPTION OF THE REFERENCE NUMERALS
• 1processing chamber1
• 2 stage
• 4 support
• 5 bevel cover ring
• 6 electrostatic chuck
• 16 shower head
• 51 upper ring member
• 52 lower ring member
• 90 control unit

Claims (8)

1. A plasma etching apparatus that performs plasma etching on a substrate having a surface portion on which a resist pattern is formed and an outer edge portion where a substrate surface of the substrate is exposed, the plasma etching apparatus comprising:

a support part that supports the substrate;

a cover member that covers the outer edge portion of the substrate that is supported by the support part, the cover member being configured to prevent plasma from coming around the outer edge portion of the substrate; and

a control unit that generates plasma by controlling application of a first high frequency power from a first high frequency power supply and supply of a processing gas for etching from a first processing gas supply source, and uses the generated plasma to etch the substrate that is supported by the support part and has the outer edge portion covered by the cover member, wherein after etching the substrate, the control unit generates plasma by controlling application of a second high frequency power from a second high frequency power supply and supply of a processing gas for ashing from a second processing gas supply source, and uses the generated plasma to perform ashing on the resist pattern on the etched substrate.

2. The plasma etching apparatus as claimed inclaim 1, wherein

the substrate subject to the plasma etching is a bonded substrate, which includes a first substrate and a second substrate that are bonded together via an adhesive, the bonded substrate having the surface portion on which the resist pattern is formed and the outer edge portion where the adhesive is exposed.

3. The plasma etching apparatus as claimed inclaim 1, wherein

the substrate has a circular plate form and the substrate surface of the substrate is exposed at a region extending over a first predetermined width from an outer edge of the substrate; and

the cover member has a ring-shaped form, and an inner diameter of the cover member is determined based on an outer diameter of the substrate and the first predetermined width.

4. The plasma etching apparatus as claimed inclaims 3, wherein

the inner diameter of the cover member is determined based on the outer diameter of the substrate, the first predetermined width, and a second predetermined width that depends on a positioning accuracy of a relative position of the substrate with respect to the cover member.

5. A plasma etching method for performing plasma etching on a substrate having a surface portion on which a resist pattern is formed and an outer edge portion where a substrate surface of the substrate is exposed, the plasma etching method comprising the steps of:

supporting the substrate by a support part;

arranging a cover member to cover the outer edge portion of the substrate that is supported by the support part, the cover member being configured to prevent plasma from coming around the outer edge portion of the substrate;

generating plasma by controlling application of a first high frequency power from a first high frequency power supply and controlling supply of a processing gas for etching from a first processing gas supply source, and using the generated plasma to etch the substrate that is supported by the support part and has the outer edge portion covered by the cover member; and

after etching the substrate, generating plasma by controlling application of a second high frequency power from a second high frequency power supply and controlling supply of a processing gas for ashing from a second processing gas supply source, and using the generated plasma to perform ashing on the resist pattern on the etched substrate.

6. The plasma etching method as claimed inclaim 5, wherein

the substrate subject to the plasma etching is a bonded substrate, which includes a first substrate and a second substrate that are bonded together via an adhesive, the bonded substrate having the surface portion on which the resist pattern is formed and the outer edge portion where the adhesive is exposed.

7. The plasma etching method as claimed inclaim 5, wherein

the substrate has a circular plate form, and the substrate surface of the substrate is exposed at a region extending over a first predetermined width from an outer edge of the substrate; and

the cover member has a ring-shaped form, and an inner diameter of the cover member is determined based on an outer diameter of the substrate and the first predetermined width.

8. The plasma etching method as claimed inclaims 7, wherein

the inner diameter of the cover member is determined based on the outer diameter of the substrate, the first predetermined width, and a second predetermined width that depends on a positioning accuracy of a relative position of the substrate with respect to the cover member.

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