US20130329555A1 - Dual counter - Google Patents

Abstract

An integrated circuit device for receiving packets. The integrated circuit device includes a first counter for counting a number of the packets, and a second counter for counting bytes of the packets. The first counter and the second counter are configured to be incremented by a single command from a packet processor.

Description

CROSS-REFERENCE TO RELATED U.S. APPLICATIONS
• This application claims priority to and benefit of co-pending U.S. Patent Application No. 61/656,377, filed on Jun. 6, 2012, entitled, “MEMORY DEVICE WITH AN EMBEDDED LOGIC UNIT,” by Tang et al., having Attorney Docket No. MP-1234.PRO, and assigned to the assignee of the present application.
• This Application is related to U.S. patent application Ser. No. ______, filed on ______, entitled “HIGH UTILIZATION MULTI-PARTITIONED MEMORY WITH WRITE CACHE, BIST, AND STATISTICS FUNCTIONS,” by Miller et al., having Attorney Docket No. MP-1237, and assigned to the assignee of the present application.
BACKGROUND
• In modern communication networks data is transferred using a formatted unit of data referred to as a packet. When data is formatted into packets, the bitrate of the communication medium is better shared among users than if the network were circuit switched. Packet processors have specific features or architectures that are provided to enhance and optimize packet processing within these networks.
DISCLOSURE
• A memory device with an embedded logic unit is disclosed. In particular, a packet processing acceleration device, also referred to as a bandwidth engine that integrates high density memory, a high speed interface, and an arithmetic logic unit is disclosed. The bandwidth engine receives signals external to the bandwidth engine including one or more instructions. The bandwidth engine also comprises a programmable instruction memory, a programmable configuration memory, and in some embodiments a plurality of counters. Additionally, embodiments in accordance with the present invention can be described as follows:
BRIEF DESCRIPTION OF THE DRAWINGS
• The accompanying drawings, which are incorporated in and form a part of this application, illustrate embodiments of the present invention, and together with the description, serve to explain the principles of the invention. Unless noted, the drawings referred to in this description should be understood as not being drawn to scale. It should be noted that a break in a line in the drawings referred to in this description signifies that a line and the perpendicular line(s) crossing it do not connect.
• FIG. 1 is a diagram of an example of a memory system including a bandwidth engine, in accordance with various embodiments.
• FIG. 2 is a diagram of an example packet processor coupled to a plurality of bandwidth engines, in accordance with various embodiments.
• FIG. 3 is a block diagram of an example metering logic unit, in accordance with various embodiments.
• FIG. 4 is a block diagram of an example traffic conditioner, in accordance with various embodiments.
• FIG. 5 is a block diagram of an example bandwidth engine, in accordance with various embodiments.
• FIG. 6 is a block diagram of an example bandwidth engine, in accordance with various embodiments.
• FIG. 7 is a diagram of an example programmable partitionable counter, according to various embodiments.
• FIG. 8 is a block diagram of an example bandwidth engine, in accordance with various embodiments.
• FIG. 9 illustrates a flow diagram of an example method of partitioning and incrementing a counter in a memory, in accordance with various embodiments.
• FIG. 10 is a block diagram of a system used in accordance one embodiment.
DESCRIPTION OF EMBODIMENTS
• Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. While the subject matter will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the subject matter to these embodiments. Furthermore, in the following description, numerous specific details are set forth in order to provide a thorough understanding of the subject matter. In other instances, conventional methods, procedures, objects, and circuits have not been described in detail as not to unnecessarily obscure aspects of the subject matter.
NOTATION AND NOMENCLATURE
• Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present Description of Embodiments, discussions utilizing terms such as “programming,” “partitioning,” “receiving,” “performing,” “adding,” “merging,” “correcting,” “writing,” or the like, refer to the actions and processes of a computer system or similar electronic computing device (or portion thereof) such as, but not limited to: an electronic control module, field programmable gate array (FPGA), application-specific integrated circuit (ASIC), and/or a management system (or portion thereof). The electronic computing device manipulates and transforms data represented as physical (electronic) quantities within the electronic computing device's processors, registers, and/or memories into other data similarly represented as physical quantities within the electronic computing device's memories, registers and/or other such information storage, processing, transmission, or/or display components of the electronic computing device or other electronic computing device(s).
Overview of Discussion
• Example techniques, devices, systems, and methods for a memory system comprising a memory with an embedded logic unit are described herein. Discussion begins with a high level description of a memory system comprising a memory with an embedded logic unit, also known as a “bandwidth engine.” Example methods of governing network traffic are then described, including metering, policing and shaping. Discussion continues with a description of the memory system performing a plurality of operations in response to a single command. A memory system that comprises a programmable partitionable counter is then described. Next, an example method of use is described. Lastly, an example computer environment is described.
Bandwidth Engine Overview
• FIG. 1 shows a block diagram of amemory system100 in accordance with one embodiment of the present invention.Memory system100 comprisesbandwidth engine105 and is located on an integrated circuit chip.Bandwidth engine105 comprisesmemory core110 andlogic unit120.Bandwidth engine105 may be used for data that is accessed often.
• In various embodiments,bandwidth engine105 is configured to receive packets from a second apparatus via a communication path. In some embodiments, the second apparatus ispacket processor150.Packet processor150 may be any type of processor including, but not limited to: a central processing unit, a microprocessor, a graphics processing unit, a physics processing unit, a digital signal processor, a network processor, a front end processor, a coprocessor, a data processor, an audio processor, a multi core processor, an ASIC, a system-on-chip (SoC), a structured ASIC, an FPGA, etc.
• Packet processor150 is capable of performing commands on external memory. As an example,packet processor150 may fetch data from a memory block, perform a command using the data received from the memory block, write back to the memory block, and then send a command which updates the memory block's internal counters.
• Bandwidth engine105 contains an internal arithmetic logic unit (ALU or logic unit)120 such that whenpacket processor150 attempts to perform an operation using data located inmemory core110, rather than sending the data directly frommemory core110 topacket processor150 to perform a command,logic unit120 can perform a command, update the internal counter ofmemory core110, send data tomemory core110, and/or send data to packetprocessor150. In some embodiments,memory core110 may be partitioned memory.Logic unit120 can access, modify and retire networking operations wholly withinbandwidth engine105.Logic unit120 supports statistics, counters and other applications, and reduces the latency and bandwidth requirements for macro operations.
• Latency is reduced withbandwidth engine105 since apacket processor150 does not need to send and receive as much data because of embeddedlogic unit120 ofbandwidth engine105. Additionally, more bandwidth is available becausebandwidth engine105 does more work locally. In some embodiments, a plurality of commands may be performed withinbandwidth engine105 afterbandwidth engine105 receives a single command frompacket processor150. As a result, the amount of packet processing operations bypacket processor150 is reduced. In particular,packet processor150 is not required to perform identical processing commands because it offloads some processing tobandwidth engine105.
• In various embodiments,memory core110 may be serial or parallel accessed. In some embodiments,memory core110 may comprise memory construction including, but not limited to: SRAM, DRAM, embedded DRAM, 1T-SRAM, Quad Data Rate SRAM, RLDRAM, or Flash as examples. Also, in someembodiments packet processor150 may be coupled to a plurality ofmemory systems100, as shown inFIG. 2.FIG. 2 shows a packet processor coupled tobandwidth engines150A,105B,105C . . .105n,105n+1 and105n+2.
• In some embodiments,bandwidth engine105 uses a serial interface using an open industry available serial protocol, which is optimized for chip-to-chip communications.Bandwidth engine105 also provides an interface for serializer/deserializer (SerDes) technology (i.e., functional blocks that convert data between serial data and parallel data interfaces in each direction).
• Bandwidth engine105 includestimer140 that sends a signal intologic unit120 andmetering logic unit160.Bandwidth engine105 can include a plurality oftimers140.Timers140 can determine the amount of time that has passed since a particular event. For example,timers140 may determine the amount of time that has passed since a record or information about a user/account was accessed.
• Bandwidth engine105 includes lookup table130. In one embodiment, as traffic passes throughlogic unit120 lookup table130 provideslogic unit120 and/ormetering logic unit160 with actions that should be performed on the traffic. In one embodiment, when eitherlogic unit120 ormetering logic unit160 receives a packet, lookup table130 may look up whether a bucket contains sufficient tokens and whether that traffic may be passed. The bandwidth engine then returns a metering result (e.g., whether that traffic may be passed) to the host ASIC/packet processor150. In some embodiments, the lookup table130 may be configured to carry out a plurality of procedures.
• Metering logic unit160, in some embodiments, runs in parallel withlogic unit120 and, as discussed below, meters and marks traffic to ensure compliance with a traffic contract. Note that in some embodiments,bandwidth engine105 does not comprise ametering logic unit160. In some embodiments, thelogic unit120 performs operations related to metering traffic, marking traffic, and sending signals topacket processor150 ortraffic conditioner170.
• Packet processor150 includestraffic conditioner170 that, as discussed below, shapes and drops packets in response to signals/recommendations received bymetering logic unit160 orlogic unit120. In some embodiments,packet processor150 may disregard incoming data frombandwidth engine105 that recommends whetherpacket processor150 should send, delay or drop a packet.
Metering, Policing, and Shaping
• Embodiments of the present invention provide for metering data packets. Metering is the process of governing network traffic for compliance with a traffic contract and taking steps to enforce that contract.
• A traffic contract is similar to a service level agreement with a broadband network. In various embodiments, networks employ an asynchronous transfer mode (ATM). When a service or application wishes to use a broadband network to transport traffic, it must first inform the network about what kind of traffic is to be transported, and in some cases the performance requirements of the traffic. In some networks, regardless of the traffic contract, if bandwidth is available packets may be sent. In some networks, the time of day or the network congestion may be used to determine whether packets may be sent. In other words, the decision to send a packet may be based on the time of day or the congestion on a given network. A network may require an application wishing to send traffic over the network to indicate the type of service required, traffic parameters of the data flow in each direction, and/or the quality of service parameters requested in each direction. Services include, but are not limited to: the constant bit rate, the real-time variable bit rate, the non-real-time variable bit rate, the applicable bit rate and the unspecified bit rate.
• When metering traffic, traffic that is in violation of a traffic contract may be dropped, marked as non-compliant, or left as-is depending on the policies of a network. Policing refers to dropping or disregarding traffic. “Coloring” refers to marking traffic as compliant, semi-compliant, or in violation/non-compliant. Also, shaping refers to rate limiting, or delaying traffic to bring packets into compliance with a traffic policy.
• FIG. 3 shows ametering logic unit160.
• Metering logic unit160 comprises ameter310 to determine whether the incoming traffic flow complies with a traffic contract.Meter310 may determine whether a packet is compliant, semi-compliant, or in violation of a contract. As discussed above, in some embodiments there is nometering logic unit160, in whichcase logic unit120 performs the operations described herein as being performed bymetering logic unit160. In one embodiment,meter310 determines the status of a packet based on its “color.” It should be understood by those skilled in the art that a color comprises at least one bit comprising a particular value. As an example, a packet may be marked as green, yellow or red. Green typically indicates that a packet is compliant. In one embodiment, green may indicate that a packet does not exceed a committed burst size. Yellow typically indicates that a packet is not compliant, but is not in violation of the traffic contract. In one embodiment, yellow indicates that a packet exceeds the committed burst size, but does not exceed an excess burst size. Red typically indicates that the packet is in violation of the traffic contract.
• In some embodiments,metering logic unit160 further comprisesmarker320 that can mark, or re-mark, a packet based on information provided by themeter310. In some embodiments, themarker320 changes the color of a packet from one color to a different color.
• In some embodiments,packet processor150 comprisestraffic conditioner170 that comprises a shaper/dropper410 as shown inFIG. 4. Shaper/dropper410 ensures the traffic sent bypacket processor150 complies with the traffic contract. In some cases, compliance may be enforced by policing (dropping packets). In some embodiments, a token bucket is used. In some embodiments, metered packets are stored in a FIFO buffer/queue until they can be transmitted in compliance with the traffic contract. It should be understood that policing and shaping may occur concurrently. Also, as discussed above, in some embodiments afterpacket processor150/traffic conditioner170 receives a recommendation regarding whether to send, delay, or drop a packet,packet processor150/traffic conditioner170 may disregard the recommendation and either send, delay or drop a packet regardless of the data sent bymetering logic unit160 orlogic unit120.
• In some embodiments, metering is performed using at least one token bucket. Whenmetering logic unit160 is determining whether a packet is in compliance with a traffic contract, it will determine whether a bucket contains sufficient tokens to send the packet. Bucket tokens may be credited or debited. If a bucket contains a sufficient number of tokens such that a packet is in compliance, the appropriate number of tokens (which may be equivalent to the length of a packet in bytes) are removed, or debited/charged, from the token bucket and the packet is sent. In one embodiment, the packet is colored based on whether sufficient tokens are available. In another embodiment, if there are insufficient tokens in a bucket or buckets (e.g., main bucket, sister bucket, etc.) the packet is not in compliance and the contents of the bucket are not charged. Non-compliant packets may be dropped, queued for subsequent transmission when sufficient tokens have accumulated in a bucket, or transmitted after it is marked as in violation/non-compliant. If a packet is marked as in violation, it may be dropped if the network is subsequently overloaded. It should be understood that a leaky bucket may be employed in some embodiments. In general, a leaky bucket is used to check that data transmissions, in the form of packets, conform to defined limits on bandwidth and burstiness (a measure of the unevenness or variations in the traffic flow).
• FIG. 5 shows abandwidth engine105, in accordance with one embodiment.Bandwidth engine105 may comprise awrite buffer510 coupled tomemory core110 and bypass block520. Thewrite buffer510 comprises data to be written to the memory. If an address (sometimes referred to as a user identification (UID)) is received bymemory core110 whilewrite buffer510 has data waiting to be written to the same address/UID, the write buffer sends the data waiting to be written to the bypass block520.
Performing a Plurality of Operations in Response to a Single Command
• FIGS. 6 and 8 depict embodiments of a bandwidth engine. In some embodiments, when a packet is receivedmemory core110, statistics are updated. Statistics may comprise a number of bytes received and/or a number of packets received. A packet, received atpacket processor150, may contain statistics such as, but not limited to, a size, an address (or user identification), and a command. When a packet is received atpack processor150, a command is sent tobandwidth engine105 which contains a counter address and byte count value. Thebandwidth engine105 reads from thememory core110 the contents of the counters (e.g., byte and packet) at the address. The counters are then incremented accordingly. For example, packet counter is incremented by 1 and byte counter is incremented by the number of bytes of the packet.
• Apacket counter610B comprises the number of packets received by amemory core110. Abyte counter610A comprises the number of bytes received by amemory core110. In one embodiment, packet counters are comprised of life time counters, which store enough data such that the counter will continue to operate for the lifetime of the chip (e.g., 64b, 128b, etc.). In other words, a lifetime counter will not overflow during the lifetime of the system in which it is embedded. In some embodiments, counters smaller than lifetime counters include, but are not limited to: 32 bits, 64 bits, etc. For example,counter610B may be designed to be reset monthly, yearly, etc. In some embodiments, a counter (byte counter610A,packet counter610B or both) is unique to a user, an account, a group of users, etc.
• A packet received bypacket processor150 may be any size, for example the packets may be variable sizes. The commands send to the bandwidth engine, from the packet processor, may comprise 72 bits, wherein the command comprises 64 bits of data and 8 bits of error correcting code. In one embodiment, at least one error correcting code module (e.g., error correctingcode module650 and error correcting code module651) is comprised inmemory core110. Also, counters610 are embedded in a memory chip. In one embodiment, counters610 are remote from a memory chip.
• In various embodiments, statistics (e.g., the value of packet counters610B) are sent back topacket processor150 every time they change. Statistics may be sent topacket processor150 at predetermined intervals (e.g., every n times, once a day, once a month, etc.). In one embodiment, statistics are not sent topacket processor150.
• In various embodiments, aftermemory core110 receives a packet with one command, a plurality of functions are performed bylogic unit120. This is sometimes referred to as a dual operations or dual updating. For example, if one piece of information is received such as packet size, then thebyte counter610A and thepacket counter610B may be changed. In other words, the packet counter6108 is changed based on the receipt of a packet size which is used in updatingbyte counter610A. It should be noted that in some embodiments bytecounter610A and packet counter6108 may refer tobyte counter partition710 andpacket counter partition720 respectively (both ofFIG. 7).
• As an example, when the command PDADD (Paired Double Word Add) is received as a command, the statistics are modified. For example, the operations P_COUNT=P_COUNT+1 and BYTE_COUNT=BYTE_COUNT+PACKET_SIZE are performed bylogic unit120 when a packet is received bymemory core110. Note that the size of a word can be any size including, but not limited to: 64 bits, 128 bits, etc.
• Incrementer630 may increment thepacket counter610B. It should be understood thatincrementer630 is a characterization of an action performed bylogic unit120. In one embodiment,incrementer630 increments the packet counter by one bit. In various embodiments,incrementer630 increments the packet counter by: a static number of bits greater than one, a programmable number of bits greater than one, a number of bits based on other parameters or statistics including packet size, or a negative number of bits. In one embodiment, counters may be incremented once every memory clock cycle. Counters may be incremented every system clock cycle. Counters may be incremented sequentially or simultaneously.
• In various embodiments, to increment two lifetime counters (e.g., byte and packet) two reads and two writes are performed on 72b words (e.g., 64b+8b ECC) for a total of four commands and 4×72b data transferred between the processor and bandwidth engine. In particular, this method transfers a single 72b command from the processor to the bandwidth engine. This can improve bandwidth by as much as 5 times, as compared to conventional systems. It is noted that memory bandwidth bottleneck between processors and memory may be limiting of producing 400 Gps and 1Tbps network packet processors. Also, statistics can be as much as 25 to 30% of the chip memory bandwidth.
Programmable Partitionable Counter
• Counters (e.g.,byte counter610A andpacket counter610B) may be partitioned. In other words it may be split into multiple partitions once, twice, three times, four times, or more. For example,counter610C may be split into abyte counter partition710 and apacket counter partition720.FIG. 7 shows a programmablepartitionable counter610C comprising 64 bits. A user may program a partition toseparate counter610C intobyte counter partition710 andpacket counter partition720 at any position he or she chooses. For example, a user may want to partition the programmablepartitionable counter610C such that thepacket counter partition720 comprises 16 bits while the byte counter partition comprises 48 bits.FIG. 7 shows dashed lines indicating example partitions that occur betweenbits15 and16,31 and32, and47 and48. It should be noted that a partition may be smaller than 16 bits.
• In one embodiment, the type of account or network contract a user has determines the size and number of partitions comprised in programmablepartitionable counter610C. Partitions may be any size, and may be variable. In some embodiments, programmablepartitionable counter610C may be programmed to split into partitions as small as 1 bit. The counters may be a fixed size so the size of a partition value will not be small, such as ATM, packets.
• Programmablepartitionable counter610C may be programmed with four partitions of size s (e.g., s0, s1, s2 and s3) prior to system operation or implementation. In some embodiments, the s value is not stored inbandwidth engine105, and instead stored in slower memory. In one embodiment, each user/account comprises only one associated s value. An s value is associated with a system as opposed to a user/account. Programming entry commands e (e.g., e0, e1, e2 and e3) correspond with the s sizes. In some embodiments, an entry (e) may be used for a particular user/account that corresponds to an s value. In one example, if an e value is entered that corresponds to an s value of −16 in a 64 bit counter, thepacket counter partition710 will comprise (32+(−16)) bits, while thebyte counter partition720 will comprise (32+(16)) bits. Note that programmablepartitionable counter610C may be partitioned into partitions as small as one bit (e.g.,packet counter partition720 may comprise 4 bits, whilebyte counter partition710 comprises 60 bits). It should be understood, that in one embodiment, the sum of the bits in the partitions is 64. That is, for example, one partition includes 12 bits and another partition includes 52 bits for a total of 64 bits. Accordingly, the partitions can slide back forth to any desired granularity or setting. In one embodiment, one account/user may have a different s than another account/user. In other embodiments, an entry may be for multiple users or partitions. Multiple users may be grouped together based on the tasks they perform.
• A counter may saturate when it reaches its maximum value. When a counter reaches its maximum value, in one embodiment, a user/account may receive a message indicating that the counter610 is saturated and thememory core110 cannot receive additional packets. The user/account may receive a message indicating that if additional money is paid,memory core110 will continue to function. In one embodiment, after a counter reaches its maximum value it returns to zero.
• In an embodiment, an address (sometimes referred to as a user identification (UID)) for a user/account is received somemory core110 finds the location in the memory of thepacket counter610B and thebyte counter610A. By using an offset thememory core110 may find additional information associated with a user/account. For instance while an address may point to one location in thememory core110, the address in addition to the offset will point to another location in thememory core110 where additional information is stored (e.g., information related to metering).
• In one embodiment, the programmablepartitionable counter610C may consolidate four operations into one because operations are often paired, or in other words they are often performed at the same time. In an embodiment, the byte count is read, then the byte count is written, and the packet count may be read, and then the packet count is written. In one embodiment, an address comes in for a record, or a paired counter. In an embodiment, an address comes in, and a double word which is 144 bits is modified based on the address and the offset and stored inmemory core110.
• In various embodiments, after data is sent to thelogic unit120 and before the resulting data is sent back to an address inmemory core110, another command is received bymemory core110 attempting to access the data at the address where the resulting data is intended to be written. At that point, the data at that address inmemory core110 is considered to be stale.
Example Methods of Operation
• With reference toFIG. 9, flow diagram900 illustrates example procedures used by various embodiments. Flow diagram900 includes processes and operations that, in various embodiments, are carried out by one or more of the devices illustrated inFIGS. 1-8 or viacomputer system1000 or components thereof.
• Although specific procedures are disclosed in flow diagram900, such procedures are examples. That is, embodiments are well suited to performing various other operations or variations of the operations recited in the processes of flow diagram900. Likewise, in some embodiments, the operations in flow diagram900 may be performed in an order different than presented, not all of the operations described in one or more of these flow diagrams may be performed, and/or one or more additional operation may be added.
• The following discussion sets forth in detail the operation of some example methods of operation of embodiments. With reference toFIG. 9, flow diagram900 illustrates example procedures used by various embodiments. Flow diagram900 includes some procedures that, in various embodiments, are carried out by a processor under the control of computer-readable and computer-executable instructions. In this fashion, procedures described herein and in conjunction with flow diagram900 are or may be implemented using a computer (e.g., computer system1000), in various embodiments. The computer-readable and computer-executable instructions can reside in any tangible computer readable storage media, such as, for example, in data storage features such as RAM (e.g., SRAM, DRAM, Flash, embedded DRAM, EPROM, EEPROM, etc.), ROM, and/or storage device. The computer-readable and computer-executable instructions, which reside on tangible computer readable storage media, are used to control or operate in conjunction with, for example, one or some combination of processor, or other similar processor(s). Although specific procedures are disclosed in flow diagram900, such procedures are examples. That is, embodiments are well suited to performing various other procedures or variations of the procedures recited in flow diagram900. Likewise, in some embodiments, the procedures in flow diagram900 may be performed in an order different than presented and/or not all of the procedures described in one or more procedures described inFIG. 9 may be performed. It is further appreciated that one or more procedures described in flow diagram900 may be implemented in hardware, or a combination of hardware and firmware, or a combination of hardware and software running thereon.
• FIG. 9 is a flow diagram900 of an example method of partitioning and incrementing a counter in a memory, in accordance with an embodiment. Reference will be made to elements ofFIGS. 1,6,7 and8 to facilitate the explanation of the operations of the method of flow diagram900. In one embodiment, the method of flow diagram900 describes the use of programmablepartitionable counters610C and abandwidth engine105 that performs a plurality of operations based on one command.
• At910, in one embodiment, an entry value is programmed wherein the entry value corresponds with the size of a partition. An entry value, (e.g., e0, e1, e2 or e3) is programmed and corresponds with the size of a partition (e.g., s0, s1, s2 or s3).
• At920, in one embodiment, acounter610C is partitioned based on the size (s value) of the partition. In one embodiment, the entries must be programmed in an order such that if the first entry corresponds with the first partition of bits of a counter, the second entry corresponds with the next partition of bits in the counter, and so on.
• At930, in one embodiment, the memory receives a packet. In various embodiments,memory core110 can receive a packet sent from either thelogic unit120, thewrite buffer510, or thepacket processor150.
• At940, in one embodiment, functions are performed on the values in thepartition counter610C based on thepacket comprising operations950 and960. In one embodiment,logic unit120 updates the statistics (e.g., values in the counters).
• At950, in one embodiment, a bit/bits are added to abyte counter partition710 in a partition of the partitionedcounter610C. As discussed herein, a packet typically contains the packet size. The packet size is added to thebyte counter partition710 within programmablepartitionable counter610C in some embodiments. In some embodiments, the packet size is added to abyte counter610A.
• At960, in one embodiment, bits are added to apacket counter partition720 in the partitionedcounter610C based on adding bits to abyte counter partition710. As discussed herein, a dual operation may occur where instead of sending two commands to add to bothbyte counter partition710 andpacket counter partition720, a dual operation adds to thepacket counter partition720 whenever thebyte counter partition710 changes. As discussed herein, thepacket counter partition720 may be incremented by 1 bit, more than 1 bit, or a number of bits based on the packet.
• At970, in one embodiment, the values in the partitioned counter are merged together. In some embodiments,programmable merge module810 gathers values from a plurality of counters and sends them tomemory partition640.
• At980, in one embodiment, errors are corrected on a merged partitioned counter value. This operation occurs at errorcorrection code modules650. Note that error correcting may occur elsewhere in the bandwidth engine. For example, error correcting may occur at various times/places including, but not limited to: after data is read from thememory core110, whenbandwidth engine105 receives a packet, beforebandwidth engine105 sends a packet, before an operation is performed on data in thelogic unit120 ormetering logic unit160, after an operation is performed on data in thelogic unit120 ormetering logic unit160, before data entersmemory core110, etc.
• At990, in one embodiment, the merged partitioned counter values are written to thememory partition640. In some embodiments, the values may be sent topacket processor150.
Example Computer System Environment
• With reference now toFIG. 10, all or portions of some embodiments described herein are composed of computer-readable and computer-executable instructions that reside, for example, in computer-usable/computer-readable storage media of a computer system. That is,FIG. 10 illustrates one example of a type of computer (computer system1000) that can be used in accordance with or to implement various embodiments which are discussed herein. It is appreciated thatcomputer system1000 ofFIG. 10 is an example and that embodiments as described herein can operate on or within a number of different computer systems including, but not limited to, general purpose networked computer systems, embedded computer systems, routers, switches, server devices, client devices, various intermediate devices/nodes, stand alone computer systems, media centers, handheld computer systems, multi-media devices, and the like.Computer system1000 ofFIG. 10 is well adapted to having peripheral tangible computer-readable storage media1002 such as, for example, a floppy disk, a compact disc, digital versatile disc, other disc based storage, universal serial bus “thumb” drive, removable memory card, and the like coupled thereto. The tangible computer-readable storage media is non-transitory in nature.
• System1000 ofFIG. 10 includes an address/data bus1004 for communicating information, and aprocessor1006A coupled with bus1004 for processing information and instructions. As depicted inFIG. 10,system1000 is also well suited to a multi-processor environment in which a plurality ofprocessors1006A,1006B, and1006C are present. Conversely,system1000 is also well suited to having a single processor such as, for example,processor1006A.Processors1006A,10068, and1006C may be any of various types of microprocessors.System1000 also includes data storage features such as a computer usable volatile memory1008, e.g., random access memory (RAM), coupled with bus1004 for storing information and instructions forprocessors1006A,10068, and1006C.System1000 also includes computer usable non-volatile memory1010, e.g., read only memory (ROM), coupled with bus1004 for storing static information and instructions forprocessors1006A,10068, and1006C. Also present insystem1000 is a data storage unit1012 (e.g., a magnetic or optical disk and disk drive) coupled with bus1004 for storing information and instructions.System1000 may also include analphanumeric input device1014 including alphanumeric and function keys coupled with bus1004 for communicating information and command selections toprocessor1006A orprocessors1006A,10068, and1006C.System1000 may also includecursor control device1016 coupled with bus1004 for communicating user input information and command selections toprocessor1006A orprocessors1006A,1006B, and1006C. In one embodiment,system1000 may also includedisplay device1018 coupled with bus1004 for displaying information.
• Referring still toFIG. 10,display device1018 ofFIG. 10, when included, may be a liquid crystal device, cathode ray tube, plasma display device or other display device suitable for creating graphic images and alphanumeric characters recognizable to a user.Cursor control device1016, when included, allows the computer user to dynamically signal the movement of a visible symbol (cursor) on a display screen ofdisplay device1018 and indicate user selections of selectable items displayed ondisplay device1018. Many implementations ofcursor control device1016 are known in the art including a trackball, mouse, touch pad, joystick or special keys onalphanumeric input device1014 capable of signaling movement of a given direction or manner of displacement. Alternatively, it will be appreciated that a cursor can be directed and/or activated via input fromalphanumeric input device1014 using special keys and key sequence commands.System1000 is also well suited to having a cursor directed by other means such as, for example, voice commands.System1000 also includes an I/O device1020 forcoupling system1000 with external entities. For example, in one embodiment, I/O device1020 is a modem for enabling wired or wireless communications betweensystem1000 and an external network such as, but not limited to, the Internet. In another example I/O device1020 uses SerDes technology.
• Referring still toFIG. 10, various other components are depicted forsystem1000. Specifically, when present, anoperating system1022,applications1024,modules1026, anddata1028 are shown as typically residing in one or some combination of computer usable volatile memory1008 (e.g., RAM), computer usable non-volatile memory1010 (e.g., ROM), anddata storage unit1012. In some embodiments, all or portions of various embodiments described herein are stored, for example, as anapplication1024 and/ormodule1026 in memory locations within RAM1008, computer-readable storage media withindata storage unit1012, peripheral computer-readable storage media1002, and/or other tangible computer-readable storage media.

Claims (25)

1. An integrated circuit device for receiving packets comprising:

a first counter for counting a number of said packets; and

a second counter for counting bytes of said packets, wherein said first counter and said second counter are configured to be incremented by a single command from a packet processor.

2. The integrated circuit ofclaim 1, wherein said first counter comprises:

a lifetime counter.

3. The integrated circuit ofclaim 1, wherein said second counter comprises:

a lifetime counter.

4. The integrated circuit ofclaim 1, wherein said integrated circuit is a system-on-chip (SoC).

5. The integrated circuit ofclaim 1, further comprising:

a logic unit comprising said first counter and said second counter.

6. The integrated circuit ofclaim 5, wherein said logic unit further comprises:

an error correcting code module.

7. The integrated circuit ofclaim 1, wherein at least one of said first counter and said second counter is at least 64-bit counter.

8. The integrated circuit ofclaim 1, wherein at least one of said first counter and said second counter are reset at a predetermined interval.

9. The integrated circuit ofclaim 1, further comprising:

an incrementer for incrementing said first counter.

10. The integrated circuit ofclaim 1, wherein said single command comprises:

incrementing said first counter by 1 and incrementing said second counter by packet size.

11. The integrated circuit ofclaim 1, further comprising:

a programmable partitionable counter comprising said first counter and said second counter.

12. The integrated circuit ofclaim 1, wherein said first counter and said second counter are fixed width.

13. A data traffic governing system comprising:

an integrated circuit device comprising:

a first counter for counting a number of said packets; and

a second counter for counting bytes of said packets, wherein said first counter and said second counter are configured to be incremented by a single command.

14. The data traffic governing system ofclaim 13, wherein said first counter comprises:

a lifetime counter.

15. The data traffic governing system ofclaim 13, wherein said second counter comprises:

a lifetime counter.

16. The data traffic governing system ofclaim 13, wherein said integrated circuit is an ASIC.

17. The data traffic governing system ofclaim 13, further comprising:

a logic unit comprising said first counter and said second counter.

18. The data traffic governing system ofclaim 17, wherein said logic unit further comprises:

an error correction code module.

19. The data traffic governing system ofclaim 13, wherein said first counter is a 64-bit counter and said second counter is a 64-bit counter.

20. The data traffic governing system ofclaim 13, wherein said first counter and said second counter are reset at a predetermined interval.

21. The data traffic governing system ofclaim 13, further comprising:

an incrementer for incrementing said first counter.

22. The data traffic governing system ofclaim 13, wherein said single command comprises:

incrementing said first counter by 1 and incrementing said second counter by packet size.

23. The data traffic governing system ofclaim 13, further comprising:

a data packet processor, wherein said single command is from said data packet processor.

24. The data traffic governing system ofclaim 13, further comprising:

a programmable partitionable counter comprising said first counter and said second counter.

25. The data traffic governing system ofclaim 13, wherein said first counter and said second counter are fixed width.

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