US20130315020A1 - Semiconductor memory device, and method of controlling the same - Google Patents

Abstract

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to a semiconductor memory device having a low power consumption mode.
• 2. Description of the Related Art
• In recent years, the cellular phone has been given not only a function to have a vocal communication but also a function to transmit character-string data or image data. Moreover, the cellular phone has been expected in the future to become a kind of information terminal (for example, a portable type personal computer) as the internet services are diversified. Thus, the information volume of data to be handled by the cellular phone has been drastically increasing. Conventionally, the cellular phone has employed as its work memory SRAMs having a memory capacity of about 4 Mbit. The work memory is a memory for retaining the necessary data during the operation of the cellular phone. It is obvious that the memory capacity of the work memory will be short in the future.
• On the other hand, the transmission speed of the cellular phone has been heightening. The smaller the cellular phone becomes, the smaller the battery to be mounted becomes. Therefore, the work memory to be employed in the cellular phone is required to have a high speed, low power consumption and a large capacity. In the cellular phone serious price competitions, it is necessary to make the costs for parts as low as possible. Therefore, the work memory has to be at low price.
• The conventional SRAMs as employed in the work memory are higher per bit in cost than DRAMs. The production number of SRAMs is smaller than that of the DRAMs so that it is difficult to lower its price. Moreover, there have never been developed SRAMs having a large memory capacity (for example, 64 Mbit).
• In this situation, it has been considered to replace the SRAMs by flash memories and DRAMs in the work memory of the cellular phone.
• The flash memory has a power consumption as low as several μW during a standby state but requires several μs to several tens μs for writing data. When the flash memory is employed as the work memory of the cellular phone, therefore, it is difficult to transmit/receive massive data at high speed. The flash memory performs the write operation at the unit of a sector so that it is not suitable for rewriting bit by bit image data such as the data of a moving image.
• On the contrary, the DRAMs can execute both the read operation and the write operation within several tens ns and can process the data of the moving image easily. The power consumption during the standby state is higher than that of the flash memories. In the present DRAMs, the power consumption in the standby state is about 1 mW during a self-refresh mode for retaining written data and about 300 μW during a standby mode not required for retaining written data.
• If the power consumption during the standby mode could be reduced to that of the flash memories, the DRAMs could be employed as the work memory of the cellular phone, but such circuit technology has never been proposed.
• The power consumption of the DRAMs can be reduced to zero by stopping the power supply to the DRAMs. However, since the address terminals, the data terminals and the like of the DRAMs are connected with the terminals of other electronic parts through the wiring patterns on a circuit board, it is required to drastically change the system of the cellular phone (the pattern change of the circuit board, re-layout and so on) for the termination of the power supply to the DRAMs.
• Besides, there has not been proposed a technology which realizes exit from the standby mode without the malfunction of an internal circuit after the power supply is terminated to stop the operation of the internal circuit during the standby mode.
• Where the internal voltage to be used in the internal circuit is generated inside of the device, it has to be quickly returned to a predetermined voltage when a release is made from a standby mode (a low power consumption mode). However, this technique has never been proposed.
SUMMARY OF THE INVENTION
• An object of the present invention is to enter the device into a low power consumption mode and exit the device from a low power consumption mode with reliability.
• Another object of the present invention is to provide a semiconductor memory device capable of drastically reducing current consumption during standby mode as compared with the conventional devices and a method of controlling the semiconductor memory device.
• Still another object of the present invention is to provide a semiconductor memory device capable of drastically reducing current consumption during a standby period as compared with the conventional devices and a method of controlling the semiconductor memory device.
• Another object of the present invention is to easily enter a device into a low power consumption mode by a control signal from the exterior.
• Another object of the present invention is to prevent the feedthrough current (or leak path) of an internal circuit during a low power consumption mode.
• Still another object of the present invention is to easily enter the device into the low power consumption mode by employing an existing control signal.
• Another object of the present invention is to easily enter the device into the low power consumption mode by a command input.
• Another object of the present invention is to easily enter the device into the low power consumption mode by a dedicated control signal.
• Another object of the invention is to quickly return from the low power consumption mode.
• According to one aspect of the semiconductor memory device in the present invention, an internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. When the internal voltage generator is operated, a predetermined amount of electric power is consumed. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. The internal voltage is not to be generated due to the inactivation of the internal voltage generator so that the power consumption may be reduced. In response to the control signal from the exterior, therefore, it is possible to easily enter the device into the low power consumption mode.
• According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a booster and the generation of a boost voltage to be supplied to a word line. During the low power consumption mode the booster steadily consuming the electric power stops so that the power consumption is drastically reduced.
• According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a substrate voltage generator to stop the generation of a substrate voltage to be supplied to a substrate. During the low power consumption mode, the substrate voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
• According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of an internal supply voltage generator to stop the generation of an internal supply voltage to be supplied to a memory core. During the low power consumption mode, the internal supply voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
• According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a precharging voltage generator to stop the generation of a precharging voltage to be supplied to bit lines. During the low power consumption mode, the precharging voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
• According to another aspect of the semiconductor memory device in the present invention, an external voltage supplying circuit supplies the power supply voltage as the internal voltage to the internal circuit during the low power consumption mode. When the internal voltage generating circuit is inactive, therefore, the power supply terminal of each internal circuit is supplied with a predetermined power supply voltage. As a result, each element of the internal circuit is fixed in a predetermined state to prevent a leak path. In other words, the flow of a feedthrough current is prevented.
• According to another aspect of the semiconductor memory device in the present invention, a predetermined internal circuit is inactivated when a reset signal is supplied from the exterior. In response to this reset signal, the entry circuit enters the device into the low power consumption mode. During the resetting, the device need not be operated. Therefore, it can enter the low power consumption mode by utilizing the existing signal. The type and number of external terminals are identical to those of the conventional terminals so that adding the low power consumption mode does not lower the usability.
• According to another aspect of the semiconductor memory device in the present invention, the entry circuit receives a plurality of control signals from the exterior. The entry circuit enters the device into the low power consumption mode when it recognizes the states of the control signals as low power consumption commands. Therefore, the device can enter the low power consumption mode by the command input.
• According to another aspect of the semiconductor memory device in the present invention, the entry circuit receives a reset signal and a chip enable signal from the exterior. The entry circuit enters the device into the low power consumption mode when it recognizes the states of those control signals as low power consumption commands. Therefore, the device can enter the low power consumption mode by the command input.
• According to another aspect of the semiconductor memory device in the present invention, when the reset signal is inactivated during a predetermined period and in this state the chip enable signal is activated during a predetermined period, the device enters the low power consumption mode. Even when a glitch occurs in the reset signal or the chip enable signal due to power supply noises or the like, it is able to prevent the device from erroneously entering the low power consumption mode.
• According to another aspect of the semiconductor memory device in the present invention, the entry circuit receives a plurality of control signals from the exterior during the low power consumption mode. The entry circuit exits the device from the low power consumption mode when the levels of the control signals indicate exit of the low power consumption mode. Therefore, the device can be exited from the low power consumption mode by the command input.
• The entry circuit enters the device into the low power consumption mode when it receives the predetermined level or the transition edge of a low power consumption mode signal. Therefore, the device can reliably enter the low power consumption mode by employing a dedicated signal.
• According to another aspect of the semiconductor memory device in the present invention and controlling the semiconductor memory device, when the state of a control signal received during the low power consumption mode indicates exit of the low power consumption mode, the low power consumption mode is exited. This allows the device to be easily exited from the low power consumption mode by a control signal from the exterior. The exist from the low power consumption mode is, for example, executed by controlling the entry circuit.
• According to another aspect of the semiconductor memory device in the present invention and controlling the semiconductor memory device, after the low power consumption mode is exited, a reset signal for initializing an internal circuit is activated during a period where the internal voltage is lower than a predetermined voltage. For instance, the reset signal is activated during a period where the internal voltage is lower than a reference voltage generated by stepping down the power supply voltage. Therefore, when the low power consumption mode shifts to a normal operating mode, the internal circuit can be reliably reset, which prevents malfunction of the internal circuit.
• According to another aspect of the semiconductor memory device in the present invention, after the low power consumption mode is exited, a reset signal for initializing an internal circuit is activated during a period where a boost voltage internally generated is lower than a predetermined voltage. For example, the reset signal is activated during a period where the boost voltage is lower than the power supply voltage. In addition, the reset signal can be activated during a period where the boost voltage is lower than a reference voltage generated by stepping down the power supply voltage.
• According to another aspect of the semiconductor memory device in the present invention, after the low power consumption mode is exited, a reset signal for initializing an internal circuit is activated during a period where at least one of the internal voltage and a boost voltage internally generated is/are lower than respective predetermined voltages. Therefore, when the low power consumption mode shifts to the normal operating mode, the internal circuit can be reliably reset, which prevents malfunction of the internal circuit.
• According to another aspect of the semiconductor memory device in the present invention, at the time of the exit from the low power consumption mode, while a timer is measuring a predetermined length of time, a reset signal for initializing an internal circuit is activated. This allows reliable reset of the internal circuit, leading to preventing malfunction of the internal circuit when the low power consumption mode shifts to a normal operating mode.
• According to another aspect of the semiconductor memory device in the present invention, a timer includes a CR time constant circuit. The timer measures the length of a time based on the propagation delay time of a signal propagated to the CR time constant circuit so that the activation period of a reset signal can be set by a simple circuit.
• According to another aspect of the semiconductor memory device in the present invention, at the time of the exit from the low power consumption mode, a reset signal for initializing an internal circuit is activated while a counter operating in the normal operation counts a predetermined number. This allows reliable reset of the internal circuit, leading to preventing malfunction of the internal circuit when the low power consumption mode shifts to a normal operating mode. For example, a refresh counter for indicating the refresh address of memory cells or the like is employed as a counter.
• According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, a self-refresh control circuit automatically refreshes memory cells at a predetermined cycle. An internal voltage generator generates an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from the exterior. The semiconductor memory device when receiving a control signal from the exterior, inactivates the self-refresh control circuit and lowers the supply capability of the internal voltage generator, thereby entering into a low power consumption mode. When the data of the memory cells need not be retained during the low power consumption mode, the operations of the self-refresh control circuit are unnecessary. Owing to not executing refresh, the internal voltage generator may operate with a power enough to compensate an electric power (leakage current) to be consumed by the internal circuit. As a result, the power consumption during the low power consumption mode can be reduced.
• The internal voltage is supplied to the internal circuit even during the low power consumption mode. Therefore, the internal circuit can operate immediately after a release from the low power consumption mode.
• According to another aspect of the semiconductor memory device in the present invention, the internal voltage generator includes a plurality of units for generating the internal voltage. During the low power consumption mode, a part of the units suspend(s) so that the power consumption during the low power consumption mode can be further reduced.
• According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, a stabilized capacitor connected with a power supply line stores a portion of electric charge to be supplied to the power supply line. The semiconductor memory device when receiving a control signal from the exterior, keeps a connection between the power supply line and the stabilized capacitor but disconnects the power supply line and the internal circuit, thereby entering into the low power consumption mode. Therefore, the power consumption of the internal circuit can be reduced to zero during the low power consumption mode. After the release from the low power consumption mode, the voltage corresponding to the electric charge stored in the stabilized capacitor is applied to the internal circuit through the power supply line when the power supply line and the internal circuit are connected. As a result, the semiconductor memory device can operate immediately after the release from the low power consumption mode.
• According to another aspect of the semiconductor memory device in the present invention, an internal voltage generator generates an internal voltage upon receipt of a power supply voltage from the exterior. The internal voltage is supplied to the internal circuit through the power supply line. After the release from the low power consumption mode, therefore, the voltage corresponding to the electric charge stored in the stabilized capacitor can be supplied to the internal circuit.
• According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, an internal voltage generator generates an internal voltage to be supplied to a predetermined internal circuit, upon receipt of a power supply voltage from the exterior. An internal voltage detector detects the level of the internal voltage and controls the internal voltage generator according to its detection result. The semiconductor memory device receiving a control signal from the exterior, weakens the response of the internal voltage detector, thereby entering to a low power consumption mode. Weakening the response of the internal voltage detector results in lowering the operation frequency of the internal voltage generator to be operated under the control of the internal voltage detector. As a result, the power consumption during the low power consumption mode can be reduced.
• According to another mode of the semiconductor memory device of the invention, the internal voltage generator includes a plurality of units for detecting the level of the internal voltage. During the low power consumption mode, a part of the units suspend(s) their operations so that the power consumption during the power consumption mode can be further reduced.
• According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, an internal voltage generator generates an internal voltage to be supplied to a predetermined internal circuit, upon receipt of a power supply voltage from the exterior. An internal voltage detector detects the level of the internal voltage and controls the internal voltage generator according to its detection result. The semiconductor memory device receiving a control signal from the exterior, lowers the detection level of the internal voltage in the internal voltage detector and reduces the absolute value of the internal voltage generated by the internal voltage generator, thereby entering into a low power consumption mode. Therefore, the drivability of the internal voltage generator can be lowered, which reduces the power consumption.
• According to another aspect of the semiconductor memory device in the present invention, a reference voltage generator generates a reference voltage. The internal voltage detector detects the level of the internal voltage by comparing the internal voltage with the reference voltage. The semiconductor memory device receiving a control signal from the exterior, lowers the level of the reference voltage generated by the reference voltage generator, thereby decreasing the absolute value of the detection level of the internal voltage in the internal voltage detector. This results in reducing the absolute value of the level of the internal voltage and the off current of transistors and so on in the internal circuit, thereby reducing the power consumption.
• According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, a self-refresh control circuit automatically refreshes memory cells at a predetermined cycle. When the semiconductor memory device receives a control signal from the exterior, it inactivates the self-refresh control circuit and enters into a low power consumption mode. Owing to not executing refresh during the low power consumption mode, a current amount consumed for the refresh can be reduced.
• According to another aspect of the semiconductor memory device in the present invention, the self-refresh control circuit includes a timer for determining a length of refresh cycle. The timer suspends during the low power consumption mode so that the power consumption can be reduced.
• According to one aspect of a method of controlling the semiconductor memory device in the present invention, the internal voltage generator when activated, generates the internal voltage to be supplied to a predetermined internal circuit. When the internal voltage generator is operated, a predetermined amount of electric power is consumed. In response to the control signal from the exterior, the internal voltage generator is inactivated. The internal voltage is not to be generated due to the inactivation of the internal voltage, which results in reducing the power consumption. In response to the control signal from the exterior, therefore, the device can easily enter the low power consumption mode.
• According to another aspect of the method of controlling the semiconductor memory device in the present invention, a plurality of control signals is received from the exterior. The device enters the low power consumption mode when it recognizes the states of the control signals as the low power consumption commands. Therefore, the device can enter the low power consumption mode by the command input.
• According to another aspect of the method of controlling the semiconductor memory device in the present invention, when the power supply is switched on, the chip enable signal remains inactivated until the power supply voltage reaches a predetermined voltage. This makes it possible to prevent an erroneous entry to the low power consumption mode when the power supply is switched on.
BRIEF DESCRIPTION OF THE DRAWINGS
• The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
• FIG. 1 is a state transition diagram of a semiconductor memory device of the present invention;
• FIG. 2 is a block diagram showing a basic principle of a first embodiment;
• FIG. 3 is a block diagram showing the first embodiment;
• FIG. 4 is a circuit diagram showing the details of a booster and a precharging voltage generator ofFIG. 3;
• FIG. 5 is a circuit diagram showing the details of an internal supply voltage generator and a substrate voltage generator ofFIG. 3;
• FIG. 6 is a circuit diagram showing the detail of an essential portion of a memory core ofFIG. 3;
• FIG. 7 is a timing chart showing the operations of the first embodiment at the switch-on of a power supply and at the times of entry into and exit from a low power consumption mode;
• FIG. 8 is a block diagram showing an example in which the semiconductor memory device of the first embodiment is used in a cellular phone;
• FIG. 9 is an explanatory diagram showing the state of using the cellular phone shown inFIG. 8;
• FIG. 10 is a flow chart showing the state of controlling the cellular phone shown inFIG. 8;
• FIG. 11 is a block diagram showing a second embodiment;
• FIG. 12 is a circuit diagram showing the detail of a low power entry circuit ofFIG. 11;
• FIG. 13 is a timing chart showing the operations of the low power entry circuit ofFIG. 12;
• FIG. 14 is a block diagram showing a third embodiment;
• FIG. 15 is a circuit diagram showing a VII starter in a fourth embodiment;
• FIG. 16 is a circuit diagram showing a VII starter in the fourth embodiment;
• FIG. 17 is a timing chart showing operations at the entry to and the exit from a low power consumption mode in the fourth embodiment;
• FIG. 18 is a circuit diagram showing a level detecting circuit in a fifth embodiment;
• FIG. 19 is a timing chart showing operations at the entry to and the exit from a low power consumption mode in the fifth embodiment;
• FIG. 20 is a circuit diagram showing a start signal generator in a sixth embodiment; and
• FIG. 21 is a timing chart showing operations at the entry to and the exit from a low power consumption mode in the sixth embodiment.
• FIG. 22 is a block diagram showing a seventh embodiment;
• FIG. 23 is a circuit diagram showing the detail of a reference voltage generator ofFIG. 22;
• FIG. 24 is a circuit diagram showing the detail of an internal supply voltage generator ofFIG. 22;
• FIG. 25 is a block diagram showing a booster, a VPP detector, a substrate voltage generator and a VBB detector;
• FIG. 26 is a circuit diagram showing the detail of a unit of the booster ofFIG. 25;
• FIG. 27 is a circuit diagram showing the detail of the unit of the booster ofFIG. 25;
• FIG. 28 is a circuit diagram showing the detail of the VPP detector ofFIG. 22;
• FIG. 29 is a circuit diagram showing the detail of a unit of the substrate voltage generator ofFIG. 25;
• FIG. 30 is a circuit diagram showing the detail of the unit of the substrate voltage generator ofFIG. 25;
• FIG. 31 is a circuit diagram showing the detail of the VBB detector ofFIG. 22;
• FIG. 32 is a circuit diagram showing the detail of a precharging voltage generator ofFIG. 22;
• FIG. 33 is a circuit diagram showing the detail of an oscillator ofFIG. 22;
• FIG. 34 is a circuit diagram showing the detail of a generator ofFIG. 23; and
• FIG. 35 is a timing chart showing the operations of the oscillator and a frequency divider in the seventh embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Embodiments of the present invention will be described with reference to the accompanying drawings.
• FIG. 1 shows a state transition diagram of a semiconductor memory device of the present invention.
• First of all, the semiconductor memory device comes into an idle mode when the power supply is switched on. When a read command or a write command is received in the idle mode, the mode shifts to an operating mode to execute a read operation or a write operation. After the execution of the read operation or the write operation, the idle mode is automatically restored. When a self-refreshing command is received in the idle mode, the device enters the self-refreshing mode to execute self-refresh. Herein the self-refreshing mode, a refresh address is automatically generated to sequentially execute refreshing operations in memory cells.
• The semiconductor memory device enters the low power consumption mode by detecting a predetermined state of a signal in the idle mode. In a first embodiment described below, in response to a chip enable signal CE2, the device enters the low power consumption mode. Specifically, by the chip enable signal CE2 a predetermined internal circuit is inactivated and the device enters the low power consumption mode. In a second embodiment described below, in response to a command input by chip enable signals /CE1 and CE2, the device enters the low power consumption mode. In a third embodiment described below, in response to a dedicated low power consumption mode signal /LP, the device enters the low power consumption mode.
• The semiconductor memory device detects a predetermined state of a signal during the low power consumption mode and exits the mode.
• FIG. 2 shows the basic principle of the semiconductor memory device of the present invention.
• The semiconductor memory device includes anentry circuit1, aninternal voltage generator2, an externalvoltage supplying circuit3, and aninternal circuit4.
• Theinternal voltage generator2 generates an internal voltage in each mode after the power supply is switched on, and supplies the internal voltage to theinternal circuit4. Theentry circuit1 receives a control signal and inactivates theinternal voltage generator2 when it detects a predetermined state of the control signal. When theinternal voltage generator2 is inactivated, the generation of the internal voltage is stopped. At the same time, theentry circuit1 activates the externalvoltage supplying circuit3. This externalvoltage supplying circuit3 supplies the power supply voltage as the internal voltage to theinternal circuit4. And, the semiconductor memory device enters the low power consumption mode.
• FIG. 3 shows a first embodiment of the semiconductor memory device and its control method in the present invention. The semiconductor memory device of this embodiment is formed as a DRAM on a p-type silicon substrate by employing the CMOS process technology.
• The DRAM is provided with aVII starter10, aVDD starter12, a lowpower entry circuit14, acommand decoder16, aninternal voltage generator18 and amain circuit unit20. Theinternal voltage generator18 has a low-pass filter22, areference voltage generator24, aVDD supplying circuit26, abooster28, aprecharging voltage generator30, an internalsupply voltage generator32, asubstrate voltage generator34 and aVSS supplying circuit36. Themain circuit unit20 has amemory core38 and aperipheral circuit40. Here, the lowpower entry circuit14 corresponds to theentry circuit1 shown inFIG. 2, and theVDD supplying circuit26 and theVSS supplying circuit36 correspond to the externalvoltage supplying circuit3 shown inFIG. 2.
• The DRAM is supplied with a power supply voltage VDD (e.g., 2.5 V) from the exterior, a ground voltage VSS, chip enable signals /CE1 and CE2 as the control signals, a plurality of address signal AD, a plurality of data input/output signals DQ, and another control signal CN.
• This DRAM does not adopt the address multiplex method. Therefore, the address signals AD is supplied once at each read operation and at each write operation. The power supply voltage VDD and the ground voltage VSS are supplied to almost all the circuits excepting a partial circuit of thememory core38. Here, the signals headed by the letter “/” are those of negative logic. The “address signals AD” may be abbreviated into the “AD signals” in the following description by omitting its signal name.
• The /CE1 signal is turned to a low level when the read operation and the write operation are executed to activate the DRAM. The CE2 signal functions as a reset signal to inactivate a predetermined internal circuit in themain circuit unit20 when at the low level. TheVII starter10 receives the internal supply voltage VII and the ground voltage VSS and outputs a start signal STTVII to themain circuit unit20. TheVII starter10 is resets themain circuit unit20 after the power supply is switched on until the internal supply voltage VII reaches a predetermined voltage, and it prevents the malfunction of themain circuit unit20. TheVDD starter12 receives the power supply voltage VDD and the ground voltage VSS and outputs a start signal STTCRX. TheVDD starter12 inactivates the lowpower entry circuit14 after the power supply is switched on until the power supply voltage VDD reaches a predetermined voltage and it prevents the malfunction of thecircuit14.
• The lowpower entry circuit14 receives the start signal STTCRX and the CE2 signal and activates a low power signal ULP.
• In response to the /CE1 signal and another control signal CN, thecommand decoder16 decodes a command and outputs the decoded command as an internal command signal to theperipheral circuit40.
• The low-pass filter22 has a function to filter out the noise contained in the power supply voltage VDD. The power supply voltage VDD thus cleared of the noise is fed to thereference voltage generator24 or the like. In the low power consumption mode, the switch in the low-pass filter22 is switched off and the power supply voltage VDD is not supplied to thereference voltage generator24 so that the current is not consumed.
• Thereference voltage generator24 receives the power supply voltage VDD and generates reference voltages VPREF (e.g., 1.5 V), VPRREFL (e.g., 0.8 V), VPRREFH (e.g., 1.2 V) and VRFV (e.g., 2.0 V).
• TheVDD supplying circuit26 turns a boost voltage VPP and an internal supply voltage VII to the power supply voltage VDD during the low power consumption mode.
• Thebooster28 receives the reference voltage VPREF and generates the boost voltage VPP (e.g., 3.7 V) and supplies the boost voltage VPP to thememory core38.
• Theprecharging voltage generator30 receives the reference voltage VPRREFL and the reference voltage VPRREFH and generates a precharging voltage VPR (e.g., 1.0 V) to be supplied to thememory core38.
• The internalsupply voltage generator32 receives the reference voltage VRFV and generates the internal supply voltage VII (e.g., 2.0 V) to be supplied to thememory core38 and theperipheral circuit40.
• Thesubstrate voltage generator34 receives the reference voltage VRFV and generates a substrate voltage VBB (e.g., −1.0 V) to be fed to the substrate and the p-wells of the memory cells.
• TheVSS supplying circuit36 turns the precharging voltage VPR and the substrate voltage VBB to the ground voltage VSS during the low power consumption mode.
• FIG. 4 shows the details of thebooster28 and theprecharging voltage generator30.
• Thebooster28 is composed of resistors R1 and R2 connected in series, adifferential amplifier28a, apumping circuit28b, annMOS28c, and aswitching circuit28dfor controlling the gate of thenMOS28c. The resistor R1 is supplied at its one end with the boost voltage VPP, and the resistor R2 is supplied at its one end with the ground voltage VSS through thenMOS28c. A divided voltage V1 is generated from the connection node of the resistors R1 and R2. ThenMOS28creceives the power supply voltage VDD from the switchingcircuit28dduring the low power consumption mode. Thedifferential amplifier28ais formed of a MOS differential amplifier using a current mirror circuit, for example, as the current source. Thedifferential amplifier28aoutputs a high level when the voltage V1 is lower than the reference voltage VPREF. Thepumping circuit28breceives the high level from thedifferential amplifier28aand starts a pumping operation. By this pumping operation, the voltage VPP is raised, and the voltage V1 is raised. When this voltage V1 coincides with the reference voltage VPREF (i.e., 1.5 V), the output of thedifferential amplifier28areaches the low level so that the pumping operation stops. By repeating these operations, the boost voltage VPP is retained at a constant voltage.
• Theprecharging voltage generator30 is composed of twodifferential amplifiers30aand30bconnected at their outputs with each other. Thedifferential amplifier30ais supplied with the reference potential VPRREFL and the precharging voltage VPR. Thedifferential amplifier30bis supplied with the reference potential VPRREFL and the precharging voltage VPR. Moreover, thesedifferential amplifiers30aand30bgenerate the precharging voltage VPR at an intermediate value between the reference voltages VPRREFL and VPRREFH.
• FIG. 5 shows the details of the internalsupply voltage generator32 and thesubstrate voltage generator34. The internalsupply voltage generator32 is composed of a negative feedbacktype differential amplifier32a, a compensatingcircuit32b, aregulator32cmade of an nMOS, annMOS32d, and aswitching circuit32efor controlling the gate of the nMOS. Thedifferential amplifier32areceives the reference voltage VRFV and a voltage V2 generated by the compensatingcircuit32b, and supplies a predetermined voltage to a node VG. In the compensatingcircuit32b, an nMOS and resistors R3 and R4 in a diode connection are arranged in series between the node VG and the ground line VSS. The voltage V2 is generated at the connection node between the resistors R3 and R4. Theregulator32cis connected at its gate with the node VG, receives the power supply voltage VDD at its drain and generates the internal supply voltage VII at its source.
• ThenMOS32dis grounded at its source and connected at its drain with the node VG. The switchingcircuit32esupplies the power supply voltage VDD to a gate of thenMOS32dduring the lower power consumption mode. ThenMOS32dreceives the power supply voltage VDD from the switchingcircuit32eduring the low power consumption mode, and fixes the node VG at the ground level.
• In this internalsupply voltage generator32, when the threshold voltage of theregulator32cis lowered due to the rise in the ambient temperature, for example, the threshold voltage of the nMOS of the compensatingcircuit32balso drops, so that the voltage V2 rises. In response to the rise in the voltage V2, thedifferential amplifier32alowers the voltage of the node VG. Moreover, the source-to-drain current of thenMOS32cis made constant so that the internal supply voltage VII is made constant.
• Thesubstrate voltage generator34 is composed of anoscillator34aand apumping circuit34b. In response to the high level of a control signal VBBEN, theoscillator34astarts the oscillating operation to output an oscillating signal OSC. Thepumping circuit34bhas a capacitor for repeating charge and discharge in response to the oscillating signal OSC from theoscillator34a, and a diode-connected nMOS transistor connected with one end of the capacitor. The charges of a p-type substrate connected with the anode are discharged by the pumping operation, which lowers the substrate voltage VBB. Making the substrate voltage VBB negative leads to gaining some effects such as reducing the influences of a shift in the threshold voltage of the memory cells due to the substrate effect so that the characteristics of the memory cells may be improved.
• FIG. 6 shows the detail of an essential portion of thememory core38.
• Thememory core38 has a memory cell MC, nMOS switches42aand42b, aprecharging circuit44 and a sense amplifier46.
• The memory cell MC is composed of a data transferring nMOS and a capacitor. The gate of the nMOS is connected with a word line WL0 (or WL1).
• The nMOS switches42aand42bcontrol the connection between a bit line BL (or /BL) on the side of the memory cell MC and a bit line BL (or /BL) on the side of a sense amplifier SA. The nMOS switches42aand42breceive a control signal BT at their gates.
• Theprecharging circuit44 is composed of three nMOSes44a,44band44c. The nMOS44ais connected at its source and drain, respectively, with the bit lines BL and /BL. The nMOSes44band44care connected at one of their sources and drains, respectively, with the bit lines BL and /BL, and are supplied at their others with the precharging voltage VPR. The nMOSes44aand44band44creceive a bit line control signal BRS at their gates.
• The sense amplifier46 is constructed by connecting the inputs and outputs of two CMOS inverters with each other. Each of these CMOS inverters is connected at its outputs individually with the bit lines /BL and BL. The source of the pMOS and the source of the nMOS of each CMOS inverter are connected with power supply lines PSA and NSA, respectively. The voltages of these power supply lines PSA and NSA individually reach the VPR level during a standby state and during the inactivation of the sense amplifiers, and respectively change to the internal supply voltage VII and the ground voltage VSS when the bit lines are amplified.
• FIG. 7 shows the operations of the switch-on of the power supply, the shifting (entry) to the low power consumption mode, and the release (exit) from the low power consumption mode with regard to the aforementioned semiconductor memory device.
• First of all, when the power supply is switched on, the power supply voltage VDD rises gradually (FIG. 7(a)). TheVDD starter12 shown inFIG. 3 inactivates the start signal STTCRX (to the low level) till the power supply voltage VDD reaches a predetermined voltage (FIG. 7(b)). By this control, it is possible to prevent the ULP signal from being activated due to the malfunctioning of the lowpower entry circuit14 when the power supply is switched on. An exterior controller (e.g., a CPU or a memory controller) for controlling the DRAM turns the CE2 signal at the high level a predetermined time T0 after the power supply voltage VDD reaches the minimum operable voltage VDDmin (FIG. 7(c)).
• After this, the DRAM becomes the standby state or executes an ordinary operation. The exterior controller turns the CE2 signal to the low level when the DRAM enters the low power consumption mode (FIG. 7(d)). The lowpower entry circuit14 activates the ULP signal (to the high level) in response to the fall of the CE2 signal when the STTCRX signal is at the high level (FIG. 7(e)).
• In response to the high level of the ULP signal, the low-pass filter22 of theinternal voltage generator18 stops the supply of the power supply voltage to thereference voltage generator24 and instead supplies the ground voltage VSS from theVSS supplying circuit36. In response to the ground voltage VSS, thereference voltage generator24 turns the reference voltages VPREF, VPRREFL, VPRREFH and VRFV to the ground level. ThenMOS28bof thebooster28 shown inFIG. 4 and thenMOS32dof the internalsupply voltage generator32 shown inFIG. 5 are switched off. As a result, thebooster28, theprecharging voltage generator30, the internalsupply voltage generator32 and thesubstrate voltage generator34 are inactivated to stop their operations. Thus, all the conventional circuits remaining operative during the low power consumption mode are stopped. Therefore, the power consumption in the low power consumption mode is drastically reduced as compared with the conventional.
• When these circuits are inactivated, the generations of the boost voltage VPP, the precharging voltage VPR, the internal supply voltage VII and the substrate voltage VBB are stopped. However, the boost voltage VPP and the internal supply voltage VII are changed into the power supply voltage VDD by theVSS supplying circuit36, and the substrate voltage VBB and the precharging circuit VPR are changed into the ground voltage VSS by theVSS supplying circuit36. Therefore, the internal circuit of themain circuit unit20 is prevented from having a leak path.
• The exterior controller turns the CE2 signal to the high level when the low power consumption mode is released (FIG. 7(f)). In response to the high level of the CE2 signal, the lowpower entry circuit14 inactivates the ULP signal (to the low level) (FIG. 7(g)). In response to the inactivation of the ULP signal, the low-pass filter22 supplies the power supply voltage VDD to thereference voltage generator24. In response to the inactivation of the ULP signal, theVDD supplying circuit26 and theVSS supplying circuit36 stop the supplies of the power supply voltage VDD and the ground voltage VSS. Then, thebooster28, theprecharging voltage generator30, the internalsupply voltage generator32 and thesubstrate voltage generator34 are activated again to start their operations.
• Here, the DRAM enters the idle mode a time T1 after the high level of the CE2 signal. This time T1 is a time required for the individual internal voltages VPP, VPR, VII and VBB to become stable.
• FIG. 8 shows an example in which the semiconductor memory device of the first embodiment is employed in a cellular phone.
• This cellular phone has the DRAM of this embodiment, the CPU and the flash memory mounted on the circuit board.
• The CPU controls the read/write operation of the data from/in the DRAM and the flash memory. The DRAM is employed as the work memory, and the flash memory is employed as the backup memory when the cellular phone is switched off or in the waiting state.
• FIG. 9 shows the state of using the cellular phone shown inFIG. 8.
• In this example, the DRAM is in the low power consumption mode by the control of the CPU when the cellular phone is in the waiting state. At this time, the power consumption of the DRAM is as much as that of the flash memory in the standby state.
• When the cellular phone then enters the service state from the waiting state, the CPU raises the CE2 signal shown inFIG. 8 to the high level. After the DRAM entered the idle mode, the data retained in the flash memory are transferred to the DRAM (FIG. 9(a)). During the service state, the DRAM is used as the work memory. Here, the service state includes not only the state of exchanging vocal communications but also the state of transferring data.
• When the service state shifts to the waiting state, those, of the data of the DRAM, necessary to be retained are saved in the flash memory (FIG. 9(b)). After this, the CPU lowers the CE2 signal to the low level and enters the DRAM to the low power consumption mode. The DRAM does not perform refresh operation in the low power consumption mode so that the unnecessary data is lost.
• When the power supply is switched off, the necessary data are retained in the flash memory. By applying the DRAM of the first embodiment to the work memory of the cellular phone, the power consumption when the cellular phone is in the waiting state is drastically reduced.
• Here, the DRAM and the flash memory may be controlled not by the CPU but by a dedicated memory controller or the like. The data transfer may also be done during the service state if necessary not only when the switching over the waiting state and the service state. Moreover, the memory for backing up the data should not be limited to the flash memory but may be an SRAM. The data may be saved in a server such as the base station of the cellular phone.
• FIG. 10 is a flow chart showing a control of the cellular phone shown inFIG. 8.
• At first Step S1, an entry to the low power consumption mode is prevented when the power supply is switched on. As shown inFIG. 7, specifically, the malfunction is prevented during the activation period of the STTCRX signal of theVDD starting circuit12.
• Next, at Step S2, the CPU turns the CE2 signal to the low level to enter the DRAM into the low power consumption mode. At Step S3, the cellular phone is in the waiting state.
• Next, at Step S4, the CPU detects whether or not the power supply is switched off. When the power supply is switched off, the procedure is complete. When the power supply is not switched off, the procedure advances to Step S5.
• At Step S5, the CPU repeats the waiting state until it becomes the service state. When it becomes the service state, the procedure advances to Step S6.
• At Step S6, the CPU raises the CE2 signal to the high level to shift the DRAM from the low power consumption mode to the idle mode. Then, the individualpower supply circuits28,30,32 and34 shown inFIG. 3 are started again.
• Next, at Step S7, the CPU transfers the data retained in the flash memory to the DRAM (return the data).
• Next, at Step S8, the service or the data transfer is performed.
• At Step S9, the CPU detects whether or not the DRAM becomes the waiting state. When it does not, the procedure returns to Step S7. When it does, the procedure advances to Step S10.
• At Step S10, the CPU transfers those of the data of the DRAM necessary to be retained, to the flash memory (save the data).
• Then, the procedure returns to Step S2, at which the cellular phone enters again the waiting state. The DRAM enters the low power consumption mode.
• In the semiconductor memory device and its control method of the present invention, the operations of thebooster28, theprecharging voltage generator30, the internalsupply voltage generator32 and thesubstrate voltage generator34 are stopped during the low power consumption mode. Therefore, the power consumption in the low power consumption mode can be drastically reduced, as compared with the conventional.
• In the low power consumption mode, the boost voltage VPP and the internal supply voltage VII, and the substrate voltage VBB and the precharging voltage VPR are set at the power supply voltage VDD and the ground voltage VSS, respectively. Therefore, the internal circuit of themain circuit unit20 can be prevented from having the leak path thereby to reduce the power consumption.
• By utilizing the CE2 signal existing in the conventional, the DRAM is entered to the low power consumption mode. Therefore, the kind and the number of the external terminals can be identical to those of the conventional terminals. As a result, the user of the DRAM is not required to drastically change the circuit due to adding the low power consumption mode.
• When the power supply is switched on, theVDD starter12 inactivates the start signal STTCRX (to the low level) until the power supply voltage VDD reaches the predetermined voltage. As a result, the lowpower entry circuit14 can be prevented from any malfunction when the power supply is switched on, to prevent the ULP signal from being activated and the DRAM from entering the low power consumption mode.
• When the power supply is switched on, the CE2 signal is raised to the high level the predetermined time T0 after the power supply voltage VDD reaches the minimum operating voltage VDDmin. This makes it possible to prevent the erroneous entry into the low power consumption mode when the power supply is switched on.
• By applying the DRAM of the present invention to the work memory of the cellular phone, therefore, the power consumption of the cellular phone during the waiting state can be drastically reduced. Moreover, the malfunction can be prevented.
• FIG. 11 shows a second embodiment of the semiconductor memory device and its control method of the present invention. The same circuits as those described in the first embodiment are designated by the common reference numerals, and their detailed description will be omitted.
• In this embodiment, a lowpower entry circuit50 is supplied with the /CE1 signal and the CE2 signal. Acommand decoder52 is supplied with the /CE1 signal, the CE2 signal and another control signal CN. The remaining construction is identical to that of foregoing first embodiment.
• FIG. 12 shows the detail of the lowpower entry circuit50.
• The lowpowder entry circuit50 hastiming adjusting circuits54aand54b, alevel shifter56, an RS flip-flop58 and acombinational circuit60.
• Thetiming adjusting circuit54ais formed by connecting a two-input NOR gate connected at its one input with adelay circuit54cand a two-input NAND gate connected at its one input with thedelay circuit54c, in plurality in cascade. Eachdelay circuit54chas an MOS capacity arranged between a plurality of inverters connected in cascade. Thetiming adjusting circuit54adelays the falling edge of a chip enable signal CE2Z by about 100 ns and outputs it to a node ND1. The CE2Z signal is the CE2 signal which is supplied from the exterior and received at the input buffer (not shown).
• Thetiming adjusting circuit54bis identical to thetiming adjusting circuit54a. Thetiming adjusting circuit54bdelays the falling edge of the signal transmitted to a node ND3, by about 100 ns.
• Thelevel shifter56 has two sets of pMOSes and nMOSes connected in series. Each nMOS receives at its gate the signals in phase and in inverted phase of a row address strobe signal RASX. The inverter for generating these inverted and uninverted signals of the RASX signal receives the internal supply voltage VII and the ground voltage VSS. The RASX signal is a control signal which turns to a low level when the word line is activated. The gates of the pMOSes are individually connected with the drains of the adjacent pMOSes, and the drains (or output nodes) of the nMOSes for receiving the positive logic of the RASX signal are connected with the RS flip-flop58. Each pMOS receives the power supply voltage VDD at its source, and each nMOS receives the ground voltage VSS at its source.
• The RS flip-flop58 is composed of two two-input NOR gates. One input corresponding to an output node ND2 receives the start signal STTCRX, and the other input receives the output signal of thelevel shifter56.
• Thecombinational circuit60 receives the low level of the nodes ND1, ND2 and the chip enable signal CE1X and it turns the output node ND3 at the low level. The CE1X signal is generated at the input buffer (not shown) receiving the /CE1 signal supplied from the exterior and is also the negative logic signal.
• Thetiming adjusting circuit54bactivates the ULP signal (to the high level) through the inverter about 100 ns after receiving the low level of the node ND3.
• FIG. 13 shows the operations of the lowpower entry circuit50.
• First, when the power supply is switched on, the STTCRX signal turns to the low level so that the voltage of the /CE1 signal rises following the power supply voltage VDD. Thus, the malfunction is prevented.
• A predetermined time after the power supply was switched on, the STTCRX signal turns to the high level (FIG. 13(a)). After this, the exterior controller for controlling the DRAM raises the CE2 signal to the high level (FIG. 13(b)). The timings above are identical to those of the first embodiment. In response to the high level of the CE2Z signal, the node ND1 shown inFIG. 12 turns to the high level (FIG. 13(c)).
• The initial cycle is executed to turn the RASX signal to the low level (FIG. 13(d)). In response to the low level of the RASX signal, the RS flip-flop58 raises the node ND2 to the high level (FIG. 13(e)). After this, there are started the operations of theinternal voltage generator18 shown inFIG. 11.
• Next, there is supplied an entry command for the entry into the low power consumption mode. In this embodiment, the DRAM enters the low power consumption mode by turning the /CE1 signal to the low level a predetermined time after turning the CE2 signal to the low level.
• Thetiming adjusting circuit54aturns the node ND1 to the low level about 100 ns after receiving the low level of the CE2Z signal (FIG. 13(f)). 100 ns or more after the falling edge of the CE2Z signal, the CE1X signal is turned to the low level (FIG. 13(g)). In response to the low level of the CE1Z signal and the low level of the node ND1, thecombinational circuit60 shown inFIG. 12 turns the node ND3 to the low level (FIG. 13(h)). Thetiming adjusting circuit54braises the ULP signal to the high level (FIG. 13(i)) about 100 ns after receiving the low level of the node ND3. The DRAM enters the low power consumption mode.
• Thus, the DRAM enters the low power consumption mode by the command input. At this time, the inverter of thelevel shifter56 shown inFIG. 12 receives the power supply voltage VDD in place of the internal supply voltage VII. As a result, thelevel shifter56 is prevented to have the leak path because the gate of the nMOS is reliably switched off.
• When the low power consumption mode is released, the CE1X signal is first turned to the high level (FIG. 13(j)). Thecombinational circuit60 receives the high level of the CE1X signal to turn the node ND3 to the high level (FIG. 13(k)) and the ULP signal to the low level (FIG. 13(l)). 200 us after the rising edge of the CE1X signal, the CE2Z signal is turned to the high level (FIG. 13(m)). In response to the high level of the CE2Z signal, a level of the node ND1 turns to the high level. During this period of 200 μs, theinternal voltage generator18 is activated to stabilize the individual internal voltages VPP, VPR, VII and VBB at predetermined levels.
• Here, the activations and inactivations of theinternal voltage generator18 are performed as in the first embodiment. Specifically, the controls of the individual circuits in this embodiment are identical to those of the first embodiment excepting that the entry to and exit from the low power consumption mode are executed by the command inputs.
• This embodiment can achieve effects similar to those of the foregoing first embodiment. In this embodiment, moreover, the DRAM can enter the low power consumption mode and can be released from the low power consumption mode by the command inputs using the /CE1 signal and the CE2 signal.
• FIG. 14 shows a third embodiment of the semiconductor memory device of the present invention. The same circuits as those described in the first and second embodiments are designated by the common reference numerals, and their detailed description will be omitted.
• In this embodiment, a lowpower entry circuit62 receives the low power consumption mode signal /LP. This low power consumption mode signal /LP is a signal dedicated for the DRAM to enter the low power consumption mode. The lowpower entry circuit62 detects the falling edge of the /LP signal to bring the DRAM into the low power consumption mode. Thecommand decoder52 is supplied with the /CE1 signal, the CE2 signal and another control signal CN. The remaining constructions are similar to those of the foregoing first embodiment.
• The operation timings of the DRAM at the switch-on of the power supply and at the entry into and the exit from the low power consumption mode according to this embodiment are identical to those of the case in which the CE2 signal is replaced by the /LP signal in the timing chart shown inFIG. 7.
• This embodiment can also achieve effects similar to those of the foregoing first embodiment. In this embodiment, moreover, the DRAM can reliably enter the low power consumption mode and be released from the mode by the dedicated low power consumption mode signal /LP.
• FIGS. 15 and 16 show a VII starter in a fourth embodiment of the semiconductor memory device and a third embodiment of its control method of the present invention. The same circuits as those described in the first embodiment are designated by the common reference numerals, and their detailed description will be omitted.
• In this embodiment, aVII starter70 is formed in replace of theVII starter10 inFIG. 3 (the first embodiment). The other configuration is identical to that inFIG. 3. In other words, the DRAM of this embodiment similar to that ofFIG. 7 enters the low power consumption mode by turning the CE2 signal to low level during a high-level period of the /CE1 signal and it is released from the low power consumption mode by turning the CE2 signal to high level.
• TheVII starter70 comprises arelease detecting circuit72 shown inFIG. 15, alevel detecting circuit74, and a power-oncircuit76 shown inFIG. 16. InFIGS. 15 and 16, a logic circuit is supplied with a power supply voltage VDD except the circuit with a power supply voltage indicated.
• Arelease detecting circuit72 comprises a detectingcircuit72a, alevel shifter72b, and a flip-flop72c. The detectingcircuit72areceives a low power signal ULP shown inFIG. 3 and outputs the low level of a pulse LPLS in synchronization with the falling edge of the ULP signal. Thelevel shifter72bconverts the high level voltage (internal power supply voltage VII) of a row address strobe signal RASZ to the external power supply voltage VDD and outputs a row address strobe signal RASX1 having inverted logic. Thelevel shifter72bis identical to thelevel shifter56 shown inFIG. 12. Receiving a low pulse from the detectingcircuit72a, the flip-flop72cturns a release signal REL to high level, and receiving a low level (RASZ=high level) from thelevel shifter72b, it turns the release signal REL to low level.
• InFIG. 16, alevel detecting circuit74 comprises adifferential amplifier74aincluding a current mirror circuit and aninverter row74bwhich includes an odd number of inverters and receives the output of thedifferential amplifier74a. Thedifferential amplifier74ais activated during the high level of the release signal REL, compares an internal power supply voltage VII with a reference voltage VREF, and outputs the comparison result to aninverter row74b. A generator for the internal power supply voltage VII generates a constant value of the internal power supply voltage VII independent of the fluctuation of the power supply voltage VDD supplied from the exterior. On the other hand, the reference voltage VREF varies depending on the fluctuation of the power supply voltage VDD.
• The output voltage of thedifferential amplifier74agoes low when the internal power supply voltage VII is lower than the reference voltage VREF. Thedifferential amplifier74acomprises aMOS capacitor74cfor receiving the reference voltage VREF in order to prevent its response to insignificant fluctuation of the reference voltage VREF. In addition, annMOS74dfor receiving the reference voltage VREF is disposed on a path to a ground line VSS in order to limit the amount of current flow to the ground line VSS and reduce the power consumption during the operation of thedifferential amplifier74a. ThenMOS74doperates as high-resistance. Aninverter74ein the initial stage of theinverter row74bhas an nMOS connected in serial so as to have the logic threshold of an input signal in conformity with the output of thedifferential amplifier74a.
• A power-oncircuit76 turns a start signal STT to high level during a predetermined period since the power supply voltage is supplied to the DRAM. An ORcircuit78, upon receiving the high level of a start signal STTPZ or the high level of the start signal STT, outputs the high level of a start signal511 VII (reset signal). The start signal STTVII, similarly to that ofFIG. 3, is supplied to themain circuit unit20 and initializes a predetermined internal circuit.
• FIG. 17 shows the operation timings of the above-described DRAM at the time of entry to and exit from the low power consumption mode.
• Firstly, when the CE2 signal (not shown) is turned to low level, the DRAM enters the low power consumption mode by a lowpower entry circuit14 shown inFIG. 3 and a generator for the internal power supply voltage VII terminates its operation. The internal power supply voltage VII (for example, 2.0V in a normal operation) becomes equal to the power supply voltage VDD (for example, 2.5V)(FIG. 17(a)) and an ULP signal turns to high level (FIG. 17(b)).
• Subsequently, the CE2 signal being turned to high level, the DRAM is released from the low power consumption mode and the ULP signal turns to low level (FIG. 17(c)). In other words, the DRAM is released from the low power consumption mode in accordance with the level of the CE2 signal received during the low power consumption mode. The exit from the low power consumption mode is controlled by the lowpower entry circuit14 shown inFIG. 3.
• Receiving the falling edge of the ULP signal, the detectingcircuit72ainFIG. 15 turns an LPLS signal to low level (pulse) (FIG. 17(d)). Receiving the low level of the LPLS signal, the flip-flop72cinFIG. 15 turns the REL signal to high level (FIG. 17 (e)).
• Due to the exit from the low power consumption mode, a power supply line of the internal power supply voltage VII and that of the power supply voltage VDD are disconnected and simultaneously the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator (FIG. 17(f)). Thedifferential amplifier74ainFIG. 16 outputs low level to theinverter row74bwhen the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25V). Theinverter row74b, upon receiving the low level of thedifferential amplifier74a, outputs the high level of the STTPZ signal (FIG. 17(g)). The ORcircuit78, upon receiving the high level of the STTPZ signal, turns a start signal STTVII to high level. The start signal STTVII functions as a reset signal and a predetermined internal circuit of themain circuit unit20 shown inFIG. 3 is initialized.
• After the exit from the low power consumption mode, by issuing an operation command to the DRAM, the RASZ signal is turned to high level (FIG. 17(h)) and the REL signal to low level (FIG. 17(i)). Thedifferential amplifier74ais inactivated due to the low level of the REL signal.
• As described above, at the time of the exit from the low power consumption mode, the initialization of the internal circuit prevents it from malfunctioning when the operation of the internal circuit supplied with the internal power supply voltage VII cannot be ensured because of the internal power supply voltage VII lower than a predetermined voltage (reference voltage VREF).
• in this embodiment above, when the state of the CE2 signal received during the low power consumption mode indicates exit of the low power consumption mode, the low power consumption mode is released. This allows the easy exit of a chip from the low power consumption mode by the control signal from the exterior.
• At the exit from the low power consumption mode, the start signal STTVII which is a reset signal for initializing an internal circuit is activated during a period where the internal power supply voltage VII is lower than the reference voltage VREF. This makes it possible to securely reset the internal circuit and prevent the malfunction of the internal circuit when the low power consumption mode shifts to the normal operating mode.
• One control signal (CE2 signal) enables the entry of a chip to the low power consumption mode and the exit of a chip from the low power consumption mode.
• FIG. 18 shows alevel detecting circuit80 in a fifth embodiment of the semiconductor memory device and its control method of a fourth embodiment of the present invention. The same circuits as those described in the first and forth embodiments are designated by the common reference numerals, and their detailed description will be omitted.
• In this embodiment, alevel detecting circuit80 is formed in replace of thelevel detecting circuit74 described in the forth embodiment. The other configuration is identical to that in the forth embodiment.
• Thelevel detecting circuit80 comprises: adifferential amplifier80 for comparing the internal power supply voltage VII with the reference voltage VREF; aninverter row80bincluding an even number of inverters; adifferential amplifier80cfor comparing a boost voltage VPP of a word line (not shown) with the power supply voltage VDD from the exterior; aninverter row80dincluding an even number of inverters; and anNAND gate80e. The boost voltage VPP generated by a booster is formed inside of the chip. Thedifferential amplifiers80aand80care identical to thedifferential amplifier74ainFIG. 16 and are activated upon receipt of the high level of the REL signal. Theinverter rows80band80dare constructed of the inverter in the initial stage and the inverter in the second stage of theinverter row74binFIG. 16. Theinverter row80breceives the output of thedifferential amplifier80aand outputs the received logic level to aNAND gate80eas a start signal STT1X. Theinverter row80dreceives the output of thedifferential amplifier80cand outputs the received logic level to theNAND gate80eas a start signal STT2X. TheNAND gate80eoperates as an OR circuit of negative logic and outputs a start signal STTPZ.
• FIG. 19 shows the operation timings of the above-described DRAM at the time of entry to and exit from a low power consumption mode.
• Firstly, when the CE2 signal (not shown) is turned to low level, the DRAM enters the low power consumption mode and a generator for the internal power supply voltage VII and a generator for the boost voltage VPP terminate their operation. The internal power supply voltage VII (for example, 2.0V in the normal operation) and the boost voltage VPP (for example, 3.7V in the normal operation) become equal to the power supply voltage VDD (for example, 2.5V)(FIG. 19(a)) and an ULP signal turns to high level (FIG. 18(b)).
• Subsequently, the CE2 signal being turned to high level, the DRAM is released from the low power consumption mode and the ULP signal turns to low level (FIG. 19(c)). The LPLS signal is turned to low level (pulse) as well as inFIG. 17 (FIG. 19(d)) and the REL signal is turned to high level (FIG. 19(e)).
• Due to the exit from the low power consumption mode, the power supply line of the internal power supply voltage VII and the power supply line of the power supply voltage VDD are disconnected and the generator for the internal power supply voltage VII initiates its operation. The internal power supply voltage VII goes low for some time from the initiation of the generator (FIG. 19(f)). The low level of the STT1X signal is output during a period where the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25V) (FIG. 19(g)). Similarly, the connection between the power supply line of the boost voltage VPP and that of the power supply voltage VDD is disconnected and the generator for the boost voltage VPP initiates its operation. The boost voltage VPP goes low for some time from the initiation of the generator (FIG. 19(h)). The low level of the STT2X signal is output during a period where the boost voltage VPP is lower than the power supply voltage VDD (FIG. 19(i)).
• TheNAND gate80einFIG. 18 outputs the high level of the STTPZ signal during a period where the STT1X signal or the STT2X signal is at low level (FIG. 19(j)). During the high level of the STTPZ signal, the start signal STTVII (FIG. 16) is turned to high level. The start signal STTVII functions as a reset signal and initializes a predetermined internal circuit of themain circuit unit20 shown inFIG. 3.
• After the exit from the low power consumption mode, the DRAM initiates its operation, thereby the RASZ signal being turned to high level (FIG. 19(k)) and the REL signal to low level (FIG. 19(l)) as well as inFIG. 17. Thedifferential amplifier80aand80care inactivated due to the low level of the REL signal.
• This embodiment can also achieve effects similar to those of the foregoing fourth embodiment. In this embodiment, moreover, at the time of the exit from the low power consumption mode a start signal STTVII for initializing an internal circuit is activated during a period where the boost voltage VPP internally generated is lower than the power supply voltage VDD from the exterior. Specifically, at the time of the exit from the low power consumption mode, the start signal STTVII for initializing an internal circuit is activated during a period where at least one of the internal power supply voltage VII and is/are respectively lower than the reference voltage VREF and the power supply voltage VDD. This makes it possible to securely reset the internal circuit and prevent the malfunction of the internal circuit when the low power consumption mode shifts to the normal operating mode.
• FIG. 20 shows a start signal generator of the semiconductor memory device in a sixth embodiment and its control method of a fifth embodiment of the present invention. The same circuits as those described in the first and forth embodiments are designated by the common reference numerals, and their detailed description will be omitted.
• In the DRAM of this embodiment, astart signal generator82 is formed in replace of therelease detecting circuit72 and thelevel detecting circuit74 described in the forth embodiment. The other configuration is identical to that inFIG. 3 (the first embodiment).
• Thestart signal generator82 are constructed of aCMOS inverter82afor receiving a CE2X signal (internal signal) which is an inverted CE2 signal, aMOS capacitor82bconnected with the output of theCMOS inverter82a, and adifferential amplifier82cfor receiving the input of theCMOS inverter82aand the reference voltage VREF. Thedifferential amplifier82ccomprising a current mirror circuit, turns a start signal STTPZ to high level when the voltage of a node ND4 is lower than the reference voltage VREF.
• The pMOS of theCMOS inverter82ahas a long channel length to have high on-resistance. A CR time constant circuit is constructed of the pMOS of theCMOS inverter82aand theMOS capacitor82b. Utilizing the on-resistance of a transistor to construct the CR time constant circuit allows the layout to be reduced in size than the case of utilizing diffused resistance.
• FIG. 21 shows the operation timings of the above-described DRAM at the time of entry to and exit from the low power consumption mode.
• Firstly, when the CE2 signal (not shown) is turned to low level, the CE2X signal is turned to high level and the DRAM enters the low power consumption mode. A generator for the internal power supply voltage VII and a generator for the boost voltage VPP terminate their operation. TheCMOS inverter82ainFIG. 20 upon receiving the high level of the CE2X signal, turns the nMOS on and a node ND4 to low level (FIG. 21(a)). Thedifferential amplifier82cturns a STTPZ signal to high level when the voltage of the node ND4 is lower than the reference voltage VREF (FIG. 21(b)).
• Subsequently, the CE2 signal being turned to high level and the CE2X signal to low level, the DRAM is released from the low power consumption mode (FIG. 21(c)). TheCMOS inverter82 inFIG. 20 upon receiving the low level of the CE2X signal, turns the pMOS on and the node ND4 to high level (FIG. 21 (d)). At this time the voltage of the node ND4 gradually rises in accordance with the time constant determined by the on-resistance of the pMOS and the CMOS capacitor. Thedifferential amplifier82cturns the STTPZ signal to low level when the voltage of the node ND4 is higher than the reference voltage VREF (FIG. 21(e)).
• Consequently, the STTPZ signal (reset signal) is activated (high level) and the internal circuit is initialized during a period T2 from the exit from the low power consumption mode. The period T2 is set after the exit from the low power consumption mode in correspondence with a period where the internal power supply voltage VII is lower than a predetermined voltage so that the operation of the internal circuit supplied with the internal power supply voltage VII can not be ensured. In other words, thestart signal generator82 operates as a timer for determining the length of the period T2.
• This embodiment can also achieve effects similar to those of the foregoing fourth embodiment. In this embodiment, moreover, at the time of the exit from the low power consumption mode thestart signal generator82 is operated as a timer to generate the STTPZ signal and the internal circuit is initialized during the period T2 after the exit from the low power consumption mode. This makes it possible to reliably reset the internal circuit and prevent the malfunction of the internal circuit when the low power consumption mode shifts to the normal operating mode.
• Since thestart signal generator82 is operated as a CR time constant circuit, it is possible to set the period T2 based on the propagation delay time of a signal propagated to the CR time constant circuit. This makes it possible to set a period necessary for resetting the internal circuit by a simple circuit.
• The on-resistance of the pMOS is utilized to form the CR time constant circuit so that the layout of thestart signal generator82 can be reduced in size.
• FIG. 22 shows a seventh embodiment of a semiconductor memory device and a method of controlling the same in the present invention. Here, the same circuits as those described in the first embodiment will not be described in detail by designating them by the common reference numerals.
• In this embodiment, the DRAM includes theVII starter10, theVDD starter12, a lowpower entry circuit84, thecommand decoder16, aninternal voltage generator86 and amain circuit unit88. Theinternal voltage generator86 has the low-pass filter22, thereference voltage generator24, aVPP detector90, abooster92, aprecharging voltage generator94, an internalsupply voltage generator96, aVBB detector98 and asubstrate voltage generator100. Themain circuit unit88 has thememory core38, theperipheral circuit40, afrequency divider102 and anoscillator104. Thesefrequency divider102 andoscillator104 are control circuits for generating timing signals to execute the refresh operations automatically in the self-refresh mode.
• FIG. 23 shows the detail of thereference voltage generator24.
• Thereference voltage generator24 is provided with areference voltage generator24afor generating a reference voltage VREF, astarter24bconsisting of pMOS, adifferential amplifier24c, and aregulator24d.
• Thereference voltage generator24ahas a current mirror circuit made of a pMOS, two nMOSes connected individually in series with the current mirror circuit, and a register connected between the source of one of the nMOSes and the ground line VSS. The output of thereference voltage generator24ais connected with the gate of one nMOS and the drain of the other nMOS, from which the reference voltage VREF is generated. The gate of the other nMOS is connected with the source of the one nMOS.
• Thestarter24braises the reference voltage VREF to the high level while the start signal STTCRX is activated after the power-on.
• Thedifferential amplifier24chas a current mirror part made of pMOSes, a differential input part made of nMOSes and an nMOS supplying the gate with reference voltage and connecting the differential input part with the ground line VSS. The one nMOS of the differential input part is supplied at its gate with the reference voltage VREF, and the other nMOS is supplied at its gate with the reference voltage VRFV.
• Theregulator24dis constructed by connecting a pMOS and five resistors in series between the power supply line VDD and the ground line VSS. From the connection nodes of the individual elements, there are individually outputted reference voltages VRFV, VPREF, VPRREFL and VPRREFH. With the two terminals of the resistor connected with the ground line VSS, there are connected the source and drain of the nMOS which is controlled by a low power signal NAPX. The resistor, as connected with the ground line VSS, is bypassed when the low power signal NAPX is activated (to a low level). During the low power consumption mode, therefore, the levels (absolute values) of the reference voltages VRFV, VPREF, VPRREFL, and VPRREFH vary, thereby lowering the voltages, compared with the normal operation mode.
• FIG. 24 shows the detail of the internalsupply voltage generator96.
• This internalsupply voltage generator96 is constructed by eliminating theswitch circuit32eand thenMOS32dfrom the VII internalsupply voltage generator32 of the first embodiment shown inFIG. 5 and by adding a stabilizedcapacitor96a, aswitch96b, and annMOS96c. The stabilizedcapacitor96astores a portion of the electric charge supplied to the internal power supply line VII to reduce the shift of the power supply voltage VII, as might otherwise be caused by the power supply noise. Theswitch96bis formed of a CMOS transmission gate, for example. ThenMOS96c, as arranged between the internal power supply line VII and the ground line VSS, is supplied at its gate with the inverted logic of the low power signal NAPX through an inverter.
• Theswitch96bis turned off, when the low power signal NAPX is activated, to disconnect theregulator32cand the internal circuit. At this time, thenMOS96cis turned off so that the internal power supply line VII drops to the ground voltage (0 V). The power supply voltage VII is not supplied to the internal circuit so that the leakage current of the transistor or the like in the internal circuit does not occur during the power consumption mode. Specifically, the power consumption of the internal circuit can be lowered to zero. At this time, the connection between theregulator32cand the stabilizedcapacitor96ais kept so that the stabilizedcapacitor96astores the electric charge as in the normal operation.
• After the low consumption mode is released, theswitch96bis turned on when the low power signal NAPX is inactivated. Simultaneously with this, thenMOS96cis turned off to connect theregulator32cand the internal circuit. At this time, not only the electric charge supplied from theregulator32cbut also the electric charge stored in the stabilizedcapacitor96ais supplied to the internal power supply line VII so that this internal power supply voltage VII is raised and supplied to the internal circuit. As a result, this internal circuit can be operated immediately after the low power consumption mode is released.
• FIG. 25 shows thebooster92, theVPP detector90, thesubstrate voltage detector100 and theVBB detector98.
• Thebooster92 is provided with anoscillator106 to be operated when a boost enable signal VPPEN is activated, and a plurality ofunits108 and110. Theunit108 receives pulse signals PLS1-PLS6 from theoscillator106 to generate the boost voltage VPP when the low power signal NAPX is activated. Theunit110 generates the boost voltage VPP at all times in response to the pulse signals PLS1-PLS6 from theoscillator106, irrespective of the low power signal NAPX. On the basis of the activation of the low power signal NAPX, theunit108 stops its operation so that the power consumption of thebooster92 is lowered during the power consumption mode. In this low power consumption mode, the refreshing operation is not executed so that no problem arises even if the drivability of thebooster92 drops, as will be described hereinafter. The number of theunits110 to be operated at all times irrespective of the operation mode is determined according to the time period (i.e., the timing specification) till the normal operation or the refreshing operation is executed after the return from the low power consumption mode.
• Thesubstrate voltage generator100 is provided with a plurality ofunits112 to be operated by activating a substrate voltage detection signal VBBDET and inactivating the low power signal NAPX, and a plurality ofunits114 to be operated by activating the substrate voltage detection signal VBBDET. When the operations of theunits112 are stopped on the basis of the activation of the low power signal NAPX, the power consumption of thesubstrate voltage generator100 drops during the power consumption mode. The number of theunits114 to be operated at all times irrespective of the operation mode is determined according to the time period (i.e., the timing specification) after the return from the low power consumption mode to the execution of the normal operation or the refreshing operation.
• FIG. 26 shows the detail of theunit108 of thebooster92.
• Thisunit108 has fourcapacitors108a,108b,108cand108deach made of an nMOS, andpMOSes108eand108fto operate as switches. Thecapacitors108a,108b,108cand108dreceive the inverted logics of pulse signals PLS1, PLS2, PLS3 and PLS4, respectively, at their one-side terminals when the low power signal NAPX is inactivated. The other terminals of thecapacitors108a-108dare connected with the power supply line VDD through a plurality of diode-connected nMOSes. The gates of thepMOSes108eand108freceive pulse signals PLS5 and PLS6, respectively, at their gates through the logic gates when the low power signal NAPPX is inactivated.
• The pulse signals PLS1, PLS2 and PLS5 and the pulse signals PLS3, PLS4 and PLS6 are in opposite phases to each other. The high-level voltages of the low power signal NAPX and the pulse signals PLS5 and PLS6 are so equalized to the boost voltage VPP as to turn off thepMOSes108eand108freliably.
• Thecapacitors108aand108b, and108cand108dare alternately charged and discharged in response to the pulse signals PLS1, PLS2, PLS3 and PLS4 inputted. ThepMOSes108eand108fare alternately turned on in synchronization with the pumping operations of thecapacitors108aand108b, and thecapacitors108cand108d. By these pumping operations, moreover, the power supply voltage VDD is boosted to the boost voltage VPP. Theunit108 stops its operation when the low power signal NAPX is activated.
• FIG. 27 shows the detail of theunit110 of thebooster92.
• Thisunit110 is a circuit which is made by eliminating the logics of the low power signals NAPX and NAPPX from theunit108. In other words, theunit110 operates at all times after the power supply on to generate the boost voltage VPP.
• FIG. 28 shows the detail of theVPP detector90.
• ThisVPP detector90 is provided with adifferential amplifier90aand avoltage generator90bfor supplying its voltage to one input of thedifferential amplifier90a.
• Thisdifferential amplifier90ahas acurrent mirror part90ccomposed of pMOSes, and a pair ofdifferential input parts90dand90ecomposed of nMOSes. Both the inputs of thedifferential input parts90dand90ereceive the reference voltage VPREF and a control voltage VPP2 which is generated by shifting the level of the boost voltage VPP from thevoltage generator90b. Thedifferential input part90dis connected with the ground line VSS through the nMOS which is always on, and thedifferential input part90eis connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
• In short, thedifferential input part90doperates at all times, and thedifferential input part90eoperates only when the low power signal NAPX is inactivated. During the low power consumption mode, thedifferential input part90estops its operation so that the power consumption is reduced. Thedifferential amplifier90aactivates the boost enable signal (to the high level) when the control voltage VPP2 is lower than the reference voltage VPREF.
• Thevoltage generator90bis constructed by connecting three resistors in series between the node for generating the boost voltage VPP and the ground line VSS. The control voltage VPP2 is outputted from the other terminal of the resistor on the side of the node for supplying the boost voltage VPP. With the two terminals of the resistor connected with the ground line VSS, there are individually connected the source and the drain of the nMOS which is controlled with the low power signal NAPX. The resistor connected with the ground line VSS is bypassed when the low power signal NAPX is activated. During the low power consumption mode, therefore, the level of the control voltage VPP2 drops.
• FIG. 29 shows the detail of theunit112 of thesubstrate voltage generator100.
• Thisunit112 is provided with anoscillator112aand apumping circuit112b.
• Theoscillator112ais constructed as a ring oscillator composed of odd stages of logic gates. Theoscillator112aoperates when the substrate voltage detection signal VBBDET is activated but when the low power signal NAPX is inactivated.
• Thepumping circuit112bincludes avoltage supplying part112chaving three pMOSes and one nMOS connected in series between the power supply line VDD and the pumping node PND, acapacitor112dcomposed of a pMOS connected at its gate with the pumping node PND, annMOS112efor connecting the pumping node PND and the ground line VSS when the pumping node PND is at the high level, and a diode-connectednMOS112ffor connecting the pumping node PND and the substrate node VBB.
• In thepumping circuit112b, the pumping node PND interchangeably has the ground voltage and a negative voltage when the pMOSes and nMOS of thevoltage supplying part112cand thecapacitor112dreceive the clock signal from theoscillator112a. When the pumping node PND has a negative voltage, moreover, the electric charge of the substrate node VBB is pumped out to set the substrate node VBB to a negative voltage. Theunit112 stops its operation during the power consumption mode (while the low power signal NAPX is active).
• FIG. 30 shows the detail of theunit114 of thesubstrate voltage generator100.
• Thisunit114 is provided with anoscillator114aand apumping circuit114b.
• Theoscillator114ais a circuit which is made by eliminating the logic of the low power signal NAPX from theoscillator112aof theunit112. In short, theoscillator114aoperates in response to the substrate voltage detection signal VBBDET even during the power consumption mode to generate the substrate voltage VBB. Thepumping circuit114bis a circuit identical to thepumping circuit112bof theunit112.
• FIG. 31 shows the detail of theVBB detector98.
• ThisVBB detector98 is provided with twodetection units98aand98b, and anOR circuit98cfor outputting the OR logic of the detection results of thoseunits98aand98bas the substrate voltage detection signal VBBDET.
• Thedetection unit98aincludes: a referencevoltage generating part98dhaving a resistor; a pMOS and a resistor connected in series between the internal power supply line VII and the ground line VSS; alevel detecting part98ehaving two nMOSes connected in series; aCMOS inverter98fhaving a pMOS connected with the power supply line VII through a pMOS load circuit; and annMOS98gfor connecting the output node NOUT1 of thelevel detecting part98fwith the ground line VSS. The gate of the pMOS of the referencevoltage generating part98dand the gate of thenMOS98greceive the low power signal NAPX. Therefore, thedetection unit98ais inactivated in the normal operation mode but is activated during the power consumption mode. The voltage of the output node NOUT1 of thelevel detecting part98erises, when activated, with the rise of the substrate voltage VBB. In this embodiment, theCMOS inverter98foutputs the low level in response to the detection result (i.e., the voltage of the output node NOUT1) at thelevel detecting part98dwhen the substrate voltage VBB is boosted to −0.5 V. The ORcircuit98cactivates the substrate voltage detection signal VBBDET when it receives the low level from theCMOS inverter98f.
• In thedetection unit98b, the gate of the pMOS of the referencevoltage generating part98dand the gate of thenMOS98gare supplied with the inverted logic of the low power signal NAPX. The remaining constructions are identical to those of thedetection unit98a. In this embodiment, theCMOS inverter98foutputs the low level in response to the detection result at thelevel detecting part98e(i.e., the voltage of the output node NOUT1) when the substrate voltage VBB rises to −1.0 V in the normal operation mode. The output of the referencevoltage generating part98dof thedetection unit98bhas the ground voltage VSS (at 0 V) when the low power signal NAPX is at the low level (during the power consumption mode). Therefore, the output node NOUT2 of thelevel detecting part98ehas the low level at all times. In short, thedetection unit98bis inactivated during the power consumption mode.
• Therefore, theVBB detector98 uses only thedetection unit98bin the normal operation mode and activates the substrate voltage detection signal VBBDET when the substrate voltage VBB rises to −1.0 V. When the substrate voltage detection signal VBBDET is activated, theunits112 and114 of the substratevoltage generating circuit100, as shown inFIGS. 29 and 30, operate so that the substrate voltage VBB drops.
• During the low power consumption mode, on the other hand, theVBB detector98 activates thedetection unit98abut inactivates thedetection unit98bwhen the low power signal NAPX is activated. As a result, the power consumption of theVBB detector98 is reduced. The level of the substrate voltage VBB is detected during the power consumption mode only by thedetection unit98aso that the substrate voltage detection signal VBBDET is activated when the substrate voltage VBB rises to −0.5 V. The detection level (in an absolute value) of the substrate voltage VBB becomes low so that the absolute value of the substrate voltage VBB to be generated by thesubstrate voltage generator100 is reduced. In other words, the operation of thesubstrate voltage generator100 is further suppressed during the power consumption mode than during the normal operation mode. As a result, the power consumption can be reduced. The difference between the substrate voltage VBB and the ground voltage VSS is decreased, thereby reducing the substrate leakage. Therefore, the occurrence frequency of the substrate voltage detection signal VBBDET is lowered to decrease the operation frequency of thesubstrate voltage generator100. As a result, the power consumption can be further reduced.
• FIG. 32 shows the detail of theprecharging voltage generator94.
• Thisprecharging voltage generator94 is provided withdifferential amplifiers94aand94band aVPR generator94c.
• Thedifferential amplifier94ahas acurrent mirror part94dcomposed of pMOSes, and a pair ofdifferential input parts94eand94fcomposed of nMOSes. Both the inputs of thedifferential input parts94eand94freceive the reference voltage VPRREFL and the precharging voltage VPR. Thedifferential input part94eis connected with the ground line VSS through the always on nMOS, and thedifferential input part94fis connected with the ground line VSS through the nMOS which is turned on when the low power signal NAPX is inactivated.
• In short, thedifferential input part94eoperates at all times, but thedifferential input part94foperates only when the low power signal NAPX is inactivated. Thedifferential input part94fstops its operation during the power consumption mode so that the power consumption is reduced. Thedifferential amplifier94asets the output node NOUT3 to the low level when the reference voltage VPRREFL is higher than the precharging voltage VPR.
• Thedifferential amplifier94bhas acurrent mirror part94gcomposed of nMOSes, and a pair ofdifferential input parts94hand94icomposed of pMOSes. Both the inputs of thedifferential input parts94hand94ireceive the reference voltage VPRREFH and the precharging voltage VPR. Thedifferential input part94gis connected with the power supply line VDD through the always on pMOS, and thedifferential input part94iis connected with the power supply line VDD through the pMOS which is turned on when the low power signal NAPX is inactivated.
• Thedifferential input part94hoperates at all times, but thedifferential input part94ioperates only when the low power signal NAPX is inactivated. During the low power consumption mode, thedifferential input part94istops its operation so that the power consumption is reduced. Thedifferential amplifier94bsets the output node NOUT4 to the low level when the reference voltage VPRREFH is lower than the precharging voltage VPR.
• TheVPR generator94chas a pMOS and an nMOS connected in series between the power supply line VDD and the ground line VSS. The gate of the pMOS connects the output node NOUT3. The gate of the nMOS connects the output node NOUT4. From the drains of the pMOS and the nMOS, there is outputted the precharging voltage VPR. This precharging voltage VPR is used as the equalizing voltage of the paired bit lines and the plate voltage of the memory cells in thememory core38.
• The inactivation of thedifferential input parts94fand94iduring the power consumption mode deteriorates the response of theprecharging voltage generator94 to a shift in the precharging voltage. As will be described hereinafter, however, the reading operation and the refreshing operation are not executed during the power consumption mode so that no problem arises even if the response of theprecharging voltage generator94 is lowered.
• FIG. 33 shows the detail of theoscillator104.
• Thisoscillator104 is provided with aring oscillator104ahaving odd stages of CMOS inverters connected in cascade, and abuffer104bfor extracting an oscillating signal OSCZ from thering oscillator104a. Frames of broken lines inFIG. 33 are switches for adjusting the stage number (corresponding to the self-refreshing period) of thering oscillator104a. The on/off of these switches are set by the blow of the polysilicon fuse or by the layout pattern of the photomask of the wiring layer. In this example, the stage number of thering oscillator104ais set to “7”. The sources of the pMOSes and the nMOSes of the CMOS inverters are connected with the internal power supply line VII and the ground line VSS, respectively, through the pMOS loads and the nMOS loads. The gates of the pMOS loads and the nMOS loads are controlled with the control voltages PCNTL and NCNTL, respectively. Theoscillator104 has pMOSes and nMOSes for receiving the control of the low power signal NAPX. When the low power signal NAPX is activated, those pMOSes are turned on to fix the predetermined is node of thering oscillator104ato the high level, but the connections between the nMOSes of the CMOS inverters and the ground line VSS are broken when those nMOSes are turned off. As a result, theoscillator104 stops its operation during the power consumption mode.
• FIG. 34 shows agenerator116 formed in theoscillator104 for generating the control voltages PCNTL and NCNTL.
• Thisgenerator116 is provided with: a pMOS, a pMOS diode and a resistor connected in series between the internal power supply line VII and the ground line VSS; a resistor, an nMOS diode and an nMOS connected in series between the internal power supply line VII and the ground line VSS; a MOS capacitor arranged between a node for generating the control voltage PCNTL and the internal power supply line VII; and a MOS capacitor arranged between a node for generating the control voltage NCNTL and the ground line VSS.
• The control voltage PCNTL is generated from the connection node between the pMOS diode and the resistor, and varies with the shift of the internal power supply voltage VII. The control voltage NCNTL is generated from the connection node between the nMOS diode and the resistor, and varies with the shift of the ground voltage VSS. Therefore, the gate-to-source voltage of the pMOS and the nMOS of the CMOS inverter shown inFIG. 33 is always constant so that the oscillation period of thering oscillator104ais constant irrespective of the shift of the internal power supply voltage VII. The MOS capacitor prevents the high-frequency noises to occur on the internal power supply line VII and the ground line VSS from influencing the control voltage PCNTL and the control voltage NCNTL. As a result, the shifts of the internal power supply voltage VII and the ground voltage VSS are canceled so that the oscillating signal OSCZ is generated always for a predetermined period while theoscillating circuit104 is active (in the self-refreshing mode).
• The pMOS and the nMOS are turned off when the low power signal NAPX is active. In other words, thegenerator116 is inactivated during the power consumption mode. At this time, the control voltages PCNTL and NCNTL turns to the low level and the high level, respectively.
• In the DRAM thus far described, like the first embodiment, the lowpower entry circuit84 shown inFIG. 22 activates the low power signal NAPX (to the low level) to enter the chip to the low power consumption mode when it receives the chip enable signal CE2 at the low level from the exterior.
• When the low power signal NAPX is activated, thereference voltage generator24 shown inFIG. 23 lowers the levels of the reference voltages VRFV, VPREF, VPREFL and VPREFH. TheVPP detector90 shown inFIG. 28 inactivates thedifferential input part90eand simultaneously lowers the level of the control voltage VPP2 to be supplied to thedifferential input part90d. Theunit108 of thebooster92, as shown inFIG. 25, and theunit112 of thesubstrate voltage generator100 stop their operations. TheVBB detector98 shown inFIG. 31 inactivates thedetection unit98bbut activates thedetection unit98ato raise the detection level of the substrate voltage VBB. Specifically, the substrate voltage detection signal VBBDET is activated when the substrate voltage VBB rises to −0.5 V. Thedifferential amplifiers94aand94bof theprecharging voltage generator94 shown inFIG. 32 inactivate thedifferential input parts94fand94i, respectively. Theoscillator104 shown inFIG. 33 stops its operation. Thegenerator116 shown inFIG. 34 is inactivated.
• FIG. 35 shows the operations of theoscillator104 and thefrequency divider102.
• When the low power signal NAPX is activated, theoscillator104 sets the oscillating signal OSCZ to the low level. Since the oscillating signal OSCZ stops its oscillation, the frequency division by thefrequency divider102 stops so that the self-refreshing timer signal SRTZ turns to the low level. Therefore, the power consumption of thefrequency divider102 is substantially zero.
• Thus, the plurality of control circuits suspends their operations or lower detection capability of signal level, thereby substantially reducing the power consumption during the low power consumption mode, compared to the conventional art. Some of the control circuits continue their operations in the low detection state so that the normal operation can be started immediately after the release from the low power consumption mode.
• In this embodiment, theoscillator104 for self-refresh is stopped during the power consumption mode to stop operations performed in the self-refreshing mode, as has been described above. As a result, the power consumption during the power consumption mode can be reduced.
• Since the refreshing operation is not executed, theinternal voltage generator86 may be operated with a power enough to compensate the electric power (the leakage current) to be consumed by theperipheral circuit40. As a result, the power consumption during the power consumption mode can be reduced.
• The internal voltages VPP, VBB and VPR are supplied to the internal circuit (including theperipheral circuit40, thememory core38, and the like) even during the power consumption mode. Therefore, theperipheral circuit40, thememory core38, and the like can be operated just after the release from the low power consumption mode.
• During the low power consumption mode, the operations of theunit108 of thebooster92 and theunit112 of thesubstrate voltage generator100 are stopped so that the power consumption during the power consumption mode can be further reduced.
• During the low power consumption mode, the connection between the internal power supply line VII and the stabilizedcapacitor96ais kept, and the connection between the internal power supply line VII and the internal circuit (theperipheral circuit40 and the memory core38) is broken. The power supply to theperipheral circuit40 is stopped so that the leakage current to theperipheral circuit40 can disappear to reduce the power consumption to zero. When the internal power supply line VII and the internal circuit are connected after the release from the low power consumption mode, the voltage corresponding to the electric charge stored in the stabilizedcapacitor96ais supplied to the internal circuit through the internal power supply line VII. Before the internalsupply voltage generator96 generates a predetermined internal power supply voltage VII after the release from the low power consumption mode, therefore, the voltage corresponding to the electric charge stored in the stabilizedcapacitor96acan be applied to the internal circuit. As a result, the internal circuit can operate immediately after the release from the low power consumption mode.
• During the low power consumption mode, thedifferential input part90ein thedifferential amplifier90aof theVPP detector90 and thedifferential input parts94fand94iin thedifferential amplifiers94aand94bof theprecharging voltage generator94 are inactivated so that the power consumption of thedifferential amplifiers90a,94a, and94bcan be reduced.
• During the low power consumption mode, the operations of theunit108 of thebooster92 and theunit112 of thesubstrate voltage generator100 are stopped, so that the transient dispersions of the boost voltage VPP and the substrate voltage VBB are suppressed. In other words, the difference between the maximum and the minimum of the boost voltage VPP and the substrate voltage VBB can be decreased to reduce the leakage current.
• By lowering the levels of the reference voltages VPREF, VRFV (VII), VPRREFH and VPRREFL to be generated by thereference voltage generator24, the absolute values of the detection levels of theVPP detector90, theVBB detector98 and theprecharging voltage generator94 are reduced, and the levels (in absolute values) of the boost voltage VPP, the substrate voltage VBB and the precharging voltage VPR to be generated by theprecharging voltage generator94 are reduced. Since the voltages are lowered, the leakage current can be reduced to lower the power consumption.
• In the embodiment described above, the present invention is applied to the DRAM. However, the present invention is not limited to this embodiment. For example, the present invention may be applied to a semiconductor memory such as SDRAMs (Synchronous DRAMs), DDR SDRAMs (Double Data Rate SDRAMs), or FCRAMs (Fast Cycle RAMs).
• A semiconductor fabrication process to which the present invention is applied is not restricted to the CMOS process, but it may well be a Bi-CMOS process.
• The foregoing second embodiment has been described on an example in which the lowpower entry circuit50 is formed by connecting the plurality ofdelay circuits54cin series. However, the present invention should not be limited thereto but may form the low power entry circuit by using a latch circuit to be controlled by the STTCRX signal, for example. In this modification, the circuit scale is reduced.
• The foregoing third embodiment has been described on the example using the dedicated low power consumption mode signal /LP. This DRAM can be supplied even to the user requiring no low power consumption mode, for example, by pulling up the /LP signal on the chip and providing no terminal for the /LP signal. This /LP signal may be connected with the power supply voltage VDD by bonding or blowing the fuse. Alternatively, the /LP signal may be connected with the power supply voltage VDD by selecting photo masks of a wiring layer.
• The foregoing fifth embodiment has been described on an example of the comparison between the boost voltage VPP and the power supply voltage VDD. However, the present invention is not limited to this embodiment, for example, the boost voltage VPP may well be compared with the reference voltage VREF which is generated by stepping down the power supply voltage VDD.
• The foregoing sixth embodiment has been described on an example of operating thestart signal generator82 as a timer for determining the length of the period T2 at the exit from the low power consumption mode and activating a STTPZ signal (reset signal) for initializing an internal circuit during the period T2. The present invention is not limited to this embodiment. For example, at the time of the exit from the low power consumption mode, a counter operating in normal operation is operated as a timer so as to count a predetermined number. The reset signal for initializing an internal circuit may well be activated during a period where the counter counts the number. A refresh counter indicating the refresh address of memory cells or the like can be used as the counter.
• The invention is not limited to the above embodiments and various modifications may be made without departing from the spirit and the scope of the invention. Any improvement may be made in part or all of the components.

Claims (17)

1-6. (canceled)

7. A method of controlling a dynamic random access memory including dynamic memory cells, comprising:

generating a first command to put the dynamic random access memory in a low power consumption mode, the first command including a first combination of a plurality of control signals, in which the dynamic memory cells in the dynamic random access memory do not retain data therein by stopping an operation of an internal voltage generator configured to supply an internal voltage to the dynamic memory cells in the low power consumption mode; and

generating a second command to put the dynamic random access memory out of the low power consumption mode, the second command including a second combination of the plurality of control signals,

wherein the dynamic random access memory continues to be supplied with a power supply voltage in the low power consumption mode.

8. The method of controlling the dynamic random access memory according toclaim 7, further comprising

keeping at least one signal of the plurality of control signals to a first voltage to maintain the low power consumption mode after the generating the first command.

9. The method of controlling the dynamic random access memory according toclaim 7, further comprising

waiting for completion of initialization of the dynamic random access memory during a first period after the generating the second command, the initialization being performed in response to the second command.

10. The method of controlling the dynamic random access memory according toclaim 9, wherein

the internal voltage supplied to the dynamic memory cells in response to the second command is stabilized by the initialization.

11. The method of controlling the dynamic random access memory according toclaim 9, wherein

the first period is equal to or more than 200 micro seconds.

12. A method of controlling a dynamic random access memory including dynamic memory cells, comprising:

generating a first command to put the dynamic random access memory in a low power consumption mode, the first command including first combination of a plurality of control signals, in which the dynamic memory cells in the dynamic random access memory do not retain data therein by stopping a supply of an internal voltage in the low power consumption mode; and

generating a second command to put the dynamic random access memory out of the low power consumption mode, the second command including a second combination of the plurality of control signals,

wherein the dynamic random access memory continues to be supplied with a power supply voltage in the low power consumption mode.

13. The method of controlling the dynamic random access memory according toclaim 12, further comprising

keeping at least one of the plurality of control signals to a first voltage to maintain the low power consumption mode after the generating the first command.

14. The method of controlling the dynamic random access memory according toclaim 12, further comprising

waiting for completion of initialization of the dynamic random access memory during a first period after the generating the second command, the initialization being performed in response to the second command.

15. The method of controlling the dynamic random access memory according toclaim 14, further comprising

generating the internal voltage by an internal voltage generator in response to the second command, in which the internal voltage is stabilized by the initialization.

16. The method of controlling the dynamic random access memory according toclaim 14, wherein

the first period is equal to or more than 200 micro seconds.

17. A memory system comprising:

a dynamic random access memory including dynamic memory cells;

a memory bus; and

a CPU coupled to the dynamic random access memory through the memory bus and configured to control the dynamic random access memory,

wherein the CPU

generates a first command to put the dynamic random access memory in a low power consumption mode, the first command including a first combination of a plurality of control signals, in which the dynamic memory cells in the dynamic random access memory do not retain data therein by stopping a supply of an internal voltage in the low power consumption mode, and

generates a second command to put the dynamic random access memory out of the low power consumption mode, the second command including a second combination of the plurality of control signals, and

wherein the dynamic random access memory continues to be supplied with a power supply voltage in the low power consumption mode.

18. The memory system according toclaim 17, wherein

the CPU controls a non-volatile memory including flash memory cells through the memory bus.

19. The memory system according toclaim 17, wherein

the CPU keeps at least one signal of the plurality of control signals to a first voltage to maintain the low power consumption mode after the generating the first command.

20. The memory system according toclaim 17, wherein

the CPU waits for completion of initialization of the dynamic random access memory during a first period after the generating the second command, the initialization being performed in response to the second command.

21. The memory system according toclaim 20, wherein

the internal voltage supplied to the dynamic memory cells in response to the second command is stabilized by the initialization.

22. The memory system according toclaim 20, wherein

the first period is equal to or more than 200 micro seconds.

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