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US20130140067A1 - Wafer or circuit board and joining structure of wafer or circuit board - Google Patents

Wafer or circuit board and joining structure of wafer or circuit board
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Publication number
US20130140067A1
US20130140067A1US13/683,252US201213683252AUS2013140067A1US 20130140067 A1US20130140067 A1US 20130140067A1US 201213683252 AUS201213683252 AUS 201213683252AUS 2013140067 A1US2013140067 A1US 2013140067A1
Authority
US
United States
Prior art keywords
melting point
metal
protrusion
conductive film
joining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/683,252
Inventor
Masakazu Ishino
Hiroaki Ikeda
Hideharu Miyake
Shiro Uchiyama
Hiroyuki Tenmei
Kunihiko Nishi
Yasuhiro Naka
Nae Hisano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PS4 Luxco SARL
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory IncfiledCriticalElpida Memory Inc
Priority to US13/683,252priorityCriticalpatent/US20130140067A1/en
Publication of US20130140067A1publicationCriticalpatent/US20130140067A1/en
Assigned to ELPIDA MEMORY INC.reassignmentELPIDA MEMORY INC.SECURITY AGREEMENTAssignors: PS4 LUXCO S.A.R.L.
Assigned to PS4 LUXCO S.A.R.L.reassignmentPS4 LUXCO S.A.R.L.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: ELPIDA MEMORY, INC.
Abandonedlegal-statusCriticalCurrent

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Abstract

A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion20 which is provided in low melting point metal15 for electrically connecting mutually joined wafers61 and62, and which defines an interval between mutually joined wafers61 and62 without being deformed at the time when low melting point metal15 is melted. A joining structure of wafers61 and62 is manufactured by using wafers61 and62, at least one of which has protrusion20. In the manufactured joining structure of wafers61 and62, wafers61 and62 are electrically connected to each other by low melting point metal15, and protrusion20, which defines the interval between wafers61 and62 without being deformed at the time when low melting point metal15 is melted, is provided in low melting point metal15.

Description

Claims (22)

What is claimed is:
1. A device, comprising:
a first substrate;
a first conductor penetrating the first substrate;
a first conductive film disposed on a first surface of the first substrate and electrically connected to the first conductor;
a first protrusion disposed on the first conductive film; and
a low-melting point metal disposed over the first conductive film,
wherein the first protrusion has a melting point higher than a melting point of the low-melting point metal.
2. The device according toclaim 1, further comprising a first metal, wherein
the first metal covers an upper surface and a side surface of the first protrusion and a part of the first conductive film,
the first metal has a first top surface and a second top surface, and
the first top surface is higher than the second top surface from the first conductive film.
3. The device according toclaim 2, wherein the first metal has a melting point higher than the melting point of the low—melting point metal.
4. The device according toclaim 1, further comprising a second conductive film disposed on a second surface of the first substrate, the second surface being opposite to the first surface, and the second conductive film being electrically connected to the first conductor.
5. The device according toclaim 1, wherein the first conductor comprises at least one of a poly-silicon and a metal.
6. The device according toclaim 1, wherein a diameter of the first conductor is substantially equal or smaller than 50 μm and a depth of the first conductor is substantially equal or smaller than 100 μm.
7. The device according toclaim 1, wherein the first conductive film comprises titanium and copper.
8. The device according toclaim 4, further comprising a second metal on the second conductive film.
9. The device according toclaim 8, further comprising a first insulation film disposed on the second surface of the first substrate, a part of the first insulation film being covered with the second metal.
10. The device according toclaim 1, further comprising a second substrate, and a second conductive film disposed on a first surface of the second substrate,
wherein the first and second conductive films are electrically connected and the low melting point metal is disposed between the first and second conductive films.
11. The device according toclaim 10, further comprising a second conductor penetrating the second substrate and electrically connected to the second conductive film.
12. The device according toclaim 10, further comprising:
a first metal covering an upper surface and a side surface of the first protrusion and a part of the first conductive film; and
a second metal on the second conductive film,
wherein the first and the second metals are electrically connected, the first and the second metals are disposed between the first and second conductive films, and the low-melting point metal is disposed between the first metal and the second metal.
13. The device according toclaim 11, further comprising:
a third conductive film disposed on a second surface of the first substrate, the second surface being opposite to the first surface of the first substrate, and the third conductive film being electrically connected to the first conductor; and
a fourth conductive film disposed on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate, and the fourth conductive film being electrically connected to the second conductor.
14. The device according toclaim 13, further comprising a fourth metal on the fourth conductive film.
15. The device according toclaim 12, wherein the first metal has a melting point higher than the melting point of the low-melting point metal and the second metal has a melting point higher than the melting point of the low-melting point metal.
16. The device according toclaim 11, wherein an each diameter of the first and the second conductors is substantially equal or smaller than 50 μm, and a depth of each of the first and the second conductors is substantially equal or smaller than 100 μm.
17. The device according toclaim 1, further comprising:
a second substrate;
a second conductor penetrating the second substrate;
a second conductive film disposed on a first surface of the second substrate and electrically connected to the second conductor; and a second protrusion disposed on the second conductive film,
wherein the first and second conductive films are electrically connected and the low-melting point metal is disposed between the first and second conductive films, the low-melting point metal is disposed over the second conductive film, and the second protrusion has a melting point higher than the melting point of the low-melting metal.
18. The device according toclaim 17, further comprising:
a first metal covering an upper surface and a side surface of the first protrusion and a part of the first conductive film; and
a second metal covering an upper surface and a side surface of the second protrusion and part of the second conductive film,
wherein the first and the second metals are electrically connected and are disposed between the first and second conductive films, a part of the first metal and a part of the second metal are disposed between the first and second protrusions, and the low-melting point metal is disposed between the first and the second metals.
19. The device according toclaim 18, wherein
the first metal has a first top surface and a second top surface, the first top surface being higher than the second top surface from the first conductive film, and
the second metal has a third top surface and a fourth top surface, the third top surface being higher than the fourth top surface from the second conductive film.
20. The device according toclaim 17, further comprising:
a third conductive film disposed on a second surface of the first substrate, the second surface of the first substrate being opposite to the first surface of the first substrate, and the third conductive film being electrically connected to the first conductor; and
a fourth conductive film disposed on a second surface of the second substrate, the second surface of the second substrate being opposite of the first surface of the second substrate, and the fourth conductive film being electrically connected to the second conductor.
21. The device according toclaim 20, further comprising a fourth metal on the fourth conductive film.
22. The device according toclaim 18, wherein the second metal has a melting point higher than the melting point of the low-melting point metal.
US13/683,2522007-10-122012-11-21Wafer or circuit board and joining structure of wafer or circuit boardAbandonedUS20130140067A1 (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
US13/683,252US20130140067A1 (en)2007-10-122012-11-21Wafer or circuit board and joining structure of wafer or circuit board

Applications Claiming Priority (4)

Application NumberPriority DateFiling DateTitle
JP2007-2667162007-10-12
JP2007266716AJP2009099589A (en)2007-10-122007-10-12 Wafer or circuit board and connection structure thereof
US12/285,222US8334465B2 (en)2007-10-122008-09-30Wafer of circuit board and joining structure of wafer or circuit board
US13/683,252US20130140067A1 (en)2007-10-122012-11-21Wafer or circuit board and joining structure of wafer or circuit board

Related Parent Applications (1)

Application NumberTitlePriority DateFiling Date
US12/286,222ContinuationUS8134616B2 (en)2008-03-122008-09-29Imaging apparatus and pixel defect compensation method implemented therein

Publications (1)

Publication NumberPublication Date
US20130140067A1true US20130140067A1 (en)2013-06-06

Family

ID=40582535

Family Applications (2)

Application NumberTitlePriority DateFiling Date
US12/285,222Active2030-06-06US8334465B2 (en)2007-10-122008-09-30Wafer of circuit board and joining structure of wafer or circuit board
US13/683,252AbandonedUS20130140067A1 (en)2007-10-122012-11-21Wafer or circuit board and joining structure of wafer or circuit board

Family Applications Before (1)

Application NumberTitlePriority DateFiling Date
US12/285,222Active2030-06-06US8334465B2 (en)2007-10-122008-09-30Wafer of circuit board and joining structure of wafer or circuit board

Country Status (3)

CountryLink
US (2)US8334465B2 (en)
JP (1)JP2009099589A (en)
KR (1)KR20090037819A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JP5316261B2 (en)*2009-06-302013-10-16富士通株式会社 Multichip module, printed circuit board unit and electronic device
KR20150139190A (en)*2014-06-032015-12-11삼성전기주식회사Device and device package
CN205726641U (en)*2016-01-042016-11-23奥特斯(中国)有限公司There is the parts carrier of different surface layer and the electronic equipment containing this parts carrier

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US7071424B1 (en)*1998-02-262006-07-04Ibiden Co., Ltd.Multilayer printed wiring board having filled-via structure
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US20040106232A1 (en)*2001-10-292004-06-03Fujitsu LimitedMethod of making electrode-to-electrode bond structure and electrode-to-electrode bond structure made thereby
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US20040245623A1 (en)*2003-03-282004-12-09Kazumi HaraSemiconductor device, circuit substrate and electronic instrument
US20050003649A1 (en)*2003-06-092005-01-06Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereof
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US20050013088A1 (en)*2003-07-142005-01-20Yasuyoshi HorikawaCapacitor device and method of manufacturing the same
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Also Published As

Publication numberPublication date
US8334465B2 (en)2012-12-18
JP2009099589A (en)2009-05-07
KR20090037819A (en)2009-04-16
US20090109641A1 (en)2009-04-30

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Legal Events

DateCodeTitleDescription
ASAssignment

Owner name:ELPIDA MEMORY INC., JAPAN

Free format text:SECURITY AGREEMENT;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:032414/0261

Effective date:20130726

ASAssignment

Owner name:PS4 LUXCO S.A.R.L., LUXEMBOURG

Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ELPIDA MEMORY, INC.;REEL/FRAME:032898/0001

Effective date:20130726

STCBInformation on status: application discontinuation

Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION


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