US20130100146A1 - Dynamically reconfigurable pipelined pre-processor - Google Patents

Abstract

A pipelined video pre-processor includes a plurality of configurable image-processing modules. The modules may be configured using direct processor control, DMA access, or both. A block-control list, accessible via DMA, facilitates configuration of the modules in a manner similar to direct processor control. Parameters in the modules may be updated on a frame-by-frame basis.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application claims priority to and the benefit of U.S. Provisional Patent Application Ser. No. 61/547,442, filed on Oct. 14, 2011, which is hereby incorporated herein by reference in its entirety.
BACKGROUND
• A stream of video frames, such as that generated by a video camera or read from a memory, frequently requires processing to improve the quality of the video or to extract features from the video. This processing is traditionally done by software in a post-processing operation. The post-processing operation may vary because (i) the parameters/coefficients of the algorithmic processing modules need to be modified; (ii) fine variations of a given algorithm need to be performed; and/or (iii) the operations that need to be performed on the video need to be changed. A software solution, however, while versatile, is slow and expensive in terms of processing power. Hardware-based algorithms are typically faster and more efficient, but hardware, by its nature, is difficult to reconfigure quickly and easily, especially when it must keep pace with live, streaming video. Existing hardware-based image processing systems thus produce non-optimal results because of their limitations in flexibility. A need therefore exists for a fast, efficient, and reconfigurable hardware-based image-processing system.
SUMMARY
• In one embodiment of the current invention, a pipelined video pre-processor (“PVP”) is made up of several algorithmic transformation image-processing modules that may be connected to each other in a variety of different, customizable configurations. Each of these modules has a plurality of parameter registers that control finite variations of a given algorithm implementation. The parameters of the modules may be re-configured on a frame-by-frame basis with no loss of data, and the configuration of modules may be changed with minimal or no loss of data. The parameters may be changed via a connected processor, via DMA access, or both simultaneously. The differing control schemes are designed to be compatible with each other, ensuring seamless transitions between them.
• In one aspect, a pipelined video pre-processor includes a plurality of image-processing modules arranged in a pipeline. An input port receives configuration parameters for the plurality of modules, and an image-pipe controller decodes the configuration parameters. A shadow register applies the configuration parameters to the plurality of modules, thereby altering the image-processing characteristics of the modules.
• The pipeline may be a memory pipeline for processing image data from a memory or a camera pipeline for processing image data from a digital camera. One or more additional pipelines (e.g., memory pipelines or camera pipelines) may be included. The configuration parameters may be received from a processor or a direct-memory access (“DMA”) engine. The configuration parameters may be arranged in a memory in a block-control structure and are accessed via a DMA channel; the block-control structure may include a block-control header and one or more block-control words. The offsets of the block-control words in the block-control structure may correspond to addresses in a memory-mapped register (“MMR”) space. The configuration parameters may be applied to a first frame of video data, and updated configuration parameters may be applied to a second frame of video data. Different pipeline stages in a module may receive the updated configuration parameters at different points in time in accordance with a data boundary.
• In another aspect, a method of processing image frames in a pipelined video pre-processor includes receiving configuration parameters for a plurality of image-processing modules in the pipelined video pre-processor. The configuration parameters may be stored in a shadow register and applied to the plurality of image-processing modules to thereby alter the image-processing characteristics of the modules.
• The configuration parameters may be received from a processor or a DMA engine; the modules may be arranged in one or more pipelines. The one or more pipelines may include a memory pipeline for processing image data from a memory or a camera pipeline for processing image data from a digital camera. The configuration parameters may be arranged in a memory in a block-control structure and may be accessed via a DMA channel. The block-control structure may include a block-control header and one or more block-control words. The offsets of the block-control words in the block-control structure may correspond to addresses in a memory-mapped register (“MMR”) space. The configuration parameters may be applied to a first frame of video data and updated configuration parameters may be applied to a second frame of video data. Different pipeline stages in a module may receive the updated configuration parameters at different points in time in accordance with a data boundary.
• In another aspect, a pipelined video pre-processor in a digital-signal processor includes a plurality of image-processing modules arranged in a pipeline and an input port for receiving configuration parameters for the plurality of modules. An image-pipe controller decodes the configuration parameters, and a shadow register applies the configuration parameters to the plurality of modules, thereby altering the image-processing characteristics of the modules. The pipeline may be a memory pipeline for processing image data from a memory or a camera pipeline for processing image data from a digital camera.
• These and other objects, along with advantages and features of the present invention herein disclosed, will become more apparent through reference to the following description, the accompanying drawings, and the claims. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
BRIEF DESCRIPTION OF THE DRAWINGS
• In the drawings, like reference characters generally refer to the same parts throughout the different views. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:
• FIG. 1 is a block diagram of a PVP in accordance with an embodiment of the present invention;
• FIG. 2 is a block diagram of module configuration in accordance with an embodiment of the present invention;
• FIGS. 3A and 3B are implementations of an arbitration scheme in accordance with an embodiment of the present invention;
• FIG. 4 is an illustration of a block-control list in accordance with an embodiment of the present invention;
• FIG. 5 is an illustration of a block-control header in accordance with an embodiment of the present invention;
• FIG. 6 is a block diagram of a frame-by-frame parameter update scheme in accordance with an embodiment of the present invention;
• FIG. 7 is a timing diagram of frame-by-frame updating in accordance with an embodiment of the present invention;
• FIG. 8 alogic circuit800 for gating the clocks and generating block reset in accordance with an embodiment of the present invention;
• FIG. 9 is an exemplary PVP in accordance with an embodiment of the present invention; and
• FIG. 10 is block diagram of a system incorporating a PVP in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION
• FIG. 1 illustrates an embodiment of a pipelined video pre-processor (“PVP”)100. The PVP may operate on any incoming data; in one embodiment, the data is video image data captured from a camera sensor and/or video image data fetched from a memory. The PVP may be placed on a stand-alone silicon chip; in other embodiments, the PVP is placed on a chip along with a processor, such as a digital-signal processor. A first input-data formatter102 may be used to formatincoming camera data104 from a camera source, and a second input-data formatter106 may be used to formatmemory data108 from a memory source. Data from one or more sources may be processed simultaneously. The present invention is not limited to any particular number or kind of input sources, and the input data sources may include one ormore camera sources104 and/or one ormore memory sources108. Eachsource104,108 may be received by its own input-data formatter102,106 or may share input-data formatters102,106 withother sources102,104.
• The input-data formatters102,106 output formatted input data to one or morereconfigurable pipelines110,112,114,116. Eachpipeline110,112,114,116 contains one ormore processing modules118. As explained in greater detail below, theprocessing modules118 perform a variety of different image-processing functions and tasks and may be selected and configured in accordance with a desired image-processing result. The number ofmodules118 per pipeline, the order of themodules118 within the pipeline, and the configuration of themodules118 within a pipeline may be reconfigured as necessary, and a givenmodule118 may be selected for use indifferent pipelines110,112,114,116.FIG. 1 illustrates fourmodules118 in the first pipeline110 (twomodules118 being configured to operate in parallel), twomodules118 in thesecond pipeline112, onemodule118 in thethird pipeline114, and twomodules118 in thefourth pipeline116. This configuration of modules is presented as only one possible configuration of thePVP100, however, and one of skill in the art will understand that many other configurations are possible.
• The outputs of thepipelines110,112,114,116 are received by output-data formatters120,122,124,126, which prepare the output data (by, for example, compressing or packing it) and send it off-chip viaoutput ports128. In one embodiment, the output-data formatters120,122,124,126 are connected via peer-to-peer connections to dynamic-data exchange (“DDE”) modules used for connection with a bus protocol (e.g., an AXI bus). In one embodiment, eachpipeline110,112,114,116 has its own output-data formatter120,122,124,126; in other embodiments, one ormore pipelines110,112,114,116 may share a single output-data formatters (via use of, for example, a multiplexer to select between the pipelines).
• Eachmodule118 may have internal configuration parameters that are controlled by an outside source. Eachmodule118 may have its own set of local parameter registers that determine the nature of processing offered by that module within the confines of a given algorithm; additional parameter registers may be common to some or all of themodules118. The parameter registers may include application registers130 and/or status registers132; only one set of these registers is shown for illustrative purposes, but eachmodule118 may contain its own set ofapplication130 andstatus132 registers. As explained in greater detail below, the parameter registers may be read or written by a variety of sources, including a connected processor (via aninterface134, such as an advanced peripheral bus or “APB” interface) or via direct-memory access (“DMA”) though the use of input andoutput modules136. In one embodiment, control and status information is input and output via the use of shadow registers138; the shadow registers138 read and write to the application registers130 and/or status registers132 in accordance with the timing of image data currently moving through apipeline110,112,114,116 so that, for example, a first set of parameters is applied to a first frame in the pipeline and a second set of parameters is applied to a second frame in the pipeline. An image-pipe controller140 may be used to coordinate control of themodules118, as explained in greater detail below.
• In various embodiments, themodules118 may include a convolution/down-scaler engine (“CNV”); a pixel-magnitude and angle-computation unit (“PMA”); a threshold, histogram and compression engine (“THC”); an arithmetic computation unit (“ACU”); a pixel-edge classifier (“PEC”); an integral image computation (“IIM”); and/or an up-down scaler (“UDS”). One of skill in the art will understand that other modules may be included and that the present invention is not limited to only these modules. Themodules118 may be selectively connected to each other to create one or more different pipelines using any method known in the art such as, e.g., a programmable crossbar switch. In one embodiment, illustrated inFIG. 2, themodules118 may be configured using multiplexers placed between them. In thesystem200 shown inFIG. 2, afirst module202 having three output ports and asecond module204 having one output port are connected via a system ofmultiplexers206 to athird module208 having two input ports (and three output ports). By controlling theselect lines210 of themultiplexers206, thethird module208 may receive any of the outputs of the first202 and second204 modules as either of its twoinputs212. Theselect lines210 may be configured via processor or DMA control, in a manner similar to the configuration of other module parameters. One of skill in the art will understand that other configurations for themultiplexers206 are also within the scope of the invention.
• Any given module may be moved across the camera pipe and/or memory pipe as part of the pipe reconfiguration. The camera pipes may work on the pixel clock and the memory pipe may work on the system clock; both clocks may be asynchronous with respect to each other. The PVP architecture may ensure proper synchronization across clock domains so that a module may be switched between the pipes.
• 1. Control of Modules from Multiple Sources
• In one embodiment, the image-processing modules in the PVP may be accessed by a linked processor via, for example, memory-mapped registers (“MMRs”) accessible via an APB interface (such as theinterface134 shown inFIG. 1). A hardware interrupt may be asserted, for example, and the processor may read and write status and control information to and from the PVP and its modules. Once the processing modules are appropriately configured, the flow of image data may be dictated either by the processor or by a DMA engine.
• In another embodiment, the image-processing modules may be configured by either or both of the APB interface (i.e., via the processor) and one or more DMA interfaces. In one embodiment, all of the processing modules are controlled at a first point in time by direct processor control and, at a second point in time, by DMA control. In another embodiment, a first subset of the modules is configurable by direct processor control while, simultaneously, a second subset is configurable by DMA control. For example, in the PVP, the first subset of modules may be modules that process data stored in a memory (i.e., a memory pipe) and the second subset may be modules that process data coming from a camera sensor (i.e., a camera pipe). In another embodiment, there may be a plurality (e.g., two or more) separate DMA control channels. A first DMA control channel may control the first subset of modules and a second DMA control channel may control the second subset of modules. For example, the first DMA control channel controls the camera pipe and the second controls the memory pipe. One of skill in the art will understand that other combinations of read and write control are possible and that the current invention is not limited to any particular division of direct and DMA control.
• In one embodiment, direct or DMA control of the registers is accomplished by reading or writing first to a set of scratch registers; once these scratch registers are fully written, for example, their contents are then applied to the actual application registers. Likewise, reading of the control registers may first fill one or more scratch registers, and then the scratch registers are read via DMA control. The scratch registers may be the shadow registers130,132 shown inFIG. 1. In one embodiment, direct processor control by the APB interface is not allowed during loading or unloading of the shadow registers (i.e., during the time the contents of the shadow registers are being applied to the application registers or during the time the status registers are filling the shadow registers).
• Because control of the modules may come from different sources, conflicts may arise between multiple simultaneous requests. In one embodiment, arbitration may be used to resolve conflicts between the different control mechanisms.FIG. 3A illustrates anillustrative arbitration scheme300 in accordance with an embodiment of the invention. In this embodiment, afirst DMA channel302 is used to configure modules in a camera pipeline; modules in a memory pipeline may be configured using either asecond DMA channel304 or anAPB link306 for direct control by a processor. Anarbitration unit308 is used to resolve conflicts between thesecond DMA channel304 and theAPB link306. Thearbitration unit308 may include a stall or blackout mechanism to delay access to the DMA engine during some or all of its loading phase and/or error signaling to thereby safeguard the validity of any simultaneous accesses by theAPB link306. In one embodiment, thearbitration module308 interfaces with theDMA engine304 and theAPB link306 and controls how the control data is programmed/arbitrated to the image-processing modules. In one embodiment, thearbitration module308 is incorporated into the image-pipe controller (“IPC”)140, shown inFIG. 1, and communicates with the DMA engine and processor via P2P and APB buses, respectively. The image-processing modules may use an internal bus, such as an AHB bus. One embodiment of an implementation of the arbitration logic is shown inFIG. 3B.
• The clock controlling some or all of the image-processing modules may be on a different domain than that of the clock domain of the DMA and processor interfaces. In this case, the clocks may be synchronized across the different domains. In one embodiment, subsets of the image-processing modules are arranged in a plurality of different-length pipes, and data may finish processing in a shorter pipe (and, e.g., assert a load_done signal to indicate completion) before it finishes processing in a longer pipe. Asynchronization module310 may delay synchronization of the early data until the later data is also available by, for example, receiving a load_done signal from each of the pipelines and sending a synchronization signal to thearbitration unit308 when some or all of the load_done signals have been received.
• The bits of the parameter registers may be set or cleared by the processor using polling or interrupts. In one embodiment, DMA status channels may be used to scan out one or more values in the parameter registers. For example, a histogram status may be scanned out, from the THC module, on the DMA status channel. The trigger of the DMA status channel may be based on a vsync output at a given module. If two statuses are requested over the same channel, an identifying field (e.g., numbers or letters) may be included in a status header for each module's status, and the two statuses may be sequenced, one after the other, after recording the event.
• 2. Programming through DMA
• To facilitate control through DMA, a special control-word format called a block-control structure list (“BCL”) may be defined in a system memory. The BCL is an array of control information intended for the application registers in the image-processing modules in the PVP; this control information is grouped by module, and each group contains header information (e.g., a block-control header or “BCH”) instructing the PVP where and how to apply the control information. The BCL is read in via DMA, the header information is decoded by the image-pipe controller, and the control information is thereby applied to the modules. The structure of the BCL may allow a new module to be added easily by, e.g., appending or inserting a new module's BCH in the BCL.
• FIG. 4 illustrates one embodiment of aBCL400. A number ofBCHs402 are shown, each having an associated list of block-control words404.FIG. 5 illustrates an expanded view of aBCH500. Afirst field BLOCK502 indicates a unique address assigned to each image-processing module in the PVP, and thereby instructs the image-pipe controller to which module to apply the parameters. Asecond field WCNT504 indicates the number of control words contained in this block, thereby indicating the location of the next BCH. The use of the WCNT field may obviate the need for, for example, an end-of-block indicating field at the end of the block. Another field,WOFF506, indicates an offset to be applied to the control words; for example, if a given module has a set of 256 registers, specifying an offset of 10 means that the control words are applied beginning at the tenth register. If WCNT is 12 (for example), registers10 through22 are programmed.
• Further fields in the BCH indicate how a module should be connected to upstream and downstream modules using, for example, the multiplexer control illustrated inFIG. 2. For example, IPORT fields508 may be used to select a first level of multiplexers, andIBLOCK fields510 may be used to select a second level of multiplexers. One of skill in the art will understand, however, that any other method of specifying multiplexer programming using select bits is within the scope of the current invention. Alternatively, all the IBLOCK(s) and IPORT(s) may be removed from the BCH and a separate crossbar-control header format (i.e., a crossbar-control structure or “CCS” packet) may be defined. Other fields include aSTART bit512 that indicates whether a module should be enabled or disabled and aPIPE field514 that indicates to which pipe a module should belong (i.e., a camera or memory pipe). Another field,STATWCNT516, indicates how many status registers in a module should be read out in a read operation.
• In one embodiment, a BCL for a given pipe begins with a configuration of an input-data format module, includes configuration of one or more image-processing modules, and ends with a configuration of an output-data format module. The order of the configuration information for each image-processing module may correspond to the positions of the modules in the pipe. The BCH for a module may be repeated within a BCL (e.g., two or more times) to allow programming of two separate groups of registers for a given module inside a pipe. For example, a first BCH may be used to program registers10-22 of a module, and a second BCH may be used to program registers100-110 of the same module.
• The configuration of the BCH for a given module may correlate to the direct processor control of the module via memory-mapped registers. For example, a given module may have a fixed base address for access via the processor; theBLOCK502 identification number of the module (used for DMA control) may be derived from this base address. In one embodiment, theBLOCK502 identification may be found by right-shifting the base address by five bits. Similarly, the difference between an actual MMR address and the base address may correlate directly to the WOFF offset field in the BCH. Thus, each control word in the BCL is arranged in the same order that they appear in the MMR address space, thereby simplifying the design of the BCH and of any software that configures the registers in the modules using either control scheme. For example, if a given register is36 address units removed from the base address in the MMR address space, that same register is36 units offset from theBLOCK502 identification number in the DMA control scheme. Using this configuration, a programmer and/or software utility may seamlessly shift between the two control schemes without the use of, for example, a decoder/mapping utility to translate between the schemes.
• Reading status via DMA is performed in a manner similar to writing control information through DMA. In one embodiment, module status values are moved into one or more shadow registers in accordance with the output capabilities of a given module (i.e., according to the clock rate of the module). The status information is then periodically sent via DMA in accordance with configuration registers (e.g., once every frame boundary or once every certain number of frames). The status information may be sent on a single DMA channel or simultaneously over multiple DMA channels. As explained above, aSTATWCNT field516 in the BCH indicates the number of status registers in a module to be read and sent.
3. Reprogramming Modules for Different Frames
• For a given pipe configuration, embodiments of the present invention allow seamless reprogramming of parameter registers for modules comprising of any given pipe, such that back-to-back frames may be processed with different coefficients or variations of the algorithm provided by each module. A given module may have a latency of more than one clock cycle; the pipeline stages at the end of the module may, for example, be processing a first frame while the pipeline stages at the beginning of the module may be processing a second frame. The application registers that influence the behavior of the module may thus be updated at different times for each pipeline of the module to ensure that each frame is processed in accordance with its intended parameters. In one embodiment, the application registers in each pipeline are updated as a frame boundary propagates through the pipeline in the module. As described above, shadow registers may be used to update the application registers at the appropriate times; either the direct-processor MMR mechanism or the DMA control mechanism updates the shadow registers only, and the updating of the application registers is staggered in time.
• The engine may control the granularity at which a given set of parameters or a given configuration is applied: continuously for every frame or for a fixed set of frames. Typically, the camera pipe continuously gets frames from the camera sensor, while the memory pipe receives fixed sets of frames; either mode may be used with either pipe, however. The processor may be switched from continuous mode to fixed mode (and vice versa) without disabling the entire PVP engine. To apply the parameters to every frame, a flag may be set (e.g., a frame count or “FCNT” value may be programmed to zero). If a new set of control values are programmed, the new values are be applied on the next frame boundary and applied to subsequent frames continuously thereafter. The architecture may also provide a TAG mechanism on a separate status DMA channel for ease of identification of the frames which have been processed with new control parameters; the processor may use this TAG mechanism to determine which frames received processing using a certain set of parameters. The TAG data may be sent on the status DMA channel and may also be available for processor read.
• To apply the parameters to a fixed set of frames, the FCNT value may be programmed to a nonzero value and thereafter monitored. Once the predetermined number of frames has been processed, the pipeline halts (and the last frame is stuck in the pipeline). Once a next group of frames is identified and queued for processing, the FCNT value is set again, and the next group begins processing (with, perhaps, a different set of module parameters). Processing of the next group of frames pushes out the last frame of the previous set that was stuck in the pipeline.
• The pipeline may be flushed if another parameter (e.g., a DRAIN bit) is set. If, for example, a finite set of frames is identified for processing and the DRAIN bit is set, upon completion of the last frame, the pipeline is flushed with dummy pixels so that the last frame in the set is output by the pipeline. As the last frame passes through the pipeline, the modules in the pipeline are disabled. In one embodiment, if the pipeline is in a continuous-frame mode and the DRAIN bit is set, the pipeline is immediately flushed and disabled. In either case, the next set of control words may be set to wake up the pipeline (by use of, for example, a START bit in the BCH of the frames).
• FIG. 6 illustrates anexemplary embodiment600 of afirst module602, asecond module604, a data control andcrossbar unit606 connecting them, and an image-pipe controller608. When a new set of application register values are loaded into the shadow registers either by DMA or direct-processor control, a “daisychainload” signal is driven together with a frame sync signal to thefirst module602. Thefirst module602 updates its application registers in accordance with its internal pipeline delays as the first pixel in the input data passes through the module602 (i.e., if the first module includes five pipeline stages, it applies the application-register values in turn to each of the five stages as the pixel data is processed through). When thefirst module602 completes processing of the first pixel, it asserts the daisychainload signal on its output, thereby instructing thesecond module604 to also begin applying the new application-register values (in accordance with its own pipeline configuration). A timing diagram700 of the daisychainload signal and the frame sync signal is shown inFIG. 7, andFIG. 8 illustrates alogic circuit800 for gating the clocks and generating block reset based on a drain_done and start bit.
• In addition to reconfiguring the parameters of modules for existing pipelines, the pipelines themselves may be reconfigured by adding or deleting modules. For the real-time pipes (e.g., the camera pipes, or other pipes handling real-time data), the engine may include a mechanism that permits a seamless, dynamic reconfiguration of the modules comprising the camera pipes with a loss of one frame data only. For non-real-time pipes (e.g., a memory pipe), the engine may include a mechanism that permits dynamic reconfiguration with a finite stall and no frame loss.
• This mechanism may be implemented using a DRAIN bit in a register and an auto-disabling START bit in the respective modules. After a finite set of frames, conditional to DRAIN=1, the modules in the pipe are disabled (by, e.g., setting the START bit to 0). The new set of modules making up the new configuration of the pipe may have the START bit set in the next programming structure.
4. Examples
• FIG. 9 illustrates anexemplary embodiment900 of a PVP architecture. The system includes acamera input902 and amemory input904. Thecamera input902 feeds threecamera pipelines906,908,910, and thememory input904 feeds twomemory pipelines912,914. Thefirst camera pipeline906 includes two convolution/down-scaler modules, a pixel-magnitude and angle computation module, and a pixel-edge classifier module; thesecond camera pipeline908 includes a convolution/down-scaler module and an integral image computation module; thethird camera pipeline910 contains a threshold, histogram, and compression module; thefirst memory pipeline912 includes a convolution/down-scaler module and an arithmetic computation unit; and the second memory pipeline includes an up-down scaler.
• FIG. 10 illustrates asystem1000 including aPVP1002 and its support and interface circuitry. Aprocessor1004 may directly control thePVP1002 via an MMR interface. AVSS crossbar circuit1006 provides data to the camera pipeline; thecrossbar1006 may select between a variety of input sources (e.g., PPI and PIXC inputs), thereby providing multiple camera inputs.DDE arbitration units1008 interface with external buses (e.g., AXI buses) to allow for DMA control;DDE units1010 off-load output data from the output-data format modules within thePVP1002, provide input and output control and status data, and provide an input to the memory pipeline.

Claims (20)

What is claimed is:

1. A pipelined video pre-processor comprising:

a plurality of image-processing modules arranged in a pipeline;

an input port for receiving configuration parameters for the plurality of modules;

an image-pipe controller for decoding the configuration parameters; and

a shadow register for applying the configuration parameters to the plurality of modules, thereby altering the image-processing characteristics of the modules.

2. The pipelined video pre-processor ofclaim 1, wherein the pipeline is a memory pipeline for processing image data from a memory or a camera pipeline for processing image data from a digital camera.

3. The pipelined video pre-processor ofclaim 2, further comprising one or more additional pipelines, the one or more additional pipelines being memory pipelines or camera pipelines.

4. The pipelined video pre-processor ofclaim 1, wherein the configuration parameters are received from a processor or a direct-memory access (“DMA”) engine.

5. The pipelined video pre-processor ofclaim 1, wherein the configuration parameters are arranged in a memory in a block-control structure and are accessed via a DMA channel.

6. The pipelined video pre-processor ofclaim 5, wherein the block-control structure comprises a block-control header and one or more block-control words.

7. The pipelined video pre-processor ofclaim 6, wherein the offsets of the block-control words in the block-control structure correspond to addresses in a memory-mapped register (“MMR”) space.

8. The pipelined video pre-processor ofclaim 1, wherein the configuration parameters are applied to a first frame of video data and updated configuration parameters are applied to a second frame of video data.

9. The pipelined video pre-processor ofclaim 8, wherein different pipeline stages in a module receive the updated configuration parameters at different points in time in accordance with a data boundary.

10. A method of processing image frames in a pipelined video pre-processor, the method comprising:

receiving configuration parameters for a plurality of image-processing modules in the pipelined video pre-processor;

storing the configuration parameters in a shadow register;

applying the configuration parameters to the plurality of image-processing modules to thereby alter the image-processing characteristics of the modules.

11. The method ofclaim 10, wherein the configuration parameters are received from a processor or a DMA engine.

12. The method ofclaim 10, further comprising arranging the modules in one or more pipelines.

13. The method ofclaim 12, wherein the one or more pipelines comprise a memory pipeline for processing image data from a memory or a camera pipeline for processing image data from a digital camera.

14. The method ofclaim 10, wherein the configuration parameters are arranged in a memory in a block-control structure and are accessed via a DMA channel.

15. The method ofclaim 14, wherein the block-control structure comprises a block-control header and one or more block-control words.

16. The method ofclaim 15, wherein the offsets of the block-control words in the block-control structure correspond to addresses in a memory-mapped register (“MMR”) space.

17. The method ofclaim 10, further comprising applying the configuration parameters to a first frame of video data and applying updated configuration parameters to a second frame of video data.

18. The method ofclaim 10, wherein different pipeline stages in a module receive the updated configuration parameters at different points in time in accordance with a data boundary.

19. A digital-signal processor comprising a pipelined video pre-processor, the pipelined video pre-processor comprising:

a plurality of image-processing modules arranged in a pipeline;

an input port for receiving configuration parameters for the plurality of modules;

an image-pipe controller for decoding the configuration parameters; and

a shadow register for applying the configuration parameters to the plurality of modules, thereby altering the image-processing characteristics of the modules.

20. The digital-signal processor ofclaim 19, wherein the pipeline is a memory pipeline for processing image data from a memory or a camera pipeline for processing image data from a digital camera.

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