US20120314392A1 - Capacitor array substrate - Google Patents

Abstract

A capacitor array substrate includes a substrate, first traces, second traces, capacitors, connecting lines, and signal lines. The substrate has a first, a second, and a third side. The first side is connected with the second and the third side. The first traces are disposed on the substrate in parallel and are not vertical or parallel to the first side. The second traces are disposed on the substrate in parallel. The capacitors are disposed on the substrate at intersections of the first and the second traces and are connected to the first and the second traces. The connecting lines are disposed on the second and the third side of the substrate. Each connecting line is connected to a first and a second trace. The signal lines are disposed on the substrate. Each signal line is connected to a first or a second trace and transmits signals from the first side.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application claims the priority benefit of Taiwan application serial no. 100119880, filed on Jun. 7, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The invention generally relates to a substrate, and more particularly, to a capacitor array substrate.
• 2. Description of Related Art
• FIG. 1 is a diagram of a conventional capacitor array substrate. Referring toFIG. 1, in the conventionalcapacitor array substrate100, thecapacitors110 arranged in an array are connected to thehorizontal traces120 and thevertical traces130. Because thetraces120 and thetraces130 are respectively parallel to two sides of thecapacitor array substrate100, to carry out all signal transmissions at the same side,signal lines140 for thetraces120 need to be laid out at one side of thecapacitor array substrate100. As a result, the width of the side of thecapacitor array substrate100 is greatly increased. Thus, not only the cost of thecapacitor array substrate100 is increased, but thelong signal lines140 may cause the signal quality to decrease.
SUMMARY OF THE INVENTION
• Accordingly, the invention is directed to a capacitor array substrate of reduced size.
• The invention provides a capacitor array substrate including a substrate, a plurality of first traces, a plurality of second traces, a plurality of capacitors, a plurality of connecting lines, and a plurality of signal lines. The substrate has a first side, a second side, and a third side. The first side is connected with the second side. The first side is connected with the third side. The first traces are disposed on the substrate in parallel with each other. Each of the first traces is not vertical or parallel to the first side. The second traces are disposed on the substrate in parallel with each other. The capacitors are disposed on the substrate at intersections of the first traces and the second traces and are connected to the first traces and the second traces. The connecting lines are disposed on the second side and the third side of the substrate. Each of the connecting lines is connected to one of the first traces and one of the second traces. The signal lines are disposed on the substrate. Each of the signal lines is connected to one of the first traces or one of the second traces and transmits signals from the first side.
• According to an embodiment of the invention, the first traces are vertical to the second traces.
• According to an embodiment of the invention, the angles formed by the first traces and the first side are 45°.
• According to an embodiment of the invention, the connecting lines do not intersect each other.
• According to an embodiment of the invention, the connecting lines intersect each other.
• According to an embodiment of the invention, the first side is vertical to the second side.
• As described above, in a capacitor array substrate provided by the invention, all the traces connecting the capacitors are slanted with respect to the sides of the substrate and then connected with the connecting lines, so that the layout area can be reduced.
• These and other exemplary embodiments, features, aspects, and advantages of the invention will be described and become more apparent from the detailed description of exemplary embodiments when read in conjunction with accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
• FIG. 1 is a diagram of a conventional capacitor array substrate.
• FIG. 2 is a diagram of a capacitor array substrate according to an embodiment of the invention.
• FIG. 3 is a diagram of a capacitor array substrate according to another embodiment of the invention.
• FIG. 4 is a diagram of a capacitor array substrate according to another embodiment of the invention.
• FIG. 5 is a diagram of a capacitor array substrate according to another embodiment of the invention.
• FIG. 6 is a diagram of a capacitor array substrate according to another embodiment of the invention.
DESCRIPTION OF THE EMBODIMENTS
• Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
• FIG. 2 is a diagram of a capacitor array substrate according to an embodiment of the invention. Referring toFIG. 2, in the present embodiment, thecapacitor array substrate200 includes asubstrate210, a plurality of first traces220, a plurality ofsecond traces230, a plurality ofcapacitors240, a plurality of connectinglines250, and a plurality ofsignal lines260. Thesubstrate210 has afirst side212, asecond side214, and athird side216. Thefirst side212 is connected with thesecond side214, and thefirst side212 may be vertical to thesecond side214. Thefirst side212 is connected with thethird side216, but thefirst side212 may be vertical or not vertical to thethird side216. Thesubstrate210 usually presents a rectangular shape. However, the shape of thesubstrate210 is not limited in the invention. The first traces220 are disposed on thesubstrate210 in parallel with each other, and each first trace220 is not vertical or parallel to thefirst side212. In other words, if the edge of thefirst side212 is horizontal, the first traces220 are not vertical or horizontal. Thesecond traces230 are disposed on thesubstrate210 in parallel with each other.
• Herein the terms “vertical” and “parallel” only refer to approximate instead of precise states, and near vertical and near horizontal states caused by process errors or purposeful modifications are acceptable.
• Thecapacitors240 are disposed on thesubstrate210. Eachcapacitor240 is located at the intersection of a first trace220 and asecond trace230 and is connected to a first trace220 and asecond trace230. The connectinglines250 are disposed on thesecond side214 and thethird side216 of thesubstrate210. Each connectingline250 is connected to a first trace220 and asecond trace230. Thesignal lines260 are disposed on thesubstrate210. Eachsignal line260 is connected to a first trace220 or asecond trace230 and transmits signals from thefirst side212.
• Based on the disposition described above, eachcapacitor240 is controlled through twosignal lines260, and the capacitance variation on eachcapacitor240 can be detected through twosignal lines260. Besides, only small amounts of space are reserved on thesecond side214 and thethird side216 of thesubstrate210 for disposing the connectinglines250. Thus, in the present embodiment, the purpose of transmitting signals from a single side can be accomplished in thecapacitor array substrate200 of reduced size, so that the cost of thecapacitor array substrate200 is greatly reduced. Additionally, thesignal lines260 and the connectinglines250 can be managed to have shorter lengths so that the signal transmission quality can be improved.
• In the present embodiment, the first traces220 are vertical to the second traces230. Additionally, in the present embodiment, the angles formed by the first traces220 and thefirst side212 are 45°. Moreover, in the present embodiment, the connectinglines250 do not intersect each other (i.e., each connectingline250 is connected to the closest first trace220 and second trace230).
• FIG. 3 is a diagram of a capacitor array substrate according to another embodiment of the invention. Referring toFIG. 3, thecapacitor array substrate300 in the present embodiment is similar to thecapacitor array substrate200 illustrated inFIG. 2, and the difference between the two is that in the present embodiment, the connectinglines350 intersect each other or may even intersect the signal lines360. In other words, each connectingline350 is not connected to the closestfirst trace320 orsecond trace330. Such a design optimizes the potential distribution of the capacitor array and accordingly improves the performance of thecapacitor array substrate300.
• FIG. 4 is a diagram of a capacitor array substrate according to another embodiment of the invention. Referring toFIG. 4, thecapacitor array substrate400 in the present embodiment is similar to thecapacitor array substrate200 illustrated inFIG. 2, and the difference between the two is that in thecapacitor array substrate400 of the present embodiment, thefirst side412 is longer than thesecond side414 and thethird side416. It can be understood according to the present embodiment that the invention can be applied to thecapacitor array substrate400 which presents a rectangular shape.
• FIG. 5 is a diagram of a capacitor array substrate according to another embodiment of the invention. Referring toFIG. 5, thecapacitor array substrate500 in the present embodiment is similar to thecapacitor array substrate200 illustrated inFIG. 2, and the difference between the two is that in thecapacitor array substrate500 of the present embodiment, thefirst side512 is shorter than thesecond side514 and thethird side516. It can be understood according to the present embodiment that the invention can be applied to thecapacitor array substrate500 which presents a rectangular shape and has its shorter side as the signal transmission side. Additionally, on thesecond side514 or thethird side516 of thecapacitor array substrate500, some of the connecting lines550 close to thefirst side512 can be replaced by signal lines directly connected to the signal transmission side.
• FIG. 6 is a diagram of a capacitor array substrate according to another embodiment of the invention. Referring toFIG. 6, thecapacitor array substrate600 in the present embodiment is similar to thecapacitor array substrate500 illustrated inFIG. 5, and the difference between the two is that in the present embodiment, thesignal lines660 are connected not only to thefirst traces620 and thesecond traces630 closest to thefirst side612. Instead, some of thesignal lines660 on thethird side616 are extended toward inside of thesubstrate610 and connected to thefirst traces620 or thesecond traces630 located inside thesubstrate610.
• In summary, in a capacitor array substrate provided by the invention, all the traces connecting the capacitors are slanted with respect to the sides of the substrate so that signals can be transmitted from the same side. Additionally, connecting lines are disposed to reduce the layout area without sacrificing the working area, so that the cost of the capacitor array substrate can be reduced.
• It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (6)

1. A capacitor array substrate, comprising:

a substrate, having a first side, a second side, and a third side, wherein the first side is connected with the second side, and the first side is connected with the third side;

a plurality of first traces, disposed on the substrate in parallel with each other, wherein each of the first traces is not vertical or parallel to the first side;

a plurality of second traces, disposed on the substrate in parallel with each other;

a plurality of capacitors, disposed on the substrate at intersections of the first traces and the second traces, and connected to the first traces and the second traces;

a plurality of connecting lines, disposed on the second side and the third side of the substrate, respectively connected to one of the first traces and one of the second traces; and

a plurality of signal lines, disposed on the substrate, respectively connected to one of the first traces or one of the second traces, and transmitting signals from the first side.

2. The capacitor array substrate according toclaim 1, wherein the first traces are vertical to the second traces.

3. The capacitor array substrate according toclaim 1, wherein angles between the first traces and the first side are 45°.

4. The capacitor array substrate according toclaim 1, wherein the connecting lines do not intersect each other.

5. The capacitor array substrate according toclaim 1, wherein the connecting lines intersect each other.

6. The capacitor array substrate according toclaim 1, wherein the first side is vertical to the second side.

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