US20120256642A1 - Single layer touch sensor - Google Patents

Abstract

Embodiments described herein provide capacitance sensing devices and methods for forming such devices. The capacitance sensing devices include a substrate having a central and an outer portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating material is coupled to the second end portions of the first plurality of conductors. A second plurality of conductors are coupled to the insulating material. Each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors.

Description

RELATED APPLICATION
• This application is a continuation of U.S. patent application Ser. No. 13/528,644, filed Jun. 20, 2012, which is a continuation of U.S. patent application Ser. No. 13/405,071, filed Feb. 24, 2012, which claims the benefit of U.S. Provisional Application No. 61/446,178, filed Feb. 24, 2011, and U.S. Provisional Application No. 61/559,590, filed Nov. 14, 2011, all of which are incorporated by reference herein in their entirety.
TECHNICAL FIELD
• This disclosure relates to the field of touch sensors and, in particular, to capacitive sensors.
BACKGROUND
• In recent years, touch pads, or capacitive sensor devices, have become increasing integrated in various industries and product lines. Often, these sensors have the ability to detect multiple objects (e.g., fingers) simultaneously.
• Touch sensors are an expensive part of the user interface system. One reason for the high cost of touch sensors is that conventional sensors use either multiple layers of materials formed on multiple substrates or a single substrate with a series of “jumpers” to form electrical connection between the individual electrode segments and insulate them from the other electrodes that intersect them.
BRIEF DESCRIPTION OF THE DRAWINGS
• The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
• FIG. 1 is a simplified plan view of a touch sensor device according to one embodiment;
• FIG. 2 is a simplified cross-sectional view of the touch sensor device ofFIG. 1 taken along line2-2;
• FIG. 3 is a plan view of an embodiment of a touch sensor array;
• FIG. 4 is a plan view illustrating a portion of the touch sensor array ofFIG. 3 in greater detail;
• FIG. 5 is a plan view illustrating another embodiment of a touch sensor array;
• FIG. 6 is a plan view of a bezel portion of the touch sensor array ofFIG. 1;
• FIGS. 7 and 8 are cross-sectional views of the bezel portion ofFIG. 6 taken along lines7-7 and8-8, respectively;
• FIGS. 9,10, and11 are plan views illustrating an embodiment of a bezel portion of a touch sensor array during the formation thereof;
• FIG. 12 is plan view illustrating a further embodiment of a touch sensor array;
• FIG. 13 is a plan view illustrating another embodiment of a touch sensor array;
• FIG. 14 is a schematic plan view illustrating the bezel portion of a touch sensor array and a flexible printed circuit (FPC);
• FIG. 15 is a plan view illustrating another embodiment of a touch sensor array;
• FIG. 16 is a plan view illustrating a portion of the touch sensor array, taken on Detail A, ofFIG. 15;
• FIG. 17 is a cross-sectional view of the touch sensor array ofFIG. 16 taken along line17-17;
• FIG. 18 is a plan view illustrating another embodiment of a touch sensor array;
• FIG. 19 is a plan view illustrating a portion of the touch sensor array, taken on Detail A, inFIG. 18;
• FIG. 20 is a plan view illustrating a portion of the touch sensor array, taken on Detail B, inFIG. 18;
• FIG. 21 is a plan view illustrating another embodiment of a touch sensor array;
• FIG. 22 is a plan view of a portion of another embodiment of a touch sensor array;
• FIGS. 23-25 are side views of the touch sensor array ofFIG. 22;
• FIGS. 26-30 are plan views illustrating sensor electrodes according to various alternative embodiments; and
• FIG. 31 is a block diagram illustrating an embodiment of an electronic system.
DETAILED DESCRIPTION
• Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The phrase “in one embodiment” located in various places in this description does not necessarily refer to the same embodiment.
• In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the subject matter of the present application. It will be evident, however, to one skilled in the art that the disclosed embodiments, the claimed subject matter, and their equivalents may be practiced without these specific details.
• The detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in enough detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter but rather to enable one skilled in the art to practice, make, and/or use the subject matter.
• Attempts have been made in the past to reduce the number of layers, and thus the manufacturing costs, of touch sensors. There are several single layer sensors available that are suited only for single touch reception. These sensors typically use a series of electrodes the width of which linearly change from one end to the other end of the electrode. Using the signal variation along the electrode's length, the coordinate along the electrode's axis is determined. The coordinate in the perpendicular direction to the electrodes axis is determined by the conventional digitization method.
• Another possibility for a single layer multiple-touch sensor uses an array of pads filling the sensor area, and sensing each of the pads (or electrodes) individually in a self capacitance sensing mode. However, such requires independent traces for each of the sensing pads and a very large number of measuring channels and pins on the controller chip to get an acceptable accuracy for even a small size sensor.
• Embodiments of the present invention allow for addressing the sensing pads without requiring an impractically large number of measuring ports or pins on the controller. Additionally, a method of achieving multi-touch sensors with no bezel is disclosed herein, and the performance of such sensors is demonstrated.
• Embodiments described herein provide a touch sensor device and a method for forming a touch sensor device that has a single layer active area. Additionally, the touch sensor device is provided with a wiring scheme that minimizes the number of wires, as well as the layers, (or traces) required to simultaneously detect multiple contact points (i.e., “touches”). As a result, overall manufacturing costs may be reduced.
• FIGS. 1 and 2 are simplified views of a touch sensor device, or capacitance sensing device,1 according to one embodiment. In one embodiment, thetouch sensor device1 is a “touchscreen” device that has a visible area (or portion)2 and anon-visible area3. Thetouch sensor device1 includes a liquid crystal display (LCD)panel4 arranged below a touch sensor array (or assembly)5. As is commonly understood, thevisible area2 may correspond to the size and shape of a transparent region of thetouch sensor array5, while the non-visible area may correspond to a non-transparent region of thetouch sensor array5 which may be covered by a casing (not shown). Thetouch sensor array5 includes an overlay (or protective layer)6 attached to a side thereof opposite the LCD panel by an adhesive7. Thetouch sensor device1 also includes a flexible printed circuit (FPC)tail8 extending therefrom, which as described below may be used to route electrical signals to and from thetouch sensor array10.
• FIG. 3 is a plan view illustrating a capacitive (or touch)sensor array10 according to one embodiment. Thetouch sensor array10 includes asubstrate12 having a central (or active)portion14 and outer (or bezel)portions16 on opposing sides of thecentral portion14, near the edges of thesubstrate12. Thecentral portion14 of thesubstrate12 may correspond to the visible area of the touch sensor device2 (FIG. 1), and theouter portions16 of thesubstrate12 may correspond to thenon-visible area6 of thetouch sensor device2. In one embodiment, thesubstrate12 is made of an electrically insulating material with high optical transmissivity, such as glass, polyethylene terephthalate (PET), or a combination thereof.
• An array of electrodes is formed on thecentral portion14 of thesubstrate12, which includes a first set (or plurality) of electrodes (also, “first electrodes”)18 and a second set of electrodes (also, “second electrodes”)20. In the embodiment shown inFIG. 3, thefirst electrodes18 are substantially “comb” shaped having comb members facing down as shown inFIG. 3. In the depicted embodiment, fivefirst electrodes18 are included, which are arranged horizontally (as shown inFIG. 3) and substantially extend the entire width of thecentral portion14 of thesubstrate14. It should be understood thought that other embodiments may use different numbers of electrodes.
• Still referring toFIG. 3, thesecond electrodes20 are substantially “E” shaped and arranged such that the members thereof extend upwards (as shown inFIG. 3). In the embodiment shown, thirtysecond electrodes20 are included which are arranged in rows (i.e., horizontal rows)22, each of which is associated with one of thefirst electrodes18, and columns (i.e., vertical rows)24. In the exemplary embodiment shown, each of therows22 includes six of thesecond electrodes20, and each of thecolumns24 includes five of thesecond electrodes20. Within eachrow22, thesecond electrodes20 are mated with the respectivefirst electrode18 such that the members extending from thefirst electrodes18 and thesecond electrodes20 are inter-digitated. However, specific patterns shown inFIG. 3 are exemplary, and other electrode shapes which may not be inter-digitated are possible.
• As shown inFIG. 2, the size and shape of thesecond electrodes20 vary across thecentral portion14 of thesubstrate12. In particular, the thickness of the horizontal (as shown inFIG. 1) portions (or base portions)25 of thesecond electrodes20 is greater nearer the center of thesubstrate12.
• As will be described in more detail below, thefirst electrodes18 may be used as “transmitter” (TX) electrodes, andsecond electrodes20 may be used as “receiver” (RX) electrodes. However, it should be understood that these roles may be reversed in other embodiments.
• Referring now toFIG. 4 in combination withFIG. 3, thetouch sensor array10 also includes a (first) plurality of conductors, or primary traces,26 formed on thesubstrate12. In the example shown, the primary traces26 extend substantially horizontally (as shown inFIG. 4) across thesubstrate12. As shown, each of the primary traces26 is connected to, and thus in electrical contact with, a respect one of thefirst electrodes18 or one of thesecond electrodes20 at a first end portion thereof, and has a second end portion extending into one of theouter portions16 of the substrate. The primary traces26 may be considered to include a first set associated with (i.e., in contact with) thefirst electrodes18 and a second set associated with thesecond electrodes20.
• Thefirst electrodes18, thesecond electrodes20, and the primary traces26 may be made of indium tin oxide (ITO) and may be formed in a substantially planar manner. That is, although not specifically shown inFIGS. 3 and 4, thefirst electrodes18, thesecond electrodes20, and the primary traces26 may have substantially the same thickness (e.g., 300 Angstroms (Å)) and lay in substantially the same plane.
• Still referring toFIGS. 3 and 4, an insulating material (or body or layer)28 is coupled or attached to theouter portions16 of thesubstrate12. The insulatingmaterial28 covers the end portions of the primary traces26 that extend onto theouter portions16 of thesubstrate12. The insulatingmaterial28 may be made of, for example, an epoxy or resin material and have a thickness of, for example, between 5 and 25 micrometers (μm) that is deposited on thesubstrate12. It should be noted that the insulating material (or insulating bodies)28 do not extend over thecentral portion14 of the substrate.
• A (second) plurality of conductors, or secondary traces,30 are formed on the insulatingmaterial28 over bothouter portions16 of thesubstrate12. In one embodiment, thesecondary traces30 are made of silver. Of particular interest in the depicted embodiment is that each of thesecondary traces30 is electrically connected to either one (and only one)primary trace26 associated with one of thefirst electrodes18 or all ofprimary traces26 associated with thesecond electrodes20 in one (and only one) of thecolumns24 of second electrodes.
• For example, referring specifically toFIG. 4, the “first”secondary trace30a(i.e., counting from left to right inFIG. 4) is electrically connected to the top-mostfirst electrode18a(though the appropriate primary trace26), and the “sixth”secondary trace30bis electrically connected to all of thesecond electrodes20 in theleft-most column24 ofsecond electrodes20. The remaining electrical connections between thesecondary traces30 and the primary traces26, and thus the remainingelectrodes18 and20, are shown inFIGS. 3 and 4, and are similar in bothouter portions16 of thesubstrate12.
• The insulatingmaterial28 electrically separates eachsecondary trace30 from the other primary traces26 (i.e., those to which that particularsecondary trace30 is not electrically connected). For example, inFIG. 4, the insulatingmaterial28 insulates the “sixth”secondary trace30bfrom the primary traces26 connected to thesecond electrodes20 that are not in theleft-most column24 ofsecond electrodes20. That is, the primary traces26 connected to thesecond electrodes20 that are not in theleft-most column24 extend below the “sixth”secondary trace30bwithout making an electrical connection to the “sixth”secondary trace30b. The construction of the insulatingmaterial28, along with that of thesecondary traces26, will be described in greater detail below.
• As such, thesecondary traces30 provide unique electrical connections for each “pair” of thefirst electrodes18 and the second electrodes20 (i.e., one of thefirst electrodes18 and one of thesecond electrodes20 associated and inter-digitated with that particular first electrode18). For example, referring again toFIG. 4, one such pair of electrodes may include the top-mostfirst electrode18 and the left-mostsecond electrode20 in thetop row22. Through thesecondary traces30, this pair of electrodes is provided with electrical connections specifically through the “first”secondary trace30aand the “sixth”secondary trace30b. However, the pair of electrodes that includes the top-mostfirst electrode18 and the nextsecond electrode20 to the right in thetop row22 is provided with electrical connections through the left-mostsecondary trace30 and the “fifth”secondary trace30 as shown inFIG. 4.
• It should also be understood that thetouch sensor array12 may include an additional set of traces not shown in the figures. This additional set of traces may be used to provide a ground to electrically isolate thefirst electrodes18 and the immediately neighboringprimary traces26 connected to thesecond electrodes20. As such, each of the ground traces may be electrically connected to one of thesecondary traces30 in a manner similar to the respective primary traces26. The ground traces may be all connected to the same secondary trace that is used to connect them to the system ground.
• In the particular example shown inFIGS. 3 and 4, thirty pairs of electrodes are included, and unique electrical connections are provided to each of the pairs using twelvesecondary traces30, while the central (or active)portion14 of thesubstrate12 includes only a single layer of structures formed thereon.
• It should be noted, in other embodiments, the insulatingmaterial28 may be a flexible substrate, such as an FPC, attached to thesubstrate12. However, in an embodiment utilizing an FPC, the electrical connections between theprimary traces26 and thesecondary traces30 may be similar to those described above and shown inFIGS. 3 and 4, as well as those described below with respectFIGS. 5-11. In other words, when considered schematically,FIGS. 3,4, and5-11 may be understood to illustrate the electrical connections betweens the primary traces26 and thesecondary traces30 in embodiments utilizing the insulating material formed on thesubstrate12 as well as those utilizing an FPC.
• In operation, thesecondary traces30 are coupled to (i.e., are in operable communication with) an electronic system (an example of which is described below). In general, thecapacitive sensor array10 is operated by providing a signal to one of the first electrodes18 (i.e., TX electrodes) while grounding the otherfirst electrodes18. Signals are generated in thesecond electrodes20 associated with the drivenfirst electrode18 by electrical coupling of the drivenfirst electrode18 to thesecond electrodes20 associated with the drivenfirst electrode18. The signal induced in thesecond electrodes20 may change due to the presence of an object (e.g., a finger) on, or near, that portion of thesensor array10. The signal change in thesecond electrodes20 is indicative of change in the capacitance between thesecond electrode20 and the respective first electrode (i.e., “mutual capacitance”). This process is continuously repeated for each of thefirst electrodes18 and each of the associated rows ofsecond electrodes20.
• In the embodiment shown inFIG. 3, the primary traces26 for thesecond electrodes20 are routed to the long(er) sides of thesubstrate12. As shown, the primary traces26 connected to thesecond electrodes20 that occupy the left side of the central portion14 (i.e., are closer to theouter portion16 on the left) extend into theouter portion16 on the left. Likewise, the primary traces26 connected to thesecond electrodes20 that occupy the right side of the central portion14 (i.e., are closer to theouter portion16 on the right) extend into theouter portion16 on the right. The primary traces26 for thefirst electrodes18 are arranged such that some (e.g., for thefirst electrodes18 in the upper region of the central portion14) extend into theouter portion16 on the left, while the remaining primary traces26 (e.g., for the first electrodes in the lower region of the central portion14) extend into theouter portion16 on the right. This method of routing may minimize the size of the side bezels, and also minimizes the width of the gap between thesensor rows22.
• Although the “side” bezel topology shown inFIG. 3 may be implemented using ITO formed on glass, it may be most suitable for ITO on PET, as in this topology the length of the primary traces26 is relatively short compared to the “bottom” bezel topology described below. Furthermore, due to geometrical configuration of the electrodes, there are far less traces in the gap between consecutive rows. Thus, the traces in a side bezel configuration may be wider, and the material used for the traces may have higher sheet resistance. Typically, ITO/PET has a higher sheet resistance than that of ITO/glass.
• Furthermore, to keep manufacturing costs lower than ITO/Glass technology, usually photolithography is not used for patterning ITO/PET. Therefore, the minimum line width and space in ITO/PET is much higher than those in ITO/Glass. Nevertheless, in side bezel sensors, higher sheet resistance and greater trace widths may be tolerated. Therefore, ITO/PET with greater ITO sheet resistance and wider traces may be preferred for side bezel topology.
• FIG. 5 illustrates thetouch sensor array10 according to another embodiment of the present invention. Similar to the embodiment shown inFIG. 3, thetouch sensor array10 shown inFIG. 5 includes asubstrate12 with anactive portion14 and abezel portion16. However, only onebezel portion16 is included along the bottom (as shown inFIG. 5) edge of thesubstrate12. Thetouch sensor array10 also includes an array offirst electrodes18 andsecond electrodes20. Thesubstrate12 as shown inFIG. 5 has been rotated compared to that ofFIG. 3 such that thecolumns24 correspond to thefirst electrodes18, and therows22 correspond to thesecond electrodes20.
• Because there is only onebezel portion16, all of the primary traces26 extend from thefirst electrodes18 andsecond electrodes20 towards the bottom of thesubstrate12, across the entireactive portion14. Within thebezel portion16, the primary traces26 are electrically connected to thesecondary traces30 in a manner similar to that described above (i.e., such that each electrode pair is provided electrical connections through a unique pair of the secondary traces30).
• One skilled in the art may appreciate that due to the electrical resistance of the traces, the embodiment shown inFIG. 5 may be more suitable for smaller devices (e.g., with diagonal lengths across theactive area14 of, for example, 10 centimeters or less).
• FIGS. 6,7, and8 illustrate, in greater detail, the insulatingmaterial28, the primary traces26, and thesecondary traces30 on anouter portion16 ofsubstrate12 according to one embodiment of the present invention. The example shown includes nineprimary traces26, with seven of the primary traces26 being electrically connected to a first secondary trace30 (FIG. 7) and two of the primary traces26 (extending farther into the insulating material28) being electrically connected to a second secondary trace30 (FIG. 8). The electrical connections are made through via-holes32 that are filled with aconductive material34. As shown specifically inFIG. 7, two of the primary traces26 are insulated from the first of thesecondary traces30 by the insulatingmaterial28 due, at least in part, to the lack of a via-hole32 andconductive material34 formed at those locations.
• FIGS. 9,10, and11 illustrate an outer (or bezel)portion16 of thesubstrate12 and a process for forming the connections between theprimary traces26 and thesecondary traces30 according to one embodiment. Although not specifically shown, in order to form the electrodes (e.g.,electrodes18 and20 inFIG. 3), a layer of transparent conductive material, such as ITO or a silver nano-particle film, may be deposited on (or over) thesubstrate12. The deposition method used may depend on the material chosen. For example, if the material is ITO, the material may be deposited by vacuum sputtering. If the material is silver nano-particles, the material may be deposited by variety of techniques such as dipping method, spin coating, etc. In a preferred embodiment of the invention, the sheet resistance of the conductive material is less than or equal 50 ohm/square.
• The conductive layer may then be patterned. Patterning may be achieved by various methods. For example, a resist layer may be deposited on the conductive layer, and the conductive material may be chemically removed in selected areas. Alternatively, patterning the conductive layer may be achieved by removing the material from selected areas using methods such as laser ablation and plasma etching. As another alternative, by using a mask, the conductive layer may be deposited only on the desired areas of thesubstrate12. In other words, the conductive material may be deposited in the final desired pattern (i.e., in the appropriate shape to form theelectrodes18 and20 and the primary traces26). In such a case, no removal of material is necessary.
• As another alternative, the pattern may be generated by the lift off process. In such a process, a mask material is laid down on thebare substrate12 on the deletion areas where the conductive material is not desired. The conductive material is then deposited on the whole substrate indiscriminately. The mask material may then be chemically removed from thesubstrate12 to leave the conductive material in selected areas. In a preferred embodiment of the invention, the finished pattern has a minimum line width of 30 μm, and minimum spacing of 10 μm.
• Referring now toFIG. 9, the patterning is performed such that the primary traces26 extend into theouter portion16 of thesubstrate12. The insulating material (or dielectric layer)28 is deposited (e.g., using screen printing) on theouter portion16 of thesubstrate12 such that the end portions of the primary traces26 are covered. The insulatingmaterial28 includes a series of via-holes32, with each of the via-holes32 being positioned over a respective one of the primary traces26. Thedielectric material28 may be any insulating heat curing or UV curing ink available, such as LPI resist and acrylic resin.
• Referring now toFIG. 10, the via-holes32 are then filled with a conductive material to form a conductive via34 in each of the via-holes32, which is in contact with the respectiveprimary trace26. In one embodiment, the conductive material used to form the conductive via34 is silver ink or copper ink.
• In one embodiment, theconductive vias34 are formed using the same material, and during the same process step, as that is used to form the secondary traces30. In such an embodiment, the insulatingmaterial28 is thin enough to allow the material of thesecondary traces30 to flow into the via-holes32 and make reliable contact to the primary traces26. However, the insulatingmaterial28 may be thick enough such that it does not have any pores or pinholes. In a preferred embodiment, the insulatingmaterial28 is between 5-10 μm thick. In another preferred embodiment, the insulatingmaterial28 is black and acts as a decorative band around thetouch sensor array10. In yet another embodiment of the invention, the via-holes are initially filled with black carbon ink.
• Then, as shown inFIG. 11, thesecondary traces30 are formed on the insulatingmaterial28, with eachsecondary trace30 extending over, and contacting, one (or more) of theconductive vias34. Thus, each of thesecondary traces30 is electrically connected to one (or more) of the primary traces26 through a conductive via34. As such, theconductive vias34 may represent contact points, or nodes, for the electrical connection of thesecondary traces30 to the respective primary traces26. It should be noted that these contact points are external to (i.e., not positioned over) thecentral portion14 of thesubstrate12.
• A black ink may be used as the insulatingmaterial28 to hide the traces and interconnects in theouter portion16. If the touch sensor device is a sensor on lens (SOL) design, it may be desirable to hide the metal traces. A sensor on lens is a touch sensor device that includes a lens and the electrodes deposited on its bottom surface. In such an embodiment, the black ink may serve to hide the secondary traces and provide insulation between theprimary traces26 andsecondary traces30. The via-holes32 in the black ink may still show the secondary traces30. To prevent this, the via-holes32 may be filled with conductive carbon ink (which is also black). The use of a conductive ink also facilitates the formation of a good electrical connection between theprimary traces26 and the secondary traces30.
• Other colors may be used for the insulatingmaterial28. For example, a white insulating layer may be used. In such an embodiment, the via-holes32 are filled with white ITO ink, which is a mixture of ITO and a white pigment, prior to the formation of the secondary traces30. The white ITO is also a conductive ink and is thus suitable to form theconductive vias34.
• In one embodiment, the insulating material (or bodies)28 are only applied over the primary traces26 wherever necessary to avoid undesired contacts. Such an embodiment facilitates reducing the area of the bezel used for interconnections, reduces the amount of insulating material used in the process, and eliminates any potential difficulties in making good contact between theprimary traces26 and thesecondary traces30, as via-holes and conductive vias are not needed.FIG. 12 illustrates such an embodiment, including a row ofsecond electrodes20, primary traces26, andouter portion16 of asubstrate12 according to another embodiment.
• As shown, as the primary traces26 extend into theouter portion16, the primary traces26 “fan out.” That is, as the primary traces26 extend into theouter portion16 of thesubstrate12, the distance between adjacentprimary traces26 increases. Also of particular interest in the embodiment shown inFIG. 12 is the size and shapes (e.g., a “polygonal” shape) of the insulating material (or bodies)28, which allows the insulatingmaterial28 to appropriately insulate and connect the primary traces26 and thesecondary traces30 without via-holes and/or conductive vias being formed therein. More specifically, the insulatingmaterial28 allows thesecondary traces30 to pass over, and remain insulated from, the appropriate primary traces26. In the example shown, a first insulatingbody28 is used to selectively insulate the primary traces26 connected to thesecond electrodes20 from thesecondary traces30, while a second insulatingbody28 is used to selectively insulate the primary traces26 connected to thefirst electrode18 from the secondary traces30.
• As shown, the first insulatingbody28 is shaped to have multiple tiers or portions such that the width of the insulating material decreases as the insulating material extends from thecentral portion14 of thesubstrate12. Further, it should be noted that the two outer mostsecondary traces30 do not extend over the first insulatingbody28. Thus, the size and shape of the first insulatingbody28 allows for each of the primary traces26 shown to be electrically connected to only one of thesecondary traces30 while minimizing the amount of insulating material used. Likewise, the second insulatingbody28 insulates theprimary trace26 connected to thefirst electrode18 from all but the outer most secondary electrode, also while minimizing the amount of insulating material used.
• To reduce the routing area in the bezel (or outer portion16), the trace width and spacing of the traces in the bezel area are minimized. In a preferred embodiment, a metal trace line width of 10-50 μm and a spacing of 10-50 μm is used in the bezel area.
• When the traces are very narrow (e.g., 10-50 μm) it may be difficult to establish a low contact resistant between theprimary traces26 and thesecondary traces30 unless the contact area is large enough. Still referring toFIG. 12, in one embodiment, the end portions of the primary traces26 are “bent” into an L-shaped pattern to increase the contact area between theprimary traces26 and the secondary traces30. More specifically, the end portions of the primary traces26 are bent in a direction substantially parallel to the direction in which thesecondary traces30 extend.
• As mentioned with reference toFIG. 3, in some embodiments, width of thebase portion25 of thesecond electrodes20 varies to fill the void spaces created otherwise. Referring again toFIG. 12, thesecond electrode20 nearest to the bezel (i.e., the first second electrode) uses a shortprimary trace26 and uses the minimum base portion width. The nextprimary trace26 is positioned at least the width of the first primary trace26 (e.g., 10-50 μm) plus a minimum spacing from the base portion of the firstsecond electrode20 and may also have a minimum width of 30-50 μm. Therefore, the base portion of the nextsecond electrode20 may have a width which is wider than the firstsecond electrode20 base width by an amount equal to, for example, the width of the primary traces26 combined with the distance between adjacent primacy traces26. Using such a layout method, the base of each subsequentsecond electrode20 may increase by a fixed amount which is equal to the trace width combined with the trace spacing.
• It should be noted that the order in which the components are formed on thesubstrate12 may be changed. For example, referring once again toFIG. 12, thesecondary traces30 may be formed on theouter portion16 of thesubstrate12 before the insulatingbody28 and the primary traces26 are formed. For example, thesecondary traces30 may be formed on theouter portion16 in a flat, planar manner (i.e., not over the insulating body28). The insulatingbody28 may then be formed over the secondary traces30. Then, the primary traces26 (along with theelectrodes18 and20) may then be formed such that they extend over the insulatingbody28 and connect with thesecondary traces30 in a manner similar to that described above. In such an embodiment, the lateral spatial relationships between theprimary traces26, thesecondary traces30, and the insulatingbody28 may be similar to that shown inFIG. 12.
• FIG. 13 illustrates thetouch sensor array10 according to another embodiment of the present invention, which may be particularly well suited for large screen applications (e.g., having a diagonal length greater than 25 cm). As may be apparent when comparing the embodiments shown inFIGS. 3 and 5 with that shown inFIG. 13, the embodiment shown inFIG. 13 is a combination of the of the side bezel topology and the bottom bezel topology. That is, although the bezel (or outer)portions16 are positioned on the sides, both of thebezel portions16 includes primary traces26 (and secondary traces30) connected to thefirst electrodes18 and thesecond electrodes20. When compared to the bottom bezel topology shown inFIG. 5, the embodiment shown inFIG. 13 may be considered to be a bottom bezel configuration rotated 90 degrees and “mirrored” about acenter line37 extending through thecenter portion14. However, as shown, eachrow22 of electrodes includes only onefirst electrode18 that extends across theentire center portion14, which is connected to eachbezel portion16 by a separate primary trace26 (i.e., thefirst electrodes18 are connected to both bezels portions).
• As discussed above, in other embodiments, the multi-layer routing of the traces may be accomplished by using a flexible printed circuit (FPC) (and/or a FPC tail), which includes a flexible insulating substrate (i.e., made of an insulating material) with a series of traces (i.e., secondary traces) formed thereon. In such an embodiment, the FPC tail may be coupled to the substrate (e.g., substrate12) at the edge (or edges) of theactive portion14 and may be wrapped around thesubstrate12, effectively eliminating thebezel portion16 of the array.
• FIG. 14 schematically illustrates an embodiment utilizing an FPC (and/or FPC tail)36. As shown, similar to the embodiments described above, thesubstrate12 includesprimary traces26 that extend onto theouter portion16 of thesubstrate12. However, a substrate bond pad38 (e.g., made of ITO or silver) is formed at the end portion of each of the primary traces26. Although not specifically shown inFIG. 14, theFPC36 includes one or more flexible insulating layers (e.g., polyamide, polyimide, or PET) interlaced with one or more conductive layers (e.g., copper), which may be formed (or etched) into a series of traces (i.e., the secondary traces30) that haveFPC bond pads40 at the end portions thereof.
• Eachsubstrate bond pad38 is electrically connected to a uniqueFPC bond pad40. In a manner similar to the insulatingmaterial28 formed on thesubstrate material28 described above, the desired interconnections between theprimary traces26 and thesecondary traces30 are made within theFPC36. For example, inFIG. 14 it is shown that the secondprimary trace26 from the left is connected to the eighthprimary trace26 from the left through thesecondary traces30 on theFPC36. The othersecondary traces30 that are connected to achip42 on theFPC36 and encounter thetrace30 connected to thesecond pad40 from the left will have to “jump over” (or remain insulated from) that trace to avoid unwanted electrical connection. These jumps are schematically shown inFIG. 14 byreference numeral44. In an FPC, these interconnections are realized by using two conductive layers on the FPC tail and via-holes that interconnect the two layers.
• FIGS. 15-17 illustrate an embodiment of thetouch sensor array10 that may use the bottom bezel topology shown inFIG. 5. However, as shown, thesubstrate12 has been rotated 90 degrees such that thebezel portion16 is position on the right side of thesubstrate12. In this embodiment, anFPC tail36 is used to both route the signals from the primary traces26 (e.g., viabond pads38 and40) shown inFIG. 14 as well as connecting to an external system. As shown specifically inFIG. 17, the electrical connections between theprimary traces26 and the secondary traces30 (formed on the FPC36) are made via thesubstrate bond pads40 at the end portion of the primary traces26, abonding material48, theFPC bond pads40 formed on theFPC36, and a conductive material (or via)34 formed through the FPC36 (which interconnects theFPC bond pads40 and the secondary traces30). As will be appreciated by one skilled in the art, theFPC36 may be manufactured and configured before being attached to the substrate12 (i.e., theFPC bond pads40, theconductive vias34, and thesecondary traces30 may be selectively formed on theFPC36 before theFPC36 is attached to the substrate12).
• In one embodiment, thebonding material48 is an anisotropic conductive film (ACF), which includes microscopic conductive spheres distributed in a matrix of a soft insulating material. When pressure is applied, the spheres come to contact with each other and form a conduction path for the electric signals. When the ACF is deposited between thesensor bond pads38 and theFPC bond pads40, the pressure is only applied in the regions trapped vertically between thepads38 and40. Therefore, conduction paths are formed only in the pads regions (i.e., between eachsensor bond pad38 and the associatedFPC bond pad40, even if the ACF is deposited between adjacentsensor bond pads38 on thesubstrate12 and/or between adjacentFPC bond pads40 on the FPC.
• FIGS. 18-20 illustrate an embodiment of thetouch sensor array10 that may be similar to that shown inFIG. 13. That is, thetouch sensor array10 inFIGS. 15 and 16 includes twobezel portions16. Thetouch sensor array10 is arranged such that thebezel portions16 occupy the top portion and the bottom portion of the device. As shown inFIG. 19, thetop bezel portion16 utilizes the insulatingmaterial28 formed on the substrate, such as that shown inFIGS. 6-11. However, as shown inFIG. 20, thebottom bezel portion16 utilizes anFPC tail36 for routing, as well as for connecting to an external system. Additionally, as shown in bothFIGS. 19 and 20, a series of routing traces46 (which may be similar to thesecondary traces30 formed on the insulating material28) are formed along an edge of thecentral portion14 of thesubstrate12. The routing traces46 are electrically connected to thesecondary traces30 on the insulatingmaterial28 at thetop bezel portion16 and electrically connected to the traces within theFPC tail36. It should be understood that in other embodiment, an FPC may also be used in thetop bezel portion16 for routing the signals from the primary traces26 to the routing traces46 (and not for connecting to an external system). Additionally, although the embodiment shown is depicted as having all of the second electrodes facing or oriented in the same direction, in other embodiments, particularly those used in large screen applications, the electrodes may be arranged such that some (e.g., those on one half of the substrate12) face or are oriented in one direction, while the remaining are oriented in the opposite direction.
• Furthermore, in some embodiments, an FPC with a tail may also be used in both the top andbottom bezel portions16 for both routing the signals from the primary traces26 and connecting to an external system (i.e., the top bezel portion and the bottom bezel portion utilize separate FPCs/FPC tails). An example of such an embodiment is shown inFIG. 21.
• FIGS. 22-25 illustrate a further embodiment of the present invention. Of particular interest inFIGS. 22-25 is that the insulatingmaterial28 is formed on asecond substrate50 that is separate from the (first electrode)substrate12. As shown, thesecond substrate50 is connected to thefirst substrate12 by a FPC (or a Flat Flex Connector FFC)36. As will be appreciated by one skilled in the art, particularly in light of the use of the FPC described above, theFPC36 inFIGS. 22-25 is used to electrically connect the primary traces26 on thefirst substrate12 to thesecondary traces30 on the insulatingmaterial28 via bond pads formed on the first substrate12 (e.g., near the edge or outer portion thereof), traces on theFPC36, and bond pads and additional traces on thesecond substrate50. As such, thesecondary traces30 shown inFIG. 22 may be electrically connected to the primary traces26 on thefirst substrate12 in a manner similar to that described above. Additionally, although not specifically shown, it should be understood that other components may be mounted on (or attached to) thesecond substrate12, such as integrated circuits, as well as other active and passive components.
• Furthermore, because of the flexible nature of the FPC36 (i.e., in contrast to the rigid material of the first and second substrates, such as glass and a printed circuit board, respectively), thesecond substrate50 may be mounted in various orientations and/or positions relative to thefirst substrate12. Examples of such orientations and/or positions are illustrated inFIGS. 23-25.
• FIGS. 26-30 illustrate alternative shapes and arrangements of thefirst electrodes18 and thesecond electrodes20, according to various embodiments of the present invention. For example, the embodiment shown inFIG. 26 includes afirst electrode18 andsecond electrodes20 that include intertwined “spiral” structures, as opposed to the “comb” and “E” shaped structures previously discussed. However, it should be understood that other shapes and arrangements may be used, as shown by the various embodiments illustrated inFIGS. 27-30.
• In other embodiments, different materials may be used to form the electrodes, such as copper, aluminum, silver, or any suitable conductive material that may be appropriately patterned. Furthermore, an FPC may be used to form the electrodes. In such an embodiment, the various conductive layers in the FPC may be appropriately configured to form the array of electrodes as described above, as well as to form the primary traces. As such, it should be understood that the electrodes, the traces, and the insulating material (or body) may all be formed by a single, appropriately configured FPC. As will be appreciated by one skilled in the art, such embodiments may be particularly applicable to non-transparent devices, such as mouse pads, track pads, touch pads, etc. Additionally, in other embodiments, the substrate may be made of other materials, such as any suitable plastic, including vinyl and polyamide, which may not be transparent, depending on the particular device.
• In other embodiments, the sensor may be formed by laying out the sensor electrodes using alternative conductive materials such as metal mesh. In this embodiment, the electrodes are formed by disposing metal mesh electrodes on PET substrate. In an alternative embodiment, the metal mesh electrodes may be disposed on glass substrate. In another embodiment, the electrodes may be formed with silver nano-wires on PET or silver nano-wire on glass substrate.
• In another embodiment, the sensor may be formed by bonding a glass (or other transparent insulating) lens onto another glass with the sensor pattern disposed on. In yet another embodiment, the sensor may be formed by bonding glass (or other transparent insulating material) onto a sheet of PET containing the sensor pattern.
• As such, embodiments described herein provide a capacitive sensor device with a single layer structure in the active portion of the device, while a multi-layer structure is used in the bezel (or other non-sensing) portions for routing the traces. The multi-layer routing allows the repeated use of the traces so that the device uses the absolute minimum number of traces, and the minimum number of pins on the electronic system which drives the device.
• With respect to the embodiments described above, the gap between the rows22 (e.g.,FIG. 3) is determined by the maximum number ofprimary traces26 extending into the bezel portion(s)16.
• As will be appreciated by one skilled in the art, it is preferable to minimize the gap size by minimizing the trace widths and the space between the traces. The minimum trace width may be determined by the resistance of the traces and the limits of the process used to form the traces. The width of traces made of ITO may be minimized by lowering the sheet resistance of the ITO. In some embodiments, in order to avoid cross coupling between the first and second electrodes of the neighboring rows (or columns), a ground trace may be formed, which would increase the minimum gap size.
• However, when the substrate is glass, rather than PET, lower sheet resistance of ITO and better trace width and spacing may be achieved, which leads to reducing the gap size between the neighboring electrodes.
• Further, the pitch size (i.e., the distance between the centers of the two neighboring sensor cells or electrodes) may be adjusted by varying the pad size (i.e. the width of one of the second electrodes20). However, it may be preferable to use a pitch of 6 mm or less.
• FIG. 31 illustrates a block diagram of one embodiment of an electronic system having a processing device for detecting a presence of a conductive object according to an embodiment of the present invention. Theelectronic system100 includes aprocessing device110, a touch-sensor pad120, a touch-sensor slider130, touch-sensor buttons140, ahost processor150, an embeddedcontroller160, andnon-capacitance sensor elements170. Theprocessing device110 may include analog and/or digital general purpose input/output (“GPIO”)ports107. TheGPIO ports107 may be programmable and may be coupled to a Programmable Interconnect and Logic (“PIL”), which acts as an interconnect between theGPIO ports107 and a digital block array of theprocessing device110. Theprocessing device110 may also include memory, such as random access memory (“RAM”)105 andprogram flash104. TheRAM105 may be static RAM (“SRAM”), and theprogram flash104 may be a non-volatile storage, which may be used to store firmware (e.g., control algorithms executable by processingcore102 to implement operations described herein). Theprocessing device110 may also include a memory controller unit (“MCU”)103 coupled to memory and theprocessing core102.
• Theprocessing device110 may also include one or more analog blocks array coupled to the system bus. The analog blocks array also may be configured to implement a variety of analog circuits (e.g., ADCs, DACs, analog filters, etc.). The analog block array may also be coupled to theGPIO107.
• As illustrated, thecapacitance sensing circuit101 may be integrated into theprocessing device110. Thecapacitance sensing circuit101 may include analog I/O for coupling to an external component, such as the touch-sensor pad120, the touch-sensor slider130, the touch-sensor buttons140, and/or other devices. Thecapacitance sensing circuit101 and theprocessing device110 are described in more detail below.
• The embodiments described herein are not limited to touch-sensor pads for notebook implementations, but can be used in other capacitive sensing implementations, for example, the sensing device may be a touch screen, a touch-sensor slider130, or touch-sensor buttons140 (e.g., capacitance sensing buttons). In one embodiment, these sensing devices may include one or more capacitive sensors. The operations described herein are not limited to tablet computers, smartphones, touchscreen phone handsets, mobile internet devices (MIDs), GPS navigation devices, electronic books, notebook pointer operations, but can include other operations, such as lighting control (dimmer), volume control, graphic equalizer control, speed control, or other control operations requiring gradual or discrete adjustments. It should also be noted that these embodiments of capacitive sensing implementations may be used in conjunction with non-capacitive sensing elements, including but not limited to pick buttons, sliders (ex. display brightness and contrast), scroll-wheels, multi-media control (ex. volume, track advance, etc) handwriting recognition and numeric keypad operation.
• In one embodiment, theelectronic system100 includes a touch-sensor pad120 coupled to theprocessing device110 viabus121. The touch-sensor pad120 may include a multi-dimension sensor array. The multi-dimension sensor array includes multiple sensor elements, organized as rows and columns, such as the sensor arrays described above and shown in, for example,FIGS. 3,5, and13. In another embodiment, theelectronic system100 includes a touch-sensor slider130 coupled to theprocessing device110 viabus131. The touch-sensor slider130 may include a single-dimension sensor array. The single-dimension sensor array includes multiple sensor elements, organized as rows, or alternatively, as columns. In another embodiment, theelectronic system100 includes touch-sensor buttons140 coupled to theprocessing device110 viabus141. The touch-sensor buttons140 may include a single-dimension or multi-dimension sensor array. The single- or multi-dimension sensor array may include multiple sensor elements. For a touch-sensor button, the sensor elements may be coupled together to detect a presence of a conductive object over the entire surface of the sensing device. Alternatively, the touch-sensor buttons140 may have a single sensor element to detect the presence of the conductive object. In one embodiment, the touch-sensor buttons140 may include a capacitive sensor element. The capacitive sensor elements may be used as non-contact sensor elements. These sensor elements, when protected by an insulating layer, offer resistance to severe environments.
• Theelectronic system100 may include any combination of one or more of the touch-sensor pad120, the touch-sensor slider130, and/or the touch-sensor button140. In another embodiment, theelectronic system100 may also includenon-capacitance sensor elements170 coupled to theprocessing device110 viabus171. Thenon-capacitance sensor elements170 may include buttons, light emitting diodes (“LEDs”), and other user interface devices, such as a mouse, a keyboard, or other functional keys that do not require capacitance sensing. In one embodiment,buses171,141,131, and121 may be a single bus. Alternatively, these buses may be configured into any combination of one or more separate buses.
• Theprocessing device110 may include internal oscillator/clocks106 and a communication block (“COM”)108. The oscillator/clocks106 provides clock signals to one or more of the components of theprocessing device110. Thecommunication block108 may be used to communicate with an external component, such as ahost processor150, via host interface (“I/F”)line151, using signaling protocols such as, but not limited to I2C, SPI or USB. Alternatively, theprocessing block110 may also be coupled to embeddedcontroller160 to communicate with the external components, such ashost150. In one embodiment, theprocessing device110 is configured to communicate with the embeddedcontroller160 or thehost150 to send and/or receive data.
• Theprocessing device110 may reside on a common carrier substrate such as, for example, an integrated circuit (“IC”) die substrate, a multi-chip module substrate, or the like. Alternatively, the components of theprocessing device110 may be one or more separate integrated circuits and/or discrete components. In one exemplary embodiment, theprocessing device110 may be a Programmable System on a Chip (“PSoC™”) processing device, manufactured by Cypress Semiconductor Corporation, San Jose, Calif. Alternatively, theprocessing device110 may be one or more other processing devices known by those of ordinary skill in the art, such as a microcontroller, a microprocessor or central processing unit, a controller, a special-purpose processor, a digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”), or the like.
• It should also be noted that the embodiments described herein are not limited to having a configuration of a processing device coupled to a host, but may include a system that measures the capacitance on the sensing device and sends the raw data to a host computer where it is analyzed by an application. In effect the processing that is done by processingdevice110 may also be done in the host.
• Thecapacitance sensing circuit101 may be integrated into the IC of theprocessing device110, or alternatively, in a separate IC. Alternatively, descriptions of thecapacitance sensing circuit101 may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing thecapacitance sensing circuit101, or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium (e.g., CD-ROM, hard disk, floppy disk, etc.). Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe thecapacitance sensing circuit101.
• It should be noted that the components of theelectronic system100 may include all the components described above. Alternatively, theelectronic system100 may include only some of the components described above.
• In one embodiment, theelectronic system100 may be used in a notebook computer. Alternatively, theelectronic system100 may be used in other applications, such as a mobile handset, a personal data assistant (“PDA”), a keyboard, a television, a remote control, a monitor, a handheld multi-media device, a handheld video player, a handheld gaming device, or a control panel.
• The conductive object in this case is a finger, alternatively, this technique may be applied to any conductive object, for example, a conductive door switch, position sensor, or conductive pen in a stylus tracking system.
• Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.
• Thus, in one embodiment, a capacitance sensing device is provided. The capacitance sensing device includes a substrate having a central portion and an outer portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating material is coupled to the second end portions of the first plurality of conductors. A second plurality of conductors is coupled to the insulating material. The second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors.
• In another embodiment, a capacitance sensing device is provided. The capacitance sensing device includes a substrate having a central portion and an outer portion. A first set of electrodes is formed on the central portion substrate. A second set of electrodes is formed on the central portion of the substrate. The second set of electrodes is arranged in a series of rows and is substantially co-planar with the first set of electrodes. A first plurality of conductors are formed on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the first set of electrodes and a second end portion on the outer portion of the substrate. A second plurality of conductors are formed on the substrate. Each of the second plurality of conductors has a first end portion electrically connected to one of the second set of electrodes and a second end portion on the outer portion of the substrate. An insulating body is coupled to the second end portion of each of the first plurality of conductors and the second end portion of each of the second plurality of conductors. A third plurality of conductors is coupled to the insulating body such that each is electrically connected to one of the second end portion of one of the first plurality of conductors and the second end portion of the second plurality of conductors associated with only one row of the second set of electrodes and is electrically insulated from the second end portion of the others of the first set of conductors and the second end portion of the second plurality of conductors associated with the other rows of the second set of electrodes.
• In a further embodiment, a capacitance sensing device is provided. The capacitance sensing device includes a substrate having a central portion and an outer portion. A first set of electrodes is formed on the central portion substrate. A second set of electrodes is formed on the central portion of the substrate. The second set of electrodes is arranged in a series of rows and substantially co-planar with the first set of electrodes. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one electrode of the first set of electrodes or the second set of electrodes and a second end portion on the outer portion of the substrate. A second plurality of conductors is coupled to the substrate. Each of the second plurality of conductors is electrically connected to at least one of the first plurality of conductors at a node that is external to the central portion of the substrate such that each of the second plurality of conductors is electrically connected to one electrode of the first set of electrodes or a plurality of electrodes in one of the rows of the second set of electrodes.
• In a further embodiment, a method for constructing a capacitance sensing device is provided. A plurality of electrodes are formed on a central portion of a substrate. The substrate has a central portion and an outer portion. A first plurality of conductors are formed on the substrate. Each of the first plurality of conductors is connected to and extends from at least one of the plurality of electrodes. An insulating material is formed on the outer portion of the substrate and at least partially over some of the first plurality of conductors. A second plurality of conductors are formed on the insulating material, wherein the second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to at least some of the first plurality of conductors and is insulated from the others of the first plurality of conductors.
• In a further embodiment, a method for constructing a capacitance sensing device is provided. A plurality of substantially co-planar electrodes are formed on the central portion of the substrate. A first plurality of conductors are formed on the substrate. Each of the first plurality of conductors has a first end electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate. An insulating body is attached to the outer potion of the substrate adjacent to the second end portions of the first plurality of conductors. Each of a second plurality of conductors on the insulating body is electrically connected to the second end portion of at least some of the first plurality of conductors. Each of the second plurality of conductors is insulated from the second end portion of the others of the first plurality of conductors by the insulating body.
• In a further embodiment, a method for constructing a capacitance sensing device is provided. A substrate having a central portion and an outer portion is provided. A plurality of substantially co-planar electrodes is formed over the central portion substrate. A first plurality of traces are formed over the substrate. Each of the first plurality of traces have a first end portion electrically connected to one of the plurality of electrodes and a second end portion over the outer portion of the substrate. An insulating body is formed over the outer potion of the substrate. The insulating body has a first width at a first portion thereof and a second width at a second portion thereof. The first width is greater than the second width. A second plurality of traces are formed over the outer portion of the substrate. The first plurality of traces, the second plurality of traces, and the insulating material are arranged such that each of the second plurality of traces is electrically connected to at least some of the first plurality of traces and is insulated from the others of the first plurality of traces.
• In a further embodiment, a capacitance sensing device is provided. The capacitance sensing device includes a substrate having a central portion, a first outer portion, and a second outer portion. The first outer portion and the second outer portion are on opposing sides of the central portion. A plurality of substantially co-planar electrodes are on the central portion substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors having a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the first outer portion or the second outer portion of the substrate. A first insulating body is coupled to the first outer portion of the substrate. A second insulating body is coupled to the second outer portion of the substrate. A second plurality of conductors are included. Each of the second plurality of conductors is coupled to the first insulating body or the second insulating body. The second plurality of conductors, the first insulating body, and the second insulating body are configured such that each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors on the respective outer portion of the substrate and is insulated from the others of the first plurality of conductors by the respective insulating body.
• In a further embodiment, a capacitance sensing device is provided. The capacitance sensing device includes a first substrate having a central portion and an outer portion. A plurality of substantially co-planar electrodes are on the central portion of the first substrate. A first plurality of conductors are on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the first substrate. A second substrate is also included. A second plurality of conductors are connected to the second substrate. At least one insulating body is coupled to the first substrate and the second substrate, wherein the second plurality of conductors and the at least one insulating body are configured such that each of the second plurality of conductors is electrically connected to at least some of the first plurality of conductors and is insulated from the others of the first plurality of conductors.
• In a further embodiment, a method for constructing a capacitance sensing device is provided. A substrate having a central portion, a first outer portion, and a second outer portion is provided. The first outer portion and the second outer portion are on opposing sides of the central portion. A plurality of substantially co-planar electrodes are formed on the central portion substrate. A first plurality of conductors are formed on the substrate. Each of the first plurality of conductors has a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the one of first outer portion and the second outer portion of the substrate that is closer to the respective one of the plurality of electrodes. A first insulating body is attached to the first outer portion of the substrate. A second insulating body is attached to the second outer portion of the substrate. Each of a second plurality of conductors on the first insulating body and the second insulating body are electrically connected to the second end portion of at least some of the first plurality of conductors on the respective outer portion of the substrate. Each of the second plurality of conductors is insulated from the others of the first plurality of conductors by the respective insulating body.
• Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.

Claims (20)

1. A capacitance sensing device comprising:

a substrate having a central portion and an outer portion;

a plurality of substantially co-planar electrodes on the central portion substrate;

a first plurality of conductors on the substrate, each of the first plurality of conductors having a first end portion electrically connected to one of the plurality of electrodes and a second end portion on the outer portion of the substrate;

an insulating material coupled to the second end portions of the first plurality of conductors; and

a second plurality of conductors coupled to the insulating material, wherein the second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to the second end portion of at least some of the first plurality of conductors and is insulated from the second end portion of the others of the first plurality of conductors.

2. The capacitance sensing device ofclaim 1, wherein the insulating material is formed on the outer portion of the substrate, and the second plurality of conductors are formed on the insulating material.

3. The capacitance sensing device ofclaim 1, wherein the insulating material is not formed over the central portion of the substrate.

4. The capacitance sensing device ofclaim 1, wherein the plurality of substantially co-planar electrodes comprises a first set of electrodes and a second set of electrodes, wherein the second set of electrodes is arranged in a series of rows.

5. The capacitance sensing device ofclaim 4, wherein the first plurality of conductors comprises a first set of traces and a second set of traces, wherein the first end portion of each of the first set of traces is electrically connected to one of the first set of electrodes and the first end portion of each of the second set of traces is electrically connected to one of the second set of electrodes.

6. The capacitance sensing device ofclaim 5, wherein the second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to the second end portion of a selected one of the first set of traces or the second end portions of the second set of traces having first end portions electrically connected to the electrodes in one row of the second set of electrodes.

7. The capacitance sensing device ofclaim 6, wherein the first set of electrodes and the second set of electrodes comprise a plurality of inter-digitated members.

8. The capacitance sensing device ofclaim 7, wherein the members of each of the first set of electrodes is inter-digitated with the members from more than one row of the second set of electrodes.

9. The capacitance sensing device ofclaim 6, wherein the first set of electrodes and the second set of electrodes comprise a plurality of intertwined spiral formations.

10. The capacitance sensing device ofclaim 8, wherein the plurality of electrodes and the first plurality of conductors are substantially transparent.

11. A capacitance sensing device comprising:

a substrate having a central portion and an outer portion;

a first set of electrodes formed on the central portion of the substrate;

a second set of electrodes formed on the central portion of the substrate, the second set of electrodes being arranged in a series of rows and substantially co-planar with the first set of electrodes;

a first plurality of conductors formed on the substrate, each of the first plurality of conductors having a first end portion electrically connected to one of the first set of electrodes and a second end portion on the outer portion of the substrate;

a second plurality of conductors formed on the substrate, each of the second plurality of conductors having a first end portion electrically connected to one of the second set of electrodes and a second end portion on the outer portion of the substrate;

an insulating body coupled to the second end portion of each of the first plurality of conductors and the second end portion of each of the second plurality of conductors; and

a third plurality of conductors coupled to the insulating body such that each is electrically connected to one of the second end portion of one of the first plurality of conductors and the second end portion of the second plurality of conductors associated with only one row of the second set of electrodes and is electrically insulated from the second end portion of the others of the first set of conductors and the second end portion of the second plurality of conductors associated with the other rows of the second set of electrodes.

12. The capacitance sensing device ofclaim 11, wherein the first set of electrodes and the second set of electrodes comprise a plurality of inter-digitated members.

13. The capacitance sensing device ofclaim 12, wherein the members of one of the first set of electrodes are inter-digitated with the members from more than one row of the second set of electrodes.

14. The capacitance sensing device ofclaim 13, wherein the insulating body is formed on the outer portion of the substrate, and the third plurality of conductors are formed on the insulating body.

15. The capacitance sensing device ofclaim 14, wherein the insulating body and the third plurality of conductors are not formed over the central portion of the substrate.

16. A capacitance sensing device comprising:

a substrate having a central portion and an outer portion;

a first set of electrodes formed on the central portion substrate;

a second set of electrodes formed on the central portion of the substrate, the second set of electrodes being arranged in a series of rows and substantially co-planar with the first set of electrodes;

a first plurality of conductors on the substrate, each of the first plurality of conductors having a first end portion electrically connected to one electrode of the first set of electrodes or the second set of electrodes and a second end portion on the outer portion of the substrate; and

a second plurality of conductors coupled to the substrate, each of the second plurality of conductors being electrically connected to at least one of the first plurality of conductors at a node that is external to the central portion of the substrate such that each of the second plurality of conductors is electrically connected to one electrode of the first set of electrodes or a plurality of electrodes in one of the rows of the second set of electrodes.

17. The capacitance sensing device ofclaim 16, wherein the second plurality of conductors does not extend over the central portion of the substrate.

18. The capacitance sensing device ofclaim 17, further comprising an insulating material coupled to the second end portions of the first plurality of conductors and the second plurality of conductors, the insulating material electrically insulating each of the second plurality of conductors from the others of the first plurality of conductors.

19. The capacitance sensing device ofclaim 18, wherein the insulating material does not extend over the central portion of the substrate.

20. The capacitance sensing device ofclaim 16, wherein the first set of electrodes, the second set of electrodes, and the first plurality of conductors comprise indium tin oxide.

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