US20120252169A1 - Redistributed chip packaging with thermal contact to device backside - Google Patents

Abstract

An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Description

BACKGROUND
• 1. Field
• This disclosure relates generally to integrated circuits and, more specifically, integrated circuit packaging.
• 2. Related Art
• Two primary considerations in the field of integrated circuit packaging are packaging density and heat dissipation. Generally, it is desirable to use packaging technology that increases density, improves heat dissipation, or both. In conventional wirebond modules that employ one or more high density interconnect (HDI) layers, thermal dissipation is limited by the HDI layers. Redistributed Chip Packaging (RCP) offers improved density by eliminating the need for conventional wirebonds, but uses a “die down” configuration in which thermal energy dissipates through the topside of the die via a metal interconnect that overlies the die. See, e.g., U.S. Pat. No. 6,838,776 B2, to Leal et al. forCircuit Device with At Least Partial Packaging and Method for Forming, issued Jan. 4, 2005. Even when a heat spreader is used in conjunction with RCP, the interconnect layers present a heat dissipation bottleneck. The heat dissipation issues referred to are especially problematic for devices that generate substantial thermal energy including, for example, power amplifier devices.
BRIEF DESCRIPTION OF THE DRAWINGS
• The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
• FIG. 1 is a partial cross section of a plurality of devices overlying a carrier frame;
• FIG. 2 is a subsequent view in which the devices have been thinned;
• FIG. 3 is a subsequent view, showing only one of the devices, in which a heat spreader has been attached to the device backside;
• FIG. 4 is a subsequent view in which a thermal slab is attached overlying the device backside;
• FIG. 5 is a subsequent view in which an encapsulant is formed;
• FIG. 6 is a subsequent view in which the encapsulant is planarized to the slab;
• FIG. 7 is a subsequent view in which the assembly is flipped and vias are formed in the encapsulant;
• FIG. 8 is a subsequent view in which the carrier plate is removed;
• FIG. 9 is a subsequent view in which interconnect layers are formed overlying the device;
• FIG. 10 is a subsequent view in which the assembly is attached overlying a board and external devices are attached overlying the interconnect layers;
• FIG. 11 is an embodiment alternative to the embodiment shown inFIG. 10 in which a thicker device, without a thermal slab, is used in lieu of the device and slab shown inFIG. 10;
• FIG. 12 is an embodiment alternative to the embodiment shown inFIG. 10 in which a device is used with a thicker thermal slab; and
• FIG. 13 depicts an embodiment in which a shielding layer of interconnect is formed overlying the assembly.
DETAILED DESCRIPTION
• In one aspect, a disclosed integrated circuit assembly includes a printed circuit board (PCB), a panel overlying the PCB, and one or more interconnect layers overlying the panel. The panel includes a power amplifier or other device at least partially surrounded by an encapsulant. The device may include a gallium arsenide substrate, a silicon carbide on silicon substrate, or another suitable semiconductor substrate. The device is oriented within the encapsulant with the device's active surface coplanar with an upper surface of the panel. A backside of the device is in thermal contact and may be in electrical contact with either the circuit board or a thermal slab. In the case of the thermal slab, the slab has an upper surface in thermal contact with the device backside and a lower surface in thermal contact with the PCB. The interconnect layers include an insulating film, interconnect metallization overlying the insulating film, and electrically conductive contacts formed in and extending through the insulating film.
• Some embodiments of the assembly include a set of panel vias formed in the panel encapsulant. The panel vias are electrically and thermally conductive metal vias that extend through the panel between the interconnect layers and the circuit board. The panel vias enable the elimination of wirebonds so that, in some embodiments, the panel does not include any wirebonds. In these embodiments, electrical connections between the device active surface and the circuit board traverse the panel vias and the interconnect metallization. External devices, packages, and/or modules may be attached to a bond pad overlying the topmost interconnect layer. The thermal contacts to the PCB may include thermal contacts to land grid array (LGA) pads of the PCB.
• In another aspect, an integrated circuit assembly method includes forming a panel by mold injecting or otherwise forming an encapsulant at least partially surrounding a power amplifier or other integrated circuit device. An upper surface of the panel is substantially planer and includes an upper surface of the encapsulant substantially coplanar with an active surface of the device. A panel lower surface of the panel encapsulant is substantially coplanar with either a backside of the device or a lower surface of a thermally conductive slab.
• A set of panel vias may be formed in the panel encapsulant. The thermal vias are electrically and thermally conductive contacts or conduits extending between an upper surface of the panel to a lower surface of the panel. At least one interconnect layer is formed overlying the panel. The interconnect layer includes an insulating film, contacts formed in the insulating film, and an interconnect metallization overlying the insulating film.
• Prior to forming the panel, a portion of the device substrate may be grinded, polished, or otherwise removed to thin the device. Prior to forming the encapsulant, a thermal slab may be attached in thermal contact with the backside of the device with a lower surface of the panel substantially coplanar with a lower surface of the thermal slab. Prior to forming the encapsulant, the active surface of the device may be affixed to a carrier plate with an adhesive layer. The carrier plate and adhesive layer are then removed sometime after forming the encapsulant. The panel may be attached overlying a PCB where the panel lower surface is in close proximity to the PCB and the panel upper surface is distal from the PCB. Attaching the panel to the PCB may include attaching portions of the panel to land grid array (LGA) pads of the PCB. One or more external device may also be attached overlying an uppermost of the interconnect layers. A shielding metallization layer may be formed overlying an uppermost interconnect layer.
• In still another aspect, a disclosed integrated circuit assembly includes a panel and an interconnect layer. The panel includes a power amplifier or other device at least partially surrounded by an encapsulant. The panel upper surface is substantially planar and includes an upper surface of the encapsulant and an active surface of the device. The interconnect layer overlies the upper surface of the panel and includes including an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially planar and includes a lower surface of the encapsulant and one of either the device backside or a lower surface of a thermally and electrically conductive slab. In the case of the slab, an upper surface of the slab is in thermal contact with the backside of the device. The assembly may further include a set of panel vias. The panel vias comprise thermal and electrical conduits extending through the panel and suitable for make electrical connection between the interconnect layer and a pad or other bonding structure of an underlying PCB.
• The disclosed embodiments of the integrated circuit assembly offer improved thermal and electrical paths to ground that result in lower junction temperatures compared to conventional wirebond modules or prior RCP solutions. Thermal modeling shows that junctions temperatures for a typical power amplifier device exceed 150 C with conventional RCP assembly. By improving thermal dissipation, the disclosed assemblies will enable power amplifiers and other high power devices to take advantage of the integration and cost benefits of RCP technology.
• Turning now to the drawings,FIG. 1 is a cross sectional view of asemiconductor device102 at a selected stage in one embodiment of an assembly process. As depicted inFIG. 1, three units ofintegrated circuits102 are shown. Each unit ofsemiconductor device102 includes anactive surface104, also referred to herein asactive side104, and a back surface orbackside106.Active surface104 represents, as its name suggests the surface that is proximal to the transistors and other devices withinsemiconductor device102. Theactive surface104 as shown inFIG. 1 includes one ormore contact pads108 that provide externally accessible connections to selected nodes of the circuitry (not depicted) withinsemiconductor device102. Contactpads108 are electrically conductive elements that may include tin, tin lead, gold, sliver, aluminum, any combination thereof, or any other suitable conductive material.
• As shown inFIG. 1, a group ofintegrated circuits102 overlie acarrier plate120. While some of the stages shown in the drawings illustrate a group ofintegrated circuits102, other stages illustrate asingle semiconductor device102 for the sake of clarity and simplicity. Processing represented by the illustrated stages may, in some cases, be performed at a wafer level, a “panel level” with multiple individual integrated circuits being attached to a carrier plate such ascarrier plate120 or a lead frame, while still other stages may be performed at a die level, on individualintegrated circuits102.
• As shown inFIG. 1,semiconductor device102 is oriented with respect tocarrier plate120 whereinactive surface104 ofsemiconductor device102 is proximal tocarrier player120 andbackside106 is distal fromcarrier plate102. Anadhesive layer110 is shown positioned betweenactive surface104 ofsemiconductor device102 andcarrier plate120.Adhesive layer110 has an adhesive on both of its major surfaces, analogous to double-side tape, to maintainintegrated circuits102 overlyingcarrier plate120.
• Referring toFIG. 2, an optional device thinning operation has been performed to reduce the thickness ofsemiconductor device102 and one or more throughvias107 have been formed as well. As shown inFIG. 2, the displacement betweenbackside106 ofsemiconductor device102 andactive layer104 is less than it was as shown inFIG. 1. Thinning ofsemiconductor device102 may be achieved with conventional grinding, polishing, and/or etching techniques well known in the field of semiconductor processing. In some embodiments,semiconductor device102 as shown inFIG. 1 may have a thickness of approximately 0.50 mm whilesemiconductor device102, after the thinning operation as shown inFIG. 2, may have a thickness in the range of approximately 0.05 to 0.20 mm. Throughvias107, as their name suggests, extend through the wafer substrate and enable an electrical connection to be made to an element such as a circuit board, external device, or the like that is in proximity.
• Referring toFIG. 3, athermal paste130 is depictedoverlying backside106 ofsemiconductor device102. In some embodiments,thermal paste130 is a thermally and electrically conductive compound that improves heat dissipation fromsemiconductor device102 by filling air gaps that would otherwise exist betweensemiconductor device102 and a subsequently attached heat dissipation piece. In some embodiments,thermal paste130 is epoxy based. In other embodiments, ceramic, or metal based thermal pastes may be used.
• Referring toFIG. 4, an optionalthermal slab140 is shown positioned overlyingsemiconductor device102 andthermal paste130.Thermal slab140 facilitates heat dissipation from the backside ofsemiconductor device102. In some embodiments,thermal slab140 is a substantially homogenous and uniform block of a thermally and electrically conductive material such as copper, aluminum, or the like. In other embodiments,thermal slab140 may be a leadframe based heat spreader.
• The thickness and material ofthermal slab140 is an implementation detail. In some embodiments, the thickness ofthermal slab140 is designed in conjunction with the thickness ofsemiconductor device102 to produce a desired overall thickness. For example, in some embodiments the combined thickness ofsemiconductor device102 andthermal slab140 is approximately 0.200 mm, which might include asemiconductor device102 with an approximately thickness of 0.075 mm and a thermal slab with a thickness of approximately 0.125 mm. In another 0.200 mm embodiment,thermal slab140 is eliminated andsemiconductor device102 has a thickness of approximately 0.150 to 0.200 mm. In still other embodiments, the combined thickness ofsemiconductor device102 andthermal slab140 is approximately 0.500 mm. An implementation of this embodiment may employ an integrated circuit thickness of approximately 0.075 mm and a thermal slab thickness of approximately 0.425 mm. Other embodiments may employ thinner or thicker integrated circuits and/or thermal slabs.
• Referring toFIG. 5, anencapsulant150 is formed to encapsulatesemiconductor device102 andthermal slab140. In some embodiments,encapsulant150 is a electrically non-conductive material that can be molded including, as examples, thermoset mold compounds or filled thermoplastic resins. In other embodiments,encapsulant150 may be an electrically conductive material that can be molded, e.g., a thermoset epoxy or thermoplastic with a metallic filler. In some embodiments, the formation ofencapsulant150 includes an injection molding process in which a cast or set (not depicted) is positioned overlying the assembly and the encapsulant material is injected into the cast. The encapsulant is then cured with heat and the cast is removed.
• Referring toFIG. 6, a planarizing process has been performed to make anupper surface152 ofencapsulant150 substantially co-planar with anupper surface142 ofthermal slab140. As depicted inFIG. 5,encapsulant150 as formed is thicker than the combined thickness ofsemiconductor device102 andthermal slab140. The planarizing process ofFIG. 6 removes portions ofencapsulant150 aboveupper surface142 ofthermal slab140. In different embodiments, the planarizing process may include known polishing, etchback, and/or grinding techniques. The combination of theencapsulant150 and the elements surrounded by it includingsemiconductor device102 and, in some embodiments,thermal slab140, are collectively referred to herein aspanel165.
• Referring toFIG. 7, panel vias160 have been formed inencapsulant150 ofpanel165. In some embodiments, panel vias160 facilitate thermal control ofsemiconductor device102 by providing additional heat dissipation paths while simultaneously providing electrical connections between interconnect layers above and below the assembly. The formation of panel vias160 includes a via opening processing and a via fill process. The via opening process may include a laser drilling process and/or a photo/etch process to produce vias that extend entirely or substantially entirely throughencapsulant150. The vias are then filled with thermally and electrically conductive material such as copper, aluminum, alloys thereof, and the like. The filling of panel vias160 with the electrically conductive material may include one or more conventional physical and/or chemical vapor deposition steps.
• Referring toFIG. 8,carrier plate120 and adhesive130 are removed from thepanel165, which includessemiconductor device102,thermal slab140, andencapsulant150. As seen inFIG. 8, the orientation ofslab165 is rotated180 degrees from the orientation shown inFIG. 7 so thatsemiconductor device102 as shown inFIG. 8 overliesthermal slab140. The orientation shown inFIG. 8 reflects embodiments in whichpanel165 is affixed to an underlying board, e.g., a printed circuit board, withthermal slab140 in contact with or in close proximity to the circuit board. In embodiments that do not include a thermal slab, thebackside106 ofsemiconductor device102 will be in contact with or in close proximity to the circuit board.
• Referring toFIG. 9, one or more interconnect layers are formed overlyingupper surface167 ofpanel165. As shown inFIG. 9, for example, two interconnect layers170-1 and170-2 (generically or collectively referred to herein as interconnect layer(s)170) are shown. Eachinterconnect layer170 includes a insulatingfilm174, which may include a CVD dielectric, a spin on glass, a spin on polymer, or another suitable electrical insulator, that is bonded to or otherwise formedoverlying panel165.Contacts172 are formed in insulatingfilm174 andinterconnect metallization176 is formed overlying insulatingfilm174 using, for example, laser ablation to form contact holes and sputter deposition and conventional lithography to form the metallization.Bonding pads178 are formed overlying the top interconnect layer, which is interconnect layer170-2 as shown inFIG. 9.Bonding pads178 are preferably suitable for bonding with an external device as illustrated below. AlthoughFIG. 9 illustrates twointerconnect layers170, other embodiments may have more or fewer interconnect layers.
• Referring now toFIG. 10, optional external devices180-1 through180-3 are attached torespective bonding pads178 andpanel165 has been attached to land grid array (LGA)pads183 of a printed circuit board (PCB)185 to form anintegrated circuit assembly190. External devices180-1 through180-3 may include single-die packages, multi-chip modules, or a combination thereof. Thus, as shown inFIG. 10, integratedcircuit assembly190 includespanel165 overlyingPCB185.Panel165 as shown includessemiconductor device102 at least partially surrounded byencapsulant150.Upper surface167 ofpanel165 as shown is substantially planar and includesupper surface152 ofencapsulant150 andactive surface104 ofsemiconductor device102.Device102 is oriented as depicted inFIG. 10 with itsbackside106 underlying itsactive side104 so thatbackside106 is closer to board185 thanactive side104. As depicted inFIG. 10, integrated circuit assembly includesthermal slab140 overlying and in contact with anLGA pad183 ofboard185 andbackside106 ofsemiconductor device102 in thermal contact, viathermal paste130 withthermal slab140.
• One or more layers ofinterconnect170overlie panel165. External devices180-1 through180-3 are attached overlying a top most interconnect layer170-2. A set ofvias160 formed in theencapsulant150 ofpanel165 provide electrical and thermal conduits betweeninterconnect layers170 andboard185.
• In some embodiments,device102 is characterized as a high power device, such as a power amplifier, that generates substantial thermal energy. By providing a thermal/electrical contact between thebackside106 ofdevice102 and theboard165, integratedcircuit assembly190 as shown facilitates thermal management of high power devices using a packaging configuration that desirably eliminates wirebonds to minimize the dimensions of the assembly. In addition to orienting thehigh power device102 with itsbackside106 proximal to board185, integratedcircuit assembly190 as shown further includes athermal slab140 having anupper surface142 in thermal contact withdevice102 to facilitate the dissipation of thermal energy produced bydevice102. For purposes of this disclosure, the term thermal contact includes physical contact as well as contact through a thermal intermediary such asthermal paste130. In this embodiment, alower surface169 ofpanel165 is planar and is comprised of alower surface153 ofencapsulant150 being substantially coplanar with alower surface143 ofthermal slab140.
• In addition, integratedcircuit assembly190 as shown inFIG. 10 further facilitates thermal management with the set ofthermal vias160 formed inencapsulant150 ofpanel165 and forming electrical and thermal conduits between the overlying interconnect layers170 and theunderlying PCB185.
• FIG. 11 andFIG. 12 show alternative implementations ofintegrated circuit assembly190. In the embodiment ofFIG. 11, integratedcircuit assembly190 employs athicker die102 and eliminatesthermal slab140 so thatbackside106 ofsemiconductor device102 is in thermal contact withLGA pads183 ofPCB185. In this embodiment, the panel lower surface includes the encapsulantlower surface153 anddevice backside106 and/orthermal paste130. In the embodiment depicted inFIG. 12, thethinner device102 ofFIG. 10 is used in conjunction with a thickerthermal slab140 for use in athicker panel165 that may be designed to accommodate other thicker devices (not shown) inpanel165. Although three examples ofintegrated circuit assembly190 have been specifically illustrated, other embodiments may employ thicker orthinner devices102 and thicker orthinner panels165 with or withoutthermal slab140.
• Referring now toFIG. 13, an embodiment ofintegrated circuit assembly190 suitable for use with RF applications is shown. Integratedcircuit assembly190 as shown inFIG. 13 includes a shieldingmetallization layer195 that overlies the interconnect layers170.Shielding metallization layer195 is a top-most metallization layer that provides RF shielding for theunderlying device102.Shielding matellization layer195 is, in some embodiments, an uninterrupted or substantially uninterrupted sheet of interconnect metallization. As seen inFIG. 13, the shieldingmetallization layer195 may be connected toLGA pads183 ofboard185 throughthermal vias160 andinterconnect levels170. Presumably, theLGA pads183 to whichshielding metallization layer195 is connect are ground pads or other static voltage pads.
• Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, although the depicted embodiment ofboard185 usesLGA pads183, other embodiments may employ ball grid or other types of pads. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
• Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims (12)

1.-8. (canceled)

9. An integrated circuit assembly method, comprising:

forming a panel by forming an encapsulant at least partially surrounding a device, wherein an upper surface of the panel is substantially coplanar with an active surface of the device;

forming a set of panel vias in the panel, the thermal vias extending from an upper surface to a lower surface of the panel, wherein the panel vias comprise an electrically and thermally conductive material; and

forming at least one interconnect layer overlying the panel wherein the interconnect layer includes an insulating film and an interconnect metallization.

10. The method ofclaim 9, further comprising, prior to forming the panel, removing a portion of a substrate portion of the device to thin the device.

11. The method ofclaim 9, further comprising, prior to forming the encapsulant, forming a thermal slab in thermal contact with the backside of the device, wherein the thermal slab comprises at least one thermally and electrically conductive metal.

12. The method ofclaim 11, wherein a lower surface of the panel is substantially coplanar with a lower surface of the thermal slab.

13. The method ofclaim 9, further comprising:

prior to forming the encapsulant, affixing the active surface of the device to a carrier plate with an adhesive layer; and

after forming the encapsulant, removing the carrier plate and the adhesive layer.

14. The method ofclaim 9, further comprising attaching the integrated circuit assembly to a printed circuit board (PCB) wherein the integrated circuit assembly overlies the PCB with the panel lower surface proximal to the PCB and the panel upper surface distal from the PCB.

15. The method ofclaim 14, wherein the panel lower surface is substantially coplanar with either a backside of the device or a lower surface of a thermally conductive slab having an upper surface in thermal contact with the backside of the device.

16. The method ofclaim 14, wherein said attaching of the assembly to the PCB includes attaching the panel to land grid array (LGA) pads of the PCB.

17. The method ofclaim 9, further comprising attaching at least one external device overlying an uppermost interconnect layer.

18. The method ofclaim 9, further comprising forming a shielding metallization layer overlying an uppermost interconnect layer, wherein the shielding metallization layer comprises a substantially continuous plane of metallization overlying the panel.

19.-20. (canceled)

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