US20120205727A1 - Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer - Google Patents

Abstract

A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.

Description

BACKGROUND
• The present disclosure relates generally to semiconductor integrated circuits. More particularly, the present disclosure relates to scaling of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs). In order to be able to make integrated circuits, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as MOSFETs and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions of the device.
SUMMARY
• A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in a continuous encapsulating material, the present disclosure substantially eliminates shorting of the gate structure to the source and drain regions of the semiconductor device. In one embodiment, the method for forming the semiconductor device includes forming a gate structure on a semiconductor substrate. The gate structure includes a semiconductor containing gate conductor. A spacer is adjacent to sidewalls of the gate structure. A source region and a drain region, each having a surface of a first metal semiconductor alloy, are present in the semiconductor substrate on opposing sides of the gate structure. A first interlevel dielectric layer is fowled over the surface of the first metal semiconductor alloy. The first interlevel dielectric layer has an upper surface that is coplanar with the upper surface of the gate structure. The semiconductor containing gate conductor is converted to a second metal semiconductor alloy, and the first interlevel dielectric layer is removed. A continuous encapsulating layer is formed over the surface of the first metal semiconductor alloy, the spacer and the gate structure. A second interlevel dielectric layer is formed on the continuous encapsulating layer. Interconnects are formed to the surface of the first metal semiconductor alloy on the source region and the drain region.
• In another embodiment, a method of forming a semiconductor device is provided that includes forming a gate structure on a semiconductor substrate, in which a portion of the gate structure is composed of a semiconductor containing gate conductor. A source region and a drain region are present in the semiconductor substrate on opposing sides of the gate structure. A first metal semiconductor alloy is present on the surface of each of the source region and the drain region. A conformal dielectric layer is formed over the gate structure and on a surface of the first metal semiconductor alloy. A first interlevel dielectric layer is formed over the conformal dielectric layer, and is planarized to expose an upper surface of the gate structure. The remaining portions of the conformal dielectric layer and the first interlevel dielectric layer have an upper surface that is substantially coplanar with the upper surface of the gate structure. The semiconductor containing gate conductor of the gate structure is converted to a second metal semiconductor alloy, and the first interlevel dielectric layer is removed. A continuous encapsulating layer is formed in direct contact with the remaining portion of the conformal dielectric layer and over the second metal semiconductor alloy of the gate structure. A second interlevel dielectric layer is formed on the continuous encapsulating layer, and interconnects are formed through the second interlevel dielectric layer to the surface of the first metal semiconductor alloy on the source region and the drain region.
• In another aspect, a semiconductor device is provided that includes a gate structure on a channel region of a semiconductor substrate. The gate structure includes a gate dielectric on the semiconductor substrate, a metal gate conductor on the gate dielectric and a metal semiconductor alloy gate conductor on the metal gate conductor. At least one spacer is present on the sidewalls of the gate structure, and a source region and a drain region are present in contact with the semiconductor substrate on opposing sides of the channel region. Each of the source region and the drain region includes a metal semiconductor contact having a different composition than the metal semiconductor alloy gate conductor. A continuous encapsulating layer is present extending over the gate structure, the at least one spacer and the source and drain region.
DESCRIPTION OF THE DRAWINGS
• The following detailed description, given by way of example and not intended to limit the disclosure solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
• FIG. 1 is a side cross-sectional view depicting one embodiment of an initial structure of the disclosed method including a gate structure on a semiconductor substrate including a semiconductor containing gate conductor, a source region and a drain region present in the semiconductor substrate on opposing sides of the gate structure, a spacer adjacent to the gate structure, a first metal semiconductor alloy atop the source region and the drain region, and a conformal dielectric layer over the gate structure and the surface of the first metal semiconductor alloy, in accordance with the present disclosure.
• FIG. 2 is a side cross-sectional view depicting one embodiment of removing a first dielectric cap of the gate structure with an etch that is selective to the semiconductor containing gate conductor of the gate structure, in accordance with the present disclosure.
• FIG. 3 is a side cross-sectional view depositing a second metal layer on at least an exposed surface of the semiconductor containing gate conductor of the gate structure, in accordance with one embodiment of the present disclosure.
• FIG. 4 is a side cross-sectional view depicting annealing to intermix the second metal layer and the semiconductor containing gate conductor, in which the semiconductor containing gate structure is converted to a second metal semiconductor alloy, in accordance with one embodiment of the present disclosure.
• FIG. 5 is a side cross-sectional view depicting forming a second dielectric cap on the second metal conductor alloy having an upper surface that is coplanar with the upper surface of the first interlevel dielectric layer, in accordance with one embodiment of the present disclosure.
• FIG. 6 is a side cross-sectional view depicting removing the first interlevel dielectric layer, and forming a continuous encapsulating layer over the surface of the first metal semiconductor alloy, the spacer and the gate structure, in accordance with one embodiment of the present disclosure.
• FIG. 7 is a side cross-sectional view depicting forming a second interlevel dielectric atop the structure depicted inFIG. 6, and forming interconnects to the source and drain regions of the semiconductor device, in accordance with one embodiment of the present disclosure.
• FIG. 8 is a side cross-sectional view depicting a complementary metal oxide semiconductor (CMOS) device, in accordance with one embodiment of the present disclosure.
DETAILED DESCRIPTION
• Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.
• References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
• For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
• It has been determined that one consequence of scaling semiconductor devices, such as field effect transistors (FETs), is that as the distance between adjacent semiconductor devices is decreased it is becomes increasingly difficult to form interconnects to source and drain region of the semiconductor devices without shorting the gate structures. In one aspect, the present disclosure provides a process sequence for manufacturing a semiconductor device that forms a first metal semiconductor alloy on the source and drain regions of the semiconductor device, and forms a second metal semiconductor alloy in the gate structure of the semiconductor device, before the gate structure is encapsulated in an encapsulating dielectric layer. The encapsulating dielectric layer is a single material layer that can function as an etch stop during the forming of via openings to the source and drain regions. Therefore, because the encapsulating dielectric layer is present over the gate structure of the semiconductor device, and the via openings for the interconnects are formed using an etch that is selective to the encapsulating dielectric layer, the encapsulating dielectric layer allows for a self aligned contact forming process that substantially eliminates shorting to the gate structure.
• FIGS. 1-7 depict a method of forming asemiconductor device100 that utilizes a continuous encapsulatinglayer50 to electrically isolate agate structure10 including a metal semiconductor gate conductor from being shorted to theinterconnects60 to the source anddrain regions20,25 of thesemiconductor device100. The method depicted inFIGS. 1-7 is suitable for forming any semiconductor device that contains a gate structure. As used herein, “semiconductor device” refers to an intrinsic semiconductor material that has been doped, i.e., into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentrations in an extrinsic semiconductor determine the conductivity type of the semiconductor, e.g., n-type or p-type conductivity.
• In one embodiment, thesemiconductor device100 is a field effect transistor (FET). A field effect transistor (FET) is asemiconductor device100 in which output current, i.e., source-drain current, is controlled by the voltage applied to agate structure10. A field effect transistor has three terminals, i.e., agate structure10, asource region20, and adrain region25. Thegate structure10 is a structure used to control output current, i.e., flow of carriers in the channel, i.e., channel region, of a semiconducting device, such as a field effect transistor, through electrical or magnetic fields. Thechannel region4 which is located between thesource region20 and thedrain region25 of a field effect transistor (FET), becomes conductive when thesemiconductor device100 is turned on. Thesource region20, is a doped region in thesemiconductor device100, in which majority carriers are flowing into thechannel region4. Thedrain region25 is the doped region in thesemiconductor device100 that is located at the end of thechannel region4, in which carriers are flowing out of thesemiconductor device100 through thedrain region25. Although,FIGS. 1-7 of the present disclosure depict a field effect transistor (FET), any semiconductor device having a gate structure is applicable to the present disclosure.
• By “continuous encapsulating layer” it is meant that a single material layer of a single material composition is formed over the entirety of the gate structure, in which the single material layer is entirely devoid of break or void through the thickness of the single material layer. In some embodiments, thecontinuous encapsulating layer50 is composed of a dielectric material that electrically isolates thegate structure10 from theinterconnects60. A dielectric material is a material having a room temperature conductivity of less than 10⁻¹⁰(Ω-m)⁻¹.
• FIG. 1 illustrates the results of the initial processing steps that produce agate structure10 on asemiconductor substrate5 including a semiconductor containinggate conductor8, asource region20 and adrain region25 present in thesemiconductor substrate5 on opposing sides of thegate structure10, at least onespacer15 adjacent to thegate structure10, a firstmetal semiconductor alloy30,35 atop thesource region20 and thedrain region25, and aconformal dielectric layer40 over thegate structure10 and the surface of the firstmetal semiconductor alloy30,35.
• Thesemiconductor substrate5 may be composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof. Thesemiconductor substrate5 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although thesemiconductor substrate5 is depicted as a bulk semiconductor substrate, semiconductor on insulator (SOI) substrate arrangements, such as silicon on insulator substrates, are also suitable for thesemiconductor substrate5.
• Still referring toFIG. 1, agate structure10 is formed atop thesemiconductor substrate5. In one embodiment, thegate structure10 includes agate dielectric6 present on thesemiconductor substrate5, ametal gate conductor7 on thegate dielectric6, a semiconductor containinggate conductor8 present on themetal gate conductor7, and a firstdielectric cap9 present on the semiconductor containinggate conductor8.
• In one embodiment, thegate structure10 is formed on thechannel region4 of thesemiconductor substrate5. In one embodiment, agate dielectric6 is formed in direct contact with thechannel region4 of thesemiconductor substrate5. Thegate dielectric6 may be composed of any dielectric material. For example, thegate dielectric6 may be composed of an oxide, nitride or oxynitride material. Thegate dielectric6 may be composed of a high-k dielectric material. The term “high-k” denotes a material having a dielectric constant that is greater than the dielectric constant of silicon oxide (SiO₂) at room temperature, i.e., 20° C. to 25° C. In one embodiment, the high-k dielectric that provides thegate dielectric6 is comprised of a material having a dielectric constant that is greater than 4.0, e.g., 4.1. In another embodiment, the high-k gate dielectric that provides thegate dielectric6 is comprised of a material having a dielectric constant greater than 7.0. In yet another embodiment, the high-k gate dielectric that provides thegate dielectric6 is comprised of a material having a dielectric constant ranging from greater than 4.0 to 30. The dielectric constants mentioned herein are relative to a vacuum at room temperature, i.e., 20° C. to 25° C.
• In one example, a high-k gate dielectric6 is provided by hafnium oxide (HfO₂). Other examples of suitable high-k dielectric materials for thegate dielectric6 include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof
• In one embodiment, thegate dielectric6 is formed using a deposition process, such as chemical vapor deposition (CVD). In another embodiment, thegate dielectric6 may be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. Thegate dielectric6 may have a thickness ranging from 1 nm to 5 nm. In another embodiment, thegate dielectric6 has a thickness ranging from 1 nm to 2.5 nm. In yet another example, thegate dielectric6 has a thickness that ranges from 15 Å to 20 Å.
• In one embodiment, themetal gate conductor7 is formed in direct contact with thegate dielectric6. By “metal gate conductor” it is meant that the conductive structure is composed of metal elements, and that the metal gate conductor is not composed of a semiconductor element.
• Themetal gate conductor7 may be composed of a work function metal layer. In one embodiment, in which the semiconductor device is an n-type semiconductor device, such as an nFET, the work function metal layer that provides themetal gate conductor7 is an n-type work function metal layer. As used herein, an “n-type work function metal layer” is a metal layer that effectuates an n-type threshold voltage shift. As used herein, “threshold voltage” is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. “N-type threshold voltage shift” as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device. The “conduction band” is the lowest lying electron energy band of the doped material that is not completely filled with electrons. In one embodiment, the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV. In one embodiment, the n-type work function metal layer is composed of at least one of TiAl, TaN, TiN, HfN, or combinations thereof. The n-type work function metal layer can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering or plating. In one embodiment, the n-type work function metal layer is composed of titanium aluminum (TiAl) and is deposited using sputtering. Examples of sputtering apparatus that may be suitable for depositing the n-type work function metal layer include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering.
• In another embodiment, in which the semiconductor device is a pFET, themetal gate conductor7 may be a p-type work function metal layer. As used herein, a “p-type work function metal layer” is a metal layer that effectuates a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal layer ranges from 4.9 eV to 5.2 eV. The term “p-type threshold voltage shift” as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device. A “valence band” is the highest range of electron energies where electrons are normally present at absolute zero.
• In one embodiment, the p-type work function metal layer may be composed of titanium and their nitrided/carbide. In one embodiment, the p-type work function metal layer is composed of titanium nitride (TiN). The p-type work function metal layer may also be composed of TiAlN, Ru, Pt, Mo, Co and alloys and combinations thereof. In one embodiment, the p-type work function metal layer comprising titanium nitride (TiN) may be deposited by a physical vapor deposition (PVD) method, such as sputtering. Examples of sputtering apparatus that may be suitable for depositing the p-type work function metal layer include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In addition to physical vapor deposition (PVD) techniques, the p-type work function metal layer may also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).
• In one embodiment, a semiconductor containinggate conductor8 is formed in direct contact with themetal gate conductor7. By “semiconductor containing gate conductor” it is meant that the gate conductor is composed of semiconductor element that is free of metal elements. The semiconductor containinggate conductor8 may be composed of a silicon containing material. Examples of silicon containing materials include, but are not limited to, silicon, single crystal silicon, polycrystalline silicon, silicon germanium, and amorphous silicon. In one embodiment, the semiconductor containinggate conductor8 is provided by a doped semiconductor, such as n-type doped polysilicon.
• In one embodiment, the semiconductor containinggate conductor8 is deposited and then doped by ion implantation. The material for the semiconductor containinggate conductor8 may be deposited using chemical vapor deposition (CVD). Chemical vapor deposition (CVD) is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at room temperature or greater, wherein the solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes suitable for depositing the material that provides the semiconductor containinggate conductor8 include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and others. The semiconductor containinggate conductor8 may be doped using ion implantation following the deposition of the material for the semiconductor containinggate conductor8. In another embodiment, the semiconductor containinggate conductor8 may be in-situ doped as the material layer for the semiconductor containinggate conductor8 is formed.
• The firstdielectric cap9 may present in direct contact with the semiconductor containinggate conductor8. The firstdielectric cap9 may be composed of a dielectric material that can be etched selectively to the semiconductor containinggate conductor8, and etched selectively to a subsequently formed first interlevel dielectric layer. In one embodiment, the firstdielectric cap9 may be composed of amorphous carbon (α:C). Amorphous carbon is an allotrope of carbon with substantially no crystalline structure. Hydrogenated amorphous carbon (α:C:H) and/or tetrahedral amorphous carbon (ta-C) (also called diamond-like carbon) may also be employed for the firstdielectric cap9. It is noted that the above materials for the firstdielectric cap9 are provided for illustrative purposes only, and are not intended to limit the present disclosure, as any dielectric material may be utilized for the firstdielectric cap9. For example, the firstdielectric cap9 may be composed of an oxide, nitride or oxynitride material.
• In one embodiment, thegate structure10 is formed by depositing blanket layers for each of thegate dielectric6, themetal gate conductor7, the semiconductor containinggate conductor8 and the firstdielectric cap9 to form a gate stack, and then patterning and etching the gate stack to form thegate structure10. More specifically, a pattern is produced on the gate stack by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example, a first material may be removed with a selectivity of greater than 100:1 to a second material. The remaining portion of the gate stack is positioned on at least achannel region4 of thesemiconductor substrate5, and provides thegate structure10.
• FIG. 1 also depicts one embodiment of forming at least onespacer15 on the sidewall of thegate structure10, andfowling source regions20 anddrain regions25 in thesemiconductor substrate5. The material of the at least onespacer15 is typically a dielectric material. For example, the at least onespacer15 may be an oxide, nitride or oxynitride material. In one example, the at least onespacer15 is composed of silicon oxide. In another example, the at least onespacer15 is composed of silicon nitride.
• The at least onespacer15 may be formed using deposition, photolithography and etch processes. In one embodiment, the material for the at least onespacer15 is first blanket deposited over thegate structure10 and the exposed portions of thesemiconductor substrate5. The material for the at least onespacer15 may be deposited as a conformal layer. As used herein, “a conformal layer”, such as a conformal dielectric layer, is a deposited material having a thickness that remains substantially the same regardless of the geometry of underlying features on which the layer is deposited. In one example, the thickness of the conformal layer that is deposited for thefirst spacer15 varies by no greater than 20% of the average thickness for the layer.
• In one embodiment, the material layer for the at least onespacer15 may be formed using thermal growth or deposition. In one example, the material layer for the at least onespacer15 is deposited using thermal oxidation and is composed of silicon oxide. In another example, the material layer for the at least onespacer15 is formed by a deposition process, such as chemical vapor deposition (CVD). Variations of CVD processes suitable for the material layer for the at least onespacer15 include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and others. Following deposition, the material layer for the at least onespacer15 is etched to remove the portions of the material layer from the upper surfaces of thesemiconductor substrate5 that are not adjacent to thegate structure10, and from the upper surface of thegate structure10. The etch process for forming the at least onespacer15 may be a spacer etch back process. In one example, the etch process for forming the at least onespacer15 is an anisotropic etch. As used herein, an “anisotropic etch process” denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is higher than in the direction parallel to the surface to be etched. Examples of anisotropic etch process suitable for forming the at least onespacer15 include, but are not limited to, reactive-ion etching (RIE), ion beam etching, plasma etching and/or laser ablation. Reactive ion etch (RIE) is a form of plasma etching, in which the surface to be etched may be placed on an RF powered electrode and takes on a potential that accelerates an etching species, which is extracted from a plasma, towards the surface to be etched, wherein a chemical etching reaction takes place in the direction normal to the surface being etched. Following etching, the remaining portion of the material layer for the at least onespacer15 is in direct contact with the sidewall of thegate structure10. In one embodiment, the at least onespacer15 was a width that ranges from 1.0 nm to 10.0 nm. In another embodiment, the at least onespacer15 has a width that ranges from 2.0 nm to 5.0
• Referring toFIG. 1, asource region20 and adrain region25 may be on opposing sides of thechannel region4. The conductivity-type of thesource region20 and thedrain region25 determines the conductivity of the semiconductor device. The source and drainregions20,25 may each include a source and drain extension region, a deep source and drain region (not shown), and optionally a raised source and drain region (not shown). Conductivity-type denotes whether thesource region20 and thedrain regions25 of the semiconductor device have been doped with a p-type or n-type dopant. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of p-type dopants, i.e., impurities, include but are not limited to boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to, antimony, arsenic and phosphorous.
• In one embodiment, the extension portion of thesource region20 and thedrain region25 is formed using an ion implantation process. In one embodiment, the dopant species for the extension portion of thesource region20 is boron (B) or BF₂. Boron may be implanted utilizing implant energies ranging from 0.2 keV to 3.0 keV with an implant dose ranging from 5×10¹⁴atoms/cm²to 5×10¹⁵atoms/cm². BF₂may be implanted utilizing implant energies ranging from 1.0 keV to 15.0 keV and a dose ranging from 5×10¹⁴atoms/cm²to 5×10¹⁵atoms/cm². In one embodiment, a typical implant for the extension portion of the n-type drain region25 is arsenic. The n-type extension portion of thedrain region25 can be implanted with arsenic using implant energies ranging from 1.0 keV to 10.0 keV with a dose ranging from 5×10¹⁴atoms/cm²to 5×10¹⁵atoms/cm². Typically, the dopant concentration of the extension portion of thesource region20 and thedrain region25 having a p-type dopant ranges from 5×10¹⁹atoms/cm³to 5×10²⁰atoms/cm³. In another embodiment, the dopant concentration of the extension portion of thesource region20 and thedrain region25 having p-type dopant ranges from 7×10¹⁹atoms/cm³to 2×10²⁰atoms/cm³.
• The deep dopant regions (not shown) typically have the same conductivity dopant as the extension portion of thesource region20 and thedrain region25. The dopant for the deep source region and the deep drain region is present in greater concentration and at greater depths into thesemiconductor substrate5 than the dopant for the extension portion of thesource region20 and thedrain region25. In some embodiments, a halo implant (not shown) may also be formed at the corner of the junction opposite the upper surface of thechannel region4. The halo implant region is typically of an opposite conductivity, as the extension portion of the source and drainregions20,25, and the deep source and drain regions.
• In one embodiment, a raised source region and a raised drain region (not shown) is formed on the portion of thesemiconductor substrate5 including at least the source extension region and the drain extension region. The raised source region and the raised drain region may have the same conductivity as the source extension region and the drain extension region. The raised source region and the raised drain region may be deposited using an epitaxial growth process. “Epitaxial growth and/or deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. The raised source region and the raised drain region may be doped using ion implantation after epitaxial growth, or the raised source region and raised drain region may be doped in-situ during the epitaxial growth process.
• The source and drainregions20,25 are activated by activation annealing using an annealing processes such as, but not limited to, rapid thermal annealing, furnace annealing, flash lamp annealing or laser annealing. In one embodiment, activation anneal is conducted at a temperature ranging from 850° C. to 1350° C.
• At least a portion of thesemiconductor substrate5 that contains the source and drainregions20,25 is converted into a firstmetal semiconductor alloy30,35. In one embodiment, the firstmetal semiconductor alloy30,35 is present at the upper surface of thesemiconductor substrate5, and is adjacent to the at least onespacer15. In one embodiment, the firstmetal semiconductor alloy30,35 is composed of silicon and an elemental metal, which is hereafter referred to as a silicide. Silicide formation typically includes depositing a refractory metal such as Ni, Co, Pd, Pt, Rh, Ir, Zr, Cr, Hr, Er, Mo or Ti, onto the surface of a Si-containing material. The refractory metal may be deposited on thesemiconductor substrate5 using a deposition process, such as physical vapor deposition (PVD). Examples of physical vapor deposition (PVD) that are suitable for forming the firstmetal semiconductor alloy30,35 include sputtering and plating. Examples of sputtering apparatuses suitable for forming the firstmetal semiconductor alloy30,35 include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. Following deposition, the structure is then subjected to an annealing step using conventional processes such as, but not limited to, rapid thermal annealing. During thermal annealing, the deposited metal reacts with Si forming a metal silicide. The remaining unreacted metal is removed by an etch process that is selective to the silicide. In addition to silicide, other metal semiconductor alloys can be formed utilizing similar processes as described above.
• In one example, the firstmetal semiconductor alloy30,35 is composed of nickel (Ni), platinum (Pt) and silicon (Si), which in some instances can be referred to as nickel platinum silicide. In another example, the firstmetal semiconductor alloy30,35 is composed of nickel silicide (NiSi, NiSi₂).
• FIG. 1 further depicts one embodiment of forming aconformal dielectric layer40 over at least thegate structure10, the at least onespacer15, the firstmetal semiconductor alloy30 that is present on thesource region20, and the firstmetal semiconductor alloy35 that is present on thedrain region25. Theconformal dielectric layer40 may be formed using thermal growth or deposition. In one example, theconformal dielectric layer40 is formed using thermal oxidation and is composed of silicon oxide. In another example, theconformal dielectric layer40 is formed by a deposition process, such as chemical vapor deposition (CVD). Variations of CVD processes suitable for depositing theconformal dielectric layer40 include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and others. The thickness of the material layer for theconformal dielectric layer40 typically ranges from 1.0 nm to 10.0 nm. In another embodiment, the material layer for theconformal dielectric layer40 has a thickness that ranges from 2.0 nm to 5.0 nm.
• The material of theconformal dielectric layer40 is typically a dielectric material. For example, the material of theconformal dielectric layer40 may be an oxide, nitride or oxynitride material. In one embodiment, theconformal dielectric layer40 is composed of silicon nitride. The material for theconformal dielectric layer40 is selected so that it may be etched selectively to the at least onespacer15, thegate structure10 and thesemiconductor substrate5. In one example, when the at least onespacer15 is composed of silicon oxide (SiO₂), theconformal dielectric layer40 may be composed of silicon nitride (Si₃N₄). In another example, when the at least onespacer15 is composed of silicon nitride (Si₃N₄), theconformal dielectric layer40 may be composed of silicon oxide (SiO₂). It is noted that these materials are provided for illustrative examples only, and is not intended to limit the disclosure.
• In one embodiment, a firstinterlevel dielectric layer45 is deposited atop theconformal dielectric layer40. The composition of the firstinterlevel dielectric layer45 may be selected from the group consisting of silicon-containing materials such as SiO₂, Si₃N₄, SiO_xN_y, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the firstinterlevel dielectric layer45 include, any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.
• In one embodiment, in which theconformal dielectric layer40 is composed of amorphous carbon, the firstinterlevel dielectric layer45 may be composed of silicon oxide. The firstinterlevel dielectric layer45 may be deposited using chemical vapor deposition (CVD). In addition to chemical vapor deposition (CVD), the firstinterlevel dielectric layer45 may also be formed using spinning from solution, spraying from solution, and evaporation.
• Following deposition, the firstinterlevel dielectric layer45 is planarized until the upper surface of thegate structure10 is exposed. In one embodiment, the planarization is continued until the firstinterlevel dielectric layer45 and theconformal dielectric layer40 is removed from over thegate structure10 to expose the upper surface of the firstdielectric cap9. “Planarization” is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface. In one embodiment, the planarization process includes chemical mechanical polishing (CMP) or grinding. Chemical mechanical planarization (CMP) is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface.
• FIG. 2 depicts removing the firstdielectric cap9 of thegate structure10 with an etch that is selective to the semiconductor containinggate conductor8 of thegate structure10. The etch may be an isotropic etch or an anisotropic etch. The anisotropic etch may include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used at this point of the present disclosure includes ion beam etching, plasma etching or laser ablation. In comparison to anisotropic etching, isotropic etching is non-directional. One example of an isotropic etch is a wet chemical etch.
• FIG. 3 depicts depositing asecond metal layer11 on at least an exposed surface of the semiconductor containinggate conductor8 of thegate structure10. In one embodiment, thesecond metal layer11 is blanket deposited atop the structure depicted inFIG. 2, in which thesecond metal layer11 is also formed on the upper surface of the firstinterlevel dielectric layer45. Thesecond metal layer11 may be formed using a deposition process, such as physical vapor deposition (PVD). Examples of physical vapor deposition (PVD) that are suitable for forming thesecond metal layer11 include sputtering and plating. Examples of sputtering apparatuses suitable for forming thesecond metal layer11 include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. Thesecond metal layer11 may be composed of at least one metal selected from the group including W, Sc, Y, Ho, Gd, Lu, Dy, Tb, Er, Yb, Hf, Ir, Pt, Os or combinations thereof. The thickness of thesecond metal layer11 may range from 1.0 nm to 10.0 nm. In another embodiment, thesecond metal layer11 has a thickness that ranges from 2.0 nm to 5.0 nm.
• FIG. 4 depicts annealing to intermix thesecond metal layer11 and the semiconductor containinggate conductor8, in which the semiconductor containinggate structure8 is converted to a secondmetal semiconductor alloy12. In one embodiment, the annealing may be provided by thermal anneal, rapid thermal anneal, laser anneal or combinations thereof. In one embodiment, the annealing is at a temperature ranging from about 20° C. to about 1000° C. In another embodiment, the annealing is at a temperature ranging from about 200° C. to about 1000° C. In one embodiment, the annealing is conducted until the entire semiconductor containing gate conductor is fully silicided. By “fully silicided” it is meant that the entire thickness of the semiconductor containing gate conductor is intermixed with a metal to form the secondmetal semiconductor alloy12. The fully silicided semiconductor containing gate conductor typically includes metal elements intermixed with the semiconductor elements extending from the upper surface of the semiconductor containing gate conductor to the base surface of the semiconductor containing gate conductor. In one embodiment, the secondmetal semiconductor alloy12 that provides the fully silicided gate conductor is composed of nickel silicide, cobalt silicide (CoSi) or cobalt disilicide (CoSi₂). Examples of nickel silicides that are suitable for the secondmetal semiconductor alloy12 include Ni₃Si, Ni₃₁Si₁₂(Ni₅Si₂), Ni₂Si, Ni₃Si₂, NiSi, NiSi₂and combinations thereof. In some embodiments, the composition of the secondmetal semiconductor alloy12 is selected to limit volumetric expansion of the portion of the gate conductor that includes the secondmetal semiconductor alloy12.
• Following alloying of thesecond metal layer11 and the semiconductor containinggate structure8, the non-reacted portions of thesecond metal layer11 are removed with an etch that is selective to the secondmetal semiconductor alloy12. The etch for removing the non-reacted portions of thesecond metal layer11 may also be selective to the firstinterlevel dielectric layer45.
• FIG. 5 depicts forming asecond dielectric cap13 on the second metalconductor alloy layer12. Thesecond dielectric cap13 typically has an upper surface that is coplanar with the upper surface of the firstinterlevel dielectric45. Thesecond dielectric cap13 may be composed of any material that allows for the firstinterlevel dielectric layer45 to be removed by an etch that is selective to thesecond dielectric cap13. For example, thesecond dielectric cap13 may be composed of a nitride, oxide or oxynitride material. In some embodiments, thesecond dielectric cap13 is composed of an oxide, nitride or oxynitride material. In one embodiment, in which theconformal dielectric layer40 is composed of a nitride, such as silicon nitride, and the firstinterlevel dielectric layer45 is composed of an oxide, such as silicon oxide, thesecond dielectric cap13 may be composed of a nitride, such as silicon nitride.
• Thesecond dielectric cap13 is typically formed using a deposition method. In one example, thesecond dielectric cap13 is formed from a blanket deposited material layer. The material layer for thesecond dielectric cap13 may be deposited on the upper surface of the firstinterlevel dielectric layer45, and may be deposited to a thickness that fills the void over the secondmetal semiconductor alloy12 of thegate structure10 that is produced by removing the firstdielectric cap9. Following deposition, the material layer for thesecond dielectric cap13 is planarized until the upper surface of the remaining portion of the material for thesecond dielectric cap13 is coplanar with the upper portion of the firstinterlevel dielectric layer45. In one embodiment, the planarization process includes chemical mechanical polishing (CMP) or grinding.
• FIG. 6 depicts removing the firstinterlevel dielectric layer45. In one embodiment, the firstinterlevel dielectric layer45 is removed by an etch process that is selective to thesecond dielectric cap13 and theconformal dielectric layer40. In one example, in which the firstinterlevel dielectric45 is composed of an oxide, such as silicon oxide, and theconformal dielectric layer40 and thesecond dielectric cap13 is composed of a nitride, such as silicon nitride, the etch process for removing the firstinterlevel dielectric layer45 may be provided by a chemical oxide removal (COR) process. In one embodiment, COR process includes exposing the structure to a gaseous mixture of HF and ammonia at a pressure of 30 mTorr or below. In one embodiment, the COR process further includes a pressure between 1 mTorr and 10 mTorr, and a temperature of 25° C. or greater. The ratio of gaseous HF to gaseous ammonia may range from 1:10 to 10:1. In one example, the ratio of gaseous HF to gaseous ammonia is 2:1. In one example, a solid reaction product is formed as a result of the structure's exposure to HF and ammonia gas. The solid reaction product includes etched oxide, reactants or combinations thereof. The solid reaction product is removed in a second step which includes heating the structure to a temperature about 100° C., thus causing the reaction product to evaporate, and rinsing the structure in water.
• FIG. 6 also depicts forming acontinuous encapsulating layer50 over the surface of the firstmetal semiconductor alloy30,35, the at least onespacer15 and thegate structure10. Thecontinuous encapsulating layer50 is typically a single material layer. Thecontinuous encapsulating layer50 may be in direct contact with theconformal dielectric layer40 that is present on the upper surface of the firstmetal semiconductor alloy30,35 and the at least one spacer, and may be in direct contact with the upper surface of thesecond dielectric cap13 of thegate structure10. Thecontinuous encapsulating layer50 is typically composed of a dielectric material, such as an oxide, nitride or oxynitride. In one embodiment, thecontinuous encapsulating layer50 is composed of a high-k dielectric material. One high-k dielectric material that is suitable for thecontinuous encapsulating layer50 is hafnium oxide (HfO₂). Other examples of suitable high-k dielectric materials for thecontinuous encapsulating layer50 include hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof. In one embodiment, thecontinuous encapsulating layer50 hermetically seals thegate structure10.
• Thecontinuous encapsulating layer50 typically protects thegate structure10 of the semiconductor device from being shorted to the later formed interconnects. As the semiconductor devices are scaled to smaller and smaller dimensions, the distance separating the gate structures of adjacent semiconductor devices is reduced. As the distance between the adjacent semiconductor devices decreases, the potential for shorting of the interconnects to thegate structures10 increases. Thecontinuous encapsulating layer50 protects thegate structure10 from being shorted by providing an etch stop that is entirely continuous, in which the etch stop is entirely free of breaks. The etch process for foaming the via openings to the source and drain regions is selected to provide that the etch chemistry is selective to thecontinuous encapsulating layer50. Because the etch process that fauns the via openings for the interconnects does not etch thecontinuous encapsulating layer50, and thecontinuous encapsulating layer50 covers the entirety of thegate structure10, theentire gate structure10 is protected by thecontinuous encapsulating layer50. Therefore, theentire gate structure10 is electrically isolated from the later formed interconnects by thecontinuous encapsulating layer50.
• FIG. 7 depicts forming a second interleveldielectric layer55 over the structure depicted inFIG. 6, and forminginterconnects60 to thesource regions20 anddrain regions25 of thesemiconductor device100. Because thecontinuous encapsulating layer50 covers the entirety of thegate structure10, and the etch process for forming the via openings for theinterconnects60 is selective to thecontinuous encapsulating layer50, the present disclosure provides a self aligned contact (SAC) forming process.
• The composition of the second interleveldielectric layer55 may be selected from the group consisting of silicon-containing materials such as SiO₂, Si₃N₄, SiO_xN_y, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the second interleveldielectric layer55 include, any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.
• Via openings may be formed to expose an upper surface of the firstmetal semiconductor alloy30,35 on thesource region20 and thedrain region25. The via openings may be formed using photolithography and etch processes. For example, a photoresist etch mask can be produced by applying a photoresist layer to the upper surface of the second interleveldielectric layer55, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer. The photoresist etch mask may be positioned so that the portions of the second interleveldielectric layer55 that are not protected by the photoresist etch mask may be etched in order to provide the via openings. The exposed portion of the second interleveldielectric layer55 is then removed by a selective etch. In one embodiment, the selective etch removes the material of the second interleveldielectric layer55 selectively tocontinuous encapsulating layer50. The etch that removes the exposed portion of the second interleveldielectric layer55 may be an anisotropic etch. Examples of anisotropic etch process suitable for forming the via openings include, but are not limited to, reactive-ion etching (RIE), ion beam etching, plasma etching and/or laser ablation. Because the etch process that forms the via openings through the second interleveldielectric layer55 does not etch thecontinuous encapsulating layer50, and thecontinuous encapsulating layer50 covers the entirety of thegate structure10, theentire gate structure10 is protected by thecontinuous encapsulating layer50.
• In one embodiment, following the etching of the second interleveldielectric layer55, the exposed portion of thecontinuous encapsulating layer50 is etched selective to theconformal dielectric layer40. Thereafter, via openings are extended to the firstmetal semiconductor alloy30,35 by etching the exposed portion of theconformal dielectric layer40 selectively to the upper surface of the firstmetal semiconductor alloy30 of thesource region20, and the upper surface of the firstmetal semiconductor alloy35 of thedrain region25.
• Interconnects60 may be formed in the via openings, in which theinterconnects60 are in direct contact with the upper surface of the firstmetal semiconductor alloy30 to thesource region20, and the upper surface of the firstmetal semiconductor alloy35 to thedrain region25.Interconnects60 are formed by depositing a conductive metal into the via openings using a deposition process, such as physical vapor deposition (PVD). Examples of physical vapor deposition (PVD) that are suitable for forming theinterconnects60 include sputtering and plating. Examples of sputtering apparatuses suitable for forming theinterconnect60 include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. Theinterconnect60 may also be formed using chemical vapor deposition. Theinterconnect60 may be composed of a conductive metal, such as tungsten, copper, aluminum, silver, gold, and alloys thereof.
• In one embodiment, the above-described method provides asemiconductor device100 that includes agate structure10 on achannel region4 of asemiconductor substrate5. Thegate structure10 includes agate dielectric6 on thesemiconductor substrate5, ametal gate conductor7 on thegate dielectric6, and a gate conductor composed of a metal semiconductor alloy, e.g., secondmetal semiconductor alloy12, on themetal gate conductor7. At least onespacer15 is present on the sidewalls of thegate structure10. Asource region20 and adrain region25 are present in thesemiconductor substrate5 on opposing sides of thechannel region4.
• Each of thesource region20 and thedrain region25 include ametal semiconductor contact30,35 that may have a different composition than the metal semiconductor alloy, e.g., secondmetal semiconductor alloy12, of thegate structure10. In one embodiment, the metal semiconductor alloy, e.g., secondmetal semiconductor alloy12, of the gate conductor is composed of cobalt silicide (CoSi₂), and themetal semiconductor contact30,35 is composed of nickel silicide.
• Thesemiconductor device100 may further include acontinuous encapsulating layer50 extending over thegate structure10, the at least onespacer15, and the source and drainregion20,25. Thecontinuous encapsulating layer50 electrically isolates thegate structure10 from theinterconnects60 to the source and drainregions20,25. By “electrically isolates” it is meant that thecontinuous encapsulating layer50 obstructs electrical current from being transmitted from theinterconnects60 to thegate structure10. In one embodiment, thecontinuous encapsulating layer50 eliminates electrical shorting between theinterconnects60 and thegate structure10. In one embodiment, the continuousencapsulating dielectric layer50 is composed of a high-k dielectric. Thesemiconductor device100 may also include auniform dielectric layer40 between thecontinuous encapsulating layer50, the at least onespacer15 and the first metalsemiconductor alloy contact30,35 that is present on thesource region20 and thedrain region25. AlthoughFIGS. 1-7 depicts asingle semiconductor device100, it is noted that the present disclosure may be applicable to any number of semiconductor devices.
• For example,FIG. 8 depicts one embodiment of a complementary metal oxide semiconductor (CMOS) device on asemiconductor device5, in which the CMOS device includes acontinuous encapsulating layer50 that is present over each of thesemiconductor devices100A,100B. A CMOS device is a semiconductor device that includes at least one p-type semiconductor device and at least one n-type semiconductor device. In one embodiment, the CMOS device includes an n-typeconductivity semiconductor device100A and a p-typeconductivity semiconductor device100B on asingle semiconductor substrate5.
• The n-type semiconductor device100A includes source and drainregions20′,25′ being doped with an n-type dopant. The n-type semiconductor device100A further includes a firstmetal semiconductor alloy30′,35′ on the upper surface of the source and drainregions20′,25′. The firstmetal semiconductor alloy30′,35′ is similar to the firstmetal semiconductor alloy30,35 described above with reference toFIG. 6. Therefore, the description of the firstmetal semiconductor alloy30,35 that is described above with reference toFIG. 6 is suitable for the firstmetal semiconductor alloy30′,35′ that is depicted inFIG. 8. The n-type semiconductor device100A further includes agate structure10′. Thegate structure10′ includes agate dielectric6′, ametal gate conductor7′, a secondmetal semiconductor alloy12′ and asecond dielectric cap13′. Thegate structure10′ depicted inFIG. 8 is similar to thegate structure10 that is described above with reference toFIGS. 1-5. Therefore, the description of thegate structure10 that is described above with reference toFIGS. 1-4 is suitable for the firstmetal semiconductor alloy30′,35′ that is depicted inFIG. 8. Themetal gate conductor7′ of thegate structure10′ may be an n-type work function metal layer, as described above with reference toFIG. 1.
• The p-type semiconductor device100B includes source and drainregions20″,25″ being doped with an p-type dopant. The p-type semiconductor device100B further includes a firstmetal semiconductor alloy30″,35″ on the upper surface of the source and drainregions20″,25″. The firstmetal semiconductor alloy30″,35″ is similar to the firstmetal semiconductor alloy30,35 described above with reference toFIG. 6. Therefore, the description of the firstmetal semiconductor alloy30,35 that is described above with reference toFIG. 6 is suitable for the firstmetal semiconductor alloy30″,35″ that is depicted inFIG. 8. The p-type semiconductor device100B further includes agate structure10″. Thegate structure10″ includes agate dielectric6″, ametal gate conductor7″, a secondmetal semiconductor alloy12″ and asecond dielectric cap13″. Thegate structure10″ depicted inFIG. 8 is similar to thegate structure10 that is described above with reference toFIGS. 1-5. Therefore, the description of thegate structure10 that is described above with reference toFIGS. 1-4 is suitable for the firstmetal semiconductor alloy30″,35″ that is depicted inFIG. 8. Themetal gate conductor7″ of thegate structure10″ may be a p-type work function metal layer, as described above with reference toFIG. 1. The n-typeconductivity semiconductor device100A is separated from the p-type semiconductor device100B by anisolation region65.
• Assemiconductor devices100A,100B are scaled to provide above described pitch or lesser pitches, theinterconnects60′,60″ to the source and drainregions20′,20″,25′,25″, can short to thegate structure10′,10″ of the n-type semiconductor device100A and the p-type semiconductor device100B. To eliminate shorting to thegate structures10′,10″, a singlecontinuous encapsulating layer50′ may extend over thegate structure10′ of the n-typeconductivity semiconductor device100A, and thegate structure10″ of p-typeconductivity semiconductor device100B. The singlecontinuous encapsulating layer50′ also extends over the upper surface of theisolation region65 that separates the n-typeconductivity semiconductor device100A from the p-typeconductivity semiconductor device100B. The singlecontinuous encapsulating layer50′ is an etch stop that is entirely continuous, in which the etch stop is entirely free of breaks. Each of the n-type semiconductor device100A and the p-type semiconductor device100B may further include aconformal dielectric layer40′,40″ that is present between thecontinuous encapsulating layer50′ and thespacer15′,15″ and the firstmetal semiconductor alloy30′,35′,30″,35″. Because thecontinuous encapsulating layer50′ covers the entirety of thegate structures10′,10″ and is free of breaks to thegate structures10′,10″, and the etch process for forming the via openings for theinterconnects60′,60″ is selective to thecontinuous encapsulating layer50′, the present disclosure provides a self aligned contact (SAC) forming process that substantially eliminates shorting between theinterconnects60′,60″ and thegate structures10′,10″.
• While the claimed methods and structures has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the presently claimed methods and structures.

Claims (20)

1. A method of forming a semiconductor device comprising:

forming a gate structure on a semiconductor substrate, the gate structure including a semiconductor containing gate conductor, wherein a source region and a drain region having a surface of a first metal semiconductor alloy are present in the semiconductor substrate on opposing sides of the gate structure and a spacer is adjacent to sidewalls of the gates structure;

forming a first interlevel dielectric layer over the surface of the first metal semiconductor alloy, wherein the first interlevel dielectric layer has an upper surface that is coplanar with the upper surface of the gate structure;

converting the semiconductor containing gate conductor to a second metal semiconductor alloy;

removing the first interlevel dielectric layer;

forming a continuous encapsulating layer over the surface of the first metal semiconductor alloy, the spacer and the gate structure;

forming a second interlevel dielectric layer on the continuous encapsulating layer; and

forming interconnects to the surface of the first metal semiconductor alloy on the source region and the drain region.

2. The method ofclaim 1, wherein the forming of the interconnects comprises etching a via opening through the second interlevel dielectric layer selective to the continuous encapsulating layer, extending the via opening through the continuous encapsulating layer to an exposed portion of the first metal semiconductor alloy, and forming the interconnect in the via opening in direct contact with the exposed portion of the first metal semiconductor alloy.

3. The method ofclaim 1, wherein the forming of the gate structure on the semiconductor substrate comprises:

depositing a gate dielectric layer directly on the semiconductor substrate;

depositing a metal gate conductor layer directly on the gate conductor layer;

depositing a semiconductor containing gate conductor layer directly on the metal gate conductor layer;

depositing a capping dielectric layer directly on the semiconductor containing gate conductor layer;

forming an etch mask overlying the semiconductor containing gate conductor layer; and

etching the capping dielectric layer, the semiconductor containing gate conductor layer, the metal gate conductor layer, and the gate dielectric layer selectively to the etch mask and the semiconductor substrate to provide the gate structure, wherein a first dielectric cap is present on an upper surface of the gate structure.

4. The method ofclaim 3, wherein the spacer is formed in direct contact with the sidewalls of the gate structure, and the source region and the drain region are formed in the semiconductor substrate by ion implantation.

5. The method ofclaim 4, wherein the first metal semiconductor alloy is formed by depositing a first metal layer on the surface of the source region and the drain region; annealing to intermix the first metal layer and a semiconductor from the semiconductor substrate in the source region and the drain region; and removing non-reacted portions of the first metal layer.

6. The method ofclaim 1, wherein the forming of the first interlevel dielectric layer over the surface of the first metal semiconductor alloy comprises:

depositing the first interlevel dielectric layer over the gate structure, the spacer and the surface of the first metal semiconductor alloy; and

planarizing the first interlevel dielectric layer until the upper surface is coplanar with an upper surface of a remaining portion of the first interlevel dielectric layer.

7. The method ofclaim 2, wherein the gate stack further includes a first dielectric cap, and the converting of the semiconductor containing gate conductor to a second metal semiconductor alloy comprises:

removing the first dielectric cap with an etch that is selective to the semiconductor containing gate conductor;

depositing a second metal layer on at least an exposed surface of the semiconductor containing gate conductor;

annealing to intermix the second metal layer and the semiconductor containing gate conductor;

removing non-reacted portions of the second metal layer; and

forming a second dielectric cap on the second metal conductor alloy having an upper surface that is coplanar with the upper surface of the first interlevel dielectric layer.

8. The method ofclaim 1, wherein the forming of the continuous encapsulating layer over the surface of the first metal semiconductor alloy comprises depositing a single dielectric material layer over the surface of the first metal semiconductor alloy, the spacer, and the second metal semiconductor alloy of the gate structure.

9. The method ofclaim 7 further comprising forming a conformal dielectric layer on the gate structure, the spacer and the surface of the first metal semiconductor alloy before forming the first interlevel dielectric layer, and removing a portion of the conformal dielectric layer from the upper surface of the gate structure when the first interlevel dielectric layer is planarized so that the first interlevel dielectric layer has an upper surface that is coplanar with the upper surface of the gate structure, wherein a remaining portion of the conformal dielectric layer is present in direct contact with the spacer and the surface of the first metal semiconductor alloy.

10. The method ofclaim 9, wherein the forming of the continuous encapsulating layer over the surface of the first metal semiconductor alloy comprises depositing a single dielectric material layer in direct contact with the conformal dielectric layer that is in direct contact with the first metal semiconductor alloy and the spacer, and in direct contact with the second dielectric cap that is in direct contact with the second metal conductor alloy.

11. The method ofclaim 1, wherein the forming of the second interlevel dielectric layer on the continuous encapsulating layer comprises forming the second interlevel dielectric layer in direct contact with the continuous encapsulating layer that is over the surface of the first metal semiconductor alloy, the spacer, and the second metal semiconductor alloy of the gate structure.

12. The method ofclaim 10, wherein the extending of the via opening through the continuous encapsulating layer to an exposed portion of the first metal semiconductor alloy comprises:

etching the continuous encapsulating layer selective to the conformal dielectric layer; and

etching the conformal dielectric layer selective to the first metal semiconductor alloy.

13. The method ofclaim 2, wherein the forming of the interconnect in the via opening in direct contact with the exposed portion of the first metal semiconductor alloy comprises depositing a metal into the via opening using physical vapor deposition (PVD).

14. A method of forming a semiconductor device comprising:

forming a gate structure on a semiconductor substrate including a semiconductor containing gate conductor, wherein a source region and a drain region having a surface of a first metal semiconductor alloy are present in the semiconductor substrate on opposing sides of the gate structure;

forming a conformal dielectric layer over the gate structure and the surface of the first metal semiconductor alloy;

forming a first interlevel dielectric layer over the conformal dielectric layer;

planarizing to expose an upper surface of the gate structure, wherein the remaining portion of the conformal dielectric layer and the first interlevel dielectric layer have an upper surface substantially coplanar with the upper surface of the gate structure;

converting the semiconductor containing gate conductor of the gate structure to a second metal semiconductor alloy;

removing the first interlevel dielectric layer;

forming a continuous encapsulating layer in direct contact with the remaining portion of the conformal dielectric and over the second metal semiconductor alloy of the gate structure;

forming a second interlevel dielectric layer on the continuous encapsulating layer; and

forming interconnects to the surface of the first metal semiconductor alloy on the source region and the drain region.

15. The method ofclaim 14, wherein the forming of the interconnects comprises etching a via opening through the second interlevel dielectric layer selective to the continuous encapsulating layer, extending the via opening through the continuous encapsulating layer to an exposed portion of the first metal semiconductor alloy, and forming the interconnect in the via opening in direct contact with the exposed portion of the first metal semiconductor alloy.

16. The method ofclaim 14, wherein the gate structure further includes a first dielectric cap, and the converting of the semiconductor containing gate conductor to a second metal semiconductor alloy comprises:

removing the first dielectric cap with an etch that is selective to the semiconductor containing gate conductor;

depositing a metal layer on at least an exposed surface of the semiconductor containing gate conductor;

annealing to intermix the metal layer and the semiconductor containing gate conductor;

removing non-reacted portions of the metal layer; and

forming a second dielectric cap on the second metal conductor alloy having an upper surface that is coplanar with the upper surface of the first interlevel dielectric layer.

17. A semiconductor device comprising:

a gate structure on a channel region of a semiconductor substrate, wherein the gate structure includes a gate dielectric on the semiconductor substrate, a metal gate conductor on the gate dielectric and a metal semiconductor alloy gate conductor on the metal gate conductor;

at least one spacer present on the sidewalls of the gate structure;

a source region and a drain region present in contact with the semiconductor substrate on opposing sides of the channel region, wherein each of the source region and the drain region include a metal semiconductor contact having a different composition than the metal semiconductor alloy gate conductor;

and

a continuous encapsulating dielectric layer extending over the gate structure, the at least one spacer and at least a portion of the source and drain region.

18. The semiconductor device ofclaim 17, further comprising a uniform dielectric layer between the continuous encapsulating dielectric layer, the at least one spacer and the metal semiconductor contact.

19. The semiconductor device ofclaim 17, wherein the metal semiconductor alloy gate conductor is comprised of cobalt silicide (CoSi₂), and the metal semiconductor contact is comprised of nickel silicide.

20. The semiconductor device ofclaim 17, wherein the continuous encapsulating dielectric layer is composed of a high-k dielectric.

Images