US20120080753A1 - Gallium arsenide based materials used in thin film transistor applications - Google Patents
Gallium arsenide based materials used in thin film transistor applicationsDownload PDFInfo
- Publication number
- US20120080753A1 US20120080753A1US13/250,766US201113250766AUS2012080753A1US 20120080753 A1US20120080753 A1US 20120080753A1US 201113250766 AUS201113250766 AUS 201113250766AUS 2012080753 A1US2012080753 A1US 2012080753A1
- Authority
- US
- United States
- Prior art keywords
- gaas
- layer
- substrate
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 0C[Ga](C)(C)[AsH](C)(C)C.C[Ga]1(C)[AsH](C)(C)[Ga](C)(C)[AsH](C)(C)[Ga](C)(C)[AsH]1(C)C.C[Ga]1(C)[AsH](C)(C)[Ga](C)(C)[AsH]1(C)CChemical compoundC[Ga](C)(C)[AsH](C)(C)C.C[Ga]1(C)[AsH](C)(C)[Ga](C)(C)[AsH](C)(C)[Ga](C)(C)[AsH]1(C)C.C[Ga]1(C)[AsH](C)(C)[Ga](C)(C)[AsH]1(C)C0.000description2
Images
Classifications
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/12—Active materials
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02601—Nanoparticles
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/17—Photovoltaic cells having only PIN junction potential barriers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/128—Annealing
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
- H10F77/143—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies comprising quantum structures
- H10F77/1437—Quantum wires or nanorods
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/20—Electrodes
- H10F77/206—Electrodes for devices having potential barriers
- H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
- H10K30/20—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising organic-organic junctions, e.g. donor-acceptor junctions
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
- H10K30/50—Photovoltaic [PV] devices
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- Embodiments of the present inventiongenerally relate to methods of manufacturing thin film transistor devices. More particularly, embodiments of the present invention relate to a group III-V based material utilized in thin film transistor devices.
- Liquid crystal displaysgenerally contain two glass substrates joined together with a layer of a liquid crystal material sandwiched there between.
- the glass substratemay be a semiconductor substrate, or may be a transparent substrate such as a glass, quartz, sapphire, or a clear plastic film.
- the LCDmay also contain light emitting diodes for back lighting.
- pixelsAs the resolution requirements for liquid crystal displays increase, it has become desirable to control a large number of separate areas of the liquid crystal cell, called pixels. In a modern display panel, more than 1,000,000 pixels may be present. At least the same number of transistors is formed on the glass substrate so that each pixel can be switched between an energized and de-energized state relative to the other pixels disposed on the substrate.
- TFT devicestypically include MOS devices built with a source region, semiconductor (e.g., or called a channel region), and drain region formed on an optically transparent substrate with or without an optional dielectric layer disposed thereon. Subsequently, a gate dielectric layer is then deposited on top of the source region, semiconductor region (e.g., or called a channel region) and drain region isolate a gate electrode from the semiconductor (e.g., or called a channel region), source and drain regions. The gate electrode is formed on top of the gate dielectric layer.
- the performance of a TFT devicedependent on the quality of the films that are deposited to form the MOS structure.
- the key performance elements of a MOS deviceare the qualities of the semiconductor layer (e.g., or called a channel layer), the gate dielectric layer, and the semiconductor layer (e.g., or called a channel layer) and gate dielectric layer interface.
- the quality of the semiconductor layere.g., or called a channel region
- Embodiments of the inventionprovide a method of forming a group III-V based material utilized in thin film transistor devices.
- a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursormay be utilized in thin film transistor devices.
- the gallium arsenide based (GaAs) layer formed from the solution based precursormay be incorporated in thin film transistor devices to improve device performance and device speed.
- a thin film transistor structureincludes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.
- a method of forming a thin film transistor structureincludes providing a substrate having a dielectric layer disposed thereon into a processing chamber, supplying a GaAs containing precursor disposed in a solvent to the processing chamber, evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate, and forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
- a thin film transistor deviceincludes a method for forming a GaAs based material in a thin film transistor structure further includes providing a substrate having a dielectric layer formed thereon, forming a semiconductor layer disposed on the dielectric layer, wherein the semiconductor layer is fabricated from a solution based GaAs based layer, and forming a source-drain metal electrode layer adjacent to the semiconductor layer.
- a method for forming a GaAs based material on a substrateincludes providing a substrate into a electrohydrodynamic jet system, and printing a plurality of GaAs droplets onto the substrate, wherein the GaAs droplets are supplied from a solution based GaAs precursor disposed in the system.
- FIG. 7is a flow chart of methods to manufacture a GaAs based solar cell according to embodiments of the invention.
- FIG. 8depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD);
- AACVDaerosol assisted chemical vapor deposition
- FIG. 9depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber.
- FIG. 10depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system.
- E-jetelectrohydrodynamic jet
- Embodiments of the disclosureprovide methods of forming group III-V based materials that may be utilized in thin film transistor devices.
- the group III-V materials that may be utilized to form the thin film transistor devicesincludes a gallium arsenide (GaAs) based material.
- the gallium arsenide (GaAs) based materialmay be fabricated from a GaAs pre-engineering solution.
- the gallium arsenide (GaAs) based materialmay also be used in photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications.
- the gallium arsenide (GaAs) based materialprovides high film mobility and stability and low film leakage, thereby efficiently enhancing the electrical performance of transistor devices. It is noted that the gallium arsenide (GaAs) based material may be used in other suitable devices beyond the application noted above.
- FIG. 1depicts a bottom gate structure thin film transistor (TFT) device 100 according to one embodiment of the present disclosure.
- the device 100includes a gate electrode layer 106 disposed on a substrate 102 covered with a gate insulator layer 104 .
- a semiconductor layer 108e.g., or called a semiconductor active layer, an active layer or a channel layer, conventionally often made from an amorphous silicon layer or a low temperature polysilicon (LTPS) layer, is disposed over the gate insulator layer 104 .
- a thin doped semiconductor layer of n-type or p-type layer 110 a , 110 bis disposed over the semiconductor layer 108 .
- a source-drain metal electrode layer 112 a , 112 bis then disposed thereon and a passivation layer 114 is then subsequently formed thereon to form the thin film transistor device 100 .
- a group III-V materialmay be used to form as may be used to form as the semiconductor layer 108 and the thin doped semiconductor layer 110 a , 110 b in the thin film transistor 100 .
- the group III-V materialis a gallium arsenide (GaAs) based material.
- gallium arsenide (GaAs) based materialcan provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as the semiconductor layer 108 and the thin doped semiconductor layer 110 a , 110 b is believed to provide the thin film transistor 100 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced to FIGS. 7-9 .
- the substrate 102may be any one of glass substrate, plastic substrate, polymer substrate, metal substrate, singled substrate, roll-to-roll substrate, or other suitable transparent substrate suitable for forming a thin film transistor thereon.
- the gate electrode layer 106may be fabricated from any suitable metallic materials, such as indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum (Al), tungsten (W), chromium (Cr), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), molybdenum (Mo), InGaZnO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuAlO, Sr
- Suitable materials for the gate insulator layer 104may be silicon oxide (SiO 2 ), silicon oxynitride (SiON), or silicon nitride (SiN), high-k materials, such as HfO 2 , or other suitable materials, or the like.
- the source-drain metal electrode layer 112 a , 112 bmay be fabricated by a metallic material selected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), alloy of aluminum(Al) and cobalt (Co), composite layers including a film stack having aluminum layer (Al) sandwiched between molybdenum (Mo), alloys thereof and combination thereof.
- a metallic materialselected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(Al), tungsten (W), molybdenum (Mo), chrom
- the passivation layer 114may be fabricated by dielectric materials including silicon oxide (SiO 2 ), silicon oxynitride (SiON), or silicon nitride (SiN), suitable polymer materials, such as polymethylmethacrylate (PMMA) and the like.
- dielectric materialsincluding silicon oxide (SiO 2 ), silicon oxynitride (SiON), or silicon nitride (SiN), suitable polymer materials, such as polymethylmethacrylate (PMMA) and the like.
- FIG. 2depicts a top metal gate structure thin film transistor (TFT) device 200 according to one embodiment of the present disclosure.
- the device 200includes a metal gate electrode 204 disposed over a backside of a substrate 202 .
- An insulator layer 203may be formed from an opposite side (e.g., front side) of the substrate 202 from wherein the metal gate electrode 204 is formed.
- a semiconductor layer 206e.g., or called a semiconductor active layer, an active layer or a channel layer, conventionally often made from an amorphous silicon layer or a low temperature polysilicon (LTPS) layer, is disposed over the insulator layer 203 .
- LTPSlow temperature polysilicon
- a source-drain metal electrode layer 208 a , 208 bis then disposed over the semiconductor layer 206 to form the thin film transistor device 200 .
- a group III-V materialmay be used to form as may be used to form as the semiconductor layer 206 in the thin film transistor 200 .
- the group III-V materialis a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed.
- gallium arsenide (GaAs) based materialas the semiconductor layer 206 is believed to provide the thin film transistor 200 a good device performance may be obtained. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced to FIGS. 7-9 .
- the materials that may be used to form the metal gate electrode 204 , the insulator layer 203 , and the source-drain metal electrode layer 208 a , 208 bmay be similar to the materials utilized to form the metal gate electrode 106 , the gate insulator layer 104 , and the source-drain metal electrode layer 112 a , 112 b described above with referenced to FIG. 1 .
- FIG. 3depicts a thin film transistor (TFT) device 300 according to one embodiment of the present disclosure.
- the device 300includes a semiconductor layer 304 (or called a semiconductor active layer, an active layer or a channel layer) disposed over a substrate 302 .
- An insulator layer 308may be formed over the semiconductor layer 304 in between a patterned source-drain metal electrode layer 306 a , 306 b .
- a gate electrode layer 310is then disposed over the insulator layer 308 to form the thin film transistor device 300 .
- a group III-V materialmay be used to form as may be used to form as the semiconductor layer 304 in the thin film transistor 300 .
- the group III-V materialis a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as the semiconductor layer 304 is believed to provide the thin film transistor 300 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced to FIGS. 7-9 .
- the materials that may be used to form the metal gate electrode layer 310 , the insulator layer 308 , and the source-drain metal electrode layer 306 a , 306 bmay be similar to the materials utilized to form the metal gate electrode 106 , the gate insulator layer 104 , and the source-drain metal electrode layer 112 a , 112 b described above with referenced to FIG. 1 .
- FIG. 4depicts a thin film transistor (TFT) device 400 according to one embodiment of the present disclosure.
- the device 400includes a buffer oxide layer 404 disposed on a substrate 402 .
- a semiconductor layer 412e.g., or called a semiconductor active layer, an active layer or a channel layer
- a gate insulator layer 408is then disposed over the semiconductor layer 412 followed by a metal gate electrode layer 410 .
- a group III-V materialmay be used to form as may be used to form as the semiconductor layer 412 in the thin film transistor 400 .
- the group III-V materialis a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as the semiconductor layer 412 is believed to provide the thin film transistor device 400 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced to FIGS. 7-9 .
- the materials that may be used to form the metal gate electrode 410 , the gate insulator layer 408 , and the source-drain metal electrode layer 406 a , 406 bmay be similar to the materials utilized to form the metal gate electrode 106 , the gate insulator layer 104 , and the source-drain metal electrode layer 112 a , 112 b described above with referenced to FIG. 1 .
- FIG. 5depicts a thin film transistor (TFT) device 500 according to one embodiment of the present disclosure.
- the device 500includes a metal gate electrode layer 504 is disposed over a substrate 502 .
- a gate insulator layer 506is disposed over the metal gate electrode 504 .
- a semiconductor layer 508(e.g., or called a semiconductor active layer, an active layer or a channel layer) is disposed over the gate insulator layer 506 .
- a passivation layer 512is disposed over the semiconductor layer 508 between a patterned source-drain metal electrode layer 510 a , 510 b .
- a group III-V materialmay be used to form as may be used to form as the semiconductor layer 508 in the thin film transistor 500 .
- the group III-V materialis a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as the semiconductor layer 508 is believed to provide the thin film transistor device 500 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced to FIGS. 7-9 .
- the materials that may be used to form the passivation layer 512 , the metal gate electrode layer 504 , the gate insulator layer 506 , and the source-drain metal electrode layer 510 a , 510 bmay be similar to the materials utilized to form the passivation layer 114 , the metal gate electrode layer 106 , the gate insulator layer 104 , and the source-drain metal electrode layer 112 a , 112 b described above with referenced to FIG. 1 .
- FIG. 6depicts a thin film transistor (TFT) device 600 according to one embodiment of the present disclosure.
- the device 600includes a gate insulator layer 604 disposed over the substrate 602 .
- a semiconductor layer 606e.g., or called a semiconductor active layer, an active layer or a channel layer
- a patterned source-drain electrode layer 608 a , 608 bis then disposed on the semiconductor layer 606 .
- a passivation layer 610is then disposed on the patterned source-drain electrode layer 608 a , 608 b .
- a group III-V materialmay be used to form as may be used to form as the semiconductor layer 606 in the thin film transistor 600 .
- the group III-V materialis a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as the semiconductor layer 606 is believed to provide the thin film transistor device 600 a greater mobility of electrons and good device performance may be obtained. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced to FIGS. 7-9 .
- the materials that may be used to form the passivation layer 610 , the gate insulator layer 604 , and the source-drain metal electrode layer 608 a , 608 bmay be similar to the materials utilized to form the passivation layer 114 , the metal gate electrode layer 106 , the gate insulator layer 104 , and the source-drain metal electrode layer 112 a , 112 b described above with referenced to FIG. 1 .
- FIGS. 1-6only depict exemplary embodiments of thin film transistors having semiconductor layers that may be formed from a group III-V material, such as a gallium arsenide (GaAs) based material or a doped gallium arsenide (GaAs) based material.
- group III-V materialsuch as a gallium arsenide (GaAs) based material or a doped gallium arsenide (GaAs) based material.
- GaAsgallium arsenide
- GaAsgallium arsenide
- GaAsdoped gallium arsenide
- Other thin film devices not illustrated here having semiconductor layers, doped semiconductor layers, or other suitable active or non-active layers formed thereinmay also suitable to be formed as group III-V material according to the methods as described below with referenced to FIGS. 7-9 .
- FIG. 7depicts a flow diagram of one embodiment of a processing sequence 700 for forming a solution based group III-V material, such as a solution based GaAs layer utilized in a thin film transistor device, such as the semiconductor layer 108 , 206 , 304 , 412 , 508 , 606 , or a doped semiconductor layer 110 a , 110 b , formed in the thin film transistor devices 100 , 200 , 300 , 400 , 500 , 600 depicted in FIGS. 1-6 .
- a solution based group III-V materialsuch as a solution based GaAs layer utilized in a thin film transistor device, such as the semiconductor layer 108 , 206 , 304 , 412 , 508 , 606 , or a doped semiconductor layer 110 a , 110 b , formed in the thin film transistor devices 100 , 200 , 300 , 400 , 500 , 600 depicted in FIGS. 1-6 .
- the semiconductor layer 108 , 206 , 304 , 412 , 508 , 606 , or a doped semiconductor layer 110 a , 110 bare configured as GaAs based materials
- these layersmay also be manufactured by the processing sequence 700 as depicted in FIG. 7 .
- FIG. 7only depicts the process of manufacturing GaAs based layer for illustration purpose, and is not intended to limiting the invention scope or certain types of the layers that may be manufactured.
- the number and sequence of steps illustrated in FIG. 7are not intended to limiting as to the scope of the invention described herein, since one or more steps can be added, deleted and/or reordered were appropriate without deviating from the basic scope of the invention described herein.
- the processing sequence 700begins at step 702 by providing a substrate, such as the substrate 102 , 202 , 302 , 402 , 502 , 602 , as shown in FIGS. 1-6 , configured to form thin film transistor devices thereon.
- the substrate 102may be any one of glass substrate, plastic substrate, polymer substrate, metal substrate, singled substrate, roll-to-roll substrate, transparent substrate, silicon containing substrate, such as a single crystal silicon substrate, a multicrystalline silicon substrate, glass substrate, quartz substrate, or other suitable materials or other suitable transparent substrate suitable for forming a thin film transistor thereon.
- the substratemay have layers previously formed thereon to readily form a semiconductor layer 108 , 206 , 304 , 412 , 508 , 606 , or a doped semiconductor layer 110 a , 110 b , as the GaAs based layer.
- a GaAs deposition processis performed to deposit a GaAs layer on the substrate.
- the GaAs deposition processis performed by providing a pre-engineered solution based GaAs precursor to a processing chamber as a source precursor to facilitate depositing the GaAs layer as the semiconductor layer 108 , 206 , 304 , 412 , 508 , 606 , or a doped semiconductor layer 110 a , 110 b on the substrate 102 .
- the pre-engineered solution based GaAs precursorcomprises a mixture of gallium complex and arsenic complex in solution, forming a gallium-arsenic complex in the solution.
- the gallium-arsenic complex formed in the pre-engineered solution based GaAs precursorgenerally has a GaAs dimer (—GaAs—), a GaAs tetramer (—Ga 2 As 2 —), or a GaAs hexamer (—Ga 3 As 3 —) structure, as shown below.
- GaAs dimer(—GaAs—), a GaAs tetramer (—Ga 2 As 2 —), or a GaAs hexamer (—Ga 3 As 3 —) structures are relatively stable complexes so make them as good candidates to be placed or stored in liquid solution under a relatively stable status.
- the GaAs solutionmay be delivered, injected, sprayed and coated onto the substrate with high uniformity and good film quality, thereby providing a reliable and repeatable GaAs layer with desired film properties and high film properties.
- the GaAs dimer, GaAs tetramer, or GaAs hexamermay have different functional groups attached thereto to form the GaAs source precursor as a stable complex in the pre-engineered solution.
- the GaAs complexmay have a formula R x (GaAs) y R′ z , wherein x, y, and z are integers having a range between 1 and 15, which R and R′ may or may not be the same function groups or the like.
- the functional groups that may be attached to the Ga and As elements in the GaAs dimer, GaAs tetramer, or GaAs hexamermay include alkyl group, such as methyl (CH 3 —), ethyl (C 2 H 5 —), propyl (C 3 H 7 —), butyl (C 4 H 9 —), pentyl (C 5 H 11 —), and so on, isopropyl and other similar isomers, aromatic groups, such as benzal, styrene, toluene, xylene, pyridine, ethylbenzene, acetophenone, methyl benzoate, phenyl acetate, phenol, cresol, furan, and the like, alicyclic group, such as cyclopropane, cyclobutane, cyclopentane, cyclopentadiene, toluene and the like, amino group, such as NR 2 (R as alkyl group),
- amino groupsuch as NR 2 (R as alkyl group) and steric hindrance ligands are selected as the functional groups attached to the GaAs dimer, GaAs tetramer, or GaAs hexamer.
- the GaAs complexrequires having a high solubility and stability in solution. Accordingly, the functional groups selected to form in the GaAs complex are desired to have 1:1 stoichiometry preactive or formed in clusters. Additionally, the functional groups are also desired to be able to be low temperature decomposed into GaAs. Furthermore, the bonding energy between the functional groups and Ga element and/or between the functional groups and As element is configured to be weaker than the bonding energy comprising the Ga—As bond. By this configuration, during a depositing reaction, the bonds between the functional groups and the Ga and/or As elements can be easily broken from the GaAs solution precursor, thereby assisting the formation of the GaAs layer on the substrate surface, and leaving GaAs bonding in the complex. As the functional groups as attached are selected to be easily removed, evaporated, or pyrolyzing during deposition or at the subsequent baking or curing process, a GaAs layer with minimum impurities or contamination may be thus obtained and formed on the substrate surface.
- GaAs precursorsthat follows the requirements as stated above includes (NMe 2 ) 2 Ga 2 As 2 ( t BuH) 2 , Me 2 GaAs(NMe 2 ) 2 , Me 2 GaAs(SiMePh 2 ) 2 , Me 2 GaAs(SiPh 3 ) 2 , Et 2 GaAs(SiMe 2 Cy) 2 , Me 2 GaAs(SiMe 2 Cy) 2 , (Me) 3 GaAs(NMe 2 ) 3 , (Et) 3 GaAs(NMe 2 ) 3 , (Me) 4 Ga 2 As 2 ( t BuH) 2 , (Et) 4 Ga 2 As 2 ( t BuH) 2 , 1:3 stoichiometry of Ga:As, such as GaAs 3 t Bu 6 , or the like.
- the structures of the GaAs precursorsinclude the followings:
- the GaAs precursor used to form the GaAs layer on the substrateis (NMe 2 ) 2 GaAs t BuH.
- (NMe 2 ) 2 GaAs t BuH precursormay be synthesized by mixing gallium amide (Ga(NMe 2 )) 3 with excess tert-butyl arsine ( t BuAsH 2 ) in hexane or toluene solvent or other suitable organic or inorganic solvent and stirring overnight, such as stirring over 16 hours.
- the process temperaturemay be controlled between about ⁇ 40 degrees Celsius and about ⁇ 90 degrees Celsius.
- (NMe 2 ) 2 GaAs t BuHis obtained and may be stored in CH 2 Cl 2 solvent or toluene solvent.
- the GaAs layermay be formed by using tris(dimethylamino)arsine (Me 6 N 3 As) and trimethylgallium (GaMe 3 ) as source precursors to synthesize and pre-engineer the GaAs source precursor.
- the tris(dimethylamino)arsine (Me 6 N 3 As) and trimethylgallium (GaMe 3 )are reacted in toluene or hexane solvent to form the desired solution based GaAs containing precursor.
- the process temperaturemay be controlled between about ⁇ 40 degrees Celsius and about ⁇ 90 degrees Celsius.
- the GaAs layermay be formed by using [ ⁇ L ⁇ HGaAsR] n or [ ⁇ L ⁇ 2 GaAs t BuH] as a precursor, in which L is nitrogen-based donor ligand, NMe 2 , or hydrazines functional groups.
- the precursors of [ ⁇ L ⁇ HGaAsR] n or [ ⁇ L ⁇ 2 GaAs t BuH]may be synthesized by a reaction of As(SiR 3 ) 3 , R 3 SiAsH 3 , or H 2 As t Bu with GaH 3 ⁇ L ⁇ or Ga ⁇ L ⁇ 3 in a hexane solution while stirring at room temperature for over 24 hours.
- the [ ⁇ L ⁇ HGaAsR] n or [ ⁇ L ⁇ 2 GaAs t BuH] precursormay be obtained and can be used as a source of GaAs to form the GaAs layer on the substrate when decomposed.
- the GaAs containing precursorsuch as (NMe 2 ) 2 GaAs t BuH, [ ⁇ L ⁇ HGaAsR] n or [ ⁇ L ⁇ 2 GaAs t BuH], or other suitable precursor as described above, is then supplied to a CVD chamber to deposit the GaAs layer on the substrate.
- the solution based GaAs containing precursoris supplied in a CVD chamber to perform an aerosol assisted chemical vapor deposition (AACVD) process.
- AACVDaerosol assisted chemical vapor deposition
- An example of the AACVD chamber that may be used to practice the present inventionwill be further discussed below with referenced to FIG. 8 .
- the precursor solutionis atomized by using an aerosol generator.
- a carrier gasis used to promote aerosol formation.
- aerosol carrying the GaAs containing solvent precursoris transported into CVD chamber by the carrier gas and evaporated in the chamber.
- the precursorAfter entering into the CVD chamber, the precursor enters into the gas phase from the liquid phase to enable the CVD process.
- the gas phase GaAs containing precursoris then decomposed and absorbed on the substrate to form the desired GaAs layer on the substrate. If the precursor does not get full vaporization, spray pyrolysis process will take place to have the precursor become as aerosol droplets to be absorbed on the substrate and form the GaAs layer on the substrate surface.
- the substrate temperatureis controlled at about 550 degrees Celsius so as to efficiently evaporate the precursor entering into the chamber.
- the GaAs layermay also be formed on the substrate by using aerojet, flash evaporation, laser assisted CVD, UV assisted CVD, laser reactive deposition, nanoparticles spray from solution, spray CVD, metalorganic vapour phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), or by other suitable techniques as needed.
- Some other wet deposition processsuch as ink-jet, spin coating, meniscus coating, dip coating, electroplating, spray coating, electrospraying, screen printing or other suitable techniques may also employed to form the GaAs layer on the substrate surface.
- vacuum techniquessuch as molecular beam epitaxy (MBE), metalorganic vapour phase epitaxy (MOVPE), pulsed laser deposition (PLD), plasma enhanced chemical vapor deposition (PECVD), sputter, evaporate, magnetron sputter, chemical beam deposition, atomic layer deposition (ALD), hardware chemical vapor deposition (HWCVD), microwave plasma and some other techniques, may also used as needed.
- MBEmolecular beam epitaxy
- MOVPEmetalorganic vapour phase epitaxy
- PLDpulsed laser deposition
- PECVDplasma enhanced chemical vapor deposition
- sputterevaporate, magnetron sputter, chemical beam deposition, atomic layer deposition (ALD), hardware chemical vapor deposition (HWCVD), microwave plasma and some other techniques, may also used as needed.
- the GaAs layeris formed as a semiconductor layer in a thin film transistor device disposed on the substrate.
- the GaAs layer as formed on the substratemay have a ratio of Ga element to As element substantially between about 1:0.8 and about 1:1.2.
- XRD analysisindicates that the GaAs layer as formed has a strong (111) plane peak.
- the GaAs layermay have a thickness between about 0.2 ⁇ m and about 3 ⁇ m.
- different dopantsmay be doped into the GaAs layer.
- Dopantsmay be in form of particles, powders, gel, liquid, solution or any other suitable forms, blending and mixing into the solution based GaAs pre-engineered precursor.
- Different dopants formed in the GaAs layermay provide different film conductivity and mobility, thereby increasing the electrical performance of the devices.
- the dopants that may be doped into the GaAs layerinclude Al, Zn, Mg, In, P, Si, Se, S, C, N and the like.
- Suitable examples of p-type and n-type dopantsmay be mixed or blended into the GaAs precursor to form a doped GaAs solution based precursor, such as the p-type or n-type doped GaAs layers.
- Suitable examples of p-type dopantsmay be added into the GaAs precursor include metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), metallic magnesium dopants, cyclopentadienyl magnesium, carbon chlorine (CCl 4 ), carbon bromide (CBr 4 ) or the like.
- Suitable examples of n-type dopantsinclude H 2 S, sulfur, silane (SiH 4 ), disilane (Si 2 H 6 ), H 2 Se, Se or the like.
- the dopant concentration in the doped GaAs layermay be controlled at between about 1 ⁇ 10 16 atom/cm 3 and about 1 ⁇ 10 2 ° atom/cm 3 .
- the p-type dopantsmay be doped in the GaAs layer with a dopant concentration between about 1 ⁇ 10 17 atom/cm 3 and about 1 ⁇ 10 19 atom/cm 3 .
- the n-type dopantsmay be doped in the GaAs layer with a dopant concentration between about 1 ⁇ 10 18 atom/cm 3 and about 1 ⁇ 10 20 atom/cm 3 .
- an anneal processis performed to thermally process the GaAs layer.
- different types of post treatment processessuch as quenching, baking, laser treatment, or the like, may also be performed on the GaAs layer as needed.
- the precursor utilized to form the GaAs layercontains elements other than Ga and As, such as carbon, nitrogen, oxide, or other elements contained in the precursor.
- the thermal annealing process and/or the post treatment process performed on the deposited layermay assist in the driving out of the impurities contained in the as-deposited GaAs layer.
- the thermal processmay also assist in the repair of defects that may be formed in the as-deposited film during the deposition process.
- the annealing processmay be performed by any suitable annealing tool, such as furnace, rapid thermal processing (RTP) chamber, spike anneal, or laser annealing chamber, and the like.
- the annealing processmay be performed at a temperature between about 400 degrees Celsius and about 600 degree Celsius to assist in the densification and/or crystallization of the GaAs layer formed on the substrate.
- FIG. 8depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD) chamber 800 that may be utilized to deposit a solution based GaAs layer on a substrate 801 , such as the substrate 102 , 202 , 302 , 402 , 502 , 602 , described above with referenced to FIGS. 1-6 .
- the AACVD chamber 800may be used to perform a AACVD deposition process, such as the deposition process described above with referenced to FIG. 3 .
- deposition processsuch as MOCVD, aerojet, flash evaporation, laser assisted CVD, UV assisted CVD, laser reactive deposition, nanoparticles spray from solution, spray CVD, MOVPE, HVPE, or by other suitable techniques may be used to form the GaAs layer as needed.
- Some other wet deposition processsuch as ink-jet, spin coating, meniscus coating, dip coating, electroplating, spray coating, electrospraying, screen printing or other suitable techniques may also employed to form the GaAs based layer on the substrate surface.
- vacuum techniquessuch as MBE, MOVPE, PLD, PECVD, sputter, evaporate, magnetron sputter, chemical beam deposition, ALD, HWCVD, microwave plasma and some other techniques, may also used as needed.
- the chamber 800includes a reaction tube 822 having a first wall 826 , a second wall 828 , and a reactor body 824 connecting between the first wall 826 and the second wall 828 .
- the first wall 826 , the second wall 828 , and the reactor body 824 formed in the reaction tube 822defines an interior processing region 818 .
- a graphite heating block 820is disposed in the reaction tube 822 to receive the substrate disposed thereon for processing. The temperature of the substrate may be monitored by a temperature sensor (not shown) disposed in the reaction tube 822 as needed.
- An exhaust 832is formed in the second wall 828 to facilitate transferring the substrate into and out of the reaction tube 822 .
- a gas inlet port 830is formed in the first wall 826 to facilitate delivering reaction gases and precursors into the interior processing region 818 during process from a mixing chamber 816 .
- a liquid ampoule container 834is attached to the mixing chamber 816 through a gas delivery passageway 836 .
- the liquid ampoule container 834may store precursors 808 to provide source materials into the interior processing region 818 to deposit a GaAs based layer based on the substrate.
- the mixing chamber 816provides a tortuous path which may extend the flow path for the GaAs precursor 808 supplied from the liquid ampoule container 834 to ensure thorough mixing.
- GaAs precursormay be stored in the liquid ampoule container 834 include (NMe 2 ) 2 GaAs t BuH, Me 2 GaAs(NMe 2 ) 2 , Me 2 GaAs(SiMePh 2 ) 2 , Me 2 GaAs(SiPh 3 ) 2 , Et 2 GaAs(SiMe 2 Cy) 2 , Me 2 GaAs(SiMe 2 Cy) 2 , (Me) 3 GaAs(NMe 2 ) 3 , (Et) 3 GaAs(NMe 2 ) 3 , (Me) 4 Ga 2 As 2 ( t BuH) 2 , (Et) 4 Ga 2 As 2 ( t BuH) 2 , or the like.
- dopant containing materialsmay be blended, added or mixed with the GaAs precursor in the liquid ampoule container 834 , forming a dopant containing GaAs precursor which can be readily supplied to the interior processing region 818 for processing.
- suitable p-type dopant materialsthat may be added into the GaAs precursor include zinc containing materials, such as metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), or the like, magnesium containing material, such as metallic magnesium dopants, cyclopentadienyl magnesium, or the like, and carbon containing materials, such as carbon chlorine (CCl 4 ), carbon bromide (CBr 4 ) or the like.
- zinc containing materialssuch as metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), or the like
- magnesium containing materialsuch as metallic magnesium dopants, cyclopentadienyl magnesium, or the like
- carbon containing materialssuch as carbon chlorine (CCl 4 ), carbon bromide (CBr 4 ) or the like.
- Suitable n-type dopant materials that may be added into the GaAs precursorinclude sulfur containing materials, such as H 2 S, sulfur, silicon containing materials such as silane (SiH 4 ), disilane (Si 2 H 6 ), and selenium containing material, such as H 2 Se, Se or the like.
- the p-type dopant materials utilized to be added to the GaAs precursoris DMZ or DEZ and n-type dopant materials utilized to be added to the GaAs precursor is disilane (Si 2 H 6 ).
- a gas panel 810is coupled to the liquid ampoule container 834 to supply a carrier gas to the liquid ampoule container 834 through a delivery passageway 812 .
- the gas panel 810introduces carrier gases to the liquid ampoule container 834 to inject and push the GaAs precursor 802 disposed in the liquid ampoule container 834 to the mixing chamber 816 and ultimately into the interior processing region 818 through the gas delivery passageway 836 .
- gasesthat may be supplied from the gas panel 810 include nitrogen containing gas, such as nitrogen (N 2 ), N 2 O, and NO, among others, or oxygen containing gas, such as, oxygen (O 2 ) or (O 3 ).
- Inert gassuch as Ar or He, may also be used to carry the GaAs precursor 802 into the interior processing region 818 .
- the carrier gas used to inject and push the GaAs precursor 808 to the interior processing region 818is nitrogen (N 2 ) gas.
- the solution based GaAs precursor 802 with/without the desired dopants disposed in the liquid ampoule container 834is heated and vaporized by a humidifier 804 .
- the humidifier 804may have a piezoelectric device 806 which may provide ultrasonic energy and/or heat energy to the solution based GaAs precursor 802 disposed therein, thereby assisting heating and evaporating GaAs precursor 802 into gas phase or in form of tiny droplets for injection into the interior processing region 818 by the carrier gas, as shown by the arrow 814 .
- Some liquid 808such as water or other suitable liquid, may be disposed between the liquid ampoule container 834 and the humidifier to maintain the solution based GaAs precursor 802 within a desired temperature range.
- the humidifier 804may vaporize the GaAs precursor at a temperature between about 100 degrees Celsius and about 250 degrees Celsius.
- FIG. 9depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber 900 that may be utilized to anneal a substrate 901 , such as the substrate 102 , 202 , 302 , 402 , 502 , 602 described above with referenced to FIGS. 1-6 .
- the processing chamber 900includes a chamber body 950 having chamber walls 930 , a bottom 932 , and a top 934 defining an interior volume 928 .
- the walls 930typically include at least one substrate access port (not shown) to facilitate entry and egress of the substrate 102 , 202 , 302 , 402 , 502 , 602 .
- a radiant heat assembly 924is mounted to the top 934 of the chamber body 950 .
- the radiant heat assembly 924is utilized to heat the substrate suspended by an edge ring 910 disposed around the periphery of the substrate.
- the radiant heat assembly 924includes a plurality of lamp tubes 902 in a water jacket assembly 904 .
- Each tube 902contains a reflector and a tungsten halogen lamp assembly.
- the lamp tubes 902are nested in a tight honeycomb pipe arrangement. This close-packed hexagonal arrangement of lamp tubes 902 provides radiant energy, such as an IR radiation and/or longer wavelength of UV radiation having a wavelength between about 400 nm and about 4000 nm with high-power density.
- the radiant heat assembly 924provides radiant energy to thermally process the substrate, such as annealing a silicon layer disposed on the substrate.
- One radiant heat assembly 924 that may be adapted to benefit from the inventionis described in U.S. Pat. No. 5,487,127, issued Jan. 23, 1996 to Gronet, et al., and is hereby incorporated by reference in its entirety.
- the edge ring 910 that supports substrateis spaced above a stainless steel base 918 by a rotatable quartz cylinder 912 mounted on the stainless steel base 918 .
- the edge ring 910may be fabricated from a hard material with a small coefficient of thermal expansion, such as silicon carbide, to prevent excessive expansion and contraction during thermal processing.
- the quartz cylinder 912is rotated between about 50 rpm and about 300 rpm during substrate processing to maximize substrate temperature uniformity by minimizing the effect of thermal asymmetries in the chamber 900 and on the substrate.
- the cylinder 912may be coated with silicon to render the cylinder opaque to a desired wavelength.
- the stainless steel base 918has a circulation circuit 946 allowing coolant, such as water, to circulate therethrough. The coolant circulation efficiently cools down the chamber temperature after processing.
- a reflector plate 914is disposed below the substrate and mounted above the stainless steel base 918 .
- An array of temperature probes 944is embedded in the reflector plate 914 through openings 942 defined therein.
- the temperature probes 944are connected to pyrometers 916 through a conduit 936 that extends from the bottom side of the stainless steel base 918 to the openings 942 in the reflector plate 914 .
- the temperature probes 944 and pyrometers 916are used to obtain a metric indicative of temperatures of regions of the substrate proximate each probe 944 such that a temperature gradient of the substrate may be determined.
- a controller 917may receive measurements from the pyrometers 916 and output control signals to radiant heat assembly 924 for real-time modify the radiation generated in the processing chamber 900 , thereby maintaining the substrate temperature within a desired processing range.
- the upper side 938 of the reflector plate 914is highly reflective, and reflects thermal radiation in a target wavelength range and absorbs thermal radiation other then the target wavelength range.
- One or more coating or layersmay be utilized to coat the reflector plate 914 on the stainless steel base 918 to provide the selective reflectivity.
- different combination of coatings with different reflectivity and absorbabilitymay be utilized to enable the reflector plate 914 to reflect thermal radiation at a desired wavelength back to the substrate and absorb (or less reflect) thermal radiation other than the desired wavelength.
- the reflector plate 914reflects the thermal wavelength between about 700 nm and about 1000 nm, and absorbs thermal wavelength below 700 nm and above 1000 nm.
- One reflector plate 914 that may be adapted to benefit from the inventionis described in U.S. Pat. No. 6,839,507, issued Jan. 4, 2005 to Adams, et al., and is hereby incorporated by reference in its entirety.
- the thermal energy not reflected to back to the substrateis absorbed by the reflector plate 914 .
- the absorbed thermal energyis efficiently and rapidly removed by the coolant circulating through the stainless steel base 918 disposed below the reflector plate 914 .
- gas provided through holes (not shown) in the reflector plate 914may be utilized to promote the cooling rate of the reflector plate 914 and the substrate positioned thereabove.
- the rapid cool down rate provided by the reflector plate 914promotes the temperature control of the substrate, thereby efficiently providing a desired temperature processing profile.
- the reflector plate 914may provide a substrate cool date rate greater than about 200 degrees Celsius per second. In another embodiment, the reflector plate 914 may provide a substrate cool down rate of about 220 degrees Celsius per second.
- FIG. 10depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system 1000 .
- Electrohydrodynamic jet (E-jet) printingis a technique that uses electric fields to create fluid flow necessary to deliver ink and/or droplet to a substrate for high resolution ( ⁇ 30 ⁇ m).
- the electrohydrodynamic jet (E-jet) printingis used herein to print a group III-V material, such as GaAs based droplets, on the backplanes for high performance thin film transistor (TFT) displays.
- TFTthin film transistor
- the electrohydrodynamic jet (E-jet) printing utilized to print GaAs based dropletsmay also be used to create backplanes for OLED displays and high resolution, high frequency (3D) LCD TVs.
- the GaAs based dropletsmay use GaAs solution based precursor, as discussed above with referenced to FIG. 7 , as the source material at relatively a low temperature.
- the high resolution of the electrohydrodynamic jet (E-jet) printing of the GaAs based dropletsmay be obtained due to a combination of nozzle sizes and droplet placement.
- the nozzle sizesmay be varied to control the size of the droplets printed onto the substrate.
- the electrohydrodynamic jet (E-jet) printing system 1000includes an ink chamber 1002 and an ink chamber holder 1004 utilized to hold and control the ink chamber 1002 at desired positions above a substrate 1016 disposed on a translation and tilting stage 1018 .
- a stage heater 1020may be attached to the translation and tilting stage 1018 to control the substrate 1016 at a desired temperature range.
- a micropipette 1010is coupled to an end of the ink chamber 1002 to deliver the ink from the ink chamber 1002 to an nozzle 1022 attached to an end of a heater 1012 coupled between the micropipette 1010 and the nozzle 1022 .
- the heater 1012may be a NiCr heater configured to maintain the ink delivered therethrough at a desired temperature range not to clog the delivery path.
- the stage 1018may be moved relative to the tip of the nozzle 1022 .
- the stage 1018may be controlled to have a scan speed at a desired range.
- the stage 1018may be controlled to move relative to the nozzle 1022 along a periphery region or center region of the substrate 1016 to inject ink to desired locations defined on the substrate surface.
- the stage 1018may be moved at a constant speed, an accelerated speed or moved other paths as desired.
- Any suitable translation mechanismmay be used, such as a conveyor system, rack and pinion system, or an x/y actuator, a robot, or other suitable mechanism, to accurate movement of the stage 1018 .
- a back pressure source 1006is coupled to a conduit 1008 attached to the ink chamber 1002 configured to apply a back pressure to the nozzle 1022 .
- Different pressure as appliedmay have different amount of ink injected onto the substrate surface as needed.
- change in back pressure and voltage as applied to the nozzle 1022may also affect the size and frequency of the ink droplets.
- the GaAs solution based precursoras discussed above with referenced to FIG. 7 , may be stored in the ink chamber 1002 configured to be printed or injected onto the substrate as needed.
- a voltage powermay be applied between the nozzle 1022 and the substrate to create an electric field so as to maintain and control consistent jetting conditions.
- the printed GaAs dropletsmay have an average measured diameter between about 1 ⁇ m and about 10 ⁇ m.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Materials Engineering (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mechanical Engineering (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Metallurgy (AREA)
- Composite Materials (AREA)
- Inorganic Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Electromagnetism (AREA)
- Photovoltaic Devices (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Sustainable Energy (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Recrystallisation Techniques (AREA)
- Junction Field-Effect Transistors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
- This application claims benefit of U.S. Provisional Application Ser. No. 61/388,943 filed Oct. 1, 2010 (Attorney Docket No. APPM/15444L), U.S. Provisional Application Ser. No. 61/452,801 filed Mar. 15, 2011 (Attorney Docket No. APPM/15444L02) and U.S. Provisional Application Ser. No. 61/468,918, filed Mar. 29, 2011 (Attorney Docket No. APPM/15444L03), all of which are incorporated by reference in their entirety.
- This application is also related to U.S. patent application Ser. No. ______, entitled “High Efficiency Solar Cell Device With Gallium Arsenide Absorber Layer”, filed ______, (Attorney Docket No. APPM/15444) which is herein incorporated by reference.
- 1. Field of the Invention
- Embodiments of the present invention generally relate to methods of manufacturing thin film transistor devices. More particularly, embodiments of the present invention relate to a group III-V based material utilized in thin film transistor devices.
- 2. Description of the Related Art
- Plasma display panels and liquid crystal displays are frequently used for flat panel displays. Liquid crystal displays (LCD) generally contain two glass substrates joined together with a layer of a liquid crystal material sandwiched there between. The glass substrate may be a semiconductor substrate, or may be a transparent substrate such as a glass, quartz, sapphire, or a clear plastic film. The LCD may also contain light emitting diodes for back lighting.
- As the resolution requirements for liquid crystal displays increase, it has become desirable to control a large number of separate areas of the liquid crystal cell, called pixels. In a modern display panel, more than 1,000,000 pixels may be present. At least the same number of transistors is formed on the glass substrate so that each pixel can be switched between an energized and de-energized state relative to the other pixels disposed on the substrate.
- In recent years, low temperature polysilicon (LIPS) TFT and micro-crystalline silicon TFT have been developed to offer an operation speed with a fast speed. TFT devices typically include MOS devices built with a source region, semiconductor (e.g., or called a channel region), and drain region formed on an optically transparent substrate with or without an optional dielectric layer disposed thereon. Subsequently, a gate dielectric layer is then deposited on top of the source region, semiconductor region (e.g., or called a channel region) and drain region isolate a gate electrode from the semiconductor (e.g., or called a channel region), source and drain regions. The gate electrode is formed on top of the gate dielectric layer. The performance of a TFT device dependent on the quality of the films that are deposited to form the MOS structure. The key performance elements of a MOS device are the qualities of the semiconductor layer (e.g., or called a channel layer), the gate dielectric layer, and the semiconductor layer (e.g., or called a channel layer) and gate dielectric layer interface. The quality of the semiconductor layer (e.g., or called a channel region) has received a lot of attention in recent years.
- Therefore, there is a need for forming a semiconductor layer with improved film qualities to provide a stable and reliable device performance.
- Embodiments of the invention provide a method of forming a group III-V based material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.
- In another embodiment, a method of forming a thin film transistor structure includes providing a substrate having a dielectric layer disposed thereon into a processing chamber, supplying a GaAs containing precursor disposed in a solvent to the processing chamber, evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate, and forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
- In yet another embodiment, a thin film transistor device includes a method for forming a GaAs based material in a thin film transistor structure further includes providing a substrate having a dielectric layer formed thereon, forming a semiconductor layer disposed on the dielectric layer, wherein the semiconductor layer is fabricated from a solution based GaAs based layer, and forming a source-drain metal electrode layer adjacent to the semiconductor layer.
- In still another embodiment, a method for forming a GaAs based material on a substrate includes providing a substrate into a electrohydrodynamic jet system, and printing a plurality of GaAs droplets onto the substrate, wherein the GaAs droplets are supplied from a solution based GaAs precursor disposed in the system.
- So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
FIG. 1-6 are cross sectional views of various embodiments of thin film transistor device structure;FIG. 7 is a flow chart of methods to manufacture a GaAs based solar cell according to embodiments of the invention;FIG. 8 depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD);FIG. 9 depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber; andFIG. 10 depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system.- To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
- It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
- Embodiments of the disclosure provide methods of forming group III-V based materials that may be utilized in thin film transistor devices. In one embodiment, the group III-V materials that may be utilized to form the thin film transistor devices includes a gallium arsenide (GaAs) based material. The gallium arsenide (GaAs) based material may be fabricated from a GaAs pre-engineering solution. The gallium arsenide (GaAs) based material may also be used in photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. The gallium arsenide (GaAs) based material provides high film mobility and stability and low film leakage, thereby efficiently enhancing the electrical performance of transistor devices. It is noted that the gallium arsenide (GaAs) based material may be used in other suitable devices beyond the application noted above.
FIG. 1 depicts a bottom gate structure thin film transistor (TFT)device 100 according to one embodiment of the present disclosure. Thedevice 100 includes agate electrode layer 106 disposed on asubstrate 102 covered with agate insulator layer 104. A semiconductor layer108 (e.g., or called a semiconductor active layer, an active layer or a channel layer), conventionally often made from an amorphous silicon layer or a low temperature polysilicon (LTPS) layer, is disposed over thegate insulator layer 104. A thin doped semiconductor layer of n-type or p-type layer semiconductor layer 108. After formation of the dopedsemiconductor layer metal electrode layer passivation layer 114 is then subsequently formed thereon to form the thinfilm transistor device 100. Instead of using conventional silicon containing layers for manufacturing thesemiconductor layer 108, a group III-V material may be used to form as may be used to form as thesemiconductor layer 108 and the thindoped semiconductor layer thin film transistor 100. In example of the group III-V material is a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as thesemiconductor layer 108 and the thin dopedsemiconductor layer FIGS. 7-9 .- In one embodiment, the
substrate 102 may be any one of glass substrate, plastic substrate, polymer substrate, metal substrate, singled substrate, roll-to-roll substrate, or other suitable transparent substrate suitable for forming a thin film transistor thereon. Thegate electrode layer 106 may be fabricated from any suitable metallic materials, such as indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum (Al), tungsten (W), chromium (Cr), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), molybdenum (Mo), InGaZnO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, GaN, InGaN, AlGaN or InGaAlN or combination thereof. Suitable materials for thegate insulator layer 104 may be silicon oxide (SiO2), silicon oxynitride (SiON), or silicon nitride (SiN), high-k materials, such as HfO2, or other suitable materials, or the like. The source-drainmetal electrode layer passivation layer 114 may be fabricated by dielectric materials including silicon oxide (SiO2), silicon oxynitride (SiON), or silicon nitride (SiN), suitable polymer materials, such as polymethylmethacrylate (PMMA) and the like. FIG. 2 depicts a top metal gate structure thin film transistor (TFT)device 200 according to one embodiment of the present disclosure. Thedevice 200 includes ametal gate electrode 204 disposed over a backside of asubstrate 202. Aninsulator layer 203 may be formed from an opposite side (e.g., front side) of thesubstrate 202 from wherein themetal gate electrode 204 is formed. A semiconductor layer206 (e.g., or called a semiconductor active layer, an active layer or a channel layer), conventionally often made from an amorphous silicon layer or a low temperature polysilicon (LTPS) layer, is disposed over theinsulator layer 203. Subsequently, a source-drainmetal electrode layer semiconductor layer 206 to form the thinfilm transistor device 200. Instead of using conventional silicon containing layers for manufacturing thesemiconductor layer 206, a group III-V material may be used to form as may be used to form as thesemiconductor layer 206 in thethin film transistor 200. In example of the group III-V material is a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as thesemiconductor layer 206 is believed to provide the thin film transistor200 a good device performance may be obtained. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced toFIGS. 7-9 .- The materials that may be used to form the
metal gate electrode 204, theinsulator layer 203, and the source-drainmetal electrode layer metal gate electrode 106, thegate insulator layer 104, and the source-drainmetal electrode layer FIG. 1 . FIG. 3 depicts a thin film transistor (TFT)device 300 according to one embodiment of the present disclosure. Thedevice 300 includes a semiconductor layer304 (or called a semiconductor active layer, an active layer or a channel layer) disposed over asubstrate 302. Aninsulator layer 308 may be formed over thesemiconductor layer 304 in between a patterned source-drainmetal electrode layer gate electrode layer 310 is then disposed over theinsulator layer 308 to form the thinfilm transistor device 300. Instead of using conventional silicon containing layers for manufacturing thesemiconductor layer 304, a group III-V material may be used to form as may be used to form as thesemiconductor layer 304 in thethin film transistor 300. In example of the group III-V material is a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as thesemiconductor layer 304 is believed to provide the thin film transistor300 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced toFIGS. 7-9 .- The materials that may be used to form the metal
gate electrode layer 310, theinsulator layer 308, and the source-drainmetal electrode layer metal gate electrode 106, thegate insulator layer 104, and the source-drainmetal electrode layer FIG. 1 . FIG. 4 depicts a thin film transistor (TFT)device 400 according to one embodiment of the present disclosure. Thedevice 400 includes abuffer oxide layer 404 disposed on asubstrate 402. A semiconductor layer412 (e.g., or called a semiconductor active layer, an active layer or a channel layer) is disposed between a patterned source-drainmetal electrode layer gate insulator layer 408 is then disposed over thesemiconductor layer 412 followed by a metalgate electrode layer 410. Instead of using conventional silicon containing layers for manufacturing thesemiconductor layer 412, a group III-V material may be used to form as may be used to form as thesemiconductor layer 412 in thethin film transistor 400. In example of the group III-V material is a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as thesemiconductor layer 412 is believed to provide the thin film transistor device400 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced toFIGS. 7-9 .- The materials that may be used to form the
metal gate electrode 410, thegate insulator layer 408, and the source-drainmetal electrode layer metal gate electrode 106, thegate insulator layer 104, and the source-drainmetal electrode layer FIG. 1 . FIG. 5 depicts a thin film transistor (TFT)device 500 according to one embodiment of the present disclosure. Thedevice 500 includes a metalgate electrode layer 504 is disposed over asubstrate 502. Agate insulator layer 506 is disposed over themetal gate electrode 504. A semiconductor layer508 (e.g., or called a semiconductor active layer, an active layer or a channel layer) is disposed over thegate insulator layer 506. Subsequently, apassivation layer 512 is disposed over thesemiconductor layer 508 between a patterned source-drainmetal electrode layer semiconductor layer 508, a group III-V material may be used to form as may be used to form as thesemiconductor layer 508 in thethin film transistor 500. In example of the group III-V material is a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as thesemiconductor layer 508 is believed to provide the thin film transistor device500 a good device performance. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced toFIGS. 7-9 .- The materials that may be used to form the
passivation layer 512, the metalgate electrode layer 504, thegate insulator layer 506, and the source-drainmetal electrode layer passivation layer 114, the metalgate electrode layer 106, thegate insulator layer 104, and the source-drainmetal electrode layer FIG. 1 . FIG. 6 depicts a thin film transistor (TFT)device 600 according to one embodiment of the present disclosure. Thedevice 600 includes agate insulator layer 604 disposed over thesubstrate 602. A semiconductor layer606 (e.g., or called a semiconductor active layer, an active layer or a channel layer) is disposed on thegate insulator layer 604. A patterned source-drain electrode layer semiconductor layer 606. Subsequently, apassivation layer 610 is then disposed on the patterned source-drain electrode layer semiconductor layer 606, a group III-V material may be used to form as may be used to form as thesemiconductor layer 606 in thethin film transistor 600. In example of the group III-V material is a gallium arsenide (GaAs) based material. It is believed that gallium arsenide (GaAs) based material can provide a high electron mobility and wide band gap so as to improve the transistor device performance and speed. Accordingly, using gallium arsenide (GaAs) based material as thesemiconductor layer 606 is believed to provide the thin film transistor device600 a greater mobility of electrons and good device performance may be obtained. Details regarding the manufacture of the gallium arsenide (GaAs) based material or doped gallium arsenide (GaAs) based material will be discussed below with referenced toFIGS. 7-9 .- The materials that may be used to form the
passivation layer 610, thegate insulator layer 604, and the source-drainmetal electrode layer passivation layer 114, the metalgate electrode layer 106, thegate insulator layer 104, and the source-drainmetal electrode layer FIG. 1 . - It is noted that
FIGS. 1-6 only depict exemplary embodiments of thin film transistors having semiconductor layers that may be formed from a group III-V material, such as a gallium arsenide (GaAs) based material or a doped gallium arsenide (GaAs) based material. Other thin film devices not illustrated here having semiconductor layers, doped semiconductor layers, or other suitable active or non-active layers formed therein may also suitable to be formed as group III-V material according to the methods as described below with referenced toFIGS. 7-9 . FIG. 7 depicts a flow diagram of one embodiment of aprocessing sequence 700 for forming a solution based group III-V material, such as a solution based GaAs layer utilized in a thin film transistor device, such as thesemiconductor layer doped semiconductor layer film transistor devices FIGS. 1-6 . In the embodiment wherein thesemiconductor layer doped semiconductor layer processing sequence 700 as depicted inFIG. 7 . It is noted thatFIG. 7 only depicts the process of manufacturing GaAs based layer for illustration purpose, and is not intended to limiting the invention scope or certain types of the layers that may be manufactured. It should be noted that the number and sequence of steps illustrated inFIG. 7 are not intended to limiting as to the scope of the invention described herein, since one or more steps can be added, deleted and/or reordered were appropriate without deviating from the basic scope of the invention described herein.- The
processing sequence 700 begins atstep 702 by providing a substrate, such as thesubstrate FIGS. 1-6 , configured to form thin film transistor devices thereon. In one embodiment, thesubstrate 102 may be any one of glass substrate, plastic substrate, polymer substrate, metal substrate, singled substrate, roll-to-roll substrate, transparent substrate, silicon containing substrate, such as a single crystal silicon substrate, a multicrystalline silicon substrate, glass substrate, quartz substrate, or other suitable materials or other suitable transparent substrate suitable for forming a thin film transistor thereon. The substrate may have layers previously formed thereon to readily form asemiconductor layer doped semiconductor layer - At
step 704, a GaAs deposition process is performed to deposit a GaAs layer on the substrate. The GaAs deposition process is performed by providing a pre-engineered solution based GaAs precursor to a processing chamber as a source precursor to facilitate depositing the GaAs layer as thesemiconductor layer doped semiconductor layer substrate 102. - The pre-engineered solution based GaAs precursor comprises a mixture of gallium complex and arsenic complex in solution, forming a gallium-arsenic complex in the solution. In one embodiment, the gallium-arsenic complex formed in the pre-engineered solution based GaAs precursor generally has a GaAs dimer (—GaAs—), a GaAs tetramer (—Ga2As2—), or a GaAs hexamer (—Ga3As3—) structure, as shown below.
- It is believed that GaAs dimer (—GaAs—), a GaAs tetramer (—Ga2As2—), or a GaAs hexamer (—Ga3As3—) structures are relatively stable complexes so make them as good candidates to be placed or stored in liquid solution under a relatively stable status. By utilizing this relatively stable solution based GaAs precursor, the GaAs solution may be delivered, injected, sprayed and coated onto the substrate with high uniformity and good film quality, thereby providing a reliable and repeatable GaAs layer with desired film properties and high film properties.
- The GaAs dimer, GaAs tetramer, or GaAs hexamer may have different functional groups attached thereto to form the GaAs source precursor as a stable complex in the pre-engineered solution. The GaAs complex may have a formula Rx(GaAs)yR′z, wherein x, y, and z are integers having a range between 1 and 15, which R and R′ may or may not be the same function groups or the like. The functional groups that may be attached to the Ga and As elements in the GaAs dimer, GaAs tetramer, or GaAs hexamer may include alkyl group, such as methyl (CH3—), ethyl (C2H5—), propyl (C3H7—), butyl (C4H9—), pentyl (C5H11—), and so on, isopropyl and other similar isomers, aromatic groups, such as benzal, styrene, toluene, xylene, pyridine, ethylbenzene, acetophenone, methyl benzoate, phenyl acetate, phenol, cresol, furan, and the like, alicyclic group, such as cyclopropane, cyclobutane, cyclopentane, cyclopentadiene, toluene and the like, amino group, such as NR2(R as alkyl group), —SiR3, —O—R, —S—R, —PR3, —POR3, halogens, 2,3,5,6-tetramethyl-1,4-benzoquinone or tetramethyl-p-benzoquinone, bidentate ligands, expedious ligands, amines pyranine, steric hindrance ligands and the like. In one exemplary embodiment, amino group, such as NR2(R as alkyl group) and steric hindrance ligands are selected as the functional groups attached to the GaAs dimer, GaAs tetramer, or GaAs hexamer.
- The GaAs complex requires having a high solubility and stability in solution. Accordingly, the functional groups selected to form in the GaAs complex are desired to have 1:1 stoichiometry preactive or formed in clusters. Additionally, the functional groups are also desired to be able to be low temperature decomposed into GaAs. Furthermore, the bonding energy between the functional groups and Ga element and/or between the functional groups and As element is configured to be weaker than the bonding energy comprising the Ga—As bond. By this configuration, during a depositing reaction, the bonds between the functional groups and the Ga and/or As elements can be easily broken from the GaAs solution precursor, thereby assisting the formation of the GaAs layer on the substrate surface, and leaving GaAs bonding in the complex. As the functional groups as attached are selected to be easily removed, evaporated, or pyrolyzing during deposition or at the subsequent baking or curing process, a GaAs layer with minimum impurities or contamination may be thus obtained and formed on the substrate surface.
- Suitable examples of the GaAs precursors that follows the requirements as stated above includes (NMe2)2Ga2As2(tBuH)2, Me2GaAs(NMe2)2, Me2GaAs(SiMePh2)2, Me2GaAs(SiPh3)2, Et2GaAs(SiMe2Cy)2, Me2GaAs(SiMe2Cy)2, (Me)3GaAs(NMe2)3, (Et)3GaAs(NMe2)3, (Me)4Ga2As2(tBuH)2, (Et)4Ga2As2(tBuH)2, 1:3 stoichiometry of Ga:As, such as GaAs3tBu6, or the like. The structures of the GaAs precursors include the followings:
- In one embodiment, the GaAs precursor used to form the GaAs layer on the substrate is (NMe2)2GaAstBuH. (NMe2)2GaAstBuH precursor may be synthesized by mixing gallium amide (Ga(NMe2))3with excess tert-butyl arsine (tBuAsH2) in hexane or toluene solvent or other suitable organic or inorganic solvent and stirring overnight, such as stirring over 16 hours. The process temperature may be controlled between about −40 degrees Celsius and about −90 degrees Celsius. After the mixing process, (NMe2)2GaAstBuH is obtained and may be stored in CH2Cl2solvent or toluene solvent.
- In another embodiment, the GaAs layer may be formed by using tris(dimethylamino)arsine (Me6N3As) and trimethylgallium (GaMe3) as source precursors to synthesize and pre-engineer the GaAs source precursor. The tris(dimethylamino)arsine (Me6N3As) and trimethylgallium (GaMe3) are reacted in toluene or hexane solvent to form the desired solution based GaAs containing precursor. The process temperature may be controlled between about −40 degrees Celsius and about −90 degrees Celsius.
- In yet another embodiment, the GaAs layer may be formed by using [{L}HGaAsR]nor [{L}2GaAstBuH] as a precursor, in which L is nitrogen-based donor ligand, NMe2, or hydrazines functional groups. The precursors of [{L}HGaAsR]nor [{L}2GaAstBuH] may be synthesized by a reaction of As(SiR3)3, R3SiAsH3, or H2AstBu with GaH3{L} or Ga{L}3in a hexane solution while stirring at room temperature for over 24 hours. After the reaction is completed, the [{L}HGaAsR]nor [{L}2GaAstBuH] precursor may be obtained and can be used as a source of GaAs to form the GaAs layer on the substrate when decomposed.
- The GaAs containing precursor, such as (NMe2)2GaAstBuH, [{L}HGaAsR]nor [{L}2GaAstBuH], or other suitable precursor as described above, is then supplied to a CVD chamber to deposit the GaAs layer on the substrate. In one embodiment, the solution based GaAs containing precursor is supplied in a CVD chamber to perform an aerosol assisted chemical vapor deposition (AACVD) process. An example of the AACVD chamber that may be used to practice the present invention will be further discussed below with referenced to
FIG. 8 . The precursor solution is atomized by using an aerosol generator. A carrier gas is used to promote aerosol formation. Subsequently, aerosol carrying the GaAs containing solvent precursor is transported into CVD chamber by the carrier gas and evaporated in the chamber. After entering into the CVD chamber, the precursor enters into the gas phase from the liquid phase to enable the CVD process. Subsequently, the gas phase GaAs containing precursor is then decomposed and absorbed on the substrate to form the desired GaAs layer on the substrate. If the precursor does not get full vaporization, spray pyrolysis process will take place to have the precursor become as aerosol droplets to be absorbed on the substrate and form the GaAs layer on the substrate surface. In one embodiment, during the AACVD deposition process, the substrate temperature is controlled at about 550 degrees Celsius so as to efficiently evaporate the precursor entering into the chamber. - In another embodiment, the GaAs layer may also be formed on the substrate by using aerojet, flash evaporation, laser assisted CVD, UV assisted CVD, laser reactive deposition, nanoparticles spray from solution, spray CVD, metalorganic vapour phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), or by other suitable techniques as needed. Some other wet deposition process, such as ink-jet, spin coating, meniscus coating, dip coating, electroplating, spray coating, electrospraying, screen printing or other suitable techniques may also employed to form the GaAs layer on the substrate surface. Furthermore, some vacuum techniques, such as molecular beam epitaxy (MBE), metalorganic vapour phase epitaxy (MOVPE), pulsed laser deposition (PLD), plasma enhanced chemical vapor deposition (PECVD), sputter, evaporate, magnetron sputter, chemical beam deposition, atomic layer deposition (ALD), hardware chemical vapor deposition (HWCVD), microwave plasma and some other techniques, may also used as needed.
- After deposition, the GaAs layer is formed as a semiconductor layer in a thin film transistor device disposed on the substrate. The GaAs layer as formed on the substrate may have a ratio of Ga element to As element substantially between about 1:0.8 and about 1:1.2. XRD analysis indicates that the GaAs layer as formed has a strong (111) plane peak. The XRD peak positions, at <111>, <220> and <311> planes, match with the standard peak positions for cubic GaAs. In one embodiment, the GaAs layer may have a thickness between about 0.2 μm and about 3 μm.
- In one embodiment, different dopants may be doped into the GaAs layer. Dopants may be in form of particles, powders, gel, liquid, solution or any other suitable forms, blending and mixing into the solution based GaAs pre-engineered precursor. Different dopants formed in the GaAs layer may provide different film conductivity and mobility, thereby increasing the electrical performance of the devices. In one embodiment, the dopants that may be doped into the GaAs layer include Al, Zn, Mg, In, P, Si, Se, S, C, N and the like. Suitable examples of p-type and n-type dopants may be mixed or blended into the GaAs precursor to form a doped GaAs solution based precursor, such as the p-type or n-type doped GaAs layers. Suitable examples of p-type dopants may be added into the GaAs precursor include metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), metallic magnesium dopants, cyclopentadienyl magnesium, carbon chlorine (CCl4), carbon bromide (CBr4) or the like. Suitable examples of n-type dopants include H2S, sulfur, silane (SiH4), disilane (Si2H6), H2Se, Se or the like.
- In one embodiment, the dopant concentration in the doped GaAs layer may be controlled at between about 1×1016atom/cm3and about 1×102° atom/cm3. For example, in a p-type doped GaAs layer, the p-type dopants may be doped in the GaAs layer with a dopant concentration between about 1×1017atom/cm3and about 1×1019atom/cm3. In another example, in a n-type doped GaAs layer, the n-type dopants may be doped in the GaAs layer with a dopant concentration between about 1×1018atom/cm3and about 1×1020atom/cm3.
- At
step 706, after the GaAs layer is formed on the substrate, an anneal process is performed to thermally process the GaAs layer. It is noted that different types of post treatment processes, such as quenching, baking, laser treatment, or the like, may also be performed on the GaAs layer as needed. As the precursor utilized to form the GaAs layer contains elements other than Ga and As, such as carbon, nitrogen, oxide, or other elements contained in the precursor. The thermal annealing process and/or the post treatment process performed on the deposited layer may assist in the driving out of the impurities contained in the as-deposited GaAs layer. The thermal process may also assist in the repair of defects that may be formed in the as-deposited film during the deposition process. - In one embodiment, the annealing process may be performed by any suitable annealing tool, such as furnace, rapid thermal processing (RTP) chamber, spike anneal, or laser annealing chamber, and the like. The annealing process may be performed at a temperature between about 400 degrees Celsius and about 600 degree Celsius to assist in the densification and/or crystallization of the GaAs layer formed on the substrate.
FIG. 8 depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD)chamber 800 that may be utilized to deposit a solution based GaAs layer on asubstrate 801, such as thesubstrate FIGS. 1-6 . TheAACVD chamber 800 may be used to perform a AACVD deposition process, such as the deposition process described above with referenced toFIG. 3 . It is noted that other types of deposition process, such as MOCVD, aerojet, flash evaporation, laser assisted CVD, UV assisted CVD, laser reactive deposition, nanoparticles spray from solution, spray CVD, MOVPE, HVPE, or by other suitable techniques may be used to form the GaAs layer as needed. Some other wet deposition process, such as ink-jet, spin coating, meniscus coating, dip coating, electroplating, spray coating, electrospraying, screen printing or other suitable techniques may also employed to form the GaAs based layer on the substrate surface. Furthermore, some vacuum techniques, such as MBE, MOVPE, PLD, PECVD, sputter, evaporate, magnetron sputter, chemical beam deposition, ALD, HWCVD, microwave plasma and some other techniques, may also used as needed.- The
chamber 800 includes areaction tube 822 having afirst wall 826, asecond wall 828, and areactor body 824 connecting between thefirst wall 826 and thesecond wall 828. Thefirst wall 826, thesecond wall 828, and thereactor body 824 formed in thereaction tube 822 defines aninterior processing region 818. A graphite heating block820 is disposed in thereaction tube 822 to receive the substrate disposed thereon for processing. The temperature of the substrate may be monitored by a temperature sensor (not shown) disposed in thereaction tube 822 as needed. - An
exhaust 832 is formed in thesecond wall 828 to facilitate transferring the substrate into and out of thereaction tube 822. Agas inlet port 830 is formed in thefirst wall 826 to facilitate delivering reaction gases and precursors into theinterior processing region 818 during process from a mixingchamber 816. Aliquid ampoule container 834 is attached to the mixingchamber 816 through agas delivery passageway 836. Theliquid ampoule container 834 may storeprecursors 808 to provide source materials into theinterior processing region 818 to deposit a GaAs based layer based on the substrate. The mixingchamber 816 provides a tortuous path which may extend the flow path for theGaAs precursor 808 supplied from theliquid ampoule container 834 to ensure thorough mixing. Examples of GaAs precursor may be stored in theliquid ampoule container 834 include (NMe2)2GaAstBuH, Me2GaAs(NMe2)2, Me2GaAs(SiMePh2)2, Me2GaAs(SiPh3)2, Et2GaAs(SiMe2Cy)2, Me2GaAs(SiMe2Cy)2, (Me)3GaAs(NMe2)3, (Et)3GaAs(NMe2)3, (Me)4Ga2As2(tBuH)2, (Et)4Ga2As2(tBuH)2, or the like. - In the embodiment wherein a doped GaAs based layer is desired to be formed on the
substrate 102, such as a p-type doped GaAs based layer or a n-type doped GaAs based layer to form a doped semiconductor layer, such as the dopedsemiconductor layer FIG. 1 , dopant containing materials may be blended, added or mixed with the GaAs precursor in theliquid ampoule container 834, forming a dopant containing GaAs precursor which can be readily supplied to theinterior processing region 818 for processing. As discussed above, suitable p-type dopant materials that may be added into the GaAs precursor include zinc containing materials, such as metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), or the like, magnesium containing material, such as metallic magnesium dopants, cyclopentadienyl magnesium, or the like, and carbon containing materials, such as carbon chlorine (CCl4), carbon bromide (CBr4) or the like. Suitable n-type dopant materials that may be added into the GaAs precursor include sulfur containing materials, such as H2S, sulfur, silicon containing materials such as silane (SiH4), disilane (Si2H6), and selenium containing material, such as H2Se, Se or the like. In one embodiment, the p-type dopant materials utilized to be added to the GaAs precursor is DMZ or DEZ and n-type dopant materials utilized to be added to the GaAs precursor is disilane (Si2H6). - A
gas panel 810 is coupled to theliquid ampoule container 834 to supply a carrier gas to theliquid ampoule container 834 through adelivery passageway 812. Thegas panel 810 introduces carrier gases to theliquid ampoule container 834 to inject and push theGaAs precursor 802 disposed in theliquid ampoule container 834 to the mixingchamber 816 and ultimately into theinterior processing region 818 through thegas delivery passageway 836. Examples of gases that may be supplied from thegas panel 810 include nitrogen containing gas, such as nitrogen (N2), N2O, and NO, among others, or oxygen containing gas, such as, oxygen (O2) or (O3). Inert gas, such as Ar or He, may also be used to carry theGaAs precursor 802 into theinterior processing region 818. In one exemplary embodiment described herein, the carrier gas used to inject and push theGaAs precursor 808 to theinterior processing region 818 is nitrogen (N2) gas. - The solution based
GaAs precursor 802 with/without the desired dopants disposed in theliquid ampoule container 834 is heated and vaporized by ahumidifier 804. Thehumidifier 804 may have apiezoelectric device 806 which may provide ultrasonic energy and/or heat energy to the solution basedGaAs precursor 802 disposed therein, thereby assisting heating and evaporatingGaAs precursor 802 into gas phase or in form of tiny droplets for injection into theinterior processing region 818 by the carrier gas, as shown by thearrow 814. Some liquid808, such as water or other suitable liquid, may be disposed between theliquid ampoule container 834 and the humidifier to maintain the solution basedGaAs precursor 802 within a desired temperature range. In one embodiment, thehumidifier 804 may vaporize the GaAs precursor at a temperature between about 100 degrees Celsius and about 250 degrees Celsius. FIG. 9 depicts a simplified sectional perspective view of one embodiment of a rapidthermal processing chamber 900 that may be utilized to anneal asubstrate 901, such as thesubstrate FIGS. 1-6 . Theprocessing chamber 900 includes achamber body 950 havingchamber walls 930, a bottom932, and a top934 defining aninterior volume 928. Thewalls 930 typically include at least one substrate access port (not shown) to facilitate entry and egress of thesubstrate - A
radiant heat assembly 924 is mounted to the top934 of thechamber body 950. Theradiant heat assembly 924 is utilized to heat the substrate suspended by anedge ring 910 disposed around the periphery of the substrate. Theradiant heat assembly 924 includes a plurality oflamp tubes 902 in awater jacket assembly 904. Eachtube 902 contains a reflector and a tungsten halogen lamp assembly. Thelamp tubes 902 are nested in a tight honeycomb pipe arrangement. This close-packed hexagonal arrangement oflamp tubes 902 provides radiant energy, such as an IR radiation and/or longer wavelength of UV radiation having a wavelength between about 400 nm and about 4000 nm with high-power density. In one embodiment, theradiant heat assembly 924 provides radiant energy to thermally process the substrate, such as annealing a silicon layer disposed on the substrate. Oneradiant heat assembly 924 that may be adapted to benefit from the invention is described in U.S. Pat. No. 5,487,127, issued Jan. 23, 1996 to Gronet, et al., and is hereby incorporated by reference in its entirety. - The
edge ring 910 that supports substrate is spaced above astainless steel base 918 by arotatable quartz cylinder 912 mounted on thestainless steel base 918. Theedge ring 910 may be fabricated from a hard material with a small coefficient of thermal expansion, such as silicon carbide, to prevent excessive expansion and contraction during thermal processing. Thequartz cylinder 912 is rotated between about 50 rpm and about 300 rpm during substrate processing to maximize substrate temperature uniformity by minimizing the effect of thermal asymmetries in thechamber 900 and on the substrate. In one embodiment, thecylinder 912 may be coated with silicon to render the cylinder opaque to a desired wavelength. Thestainless steel base 918 has acirculation circuit 946 allowing coolant, such as water, to circulate therethrough. The coolant circulation efficiently cools down the chamber temperature after processing. - A
reflector plate 914 is disposed below the substrate and mounted above thestainless steel base 918. An array of temperature probes944 is embedded in thereflector plate 914 throughopenings 942 defined therein. The temperature probes944 are connected topyrometers 916 through aconduit 936 that extends from the bottom side of thestainless steel base 918 to theopenings 942 in thereflector plate 914. The temperature probes944 andpyrometers 916 are used to obtain a metric indicative of temperatures of regions of the substrate proximate eachprobe 944 such that a temperature gradient of the substrate may be determined. - The
bottom side 920 of the substrate and theupper side 938 of thereflector plate 914 bound a reflectingcavity 940 therebetween. The reflectingcavity 940 enhances the effective emissivity of the substrate, thereby improving the accuracy of the temperature measurement. Acontroller 917 may receive measurements from thepyrometers 916 and output control signals toradiant heat assembly 924 for real-time modify the radiation generated in theprocessing chamber 900, thereby maintaining the substrate temperature within a desired processing range. - The
upper side 938 of thereflector plate 914 is highly reflective, and reflects thermal radiation in a target wavelength range and absorbs thermal radiation other then the target wavelength range. One or more coating or layers may be utilized to coat thereflector plate 914 on thestainless steel base 918 to provide the selective reflectivity. For example, different combination of coatings with different reflectivity and absorbability may be utilized to enable thereflector plate 914 to reflect thermal radiation at a desired wavelength back to the substrate and absorb (or less reflect) thermal radiation other than the desired wavelength. In one embodiment, thereflector plate 914 reflects the thermal wavelength between about 700 nm and about 1000 nm, and absorbs thermal wavelength below 700 nm and above 1000 nm. Onereflector plate 914 that may be adapted to benefit from the invention is described in U.S. Pat. No. 6,839,507, issued Jan. 4, 2005 to Adams, et al., and is hereby incorporated by reference in its entirety. - The thermal energy not reflected to back to the substrate is absorbed by the
reflector plate 914. The absorbed thermal energy is efficiently and rapidly removed by the coolant circulating through thestainless steel base 918 disposed below thereflector plate 914. Additionally, gas provided through holes (not shown) in thereflector plate 914 may be utilized to promote the cooling rate of thereflector plate 914 and the substrate positioned thereabove. The rapid cool down rate provided by thereflector plate 914 promotes the temperature control of the substrate, thereby efficiently providing a desired temperature processing profile. In one embodiment, thereflector plate 914 may provide a substrate cool date rate greater than about 200 degrees Celsius per second. In another embodiment, thereflector plate 914 may provide a substrate cool down rate of about 220 degrees Celsius per second. FIG. 10 depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet)printing system 1000. Electrohydrodynamic jet (E-jet) printing is a technique that uses electric fields to create fluid flow necessary to deliver ink and/or droplet to a substrate for high resolution (<30 μm). In one embodiment, the electrohydrodynamic jet (E-jet) printing is used herein to print a group III-V material, such as GaAs based droplets, on the backplanes for high performance thin film transistor (TFT) displays. The electrohydrodynamic jet (E-jet) printing utilized to print GaAs based droplets may also be used to create backplanes for OLED displays and high resolution, high frequency (3D) LCD TVs. The GaAs based droplets may use GaAs solution based precursor, as discussed above with referenced toFIG. 7 , as the source material at relatively a low temperature. The high resolution of the electrohydrodynamic jet (E-jet) printing of the GaAs based droplets may be obtained due to a combination of nozzle sizes and droplet placement. The nozzle sizes may be varied to control the size of the droplets printed onto the substrate.- In one embodiment, the electrohydrodynamic jet (E-jet)
printing system 1000 includes anink chamber 1002 and anink chamber holder 1004 utilized to hold and control theink chamber 1002 at desired positions above asubstrate 1016 disposed on a translation andtilting stage 1018. Astage heater 1020 may be attached to the translation andtilting stage 1018 to control thesubstrate 1016 at a desired temperature range. Amicropipette 1010 is coupled to an end of theink chamber 1002 to deliver the ink from theink chamber 1002 to annozzle 1022 attached to an end of aheater 1012 coupled between themicropipette 1010 and thenozzle 1022. Theheater 1012 may be a NiCr heater configured to maintain the ink delivered therethrough at a desired temperature range not to clog the delivery path. Thestage 1018 may be moved relative to the tip of thenozzle 1022. Thestage 1018 may be controlled to have a scan speed at a desired range. In addition, thestage 1018 may be controlled to move relative to thenozzle 1022 along a periphery region or center region of thesubstrate 1016 to inject ink to desired locations defined on the substrate surface. In one embodiment, thestage 1018 may be moved at a constant speed, an accelerated speed or moved other paths as desired. Any suitable translation mechanism may be used, such as a conveyor system, rack and pinion system, or an x/y actuator, a robot, or other suitable mechanism, to accurate movement of thestage 1018. - A
back pressure source 1006 is coupled to aconduit 1008 attached to theink chamber 1002 configured to apply a back pressure to thenozzle 1022. Different pressure as applied may have different amount of ink injected onto the substrate surface as needed. Furthermore, change in back pressure and voltage as applied to thenozzle 1022 may also affect the size and frequency of the ink droplets. In one embodiment, the GaAs solution based precursor, as discussed above with referenced toFIG. 7 , may be stored in theink chamber 1002 configured to be printed or injected onto the substrate as needed. In operation, a voltage power may be applied between thenozzle 1022 and the substrate to create an electric field so as to maintain and control consistent jetting conditions. In one embodiment, the printed GaAs droplets may have an average measured diameter between about 1 μm and about 10 μm. - While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (21)
1. A thin film transistor structure comprising:
a gate insulator layer disposed on a substrate;
a GaAs based layer disposed over the gate insulator layer; and
a source-drain metal electrode layer disposed adjacent to the GaAs based layer.
2. The structure ofclaim 1 , further comprising:
a doped GaAs layer disposed between the GaAs based layer and the source-drain metal electrode layer.
3. The structure ofclaim 2 , wherein the doped GaAs layer includes a p-type dopant or a n-type dopant formed therein.
4. The structure ofclaim 3 , wherein the p-type dopant is selected from a group consisting of metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), metallic magnesium dopants, cyclopentadienyl magnesium, carbon chlorine (CCl4) or carbon bromide (CBr4), and the n-type dopant is selected from a group consisting of H2S, sulfur, silane (SiH4), disilane (Si2H6), H2Se and Se.
5. The structure ofclaim 1 , wherein the GaAs based layer is fabricated from a solution based GaAs containing precursor.
6. The structure ofclaim 5 , wherein the solution based GaAs containing precursor includes a GaAs containing precursor selected from a group consisting of (NMe2)2GaAstBuH, Me2GaAs(NMe2)2, Me2GaAs(SiMePh2)2, Me2GaAs(SiPh3)2, Et2GaAs(SiMe2Cy)2, and Me2GaAs(SiMe2Cy)2.
7. The structure ofclaim 1 , further comprising:
a passivation layer disposed over the source-drain metal electrode layer.
8. The structure ofclaim 1 , wherein the gate insulator layer is fabricated from a dielectric layer selected from a group consisting of silicon oxide (SiO2), silicon oxynitride (SiON), or silicon nitride (SiN), high-k materials or HfO2.
9. A method of forming a thin film transistor structure, comprising:
providing a substrate having a dielectric layer disposed thereon into a processing chamber,
supplying a GaAs containing precursor disposed in a solvent to the processing chamber;
evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate; and
forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
10. The method ofclaim 9 , wherein the GaAs containing precursor is selected from a group consisting of (NMe2)2GaAstBuH, Me2GaAs(NMe2)2, Me2GaAs(SiMePh2)2, Me2GaAs(SiPh3)2, Et2GaAs(SiMe2Cy)2, and Me2GaAs(SiMe2CY)2.
11. The method ofclaim 9 , wherein evaporating the GaAs containing precursor solvent further comprises:
annealing the GaAs based layer formed on the substrate.
12. The method ofclaim 9 , further comprising:
forming a doped GaAs layer on the GaAs based layer prior to forming the source-drain metal electrode layer.
13. The method ofclaim 12 , wherein the doped GaAs layer includes a p-type dopant or a n-type dopant formed therein.
14. The method ofclaim 13 , wherein the p-type dopant is selected from a group consisting of metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), metallic magnesium dopants, cyclopentadienyl magnesium, carbon chlorine (CCl4) or carbon bromide (CBr4), and the n-type dopant is selected from a group consisting of H2S, sulfur, silane (SiH4), disilane (Si2H6), H2Se and Se.
15. The method ofclaim 9 , wherein the source-drain metal electrode layer is fabricated by a metallic material selected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), alloy of aluminum(Al) and cobalt (Co), composite layers including a film stack having aluminum layer (Al) sandwiched between molybdenum (Mo), alloys thereof and combination thereof.
16. A method for forming a GaAs based material in a thin film transistor structure further comprising:
providing a substrate having a dielectric layer formed thereon;
forming a semiconductor layer disposed on the dielectric layer, wherein the semiconductor layer is fabricated from a solution based GaAs based layer; and
forming a source-drain metal electrode layer adjacent to the semiconductor layer.
17. The method ofclaim 16 , further comprising:
forming a doped semiconductor layer between the semiconductor layer and the source-drain metal electrode layer.
18. The method ofclaim 16 , wherein the solution based GaAs based layer is fabricated from a GaAs containing precursor is selected from a group consisting of (NMe2)2GaAstBuH, Me2GaAs(NMe2)2, Me2GaAs(SiMePh2)2, Me2GaAs(SiPh3)2, Et2GaAs(SiMe2Cy)2, and Me2GaAs(SiMe2Cy)2.
19. The method ofclaim 17 , wherein doped GaAs layer includes a p-type dopant or a n-type dopant formed therein.
20. The method ofclaim 19 , wherein the p-type dopant is selected from a group consisting of metallic zinc dopants, dimethyl zinc (DMZ), diethyl zinc (DEZ), metallic magnesium dopants, cyclopentadienyl magnesium, carbon chlorine (CCl4) or carbon bromide (CBr4), and the n-type dopant is selected from a group consisting of H2S, sulfur, silane (SiH4), disilane (Si2H6), H2Se and Se.
21. A method for forming a GaAs based material on a substrate, comprising:
providing a substrate into a electrohydrodynamic jet system; and
printing a plurality of GaAs droplets onto the substrate, wherein the GaAs droplets are supplied from a solution based GaAs precursor disposed in the system.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/250,766US20120080753A1 (en) | 2010-10-01 | 2011-09-30 | Gallium arsenide based materials used in thin film transistor applications |
| US15/210,637US9780223B2 (en) | 2010-10-01 | 2016-07-14 | Gallium arsenide based materials used in thin film transistor applications |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US38894310P | 2010-10-01 | 2010-10-01 | |
| US201161452801P | 2011-03-15 | 2011-03-15 | |
| US201161468918P | 2011-03-29 | 2011-03-29 | |
| US13/250,766US20120080753A1 (en) | 2010-10-01 | 2011-09-30 | Gallium arsenide based materials used in thin film transistor applications |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US15/210,637DivisionUS9780223B2 (en) | 2010-10-01 | 2016-07-14 | Gallium arsenide based materials used in thin film transistor applications |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20120080753A1true US20120080753A1 (en) | 2012-04-05 |
Family
ID=45888752
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US13/250,748Expired - Fee RelatedUS8846437B2 (en) | 2010-10-01 | 2011-09-30 | High efficiency thin film transistor device with gallium arsenide layer |
| US13/250,766AbandonedUS20120080753A1 (en) | 2010-10-01 | 2011-09-30 | Gallium arsenide based materials used in thin film transistor applications |
| US15/210,637Expired - Fee RelatedUS9780223B2 (en) | 2010-10-01 | 2016-07-14 | Gallium arsenide based materials used in thin film transistor applications |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US13/250,748Expired - Fee RelatedUS8846437B2 (en) | 2010-10-01 | 2011-09-30 | High efficiency thin film transistor device with gallium arsenide layer |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US15/210,637Expired - Fee RelatedUS9780223B2 (en) | 2010-10-01 | 2016-07-14 | Gallium arsenide based materials used in thin film transistor applications |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US8846437B2 (en) |
| JP (2) | JP6080167B2 (en) |
| KR (2) | KR101892115B1 (en) |
| CN (2) | CN103189999B (en) |
| TW (2) | TWI565063B (en) |
| WO (2) | WO2012044980A2 (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110215322A1 (en)* | 2010-03-02 | 2011-09-08 | Jae-Woo Park | Thin film transistor and method of manufacturing the same |
| US20120132902A1 (en)* | 2010-11-26 | 2012-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20130337636A1 (en)* | 2012-06-14 | 2013-12-19 | Thomas Kuech | Carbon doping of gallium arsenide via hydride vapor phase epitaxy |
| US20150050753A1 (en)* | 2013-08-16 | 2015-02-19 | Applied Materials, Inc. | Accelerated relaxation of strain-relaxed epitaxial buffers by use of integrated or stand-alone thermal processing |
| US20150155368A1 (en)* | 2013-12-03 | 2015-06-04 | Intermolecular, Inc. | Amorphous Silicon Thin-Film Transistors with Reduced Electrode Contact Resistivity and Methods for Forming the Same |
| US20170154905A1 (en)* | 2015-05-08 | 2017-06-01 | Boe Technology Group Co., Ltd. | Thin film transistor and preparation method thereof, array substrate, and display panel |
| US9721976B2 (en)* | 2015-03-24 | 2017-08-01 | Boe Technology Group Co., Ltd. | Thin film transistor and fabrication method thereof, array substrate and display panel |
| US20170236940A1 (en)* | 2015-08-13 | 2017-08-17 | Boe Technology Group Co., Ltd. | Electrode layer, thin film transistor, array substrate and display apparatus having the same, and fabricating method thereof |
| US20180148588A1 (en)* | 2016-11-29 | 2018-05-31 | United Technologies Corporation | High temperature inks for electronic and aerospace applications |
| US10319586B1 (en) | 2018-01-02 | 2019-06-11 | Micron Technology, Inc. | Methods comprising an atomic layer deposition sequence |
| US10431695B2 (en) | 2017-12-20 | 2019-10-01 | Micron Technology, Inc. | Transistors comprising at lease one of GaP, GaN, and GaAs |
| US10457148B2 (en) | 2017-02-24 | 2019-10-29 | Epic Battery Inc. | Solar car |
| US10587221B2 (en) | 2017-04-03 | 2020-03-10 | Epic Battery Inc. | Modular solar battery |
| US10734527B2 (en) | 2018-02-06 | 2020-08-04 | Micron Technology, Inc. | Transistors comprising a pair of source/drain regions having a channel there-between |
| US10825816B2 (en) | 2017-12-28 | 2020-11-03 | Micron Technology, Inc. | Recessed access devices and DRAM constructions |
| US11038027B2 (en) | 2019-03-06 | 2021-06-15 | Micron Technology, Inc. | Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material |
| US11489082B2 (en) | 2019-07-30 | 2022-11-01 | Epic Battery Inc. | Durable solar panels |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9018517B2 (en)* | 2011-11-07 | 2015-04-28 | International Business Machines Corporation | Silicon heterojunction photovoltaic device with wide band gap emitter |
| TWI442587B (en)* | 2011-11-11 | 2014-06-21 | Hon Hai Prec Ind Co Ltd | Housing panel and electronic device using the same |
| WO2014052901A2 (en)* | 2012-09-29 | 2014-04-03 | Precursor Energetics, Inc. | Processes for photovoltaic absorbers with compositional gradients |
| CA2887900C (en)* | 2012-10-19 | 2021-10-12 | Georgia Tech Research Corporation | Multilayer coatings formed on aligned arrays of carbon nanotubes |
| US8853438B2 (en)* | 2012-11-05 | 2014-10-07 | Dynaloy, Llc | Formulations of solutions and processes for forming a substrate including an arsenic dopant |
| EP2954563A1 (en)* | 2013-02-07 | 2015-12-16 | First Solar, Inc | Semiconductor material surface treatment with laser |
| JP6097147B2 (en)* | 2013-05-16 | 2017-03-15 | 日本放送協会 | MIMO-OFDM receiving apparatus and measuring apparatus |
| CN105518838B (en)* | 2013-07-02 | 2019-11-26 | 雅达公司 | Heteroepitaxial layer formation using rapid thermal processing to remove lattice dislocations |
| US20160322224A1 (en) | 2013-12-30 | 2016-11-03 | Dow Global Technologies Llc | Processes for using flux agents to form polycrystalline group iii-group v compounds from single source organometallic precursors |
| CN104795292B (en) | 2014-01-20 | 2017-01-18 | 清华大学 | Electron emission device, manufacturing method thereof and display |
| CN104795294B (en) | 2014-01-20 | 2017-05-31 | 清华大学 | Electron emitting device and electron emission display device |
| CN104795291B (en) | 2014-01-20 | 2017-01-18 | 清华大学 | Electron emission device, manufacturing method thereof and display |
| CN104795293B (en) | 2014-01-20 | 2017-05-10 | 清华大学 | electron emission source |
| CN104795298B (en) | 2014-01-20 | 2017-02-22 | 清华大学 | Electron emission device and display |
| CN104795297B (en) | 2014-01-20 | 2017-04-05 | 清华大学 | Electron emitting device and electron emission display device |
| CN104795300B (en) | 2014-01-20 | 2017-01-18 | 清华大学 | Electron emission source and manufacturing method thereof |
| CN104795296B (en) | 2014-01-20 | 2017-07-07 | 清华大学 | Electron emitting device and display |
| CN104795295B (en) | 2014-01-20 | 2017-07-07 | 清华大学 | Electron emission source |
| CN104051542B (en)* | 2014-06-23 | 2016-10-05 | 上海和辉光电有限公司 | Organic light emitting display device and thin film transistor thereof |
| JP6368594B2 (en)* | 2014-09-09 | 2018-08-01 | シャープ株式会社 | Photoelectric conversion element |
| US10658222B2 (en) | 2015-01-16 | 2020-05-19 | Lam Research Corporation | Moveable edge coupling ring for edge process control during semiconductor wafer processing |
| US9583649B2 (en) | 2015-06-22 | 2017-02-28 | International Business Machines Corporation | Thin film solar cell backside contact manufacturing process |
| US10096471B2 (en)* | 2016-08-04 | 2018-10-09 | Lam Research Corporation | Partial net shape and partial near net shape silicon carbide chemical vapor deposition |
| JP7391296B2 (en)* | 2017-10-07 | 2023-12-05 | 株式会社Flosfia | Film forming method |
| CN118380371A (en) | 2017-11-21 | 2024-07-23 | 朗姆研究公司 | Bottom edge ring and middle edge ring |
| US11127572B2 (en) | 2018-08-07 | 2021-09-21 | Silfex, Inc. | L-shaped plasma confinement ring for plasma chambers |
| RU2727124C1 (en)* | 2020-02-05 | 2020-07-20 | Общество с ограниченной ответственностью "МеГа Эпитех" | Method of producing low-alloy layer of gaas by liquid-phase epitaxy |
| US11495561B2 (en)* | 2020-05-11 | 2022-11-08 | X Display Company Technology Limited | Multilayer electrical conductors for transfer printing |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4928154A (en)* | 1985-09-03 | 1990-05-22 | Daido Tokushuko Kabushiki Kaisha | Epitaxial gallium arsenide semiconductor on silicon substrate with gallium phosphide and superlattice intermediate layers |
| US6071780A (en)* | 1996-09-19 | 2000-06-06 | Fujitsu Limited | Compound semiconductor apparatus and method for manufacturing the apparatus |
| US20020145143A1 (en)* | 2001-04-05 | 2002-10-10 | Masahiro Kawasaki | Active matrix display device |
| US20040016965A1 (en)* | 2002-07-16 | 2004-01-29 | Fujitsu Quantum Devices Limited | Field-effect transistor and method of producing the same |
| US20090001504A1 (en)* | 2006-03-28 | 2009-01-01 | Michiko Takei | Method for Transferring Semiconductor Element, Method for Manufacturing Semiconductor Device, and Semiconductor Device |
| US20100096634A1 (en)* | 2008-10-17 | 2010-04-22 | Samsung Electronics Co., Ltd. | Panel structure, display device including same, and methods of manufacturing panel structure and display device |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1140032A (en)* | 1978-03-07 | 1983-01-25 | Marc M. Faktor | Growth of semiconductor compounds |
| US4594264A (en)* | 1984-11-20 | 1986-06-10 | Hughes Aircraft Company | Method for forming gallium arsenide from thin solid films of gallium-arsenic complexes |
| US4923524A (en)* | 1985-05-06 | 1990-05-08 | Chronar Corp. | Wide ranging photovoltaic laminates comprising particulate semiconductors |
| JPH02181976A (en)* | 1989-01-09 | 1990-07-16 | Daido Steel Co Ltd | solar cells |
| US4975299A (en)* | 1989-11-02 | 1990-12-04 | Eastman Kodak Company | Vapor deposition process for depositing an organo-metallic compound layer on a substrate |
| US5084128A (en)* | 1990-10-23 | 1992-01-28 | E. I. Du Pont De Nemours And Company | Low-temperature synthesis of group III-group V semiconductors |
| JP2719230B2 (en)* | 1990-11-22 | 1998-02-25 | キヤノン株式会社 | Photovoltaic element |
| JPH1092747A (en)* | 1996-09-13 | 1998-04-10 | Hamamatsu Photonics Kk | Manufacture of amorphous gaas thin film and manufacture of amorphous gaas tft |
| JP4189610B2 (en)* | 1998-05-08 | 2008-12-03 | ソニー株式会社 | Photoelectric conversion element and manufacturing method thereof |
| JP3753605B2 (en)* | 2000-11-01 | 2006-03-08 | シャープ株式会社 | Solar cell and method for manufacturing the same |
| US6839507B2 (en)* | 2002-10-07 | 2005-01-04 | Applied Materials, Inc. | Black reflector plate |
| JP2005003730A (en)* | 2003-06-09 | 2005-01-06 | Canon Inc | Image forming apparatus |
| JP2005268719A (en)* | 2004-03-22 | 2005-09-29 | Sharp Corp | Thin film solar cell |
| US7473943B2 (en)* | 2004-10-15 | 2009-01-06 | Nanosys, Inc. | Gate configuration for nanowire electronic devices |
| JP2006287070A (en)* | 2005-04-01 | 2006-10-19 | Seiko Epson Corp | Semiconductor device manufacturing method and electronic device manufacturing method |
| JP5078246B2 (en)* | 2005-09-29 | 2012-11-21 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method of semiconductor device |
| GB0522027D0 (en)* | 2005-10-28 | 2005-12-07 | Nanoco Technologies Ltd | Controlled preparation of nanoparticle materials |
| EP1892769A2 (en)* | 2006-08-25 | 2008-02-27 | General Electric Company | Single conformal junction nanowire photovoltaic devices |
| TWI312580B (en)* | 2006-09-04 | 2009-07-21 | Taiwan Tft Lcd Associatio | A thin film transistor, manufacturing method of a active layer thereof and liquid crystal display |
| US20100096004A1 (en)* | 2006-10-25 | 2010-04-22 | Unidym, Inc. | Solar cell with nanostructure electrode(s) |
| MY158347A (en)* | 2007-02-15 | 2016-09-30 | Massachusetts Inst Technology | Solar cells with textured surfaces |
| JP2009164161A (en)* | 2007-12-28 | 2009-07-23 | Panasonic Corp | Field effect transistor |
| CN101471394A (en)* | 2007-12-29 | 2009-07-01 | 中国科学院上海硅酸盐研究所 | Method for preparing optical absorption layer of copper indium gallium sulphur selenium film solar battery |
| KR20090108853A (en)* | 2008-04-14 | 2009-10-19 | 삼성전자주식회사 | Inorganic pattern forming composition and inorganic pattern forming method using the same |
| US20100012170A1 (en) | 2008-07-20 | 2010-01-21 | Varonides Argyrios C | High Efficiency Solar Cell |
- 2011
- 2011-09-30CNCN201180050221.4Apatent/CN103189999B/ennot_activeExpired - Fee Related
- 2011-09-30TWTW100135554Apatent/TWI565063B/ennot_activeIP Right Cessation
- 2011-09-30KRKR1020137011277Apatent/KR101892115B1/ennot_activeExpired - Fee Related
- 2011-09-30KRKR1020137011285Apatent/KR101875159B1/ennot_activeExpired - Fee Related
- 2011-09-30WOPCT/US2011/054306patent/WO2012044980A2/enactiveApplication Filing
- 2011-09-30USUS13/250,748patent/US8846437B2/ennot_activeExpired - Fee Related
- 2011-09-30JPJP2013531928Apatent/JP6080167B2/ennot_activeExpired - Fee Related
- 2011-09-30TWTW100135551Apatent/TWI594451B/ennot_activeIP Right Cessation
- 2011-09-30CNCN201180051105.4Apatent/CN103189991B/ennot_activeExpired - Fee Related
- 2011-09-30JPJP2013531926Apatent/JP5881714B2/ennot_activeExpired - Fee Related
- 2011-09-30USUS13/250,766patent/US20120080753A1/ennot_activeAbandoned
- 2011-09-30WOPCT/US2011/054301patent/WO2012044978A2/enactiveApplication Filing
- 2016
- 2016-07-14USUS15/210,637patent/US9780223B2/ennot_activeExpired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4928154A (en)* | 1985-09-03 | 1990-05-22 | Daido Tokushuko Kabushiki Kaisha | Epitaxial gallium arsenide semiconductor on silicon substrate with gallium phosphide and superlattice intermediate layers |
| US6071780A (en)* | 1996-09-19 | 2000-06-06 | Fujitsu Limited | Compound semiconductor apparatus and method for manufacturing the apparatus |
| US20020145143A1 (en)* | 2001-04-05 | 2002-10-10 | Masahiro Kawasaki | Active matrix display device |
| US20040016965A1 (en)* | 2002-07-16 | 2004-01-29 | Fujitsu Quantum Devices Limited | Field-effect transistor and method of producing the same |
| US20090001504A1 (en)* | 2006-03-28 | 2009-01-01 | Michiko Takei | Method for Transferring Semiconductor Element, Method for Manufacturing Semiconductor Device, and Semiconductor Device |
| US20100096634A1 (en)* | 2008-10-17 | 2010-04-22 | Samsung Electronics Co., Ltd. | Panel structure, display device including same, and methods of manufacturing panel structure and display device |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110215322A1 (en)* | 2010-03-02 | 2011-09-08 | Jae-Woo Park | Thin film transistor and method of manufacturing the same |
| US8492770B2 (en)* | 2010-03-02 | 2013-07-23 | Samsung Display Co., Ltd. | Thin film transistor and method of manufacturing the same |
| US20120132902A1 (en)* | 2010-11-26 | 2012-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US8936965B2 (en)* | 2010-11-26 | 2015-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20130337636A1 (en)* | 2012-06-14 | 2013-12-19 | Thomas Kuech | Carbon doping of gallium arsenide via hydride vapor phase epitaxy |
| US20150050753A1 (en)* | 2013-08-16 | 2015-02-19 | Applied Materials, Inc. | Accelerated relaxation of strain-relaxed epitaxial buffers by use of integrated or stand-alone thermal processing |
| US9443728B2 (en)* | 2013-08-16 | 2016-09-13 | Applied Materials, Inc. | Accelerated relaxation of strain-relaxed epitaxial buffers by use of integrated or stand-alone thermal processing |
| US20150155368A1 (en)* | 2013-12-03 | 2015-06-04 | Intermolecular, Inc. | Amorphous Silicon Thin-Film Transistors with Reduced Electrode Contact Resistivity and Methods for Forming the Same |
| US9136355B2 (en)* | 2013-12-03 | 2015-09-15 | Intermolecular, Inc. | Methods for forming amorphous silicon thin film transistors |
| US9721976B2 (en)* | 2015-03-24 | 2017-08-01 | Boe Technology Group Co., Ltd. | Thin film transistor and fabrication method thereof, array substrate and display panel |
| US20170154905A1 (en)* | 2015-05-08 | 2017-06-01 | Boe Technology Group Co., Ltd. | Thin film transistor and preparation method thereof, array substrate, and display panel |
| US20170236940A1 (en)* | 2015-08-13 | 2017-08-17 | Boe Technology Group Co., Ltd. | Electrode layer, thin film transistor, array substrate and display apparatus having the same, and fabricating method thereof |
| US10141451B2 (en)* | 2015-08-13 | 2018-11-27 | Boe Technology Group Co., Ltd. | Electrode layer, thin film transistor, array substrate and display apparatus having the same, and fabricating method thereof |
| US20180148588A1 (en)* | 2016-11-29 | 2018-05-31 | United Technologies Corporation | High temperature inks for electronic and aerospace applications |
| US10457148B2 (en) | 2017-02-24 | 2019-10-29 | Epic Battery Inc. | Solar car |
| US10587221B2 (en) | 2017-04-03 | 2020-03-10 | Epic Battery Inc. | Modular solar battery |
| US10431695B2 (en) | 2017-12-20 | 2019-10-01 | Micron Technology, Inc. | Transistors comprising at lease one of GaP, GaN, and GaAs |
| US10825816B2 (en) | 2017-12-28 | 2020-11-03 | Micron Technology, Inc. | Recessed access devices and DRAM constructions |
| US10319586B1 (en) | 2018-01-02 | 2019-06-11 | Micron Technology, Inc. | Methods comprising an atomic layer deposition sequence |
| US10734527B2 (en) | 2018-02-06 | 2020-08-04 | Micron Technology, Inc. | Transistors comprising a pair of source/drain regions having a channel there-between |
| US11038027B2 (en) | 2019-03-06 | 2021-06-15 | Micron Technology, Inc. | Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material |
| US11527620B2 (en) | 2019-03-06 | 2022-12-13 | Micron Technology, Inc. | Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material |
| US11489082B2 (en) | 2019-07-30 | 2022-11-01 | Epic Battery Inc. | Durable solar panels |
Also Published As
| Publication number | Publication date |
|---|---|
| US8846437B2 (en) | 2014-09-30 |
| US20120080092A1 (en) | 2012-04-05 |
| JP5881714B2 (en) | 2016-03-09 |
| KR20130091767A (en) | 2013-08-19 |
| KR101892115B1 (en) | 2018-08-27 |
| CN103189991B (en) | 2016-02-17 |
| CN103189991A (en) | 2013-07-03 |
| TWI594451B (en) | 2017-08-01 |
| WO2012044980A3 (en) | 2012-06-14 |
| KR20130121103A (en) | 2013-11-05 |
| KR101875159B1 (en) | 2018-07-06 |
| CN103189999A (en) | 2013-07-03 |
| WO2012044978A3 (en) | 2012-06-21 |
| US9780223B2 (en) | 2017-10-03 |
| TW201220501A (en) | 2012-05-16 |
| JP2013543659A (en) | 2013-12-05 |
| TW201222863A (en) | 2012-06-01 |
| JP6080167B2 (en) | 2017-02-15 |
| WO2012044978A2 (en) | 2012-04-05 |
| US20160322509A1 (en) | 2016-11-03 |
| WO2012044980A2 (en) | 2012-04-05 |
| CN103189999B (en) | 2015-12-02 |
| JP2014500610A (en) | 2014-01-09 |
| TWI565063B (en) | 2017-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9780223B2 (en) | Gallium arsenide based materials used in thin film transistor applications | |
| CN112400222A (en) | Apparatus and method for controlling flow of process material to a deposition chamber | |
| US8592810B2 (en) | Thin film, method of forming the same, and semiconductor light-emitting element comprising the thin film | |
| US7842588B2 (en) | Group-III metal nitride and preparation thereof | |
| CN104659054A (en) | Flexible display apparatus and manufacture method thereof | |
| US20240376601A1 (en) | Thin film formation method | |
| JP2007146292A (en) | Vapor deposition method for vapor-phase organic matter, and vapor deposition system for vapor-phase organic matter utilizing the same | |
| TWI570261B (en) | Surface treatment to improve cctba based cvd co nucleation on dielectric substrate | |
| JP6586768B2 (en) | Deposition method | |
| US8525166B2 (en) | Zinc-tin oxide thin-film transistors | |
| JP6613467B2 (en) | Method for forming silicon oxide film | |
| CN101156247A (en) | Method and apparatus for manufacturing polysilicon film using transparent substrate | |
| JP2010507924A (en) | Substrate holding structure with rapid temperature change | |
| KR100952313B1 (en) | Unit for supplying source and method for supplying source and apparatus for depositioning thin film | |
| KR20170136740A (en) | Method of manufacturing thin film transistor, dehydration appratus for performing the same, and organic light emitting display device including the thin film transistor manufactured by the same | |
| JP6704167B2 (en) | Method for forming inorganic oxide film | |
| US20150225845A1 (en) | Method for forming metal oxide thin film and device for printing metal oxide thin film | |
| US20150064483A1 (en) | Metal deposition using organic vapor phase deposition (vpd) system | |
| Choi et al. | Preparation and characterization of SiN water-vapor permeation barrier coated by aerosol-type liquid precursor delivery system equipped on a cyclic chemical vapor deposition system | |
| CN102108500A (en) | Vapor deposition apparatus and method of manufacturing an organic light emitting display apparatus by using the vapor deposition apparatus | |
| JP4762961B2 (en) | Method for depositing ZnO single crystal on plastic substrate | |
| KR101805107B1 (en) | Light emitting diode fabrication method and Light emitting device | |
| Tompa et al. | New Design and Development of MOCVD, Process and Modeling for ZnO-Based Materials |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment | Owner name:APPLIED MATERIALS, INC., CALIFORNIA Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SINGH, KAUSHAL K;VISSER, ROBERT JAN;KUMAR, BHASKAR;SIGNING DATES FROM 20111007 TO 20111011;REEL/FRAME:027384/0684 | |
| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION |