US20110321057A1 - Multithreaded physics engine with predictive load balancing - Google Patents

Abstract

A circuit arrangement and method utilize predictive load balancing to allocate the workload among hardware threads in a multithreaded physics engine. The predictive load balancing is based at least in part upon the detection of predicted future collisions between objects in a scene, such that the reallocation of respective loads of a plurality of hardware threads may be initiated prior to detection of the actual collisions, thereby increasing the likelihood that hardware threads will be optimally allocated when the actual collisions occur.

Description

FIELD OF THE INVENTION
• The invention is generally related to data processing, and in particular to graphical imaging processing and rendering and physics collision detection in connection therewith.
BACKGROUND OF THE INVENTION
• The process of rendering two-dimensional images from three-dimensional scenes is commonly referred to as image processing. As the modern computer industry evolves image processing evolves as well. One particular goal in the evolution of image processing is to make two-dimensional simulations or renditions of three-dimensional scenes as realistic as possible.
• In addition, image processing is often used in connection with modeling or simulating real world scenarios where virtual or simulated objects representing physical, real world objects interact with one another in the simulated scenes. Video games, for example, are increasingly capable of depicting more and more realistic virtual environments, be it through the flight of a golf ball, the real world performance characteristics of a race car, the flight of an aircraft or the result of an explosion in a warfare game. In other commercial and scientific applications of image processing, e.g., flight simulation, ballistics simulation, etc., accurate modeling of the interactions of objects in a virtual environment is an even greater concern.
• In many modern data processing systems, the modeling of the real world interaction of objects is handled by computer software commonly referred to as a physics engine. A physics engine attempts to simulate physical phenomena though the use of rigid body dynamics, soft body dynamics and/or fluid dynamics principles. A key component of most physics engines is a collision detection/collision response system, which seeks to detect when objects in a virtual environment collide with one another. Based upon detected collisions, dynamics simulation is typically performed to resolve the forces and motions applied to the objects subsequent to the collisions.
• While some higher precision physics engines are not constrained by time, many others, particularly those used in interactive video gaming applications, are required to operate in “real time.” Consequently, the operations performed in connection with physics calculations, e.g., collision detection, often need to be completed quickly and efficiently.
• Conventional collision detection techniques typically operate in a serial, single threaded application were each object in motion is tested against all other objects in the scene. In some instances, collision detection may utilize spatial culling to reduce the number of required collision calculations. Furthermore, objects may be modeled using level of detail (LOD) models to simplify objects down to more easily calculable shapes for the purpose of detecting when two objects come in contact. For example, many collision detection techniques use simple shapes such as spheres and other cubic volumes to represent more complex objects. More detailed bounding volumes can be devised in some applications to increase collision precision, however, doing so usually comes at the expense of more processing time and/or hardware requirements.
• With continued improvements in semiconductor technology in terms of clock speed and increased use of parallelism, the capabilities of real time physics engines will inevitably increase. At the chip level, multiple processor cores are often disposed on the same chip, functioning in much the same manner as separate processor chips, or to some extent, as completely separate computers. In addition, even within cores, parallelism is employed through the use of multiple execution units that are specialized to handle certain types of operations. Hardware-based pipelining is also employed in many instances so that certain operations that may take multiple clock cycles to perform are broken up into stages, enabling other operations to be started prior to completion of earlier operations. Multithreading is also employed to enable multiple instruction streams to be processed in parallel, enabling more overall work to performed in any given clock cycle.
• However, even with increased clock speed and parallelization, conventional collision detection techniques still present bottlenecks to performance in most conventional architectures. In particular, conventional techniques often require large numbers of random memory accesses in order to retrieve and manage objects in a scene, which has been found to cause low cache utilization and other performance related bottlenecks.
• Furthermore, distributing the workload among multiple parallel threads of execution can be problematic in many dynamic, real-time environments. In particular, the number of objects, and the distribution of those objects, within a given scene, can vary over time. Whereas at one point in time collisions between multiple objects, requiring substantial processing resources, may occur in one region of a scene, at a different time more extensive collisions, and thus, heavier processing workload, may occur in other regions of the scene.
• A need therefore continues to exist in the art for a manner of efficiently handing physics collision detection in a physics engine.
SUMMARY OF THE INVENTION
• The invention addresses these and other problems associated with the prior art by providing a circuit arrangement and method that utilize predictive load balancing to allocate the workload among hardware threads in a multithreaded physics engine. The predictive load balancing is based at least in part upon the detection of predicted future collisions between objects in a scene, such that the reallocation of respective loads of a plurality of hardware threads may be initiated prior to detection of the actual collisions, thereby increasing the likelihood that hardware threads will be optimally allocated when the actual collisions occur. Put another way, embodiments consistent with the invention look ahead one or more steps in time in an attempt to ensure that an optimal allocation of hardware threads is available when a collision does occur.
• Therefore, consistent with one aspect of the invention, load balancing is performed among a plurality of hardware threads in a multithreaded physics engine by allocating workload among the plurality of hardware threads in the multithreaded physics engine, detecting a future collision between objects in a scene, and initiating a workload reallocation among the plurality of hardware threads in response to detecting the future collision.
• These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a block diagram of exemplary automated computing machinery including an exemplary computer useful in data processing consistent with embodiments of the present invention.
• FIG. 2 is a block diagram of an exemplary NOC implemented in the computer ofFIG. 1.
• FIG. 3 is a block diagram illustrating in greater detail an exemplary implementation of a node from the NOC ofFIG. 2.
• FIG. 4 is a block diagram illustrating an exemplary implementation of an IP block from the NOC ofFIG. 2.
• FIG. 5 is a block diagram of a thread pipelined software engine suitable for implementation in the NOC ofFIG. 2.
• FIG. 6 is a block diagram of an exemplary software pipeline suitable for implementation in the thread pipelined software engine ofFIG. 5.
• FIG. 7 is a block diagram of an exemplary rendering software pipeline suitable for implementation in the thread pipelined software engine ofFIG. 5.
• FIG. 8 is a diagram of an exemplary scene for illustrating the generation of a geometry internal representation using the GIR generator ofFIG. 7.
• FIG. 9 is a block diagram of a geometry internal representation generated for the exemplary scene ofFIG. 9.
• FIG. 10 is a flowchart illustrating the program flow of a geometry placement routine executed by the GIR generator ofFIG. 7.
• FIG. 11 is a flowchart illustrating the program flow of an add geometry routine executed by the GIR generator ofFIG. 7.
• FIG. 12 is a block diagram of an exemplary implementation of the streaming geometry frontend referenced inFIG. 7.
• FIG. 13 is a block diagram of an exemplary implementation of the ray tracing backend referenced inFIG. 7.
• FIGS. 14A and 14B collectively illustrate in greater detail an implementation of the rendering software pipeline ofFIG. 7.
• FIG. 15 a diagram of an exemplary scene for illustrating collision detection in a manner consistent with the invention.
• FIG. 16 is a block diagram of an exemplary NOC suitable for implementing collision detection in a manner consistent with the invention.
• FIG. 17 is flowchart illustrating the program flow of an exemplary collision detection routine executed by a master thread in the NOC ofFIG. 16.
• FIG. 18 is flowchart illustrating the program flow of an exemplary collision detection routine executed by a slave thread in the NOC ofFIG. 16.
• FIG. 19 is a diagram of an exemplary scene for illustrating predictive load balancing in a manner consistent with the invention.
• FIG. 20 is a flowchart illustrating the program flow of an exemplary physics engine incorporating predictive load balancing in a manner consistent with the invention.
• FIG. 21 is a flowchart illustrating the program flow of the predictive load balancing routine referenced inFIG. 20.
• FIG. 22 is flowchart illustrating the program flow of an exemplary collision detection routine executed by a master thread in the NOC ofFIG. 16, and utilizing predictive load balancing consistent with the invention.
• FIG. 23 is flowchart illustrating the program flow of an exemplary collision detection routine executed by a slave thread in the NOC ofFIG. 16, and utilizing predictive load balancing consistent with the invention.
DETAILED DESCRIPTION
• Embodiments consistent with the invention implement predictive load balancing in a multithreaded physics engine to initiate an early reallocation of workload among a plurality of hardware threads based upon predicted future collisions between objects in a scene. A scene, within the context of the invention, refers to the “world” or multidimensional space within which objects are placed prior to rendering of an image frame. Typically, a scene is a three dimensional object space; however, to simplify the discussion hereinafter, many of the examples illustrate a two dimensional scene. It will be appreciated however that a scene may be any number of dimensions consistent with the invention.
• In some embodiments, a physics engine with predictive load balancing may implement physics collision detection by streaming level of detail components between hardware threads in a multithreaded circuit arrangement, e.g., as disclosed in U.S. patent application Ser. No. 12/778,390, filed May 12, 2010 and assigned to the same assignee as the present application, which is incorporated by reference herein. In such embodiments, a component loader hardware thread, operating as a master thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more collision detection threads, operating as slave hardware threads. Slave hardware threads may also stream level of detail data to other slave hardware threads, e.g., slave hardware threads arranged further down a software pipeline. Because the slave hardware threads receive level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance.
• Other variations and modifications will be apparent to one of ordinary skill in the art. Therefore, the invention is not limited to the specific implementations discussed herein.
Hardware and Software Environment
• Now turning to the drawings, wherein like numbers denote like parts throughout the several views,FIG. 1 illustrates exemplary automated computing machinery including anexemplary computer10 useful in data processing consistent with embodiments of the present invention.Computer10 ofFIG. 1 includes at least onecomputer processor12 or ‘CPU’ as well as random access memory14 (‘RAM’), which is connected through a highspeed memory bus16 andbus adapter18 toprocessor12 and to other components of thecomputer10.
• Stored inRAM14 is anapplication program20, a module of user-level computer program instructions for carrying out particular data processing tasks such as, for example, word processing, spreadsheets, database operations, video gaming, stock market simulations, atomic quantum process simulations, or other user-level applications. Also stored inRAM14 is anoperating system22. Operating systems useful in connection with embodiments of the invention include UNIX™, Linux™ Microsoft Windows XP™, AIX™, IBM's i5/OS™, and others as will occur to those of skill in the art.Operating system22 andapplication20 in the example ofFIG. 1 are shown inRAM14, but many components of such software typically are stored in non-volatile memory also, e.g., on adisk drive24.
• As will become more apparent below, embodiments consistent with the invention may be implemented within Network On Chip (NOC) integrated circuit devices, or chips, and as such,computer10 is illustrated including two exemplary NOCs: avideo adapter26 and acoprocessor28.NOC video adapter26, which may alternatively be referred to as a graphics adapter, is an example of an I/O adapter specially designed for graphic output to adisplay device30 such as a display screen or computer monitor.NOC video adapter26 is connected toprocessor12 through a highspeed video bus32,bus adapter18, and thefront side bus34, which is also a high speed bus.NOC Coprocessor28 is connected toprocessor12 throughbus adapter18, andfront side buses34 and36, which is also a high speed bus. The NOC coprocessor ofFIG. 1 may be optimized, for example, to accelerate particular data processing tasks at the behest of themain processor12.
• The exemplaryNOC video adapter26 andNOC coprocessor28 ofFIG. 1 each include a NOC, including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, the details of which will be discussed in greater detail below in connection withFIGS. 2-3. The NOC video adapter and NOC coprocessor are each optimized for programs that use parallel processing and also require fast random access to shared memory. It will be appreciated by one of ordinary skill in the art having the benefit of the instant disclosure, however, that the invention may be implemented in devices and device architectures other than NOC devices and device architectures. The invention is therefore not limited to implementation within an NOC device.
• Computer10 ofFIG. 1 includesdisk drive adapter38 coupled through anexpansion bus40 andbus adapter18 toprocessor12 and other components of thecomputer10.Disk drive adapter38 connects non-volatile data storage to thecomputer10 in the form ofdisk drive24, and may be implemented, for example, using Integrated Drive Electronics (‘IDE’) adapters, Small Computer System Interface (‘SCSI’) adapters, and others as will occur to those of skill in the art. Non-volatile computer memory also may be implemented for as an optical disk drive, electrically erasable programmable read-only memory (so-called ‘EEPROM’ or ‘Flash’ memory), RAM drives, and so on, as will occur to those of skill in the art.
• Computer10 also includes one or more input/output (‘I/O’)adapters42, which implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input fromuser input devices44 such as keyboards and mice. In addition,computer10 includes acommunications adapter46 for data communications withother computers48 and for data communications with adata communications network50. Such data communications may be carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus ('USB'), through data communications data communications networks such as IP data communications networks, and in other ways as will occur to those of skill in the art. Communications adapters implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Examples of communications adapters suitable for use incomputer10 include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications network communications, and 802.11 adapters for wireless data communications network communications.
• For further explanation,FIG. 2 sets forth a functional block diagram of anexample NOC102 according to embodiments of the present invention. The NOC inFIG. 2 is implemented on a ‘chip’100, that is, on an integrated circuit.NOC102 includes integrated processor ('IP') blocks104,routers110,memory communications controllers106, andnetwork interface controllers108 grouped into interconnected nodes. EachIP block104 is adapted to arouter110 through amemory communications controller106 and anetwork interface controller108. Each memory communications controller controls communications between an IP block and memory, and eachnetwork interface controller108 controls inter-IP block communications throughrouters110.
• InNOC102, each IP block represents a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC. The term ‘IP block’ is sometimes expanded as ‘intellectual property block,’ effectively designating an IP block as a design that is owned by a party, that is the intellectual property of a party, to be licensed to other users or designers of semiconductor circuits. In the scope of the present invention, however, there is no requirement that IP blocks be subject to any particular ownership, so the term is always expanded in this specification as ‘integrated processor block.’ IP blocks, as specified here, are reusable units of logic, cell, or chip layout design that may or may not be the subject of intellectual property. IP blocks are logic cores that can be formed as ASIC chip designs or FPGA logic designs.
• One way to describe IP blocks by analogy is that IP blocks are for NOC design what a library is for computer programming or a discrete integrated circuit component is for printed circuit board design. In NOCs consistent with embodiments of the present invention, IP blocks may be implemented as generic gate netlists, as complete special purpose or general purpose microprocessors, or in other ways as may occur to those of skill in the art. A netlist is a Boolean-algebra representation (gates, standard cells) of an IP block's logical-function, analogous to an assembly-code listing for a high-level program application. NOCs also may be implemented, for example, in synthesizable form, described in a hardware description language such as Verilog or VHDL. In addition to netlist and synthesizable implementation, NOCs also may be delivered in lower-level, physical descriptions. Analog IP block elements such as SERDES, PLL, DAC, ADC, and so on, may be distributed in a transistor-layout format such as GDSII. Digital elements of IP blocks are sometimes offered in layout format as well. It will also be appreciated that IP blocks, as well as other logic circuitry implemented consistent with the invention may be distributed in the form of computer data files, e.g., logic definition program code, that define at various levels of detail the functionality and/or layout of the circuit arrangements implementing such logic. Thus, while the invention has and hereinafter will be described in the context of circuit arrangements implemented in fully functioning integrated circuit devices, data processing systems utilizing such devices, and other tangible, physical hardware circuits, those of ordinary skill in the art having the benefit of the instant disclosure will appreciate that the invention may also be implemented within a program product, and that the invention applies equally regardless of the particular type of computer readable storage medium or computer readable signal bearing medium being used to distribute the program product. Examples of computer readable storage media include, but are not limited to, physical, recordable type media such as volatile and non-volatile memory devices, floppy disks, hard disk drives, CD-ROMs, and DVDs (among others), while examples of computer readable signal bearing media include, but are not limited to, transmission type media such as digital and analog communication links.
• EachIP block104 in the example ofFIG. 2 is adapted to arouter110 through amemory communications controller106. Each memory communication controller is an aggregation of synchronous and asynchronous logic circuitry adapted to provide data communications between an IP block and memory. Examples of such communications between IP blocks and memory include memory load instructions and memory store instructions. Thememory communications controllers106 are described in more detail below with reference toFIG. 3. EachIP block104 is also adapted to arouter110 through anetwork interface controller108, which controls communications throughrouters110 between IP blocks104. Examples of communications between IP blocks include messages carrying data and instructions for processing the data among IP blocks in parallel applications and in pipelined applications. Thenetwork interface controllers108 are also described in more detail below with reference toFIG. 3.
• Routers110, and the correspondinglinks118 therebetween, implement the network operations of the NOC. Thelinks118 may be packet structures implemented on physical, parallel wire buses connecting all the routers. That is, each link may be implemented on a wire bus wide enough to accommodate simultaneously an entire data switching packet, including all header information and payload data. If a packet structure includes 64 bytes, for example, including an eight byte header and 56 bytes of payload data, then the wire bus subtending each link is 64 bytes wide, 512 wires. In addition, each link may be bi-directional, so that if the link packet structure includes 64 bytes, the wire bus actually contains 1024 wires between each router and each of its neighbors in the network. In such an implementation, a message could include more than one packet, but each packet would fit precisely onto the width of the wire bus. In the alternative, a link may be implemented on a wire bus that is only wide enough to accommodate a portion of a packet, such that a packet would be broken up into multiple beats, e.g., so that if a link is implemented as 16 bytes in width, or128 wires, a 64 byte packet could be broken into four beats. It will be appreciated that different implementations may used different bus widths based on practical physical limits as well as desired performance characteristics. If the connection between the router and each section of wire bus is referred to as a port, then each router includes five ports, one for each of four directions of data transmission on the network and a fifth port for adapting the router to a particular IP block through a memory communications controller and a network interface controller.
• Eachmemory communications controller106 controls communications between an IP block and memory. Memory can include off-chipmain RAM112, memory114 connected directly to an IP block through amemory communications controller106, on-chip memory enabled as anIP block116, and on-chip caches. InNOC102, either of the on-chip memories114,116, for example, may be implemented as on-chip cache memory. All these forms of memory can be disposed in the same address space, physical addresses or virtual addresses, true even for the memory attached directly to an IP block. Memory addressed messages therefore can be entirely bidirectional with respect to IP blocks, because such memory can be addressed directly from any IP block anywhere on the network.Memory116 on an IP block can be addressed from that IP block or from any other IP block in the NOC. Memory114 attached directly to a memory communication controller can be addressed by the IP block that is adapted to the network by that memory communication controller—and can also be addressed from any other IP block anywhere in the NOC.
• NOC102 includes two memory management units (‘MMUs’)120,122, illustrating two alternative memory architectures for NOCs consistent with embodiments of the present invention.MMU120 is implemented within an IP block, allowing a processor within the IP block to operate in virtual memory while allowing the entire remaining architecture of the NOC to operate in a physical memory address space.MMU122 is implemented off-chip, connected to the NOC through adata communications port124. Theport124 includes the pins and other interconnections required to conduct signals between the NOC and the MMU, as well as sufficient intelligence to convert message packets from the NOC packet format to the bus format required by theexternal MMU122. The external location of the MMU means that all processors in all IP blocks of the NOC can operate in virtual memory address space, with all conversions to physical addresses of the off-chip memory handled by the off-chip MMU122.
• In addition to the two memory architectures illustrated by use of theMMUs120,122,data communications port126 illustrates a third memory architecture useful in NOCs capable of being utilized in embodiments of the present invention.Port126 provides a direct connection between anIP block104 of theNOC102 and off-chip memory112. With no MMU in the processing path, this architecture provides utilization of a physical address space by all the IP blocks of the NOC. In sharing the address space bi-directionally, all the IP blocks of the NOC can access memory in the address space by memory-addressed messages, including loads and stores, directed through the IP block connected directly to theport126. Theport126 includes the pins and other interconnections required to conduct signals between the NOC and the off-chip memory112, as well as sufficient intelligence to convert message packets from the NOC packet format to the bus format required by the off-chip memory112.
• In the example ofFIG. 2, one of the IP blocks is designated ahost interface processor128. Ahost interface processor128 provides an interface between the NOC and ahost computer10 in which the NOC may be installed and also provides data processing services to the other IP blocks on the NOC, including, for example, receiving and dispatching among the IP blocks of the NOC data processing requests from the host computer. A NOC may, for example, implement avideo graphics adapter26 or acoprocessor28 on alarger computer10 as described above with reference toFIG. 1. In the example ofFIG. 2, thehost interface processor128 is connected to the larger host computer through adata communications port130. Theport130 includes the pins and other interconnections required to conduct signals between the NOC and the host computer, as well as sufficient intelligence to convert message packets from the NOC to the bus format required by thehost computer10. In the example of the NOC coprocessor in the computer ofFIG. 1, such a port would provide data communications format translation between the link structure of theNOC coprocessor28 and the protocol required for thefront side bus36 between theNOC coprocessor28 and thebus adapter18.
• FIG. 3 next illustrates a functional block diagram illustrating in greater detail the components implemented within anIP block104,memory communications controller106,network interface controller108 androuter110 inNOC102, collectively illustrated at132.IP block104 includes acomputer processor134 and I/O functionality136. In this example, computer memory is represented by a segment of random access memory (‘RAM’)138 inIP block104. The memory, as described above with reference toFIG. 2, can occupy segments of a physical address space whose contents on each IP block are addressable and accessible from any IP block in the NOC. Theprocessors134, I/O capabilities136, andmemory138 in each IP block effectively implement the IP blocks as generally programmable microcomputers. As explained above, however, in the scope of the present invention, IP blocks generally represent reusable units of synchronous or asynchronous logic used as building blocks for data processing within a NOC. Implementing IP blocks as generally programmable microcomputers, therefore, although a common embodiment useful for purposes of explanation, is not a limitation of the present invention.
• InNOC102 ofFIG. 3, eachmemory communications controller106 includes a plurality of memory communications execution engines140. Each memory communications execution engine140 is enabled to execute memory communications instructions from anIP block104, including bidirectional memorycommunications instruction flow141,142,144 between the network and theIP block104. The memory communications instructions executed by the memory communications controller may originate, not only from the IP block adapted to a router through a particular memory communications controller, but also from anyIP block104 anywhere inNOC102. That is, any IP block in the NOC can generate a memory communications instruction and transmit that memory communications instruction through the routers of the NOC to another memory communications controller associated with another IP block for execution of that memory communications instruction. Such memory communications instructions can include, for example, translation lookaside buffer control instructions, cache control instructions, barrier instructions, and memory load and store instructions.
• Each memory communications execution engine140 is enabled to execute a complete memory communications instruction separately and in parallel with other memory communications execution engines. The memory communications execution engines implement a scalable memory transaction processor optimized for concurrent throughput of memory communications instructions.Memory communications controller106 supports multiple memory communications execution engines140 all of which run concurrently for simultaneous execution of multiple memory communications instructions. A new memory communications instruction is allocated by thememory communications controller106 to a memory communications engine140 and memory communications execution engines140 can accept multiple response events simultaneously. In this example, all of the memory communications execution engines140 are identical. Scaling the number of memory communications instructions that can be handled simultaneously by amemory communications controller106, therefore, is implemented by scaling the number of memory communications execution engines140.
• InNOC102 ofFIG. 3, eachnetwork interface controller108 is enabled to convert communications instructions from command format to network packet format for transmission among the IP blocks104 throughrouters110. The communications instructions may be formulated in command format by theIP block104 or bymemory communications controller106 and provided to thenetwork interface controller108 in command format. The command format may be a native format that conforms to architectural register files ofIP block104 andmemory communications controller106. The network packet format is typically the format required for transmission throughrouters110 of the network. Each such message is composed of one or more network packets. Examples of such communications instructions that are converted from command format to packet format in the network interface controller include memory load instructions and memory store instructions between IP blocks and memory. Such communications instructions may also include communications instructions that send messages among IP blocks carrying data and instructions for processing the data among IP blocks in parallel applications and in pipelined applications.
• InNOC102 ofFIG. 3, each IP block is enabled to send memory-address-based communications to and from memory through the IP block's memory communications controller and then also through its network interface controller to the network. A memory-address-based communications is a memory access instruction, such as a load instruction or a store instruction, that is executed by a memory communication execution engine of a memory communications controller of an IP block. Such memory-address-based communications typically originate in an IP block, formulated in command format, and handed off to a memory communications controller for execution.
• Many memory-address-based communications are executed with message traffic, because any memory to be accessed may be located anywhere in the physical memory address space, on-chip or off-chip, directly attached to any memory communications controller in the NOC, or ultimately accessed through any IP block of the NOC—regardless of which IP block originated any particular memory-address-based communication. Thus, inNOC102, all memory-address-based communications that are executed with message traffic are passed from the memory communications controller to an associated network interface controller for conversion from command format to packet format and transmission through the network in a message. In converting to packet format, the network interface controller also identifies a network address for the packet in dependence upon the memory address or addresses to be accessed by a memory-address-based communication. Memory address based messages are addressed with memory addresses. Each memory address is mapped by the network interface controllers to a network address, typically the network location of a memory communications controller responsible for some range of physical memory addresses. The network location of amemory communication controller106 is naturally also the network location of that memory communication controller's associatedrouter110,network interface controller108, andIP block104. Theinstruction conversion logic150 within each network interface controller is capable of converting memory addresses to network addresses for purposes of transmitting memory-address-based communications through routers of a NOC.
• Upon receiving message traffic fromrouters110 of the network, eachnetwork interface controller108 inspects each packet for memory instructions. Each packet containing a memory instruction is handed to thememory communications controller106 associated with the receiving network interface controller, which executes the memory instruction before sending the remaining payload of the packet to the IP block for further processing. In this way, memory contents are always prepared to support data processing by an IP block before the IP block begins execution of instructions from a message that depend upon particular memory content.
• InNOC102 ofFIG. 3, eachIP block104 is enabled to bypass itsmemory communications controller106 and send inter-IP block, network-addressedcommunications146 directly to the network through the IP block'snetwork interface controller108. Network-addressed communications are messages directed by a network address to another IP block. Such messages transmit working data in pipelined applications, multiple data for single program processing among IP blocks in a SIMD application, and so on, as will occur to those of skill in the art. Such messages are distinct from memory-address-based communications in that they are network addressed from the start, by the originating IP block which knows the network address to which the message is to be directed through routers of the NOC. Such network-addressed communications are passed by the IP block through I/O functions136 directly to the IP block's network interface controller in command format, then converted to packet format by the network interface controller and transmitted through routers of the NOC to another IP block. Such network-addressedcommunications146 are bi-directional, potentially proceeding to and from each IP block of the NOC, depending on their use in any particular application. Each network interface controller, however, is enabled to both send and receive such communications to and from an associated router, and each network interface controller is enabled to both send and receive such communications directly to and from an associated IP block, bypassing an associatedmemory communications controller106.
• Eachnetwork interface controller108 in the example ofFIG. 3 is also enabled to implement virtual channels on the network, characterizing network packets by type. Eachnetwork interface controller108 includes virtualchannel implementation logic148 that classifies each communication instruction by type and records the type of instruction in a field of the network packet format before handing off the instruction in packet form to arouter110 for transmission on the NOC. Examples of communication instruction types include inter-IP block network-address-based messages, request messages, responses to request messages, invalidate messages directed to caches; memory load and store messages; and responses to memory load messages, etc.
• Eachrouter110 in the example ofFIG. 3 includesrouting logic152, virtualchannel control logic154, and virtual channel buffers156. The routing logic typically is implemented as a network of synchronous and asynchronous logic that implements a data communications protocol stack for data communication in the network formed by therouters110,links118, and bus wires among the routers.Routing logic152 includes the functionality that readers of skill in the art might associate in off-chip networks with routing tables, routing tables in at least some embodiments being considered too slow and cumbersome for use in a NOC. Routing logic implemented as a network of synchronous and asynchronous logic can be configured to make routing decisions as fast as a single clock cycle. The routing logic in this example routes packets by selecting a port for forwarding each packet received in a router. Each packet contains a network address to which the packet is to be routed.
• In describing memory-address-based communications above, each memory address was described as mapped by network interface controllers to a network address, a network location of a memory communications controller. The network location of amemory communication controller106 is naturally also the network location of that memory communication controller's associatedrouter110,network interface controller108, andIP block104. In inter-IP block, or network-address-based communications, therefore, it is also typical for application-level data processing to view network addresses as the location of an IP block within the network formed by the routers, links, and bus wires of the NOC.FIG. 2 illustrates that one organization of such a network is a mesh of rows and columns in which each network address can be implemented, for example, as either a unique identifier for each set of associated router, IP block, memory communications controller, and network interface controller of the mesh or x, y coordinates of each such set in the mesh.
• InNOC102 ofFIG. 3, eachrouter110 implements two or more virtual communications channels, where each virtual communications channel is characterized by a communication type. Communication instruction types, and therefore virtual channel types, include those mentioned above: inter-IP block network-address-based messages, request messages, responses to request messages, invalidate messages directed to caches; memory load and store messages; and responses to memory load messages, and so on. In support of virtual channels, eachrouter110 in the example ofFIG. 3 also includes virtualchannel control logic154 and virtual channel buffers156. The virtualchannel control logic154 examines each received packet for its assigned communications type and places each packet in an outgoing virtual channel buffer for that communications type for transmission through a port to a neighboring router on the NOC.
• Eachvirtual channel buffer156 has finite storage space. When many packets are received in a short period of time, a virtual channel buffer can fill up—so that no more packets can be put in the buffer. In other protocols, packets arriving on a virtual channel whose buffer is full would be dropped. Eachvirtual channel buffer156 in this example, however, is enabled with control signals of the bus wires to advise surrounding routers through the virtual channel control logic to suspend transmission in a virtual channel, that is, suspend transmission of packets of a particular communications type. When one virtual channel is so suspended, all other virtual channels are unaffected—and can continue to operate at full capacity. The control signals are wired all the way back through each router to each router's associatednetwork interface controller108. Each network interface controller is configured to, upon receipt of such a signal, refuse to accept, from its associatedmemory communications controller106 or from its associatedIP block104, communications instructions for the suspended virtual channel. In this way, suspension of a virtual channel affects all the hardware that implements the virtual channel, all the way back up to the originating IP blocks.
• One effect of suspending packet transmissions in a virtual channel is that no packets are ever dropped. When a router encounters a situation in which a packet might be dropped in some unreliable protocol such as, for example, the Internet Protocol, the routers in the example ofFIG. 3 may suspend by their virtual channel buffers156 and their virtualchannel control logic154 all transmissions of packets in a virtual channel until buffer space is again available, eliminating any need to drop packets. The NOC ofFIG. 3, therefore, may implement highly reliable network communications protocols with an extremely thin layer of hardware.
• The example NOC ofFIG. 3 may also be configured to maintain cache coherency between both on-chip and off-chip memory caches. Each NOC can support multiple caches each of which operates against the same underlying memory address space. For example, caches may be controlled by IP blocks, by memory communications controllers, or by cache controllers external to the NOC. Either of the on-chip memories114,116 in the example ofFIG. 2 may also be implemented as an on-chip cache, and, within the scope of the present invention, cache memory can be implemented off-chip also.
• Eachrouter110 illustrated inFIG. 3 includes five ports, fourports158A-D connected throughbus wires118 to other routers and afifth port160 connecting each router to its associatedIP block104 through anetwork interface controller108 and amemory communications controller106. As can be seen from the illustrations inFIGS. 2 and 3, therouters110 and thelinks118 of theNOC102 form a mesh network with vertical and horizontal links connecting vertical and horizontal ports in each router. In the illustration ofFIG. 3, for example,ports158A,158C and160 are termed vertical ports, andports158B and158D are termed horizontal ports.
• FIG. 4 next illustrates in another manner one exemplary implementation of anIP block104 consistent with the invention, implemented as a processing element partitioned into an instruction unit (IU)162, execution unit (XU)164 and auxiliary execution unit (AXU)166. In the illustrated implementation,IU162 includes a plurality ofinstruction buffers168 that receive instructions from an L1 instruction cache (iCACHE)170. Eachinstruction buffer168 is dedicated to one of a plurality, e.g., four, symmetric multithreaded (SMT) hardware threads. An effective-to-real translation unit (iERAT)172 is coupled to iCACHE170, and is used to translate instruction fetch requests from a plurality of thread fetchsequencers174 into real addresses for retrieval of instructions from lower order memory. Each thread fetchsequencer174 is dedicated to a particular hardware thread, and is used to ensure that instructions to be executed by the associated thread is fetched into the iCACHE for dispatch to the appropriate execution unit. As also shown inFIG. 4, instructions fetched intoinstruction buffer168 may also be monitored bybranch prediction logic176, which provides hints to each thread fetchsequencer174 to minimize instruction cache misses resulting from branches in executing threads.
• IU162 also includes a dependency/issue logic block178 dedicated to each hardware thread, and configured to resolve dependencies and control the issue of instructions frominstruction buffer168 toXU164. In addition, in the illustrated embodiment, separate dependency/issue logic180 is provided inAXU166, thus enabling separate instructions to be concurrently issued by different threads toXU164 andAXU166. In an alternative embodiment,logic180 may be disposed inIU162, or may be omitted in its entirety, such thatlogic178 issues instructions toAXU166.
• XU164 is implemented as a fixed point execution unit, including a set of general purpose registers (GPR's)182 coupled to fixedpoint logic184,branch logic186 and load/store logic188. Load/store logic188 is coupled to an L1 data cache (dCACHE)190, with effective to real translation provided bydERAT logic192.XU164 may be configured to implement practically any instruction set, e.g., all or a portion of a 32b or 64b PowerPC instruction set.
• AXU166 operates as an auxiliary execution unit including dedicated dependency/issue logic180 along with one or more execution blocks194.AXU166 may include any number of execution blocks, and may implement practically any type of execution unit, e.g., a floating point unit, or one or more specialized execution units such as encryption/decryption units, coprocessors, vector processing units, graphics processing units, XML processing units, etc. In the illustrated embodiment,AXU166 includes a high speed auxiliary interface toXU164, e.g., to support direct moves between AXU architected state and XU architected state.
• Communication withIP block104 may be managed in the manner discussed above in connection withFIG. 2, vianetwork interface controller108 coupled toNOC102. Address-based communication, e.g., to access L2 cache memory, may be provided, along with message-based communication. For example, eachIP block104 may include a dedicated in box and/or out box in order to handle inter-node communications between IP blocks.
• Embodiments of the present invention may be implemented within the hardware and software environment described above in connection withFIGS. 1-4. However, it will be appreciated by one of ordinary skill in the art having the benefit of the instant disclosure that the invention may be implemented in a multitude of different environments, and that other modifications may be made to the aforementioned hardware and software embodiment without departing from the spirit and scope of the invention. As such, the invention is not limited to the particular hardware and software environment disclosed herein.
Software Pipelining
• Turning now toFIG. 5,NOC102 may be used in some embodiments to implement a software-based pipeline. In particular,FIG. 5 illustrates anexemplary processing unit200 incorporating a thread pipelinedsoftware engine202 that may be used to implement and execute one ormore software pipelines204 on top of an NOC architecture. Eachpipeline204 is typically allocated one ormore data structures206 in a sharedmemory208 to enable different stages of a pipeline to exchange data. Furthermore, an interruptmechanism210 is provided to enable stages of a pipeline to notify one another of pending work to be performed.
• One or more host interface processors (HIP's)212 are also provided inengine202 to handle the issue of work tosoftware pipelines204. One ormore push buffers214 are provided to interface eachHIP212 with asoftware application216 anddriver218, which are resident outside of the engine. In order to initiate work in a pipeline, asoftware application216 issues requests through anappropriate driver218 in the form of API calls, which then generates appropriate requests for the HIP and stores the requests in apush buffer214. TheHIP212 for the relevant pipeline pulls work requests off ofpush buffer214 and initiates processing of the request by the associated pipeline.
• In the illustrated embodiment, and as implemented on aNOC102, asoftware pipeline204 implements a function that is segmented into a set of modules or ‘stages’ of computer program instructions that cooperate with one another to carry out a series of data processing tasks in sequence. Each stage in a pipeline is composed of a flexibly configurable module of computer program instructions identified by a stage1D with each stage executing on a thread of execution on anIP block104 of aNOC102. The stages are flexibly configurable in that each stage may support multiple instances of the stage, so that a pipeline may be scaled by instantiating additional instances of a stage as needed depending on workload. Because each stage is implemented by computer program instructions executing on anIP block104 of aNOC102, each stage is capable of accessing addressed memory through amemory communications controller106. At least one stage, moreover, is capable of sending network-address based communications among other stages, where the network-address based communications maintain packet order.
• The network-address based communications, for example, may be implemented using “inboxes” in each stage that receive data and/or commands from preceding stages in the pipeline. The network-address based communications maintain packet order, and are communications of a same type which are able to flow through the same virtual channel as described above. Each packet in such communications is routed by arouter110 in the manner described above, entering and leaving a virtual channel buffer in sequence, in FIFO order, thereby maintaining strict packet order and preserving message integrity.
• Each stage implements a producer/consumer relationship with a next stage. The first stage receives work instructions and work piece data through aHIP212, carries out its designated data processing tasks on the work piece, produces output data, and sends the produced output data to the next stage in the pipeline, which consumes the produced output data from the first stage by carrying out its designated data processing tasks on the produced output data from the first stage, thereby producing output data that is subsequently sent on to a next stage in the pipeline. This sequence of operations continues to the last stage of the pipeline, which then stores its produced output data in an output data structure for eventual return through theHIP212 to the originatingapplication216.
• The arrangement of stages in a pipeline may vary in different embodiments, as well as for performing different functions in different applications.FIG. 6, for example, illustrates anexemplary software pipeline220 including a plurality ofstage instances222, also separately designated as instances A-I, each of which representing a thread of execution implemented on an IP block inNOC102. Thestage instances222 are arranged inpipeline220 into five stages, a first stage with instance A, a second stage with instances B and C, a third stage with instances D, E and F, a fourth stage with instances G and H, and a fifth stage with instance I. As can be seen fromFIG. 6, instances may have a one-to-one, a one-to-many and/or a many-to-one relationship with other instances in the pipeline. Instances may operate collectively with one another in a particular stage to perform parallel tasks and share the workload, thus improving the overall throughput of the stage in performing the task. Instances in a stage may also perform different tasks from one another to enable the parallel performance of different tasks. Instances can supply data to more than one instance, while other instances may collect data and process data from multiple instances.
• In the illustrated embodiment, each instance of each stage of a pipeline is typically implemented as an application-level module of computer program instructions executed on a separate IP block on a NOC, and each stage is assigned to a thread of execution on an IP block of a NOC. Each stage is assigned a stage1D, and each instance of a stage is assigned an identifier. HIP212 (FIG. 5) typically sets up the pipeline by configuring each stage with a desired number of instances, with the network location of each instance of each stage provided to other instances of other stages to enable each instance to send its resultant workload to the proper instance in the next stage. earlier and/or later stage3 to which an instance of stage2 is authorized to send its resultant workload. Multiple instances may be assigned to a particular stage to provide additional processing resources relative to other stages, e.g., so work flows through the pipeline as efficiently as possible, and no single stage presents a bottleneck to performance. It will also be appreciated that workload monitoring may be performed during runtime, and that instances may be dynamically added or removed from a stage as needed for balancing the load among the stages of the pipeline.
• Each stage is configured with a stage1D for each instance of a next stage, which may also include the number of instances in the next stage as well as the network location of each instance of that. Configuring a stage with IDs for instances of a next stage provides the stage with the information needed to carry out load balancing across stages. Such load balancing can be carried out, for example, by monitoring the performance of the stages and instantiating a number of instances of each stage in dependence upon the performance of one or more of the stages. Monitoring the performance of the stages can be carried out by configuring each stage to report performance statistics to a separate monitoring application that in turn is installed and running on another thread of execution on an IP block or HIP. Performance statistics can include, for example, time required to complete a data processing task, a number of data processing tasks completed within a particular time period, and so on, as will occur to those of skill in the art. Instantiating a number of instances of each stage in dependence upon the performance of one or more of the stages can be carried out by instantiating, by an HIP, a new instance of a stage when monitored performance indicates a need for a new instance.
Pipeline Rendering Architecture
• Now turning toFIG. 7, this figure illustrates an implementation ofprocessing unit200 configured to implement a pipeline rendering architecture that may be used in connection with a physics engine consistent with the invention. In particular,FIG. 7 illustrates a hybridrendering software pipeline230 incorporating astreaming geometry frontend232 interfaced with aray tracing backend234 via aGIR generator236.Streaming geometry frontend232 may be implemented, for example, as an OpenGL or DirectX compatible frontend, e.g., as is used in a number of different raster-based techniques, that streams a set of primitives for a scene.Frontend232 also may natively support the OpenGL or DirectX API's, and as such, may be accessed by anapplication216 developed for use with a raster-based rendering algorithm via API calls that are converted bydriver218 into work requests, which are sent toHIP212 viapush buffer214 to initiate implementation of those API calls byfrontend232.
• GIR generator236, in turn, processes the stream of primitives output by streaminggeometry frontend232 to dynamically generate and store a geometry internal representation (GIR)data structure238 inmemory208.GIR238 functions as an accelerated data structure (ADS), and as such is used byray tracing backend234 to render a frame of image data for a scene to aframe buffer240.GIR generator236 dynamically generates the GIR using a plurality of parallel threads of execution, or hardware threads, and as such, reduces the likelihood of GIR generation serving as a bottleneck on overall performance. In addition, if desired,backend234 is permitted to begin accessing the GIR in parallel with the GIR generator dynamically building the GIR, and prior to the GIR generator completing the GIR. As an alternative,backend234 may not operate on the GIR until after construction of the GIR is complete. As yet another alternative,frontend232 andbackend234 may operate on different frames of data, such thatfrontend232 streams primitive data toGIR generator236 to build a GIR for one frame whilebackend234 is processing the GIR for an earlier generated frame.
• So configured, streamingfrontend232,GIR generator236 andray tracing backend234 are each amenable to execution by a plurality of parallel threads of execution. Furthermore,GIR generator236 serves to adapt the output of a streaming geometry frontend, ordinarily configured for use with a raster-based backend, for use with a physical rendering backend such as a ray tracing or photon mapping backend. As such, the same API as would be used for a raster-based rendering technique may be repurposed for physical rendering, often without requiring changes to the API or to an application that makes calls to the API.
Dynamic ADS Generation
• An ADS may be used to enable a physical rendering algorithm such as a ray tracing algorithm to quickly and efficiently determine with which regions of a scene an issued ray intersects any objects within a scene to be rendered. An ADS may be implemented, for example, as a spatial index, which divides a three-dimensional scene or world into smaller volumes (smaller relative to the entire three-dimensional scene) which may or may not contain primitives. An image processing system can then use the known boundaries of these smaller volumes to determine if a ray may intersect primitives contained within the smaller volumes. If a ray does intersect a volume containing primitives, then a ray intersection test can be run using the trajectory of the ray against the known location and dimensions of the primitives contained within that volume. If a ray does not intersect a particular volume then there is no need to run ray-primitive intersection tests against the primitives contained within that volume. Furthermore, if a ray intersects a bounding volume that does not contain primitives then there is no need to run ray-primitive intersections tests against that bounding volume. Thus, by reducing the number of ray-primitive intersection tests that may be necessary, the use of a spatial index greatly increases the performance of a ray tracing image processing system. Some examples of different spatial index acceleration data structures are oct-trees, k dimensional Trees (kd-Trees), and binary space partitioning trees (BSP trees). While several different spatial index structures exist, and may be used in connection with the physical rendering techniques disclosed herein, the illustrated embodiments rely on a branch tree implemented as a base b tree split up into smaller trees of depth k.
• By way of example,FIGS. 8 and 9 illustrate a relatively simple branch tree implementation that uses axis aligned bounding volumes to partition the entire scene or space into smaller volumes. That is, the branch tree may divide a three-dimensional space encompassed by a scene through the use of splitting planes which are parallel to known axes. The splitting planes partition a larger space into smaller bounding volumes. Together the smaller bounding volumes make up the entire space in the scene. The determination to partition (divide) a larger bounding volume into two smaller bounding volumes may be made by the image processing system through the use of a branch tree construction algorithm.
• One criterion for determining when to partition a bounding volume into smaller volumes may be the number of primitives contained within the bounding volume. That is, as long as a bounding volume contains more primitives than a predetermined threshold, the tree construction algorithm may continue to divide volumes by drawing more splitting planes. Another criterion for determining when to partition a bounding volume into smaller volumes may be the amount of space contained within the bounding volume. Furthermore, a decision to continue partitioning the bounding volume may also be based on how many primitives may be intersected by the plane which creates the bounding volume.
• The partitioning of the scene may be represented, for example, by a binary tree structure made up of nodes, branches and leaves. Each internal node within the tree may represent a relatively large bounding volume, while the node may contain branches to sub-nodes which may represent two relatively smaller partitioned volumes resulting after a partitioning of the relatively large bounding volume by a splitting plane. In an axis-aligned branch tree, each internal node may contain only two branches to other nodes. The internal node may contain branches (i.e., pointers) to one or two leaf nodes. A leaf node is a node which is not further sub-divided into smaller volumes and contains pointers to primitives. An internal node may also contain branches to other internal nodes which are further sub-divided. An internal node may also contain the information needed to determine along what axis the splitting plane was drawn and where along the axis the splitting plane was drawn.
• FIG. 8, for example, illustrates an example two dimensional space to be rendered by an image processing system, whileFIG. 9 illustrates acorresponding branch tree258, comprising nodes260-268, for the primitives shown inFIG. 8. For simplicity, a two dimensional scene is used to illustrate the building of a branch tree, however branch trees may also be used to represent three-dimensional scenes. In the two dimensional illustration ofFIG. 8, for example, splitting lines are illustrated instead of splitting planes, and bounding areas are illustrated instead of bounding volumes as would be used in a three-dimensional structure. However, one skilled in the art will quickly recognize that the concepts may easily be applied to a three-dimensional scene containing objects.
• FIG. 8 illustrates a twodimensional scene250 containingprimitives252A,252B and252C to be rendered in the final image. The largest volume which represents the entire volume of the scene is encompassed by bounding volume1 (BV₁) (which is not shown separately inFIG. 8 because it encompasses the entire scene). In the corresponding branch tree this may be represented by thetop level node260, also known as the root or world node. In one embodiment, an image processing system may continue to partition bounding volumes into smaller bounding volumes when the bounding volume contains, for example, more than two primitives. As noted earlier the decision to continue partitioning a bounding volume into smaller bounding volumes may be based on many factors, however for ease of explanation in this example the decision to continue partitioning a bounding volume is based only on the number of primitives.
• Thus, for example, as can be seen inFIG. 8, BV₁may be broken into two smaller bounding volumes BV₂and BV₃by drawing a splittingplane254 along the x-axis at point X₁. This partitioning of BV₁is also reflected in the branch tree as the twonodes262 and264, corresponding to BV₂and BV₃respectively, under the internal (interior) orparent node BV₁260. The internal node representing BV₁may now store information such as, but not limited to, pointers to the two nodes beneath BV₁(e.g., BV₂and BV₃), along which axis the splitting plane was drawn (e.g., x-axis), and where along the axis the splitting plane was drawn (e.g., at point x₁).
• Bounding volume BV₃may then be broken into two smaller bounding values BV₄and BV₅by drawing a splittingplane256 along the y-axis at point Y₁. Since BV₃has been partitioned into two sub-nodes it may now be referred to as an internal node. The partitioning of BV₃is also reflected in the branch tree as the twoleaf nodes266 and268, corresponding to BV₄and BV₅, respectively. BV₄and BV₅are leaf nodes because the volumes they represent are not further divided into smaller bounding volumes. The two leaf nodes, BV₄and BV₅, are located under the internal node BV₃which represents the bounding volume which was partitioned in the branch tree.
• The internal node representing BV₃may store information such as, but not limited to, pointers to the two leaf nodes (i.e., BV₄and BV₅), along which axis the splitting plane was drawn (i.e., y-axis), and where along the axis the splitting plane was drawn (i.e., at point Y₁).
• Thus, if a traced ray is projected through a point (X, Y) in bounding volume BV₅, a ray tracing algorithm may quickly and efficiently determine what primitives need to be checked for intersection by traversing through the tree starting atnode260, determining from the X coordinate of the point that the point is in bounding volume BV₃and traversing tonode264, determining from the Y coordinate of the point that the point is in bounding volume BV₅and traversing tonode268.Node268 provides access to the primitive data forprimitives252C, and thus, the ray tracing algorithm can perform intersection tests against those primitives.
• FIGS. 10 and 11 next illustrate a branch tree generation algorithm suitable for use inGIR generator236 to generate a GIR implemented as a form of branch tree that is capable of being generated in a highly parallel manner. The herein-described branch tree generation algorithm generates a dynamically built accelerated data structure (ADS) for streaming data on a highly parallel machine, based upon a relatively building and traversal algorithm, that uses minimal memory and memory bandwidth, and that typically requires no additional information than common rendering API's such as DirectX and OpenGL currently supply.
• A branch tree generated by the herein-described embodiment is implemented as a base b tree split up into smaller trees of depth k, where each small tree may be referred to as a branch. If a leaf node in the branch is an interior node of the larger tree it will contain a pointer to another branch continuing the tree. If objects are only allowed to be placed at leaf nodes of the smaller trees there is no need to contain the upper levels of the depth k tree and the tree can therefore be looked at as a base b^ktree. In one embodiment, the branch tree is an oct-tree split up into small trees of depth 2 that allows data to be stored only at even levels, which is essentially equivalent to a base 64 tree.
• The branch tree may also be considered as an expanding grid. An initial grid of 64 voxels is made. If small enough geometry exists inside one of these voxels, another 64 voxel grid, or branch, is made inside it. The pattern is continued until a significant or maximum depth of grids/branches is reached. From the standpoint of storage, however, each branch is stored simply as 64 nodes, as shown below:

• 		struct branch{
  		node nodes[64];
  		};

• In the illustrated embodiment, the nodes of the branch are 4-byte words that either contain a pointer to geometry, list of geometry, a null value, or an indexed offset to another branch. If a node in the branch contains one or more pieces of geometry it will contain a pointer to the geometry or list of geometry. It is desirable for the address of the geometry or geometry list to be larger than the number of branches that will make the tree as the node data type may be determined by the node's unsigned integer value being larger or smaller than this threshold. If a node is empty it contains a null value. If it is an interior node it contains an offset to the branch that continues the tree beyond it. The offset is an index into a list of branches that is built during the construction process of the tree. For example, a node may have a structure such as:

• 		struct node{
  		union {
  		uint offset;
  		geometry *geo;
  		geometry_list * geo_list;
  		};
  		}

  
  while a geometry list may have a structure such as:

• 		struct geometry_list{
  		uint num_geometry;
  		geometry * geo_ptr;
  		};

• In the illustrated embodiment, the construction of the branch tree is designed to be performed dynamically and in parallel. The algorithm relies on two global variables, a pointer to the memory allocated for the tree and an integer next_offset that stores an index into this memory where a newly built branch can be stored. The index can either be shared globally or reserved memory can be split into groups to allow multiple next_offset pointers to be used. For simplicity of description, a single next_offset will be assumed; however, multiple offsets may be desirable in some embodiments to reduce memory conflicts.
• The algorithm also is provided with the maximum depth allowed by the tree. Because float numbers have a 24 bit significand, it may be desirable to enable each depth of a base 64 tree to use two bits in each direction, such that a maximum depth of max_d=12 may be used. A depth twelve base 64 branch tree has the equivalent precision to a 64¹²voxel grid.
• To initialize the tree, the next_offset is set to 65 and a branch with all empty nodes (null value) is written to the first branch (top branch) in the memory allocation. No other steps are required.
• Thereafter, each streamed geometry primitive from the streaming geometry frontend is placed into the scene, using an instance of a routine such asroutine270 ofFIG. 10. Thus, the GIR generator is configured to execute an instance of a placement routine in each of the plurality of parallel threads of execution allocated to the GIR generator to insert a plurality of primitives into the branch tree in parallel.
• The placement function receives as input a pointer to the geometry and the three dimensional mins and maxs converted from float world coordinates to integer grid coordinates. The grid coordinates assume a step size of one at the maximum depth. In addition, by using a few compares instead of masks, the tree building process can typically be performed without float to integer conversion.
• Routine270 begins inblock272 by deciding at which nodes to place the geometry primitive. This process typically involves building keys from the min and max values. The keys can be built either with compares or from floats converted to integer values. In the illustrated embodiment, a compare with integer values is used. A 6 bit key is the node index in the current branch and is built of a set of x, y and z integer values for a point. The equation for building the tree is:
• 
  node_key[0:5]={x[2*(max_—d−d):+1],y[2*(max_—d−d):+1],z[2*(max_—d−d):+1]};
• where d is the current depth of the branch and max_d is the maximum depth of the tree where the nodes are cubes of integer volume1.
• The algorithm can find all nodes relating to the geometry primitive by finding the x, y, and z components of the keys for the geometry's min and max points, and generating all possible keys between and including the min and max values. More precise methods may be used in the alternative.
• Thus, block274 initiates a FOR loop, and for each node, retrieves the node inblock276, determines whether the node is an interior node inblock278, and if not, jumps to the next branch inblock280.
• If, however, a node is determined to be a leaf node, rather than an interior node, block278 passes control to block282 to determine whether to place the geometry primitive at the current depth in the tree. Two factors may be used to make this determination. The first is what type of node it is in. If the node is an interior node then geometry exists below it and it will not be placed at that level, which is determined inblock278. The second factor is the size of the geometry primitive. In the illustrated embodiment, the geometry primitive is placed if the node width is greater than four times the magnitude of the vector from the geometry primitive's min to max.
• If the decision is made to place the geometry primitive, control passes to tag and add the geometry primitive inblock284, whereby the primitive is placed and the current iteration of routine270 is complete. If it is decided to not place the geometry primitive at the current depth, the node is expanded inblocks286,288,290 and292. Specifically, block288 recursively calls routine270 to place the geometry primitive in the new branch.Block290 determines if any other geometry exists in the node, and if so, passes control to block292 to recursively place the other geometry in the node by calling routine270 for each tagged geometry primitive in the node. Upon completion ofblock292, or if the node is otherwise empty as determined inblock290, routine270 is complete.
• Thus, in the case of the node being an empty node, a new empty branch is created at the location indicated by *next_offset. The value of *next_offset is then stored in the expanding node and is incremented. This is how the tree is expanded and built. If the node contains existing tagged geometry primitives, the geometry is buried in order to turn the current node into an interior node. The existing geometry is buried after placing the new geometry primitive as it is smaller and will go deeper than the tagged geometry. As such, routine270 ensures that all geometry gets pushed to the leaf nodes as they are expanded.Routine270 therefore dynamically expands the branch tree whenever a primitive needs to be inserted into a full branch.
• FIG. 11 illustrates anadd geometry routine300 that may be called, for example, inblock284 of routine270 (FIG. 10).Routine300 first determines what state (empty, single geometry, geometry list) the node is in usingblocks302 and304 and acts accordingly.
• If the node's value is 0, the node is empty, and as such, block302 passes control to block306 to link to the new geometry by replacing the value in the node with a pointer to the geometry primitive being placed, whereby routine300 will be complete. If the node has a non-zero value, block304 determines whether the node stores a pointer to a single geometry primitive or a list of geometry, by loading the value at the pointed to address as an unsigned integer. If this integer value is inclusively between one and the maximum number of primitives allowed (e.g., 15), the pointer is determined to be a geometry_list pointer, as the value is the num_geometry component of a geometry_list. Otherwise, the value is considered to be a single geometry primitive.
• It is important to note that float values or binary values equal to integer values of 1 through 15 are permitted. In addition, by avoiding processing of a list when only a single geometry primitive exists in a node can save a significant amount of time and memory but is only applicable if either only one type of geometry primitive exists in a scene or if the geometry primitive is provided with a type header. Otherwise some sort of list will be required for all primitives.
• Geometry lists in the illustrated embodiment have an integer num_geometry indicating how many pieces of geometry are in the list, and a list of pointers to geometry. The allocated space for the number of pointers is even to lower the number of reallocations necessary. Therefore when a new piece of geometry is added to the list, if the num_geometry value is even, new memory space is allocated. If it is not even, a pointer to the geometry is simply appended to the end of the pointer list. Num_geometry is incremented in both cases.
• As such, ifblock304 determines the node includes a single geometry primitive, control passes to block308 to make a geometry list and add a link for the new geometry primitive to the new list. Otherwise, block304 passes control to block310 to determine if the list is full. If not, block312 adds the geometry primitive to the list. If the list is full, block314 determines if there are too many primitives in the node. If not, a new list is created with two additional spaces inblock316, and the new geometry primitive is linked into the list. If the node is too full, however, block318 buries the new and existing geometry primitives by recursively calling routine270.
• Of note,routines270 and300 are capable of being used in a parallel hardware architecture, as multiple instantiations of such routines may be used to concurrently place different primitives in the same branch tree. Consequently, assuming sufficient numbers of parallel threads of execution are allocated to an ADS generator that implements such routines, the generation of an ADS may occur at the same rate as primitives are streamed from the streaming geometry frontend, and once all of the primitive data has been streamed for a scene from the streaming geometry frontend, a fully constructed ADS is almost immediately available for use by a physical rendering backend.
• Now turning toFIG. 12, as noted above, a number of streaming geometry frontends may be used consistent with the invention.FIG. 12, for example illustrates a raster-basedstreaming geometry frontend330 including agrouper332,geometry engine334 and postgeometry engine module336.Grouper332 groups data for streaming down the pipeline, whilegeometry engine334 performs object transformations and generates the geometry primitives.Module336 performs operations such as perspective divides, culling, sorting, or breaking up geometry, and the end result output ofmodule336 is a stream of geometry primitives. It will be appreciated that a wide variety of streaming geometry frontend architectures may be used consistent with the invention, and as such, the invention is not limited to the particular architecture illustrated inFIG. 12.
• FIG. 13 next illustrates a ray tracing implementation of aphysical rendering backend340 consistent with the invention.Backend340 includes a masterray management module342 that handles interfacing with the rendering front end, initiating and synchronizing all initial rays, performing performance monitoring and dynamic (or static) load balancing. One or more otherray management modules344 functions as a slave ray manager that receives rays from the master or other slaves and traverses the ADS until determining if the ray intersects with a full leaf node or not. If not, the default background color is applied. If so, the ray is sent to a rayprimitive intersect module346, which determines the intersections between rays and primitives. Acolor update module348 updates pixels in a scene based upon the intersections detected between rays and primitives. It will be appreciated that a wide variety of ray tracing backend architectures may be used consistent with the invention, and as such, the invention is not limited to the particular architecture illustrated inFIG. 13.
• Implementation of a software pipeline to implement the aforementioned hybrid rendering functionality is illustrated at400 inFIGS. 14A and 14B.FIG. 14A, in particular primarily illustrates the frontend aspects of the architecture, whileFIG. 14B primarily illustrates the backend aspects of the architecture.Software pipeline400 is implemented by a NOC resident in a graphics processor unit (GPU) coupled to a host processor (CPU) via a bus, e.g., a PCIexpress bus414.
• As shown inFIG. 14A, anapplication402 utilizes adriver404 to submit work requests to the software pipeline via apush buffer406.Application402 anddriver404 are executed on the CPU, whilepush buffer406 is resident in shared memory accessible to both the CPU and the GPU. Work requests are pulled frompush buffer406 by command processing logic, and in particular a host interface processor (HIP)408. In addition, driver state information is maintained in allocatedmemory410,412 in the CPU and GPU, respectively. The states of the push buffer head and tail pointers forpush buffer406 are maintained at416 and418 inmemory410 while the state of the tail pointer is maintained at420 inmemory420.
• HIP408 sets up the software pipeline, assigns threads of execution to stage instances in the pipeline, issues work requests to the pipeline, and monitors workflow to dynamically reallocate threads of execution to different stages of the pipeline to maximize throughput and minimize bottlenecks. In this regard,HIP408, which is itself typically implemented in an IP block from a NOC, assigns one or more IP blocks to handle each stage of the pipeline, as well as other supporting logic that may be required to manage operation of the pipeline. A thread of execution in this regard constitutes a hardware thread implemented within an IP block, it being understood that in IP blocks that support multiple hardware threads, multiple stage instances in a pipeline may be assigned to different threads in the same IP block.
• Examples of supporting logic includeDMA engines422,424, which are respectively used to DMA vertex data from avertex buffer426 and compressed texture data from atexture data buffer428. Ascratch memory430, including anindex array432,vertex buffer434 andcompressed texture data436, serves as a destination forDMA engines422,424.HIP408 sets up a set ofinboxes437 inDMA engines422,424 to receive work requests from the HIP. Oneinbox437 is provided for each DMA engine activated in the pipeline.
• An interruptmechanism441 is used insoftware pipeline400 to enable inter-node communication between logical units in the pipeline. Nodes, e.g.,HIP408 andDMA engines422,424 receive interrupts frommechanism441, and are capable of issuing interrupts to other nodes via memory mapped input/output (MMIO) requests issued to the interrupt mechanism.
• The frontend ofpipeline400 is implemented by a vertex processor including afirst unit450 configured as a grouper and asecond unit452 configured as a geometry shader, and atexture processor454.
• HIP408 initiates work in thevertex processor450,452 andtexture processor454 usinginboxes438,440. At least oneinbox438 is allocated for each unit in the vertex processor, and at least oneinbox440 is allocated for each unit intexture processor454. In addition, HIP is capable of writing data to a render context table442, vertex sort table444, primitive sort table446 and texture context table48.Vertex processor unit450 is responsive to requests fed to aninbox438, and retrieves working data fromindex array432 andvertex buffer434.Unit450 communicates withvertex processor unit452 via aninbox456 andunit452 outputs primitives to an array ofinboxes458,460.Texture processor454 receives requests from aninbox440, readstexture data436 fromscratch memory430 and outputs to atexture memory462.
• As shown inFIG. 14B, a set ofinboxes458,460 is allocated for each of a plurality ofGIR generator elements464 that collectively implement a GIR generator, enabling the frontend of the pipeline to provide primitive data for use in building aGIR472. As noted above, a plurality of parallel threads of execution, e.g. one or more perelement464, is used to generate the GIR in the manner described above.
• One or more masterray management elements466, one or moreray management elements468, one or more ray primitive intersectelements470 and one or morecolor update elements471 respectively implement a ray tracing backend. A variable number of threads of execution may be allocated for each type ofelement466,468,470,471 in order to optimize throughput through the software pipeline.Elements466,468 and470 use theGIR472 to perform ray tracing operations, whileelements470 retrieves texture data fromtexture memory462. Communication between stages of the backend is provided byinboxes474,476 and478, respectively allocated toelements468,470 and471.Color update elements471 output image data to a rendertarget480, e.g., an image buffer, which is then output via digital video outcircuit482.
• It will be appreciated that the implementation of a streaming geometry frontend and a ray tracing backend into the software pipeline elements and underlying NOC architecture would be well within the abilities of one of ordinary skill in the art having the benefit of the instant disclosure. It will also be appreciated that different numbers of elements may be used to implement each stage of the software pipeline, and that different stages may be used to implement the frontend and/or backend of the pipeline based upon the particular algorithms used thereby. Furthermore, by actively monitoring the workload of each stage of the pipeline, it may be desirable in some embodiments to dynamically change the allocation of IP blocks and threads of execution to different stages of the pipeline, thus providing optimal throughput for different types of tasks.
Multithreaded Rendering Software Pipeline for Physics Collision Detection
• As noted above, in some embodiments, a multithreaded rendering software pipeline may be used to perform physics collision detection by streaming level of detail (LOD) components for objects in a scene between a plurality of slave, collision detection threads.FIG. 15, for example, illustrates an example twodimensional scene490 to be rendered by an image processing system. It will be appreciated that a scene is typically representative of the physical world, and is thus typically defined in three dimensions. Two dimensions are illustrated inFIG. 15, however, for the sake of simplicity.
• Scene490 includes a plurality ofobjects492, and may be broken into a plurality ofspatial regions494, which may also be referred to as Bounding Volumes (BV's). As illustrated in the figure, thespatial regions494 may be differently sized and may be defined hierarchically such that some spatial regions represent regions of other spatial regions. Furthermore, spatial regions may be defined in a similar manner to the bounding volumes utilized for ray tracing, e.g., such that each spatial region may be defined so as to balance workload, with areas of a scene containing greater numbers ofobjects492 broken into smaller spatial regions to better balance workload among the hardware threads assigned to perform collision detection for such regions.
• Collision detection typically involves the detection of collisions between objects that are moving in a scene with other objects, both moving and fixed objects. Thus, as shown inFIG. 15, collision detection may be used to detect a collision between two movingobjects496,498 with one another, as well as theother objects492 in the scene.
• In some embodiments consistent with the invention, physics collision detection is implemented using a plurality of hardware threads of execution that stream level of detail components between one another to detect collisions between objects in a scene. As shown inFIG. 16, for example, physics collision detection may be implemented in acircuit arrangement500 including aNOC502 coupled to amemory subsystem504, both of which may be integrated onto the same integrated circuit, or alternatively implemented on separate integrated circuits.NOC502 may include IP blocks506 coupled to one another via anetwork508, which may include the networking logic discussed above in connection withNOC102 ofFIG. 2.
• As noted above, various subsets of IP blocks506 may be allocated to different functionality, and in connection with physics collision detection one or more IP blocks may host a physics engine comprising a master, orcomponent loader thread510, which is used to retrieve level of detail data for an object frommemory504 and stream the data to one or morecollision detection threads512, operating as slave hardware threads and resident on one or more other IP blocks506. Slave hardware threads may also stream level of detail data to other slave hardware threads, e.g., slave hardware threads arranged further down a software pipeline.
• Because the slave hardware threads receive level of detail data from the master thread, typically the slave hardware threads are not required to load the data frommemory subsystem504, thereby reducing memory bandwidth requirements, lowering communication costs, and accelerating performance. As such, it may be desirable to physically locatemaster thread510 on anIP block506 that is proximate to memory504 (i.e., with minimal network latency), as well as to locateslave threads512 onIP blocks506 proximate tomaster thread510 as well as to one another, again to minimize network latency when passing data from thread to thread.
• Physics collision detection may also be implemented in a software pipeline similar to that described above in connection withFIG. 5, and as illustrated by the arrows inFIG. 16, level of detail data may be streamed frommaster thread510 toslave threads512, and with the results of the collision detection streamed from thelast slave thread512 back tomaster thread510, all vianetwork508. A HIP (not shown inFIG. 16) may be used to manage the work passed to the master and slave threads, similar to the manner in which a HIP manages work in connection with rendering. Each master and slave thread may implement a stage of the pipeline, although it will be appreciated that in some embodiments, multiple hardware threads may implement a stage, and in other embodiments, one hardware thread may implement multiple stages.
• Moreover, the arrangement of threads and assignment of same to spatial regions to perform collision detection may be similar in many respects to the manner in which threads are arranged in connection with ray tracing as described above. As such, it may also be desirable to utilize an accelerated data structure as described above to store the objects in a scene for the purposes of performing collision detection consistent with the invention.
• FIG. 17 next illustrates anexemplary routine520 executed by a master thread.Routine520 executes for each time interval for which collision detection is to be performed, which may or may not be the same time interval between image frames depending upon the accuracy required in connection with collision detection.Routine520 begins inblock522 by initiating a FOR loop to process each moving object in the scene. For each such object, block524 determines first whether any level of detail component has already been created for the object. If not, a suitable level of detail component is created inblock526. As noted above, creation of a level of detail component may involve creating a component of varying complexity based upon factors such as system resources and desired accuracy. The simpler the level of detail component, and less processor intensive level of detail calculations are required, the less accuracy is typically obtained. Therefore, when available system resources are greater and accuracy is desired, more complex level of detail components may be created in some embodiments.
• Once created, the level of detail component is streamed to one or more slave threads, along with the “sweep” of the object, inblock528. Also, if it is determined inblock524 that a level of detail component already exists for the object, block526 is bypassed, and block524 passes control directly to block526. In the illustrated embodiment, the sweep of an object represents the movement of the object from a starting position to an ending position across the current interval. Thus, the sweep may be represented by a vector and starting and ending voxels representing the direction and distance an object moves over a given interval.
• Once the data for an object is streamed inblock528, control returns to block522 to process additional objects. Once all objects have been processed, block522 passes control to block530 to await the collision data generated by the slave threads, and process accordingly when it is received. For example, the slave threads may return data indicating (1) what objects have collided, and (2) when those collisions occurred in the interval.Routine520 is then complete.
• FIG. 18 next illustrates anexemplary routine540 executed by a slave thread during collision detection.Routine540 begins inblock542 by receiving the stream data from the prior stage in the pipeline (master or slave).Block544 then determines whether the object sweep intersects the region to which the thread is assigned. If not, control passes to block546 to stream the level of detail component, object sweep and any collision data generated by prior slave threads to one or more subsequent slave threads in the pipeline, or alternatively, if this is the last slave thread in the pipeline, back to the master thread for further processing.Routine540 is then complete.
• If the object sweep does intersect the region assigned to the thread, block544 passes control to block548 to determine whether the time at which the intersection occurs (e.g., relative to the time interval) is earlier than a marked collision detected by a prior slave thread. If not, any intersection occurring in the region would only occur after another collision, so there is no reason to perform further collision detection in this thread. Control therefore passes to block546.
• Otherwise, control passes to block550 to perform deep collision detection to determine whether any objects (moving or static) are in the region that intersect with the object in question. Control then passes to block552 to determine whether a collision was detected. If not, control passes to block546. If, however, a collision is detected, control passes to block556 to update the collision data to indicate the time and the object with which the object in question has collided. Control then passes to block546 to stream the updated collision data, along with the level of detail component and object sweep, to one or more slave threads, or alternatively, back to the master thread with the results of collision detection.
• Implementation of a physics collision detection software pipeline in the NOC architecture described herein, e.g., as illustrated inFIGS. 14A-14B, would be within the abilities of one of ordinary skill in the art having the benefit of the instant disclosure. In addition, it will be appreciated that additional routines, e.g., to assign threads to spatial regions, to load level of detail components for static objects in a scene, to load balance threads for optimal performance, etc., may also be utilized in embodiments consistent with the invention.
Physics Engine with Predictive Load Balancing
• As noted above, in some embodiments of the invention, it may also be desirable to utilize predictive load balancing to better allocate the workload among hardware threads in a multithreaded physics engine.
• The predictive load balancing is based, at least in part upon the movement of objects in a scene, and more particularly, upon the detection of predicted future collisions between the objects in a scene, i.e., collisions that have not yet occurred during the current time interval or step, but that are likely to occur in an upcoming time interval or step. Furthermore, while predictive load balancing may be performed in some embodiments any time a future collision is detected, it may be desirable in other embodiments to perform predictive load balancing only in circumstances where the collision is expected to have a substantial effect on hardware thread workloads.
• FIG. 19, for example, illustrates anexemplary scene600 in which a projectile602 is moving through the scene toward awall604 containing a plurality ofbricks606. The current position of projectile602 at a current point in time is illustrated by line t₀. The direction of movement forprojectile602 is illustrated byvector608, and the expected positions of projectile602 in three subsequent points in time are illustrated by lines t₁, t₂, and t₃. Also illustrated is a predictedcollision610 betweenprojectile602 andwall604 at time t₃.
• Assuming for the purposes of this example thatwall604, and thus its component bricks, are fixed in the scene, it would not be unreasonable to expect that the workload of any hardware threads allocated to perform either collision detection or impulse propagation would not be particularly great, and as such, the number of hardware threads allocated to theregion encompassing wall604 may be desirably low.
• On the other hand, a realistic simulation of the collision of projectile602 withwall604 may involve substantially greater processing overhead, as impulses and collisions betweenmultiple bricks606 would likely occur. Keeping the workload allocation static therefore would likely overburden the threads allocated to the region encompassing the wall and lead to decreased performance. Moreover, reallocating the workload upon detection of the collision may improve performance; however, there is typically an overhead associated with reallocating workloads, as data necessary for performing the work previously allocated to certain threads typically must be transferred to new threads in order for those new threads to perform the work.
• Embodiments consistent with the invention therefore attempt to predict the occurrence of future collisions and initiate a reallocation of workload among hardware threads prior to the actual collisions, such that some, if not all, of the overhead associated with the reallocation is incurred prior to the detecting current collisions corresponding to the detected future collisions, and such that an optimal allocation of threads is available once the collisions do occur.
• It will be appreciated that, by predictively initiating a reallocation of hardware threads, the reallocation desirably, but not necessarily, will be complete when a predicted collision ultimately occurs. Even in instances where the reallocation does not complete, however, the reallocation will typically complete earlier than if the reallocation was initiated in response to a detected collision. It will also be appreciated that, in some instances, a predictive load balancing operation may result in a temporary sub-optimal allocation of work between hardware threads until a predicted collision is finally detected, in contrast with many load balancing algorithms that attempt to create optimal allocations of resources based upon current workload requirements.
• Now turning toFIG. 20, this figure illustrates ahigh level routine620 for a physics engine incorporating predictive load balancing consistent with the invention. A physics engine, in this context, may be considered any software configured to perform physics-related calculations, and as such, the invention applies to any physics-related calculation software irrespective of whether that software is considered to be a distinct “engine.” In this embodiment, the physics engine is a multithreaded physics engine in which multiple hardware threads, disposed, for example, in one or more processing cores, and in one or more integrated circuit chips, share the workload of the physics engine.
• A typical physics engine at a high level executes a loop that sequences between processing movements of objects over a given time interval or step (block622), detecting collisions (block624), and propagating impulses based upon any detected collisions (block626). In the illustrated embodiment, however, an additional step of performing predictive load balancing is preformed inblock628, typically after collision detection and before impulse propagation. It will be appreciated that predictive load balancing may be performed at different points inroutine620, or may be considered to be incorporated into one of blocks622-626, in other embodiments of the invention.
• A pool of hardware threads (not shown) may be allocated to handle various functions in the physics engine. For example, separate pools of threads may be utilized to handle the movement processing, collision detection and impulse propagation functions of the physics engine. One or more master threads may also be used to coordinate the activities of these various pools of threads. In alternative embodiments, individuals threads may handle multiple functions among those performed inblocks622,624 and626. These threads are typically allocated in a manner that attempts to evenly distribute the workload among the threads, e.g., by assigning threads to particular regions of a scene, or assigning threads to particular collections of objects.
• In the illustrated embodiment, step622 of routine620 processes movement by calculating, for each object in a scene, an object sweep over a plurality of time intervals.Step624, as in a conventional physics engine, detects “current” collisions at the first time interval or step, representing the movement that has occurred in the scene during the current time interval. In addition,step624 also attempts to detect “future” collisions, representing intersections of object sweeps projected over multiple time intervals, i.e., beyond the first time interval.
• Based upon these future collisions, and illustrated in greater detail by predictive load balancing routine630 ofFIG. 21, hardware threads may be predictively reallocated. In particular, routine630 begins inblock632 by determining, based upon the analysis performed incollision detection step624, whether any future collisions have been predicted. If not, no load balancing is required, and routine630 is complete.
• On the other hand, if any future collisions are detected/predicted, control passes to block634 to analyze the characteristics of each future collision to determine whether load balancing is required. Based upon this analysis, block636 determines whether rebalancing of the load is required, and if so, passes control to block638 to rebalance the load (i.e., reallocate the hardware threads), whereby routine630 is complete. Otherwise, block638 is bypassed, and routine630 terminates.
• The analysis of whether rebalancing is required for a future detected collision may vary in different embodiments. Two factors that may be considered, for example, include the number of objects potentially involved in the collisions, and the properties of the objects potentially involved in the collisions. As to the number of objects involved, as discussed above in connection withFIG. 19, the collision of a projectile with a brick wall may involve the interaction of a large number of bricks as the wall deforms and ultimately explodes. Likewise, when objects are complex and involve numerous graphical primitives (which themselves may be considered to be objects) that may be involved in collisions, more involved processing may be required to handle these objects.
• As to the object properties, the simulated physical nature of the objects involved may necessitate greater or lesser processing by hardware threads assigned to such objects. For example, a rubber ball bouncing harmlessly off of a wall, which does not cause the bricks of the wall to become dislodged, would likely not require substantial additional processing allocation. Likewise, two rigid objects colliding with one another with insufficient force to break them apart would not require additional processing allocation. In contrast. an energetic collision between brittle and/or complex objects would likely result in (at least during the duration of the collision) substantial additional processing requirements in order to manage the collisions and/or impulse propagation associated with such objects. Therefore, object properties such as rigidity, deformability, elasticity, speed, mass, spring constants, object complexity, etc., may be considered when determining whether reallocation is desirable for a particular detected future collision.
• The reallocation of hardware threads during predictive load balancing may occur in a number of manners consistent with the invention. For example, in embodiments where collision detection and impulse propagation are performed by different pools of threads, predictive load balancing may be performed for threads performing collision detection, for threads performing impulse propagation, or for both.
• In addition, while predictive load balancing may be implemented in other multithreaded physics engine designs based upon other hardware architectures, one exemplary implementation of predictive load balancing may be for the purpose of load balancing slave collision detection threads in a NOC such asNOC500 illustrated inFIG. 16 and described above, and using a streaming, multithreaded software pipeline architecture that streams level of detail components from a master, component loader hardware thread to a plurality of slave collision detection threads.FIGS. 22 and 23, for example, illustratecollision detection routines640,660 respectively executed by master and slave threads, and similar toroutines520,540 illustrated inFIGS. 17 and 18.
• Routine640 ofFIG. 22 executes for each time interval for which collision detection is to be performed, and begins inblock642 by initiating a FOR loop to process each moving object in the scene. For each such object, block644 determines first whether any level of detail component has already been created for the object. If not, a suitable level of detail component is created inblock646. Once created, the level of detail component is streamed to one or more slave threads, along with the “sweep” of the object, inblock648. Also, if it is determined inblock644 that a level of detail component already exists for the object, block646 is bypassed, and block644 passes control directly to block648. Unlike routine520, where the sweep of an object represents the movement of the object from a starting position to an ending position across the current interval, however, the object sweep calculated and streamed inblock648 of routine640 represents the movement of the object from a starting position to an ending position across a plurality of time intervals, so that both current and future collisions may be detected.
• Once the data for an object is streamed inblock648, control returns to block642 to process additional objects. Once all objects have been processed, block642 passes control to block650 to await the collision data generated by the slave threads, and process accordingly when it is received. As withroutine520 ofFIG. 17, the slave threads may return data indicating (1) what objects have collided, and (2) when those collisions occurred in the interval. Inblock650, however, the slave threads may also return a request or recommendation for a rebalancing of load among the slave threads.
• As such, block650 passes control to block652 to determine whether a rebalancing has been recommended by any slave thread. If not, no rebalancing is performed, and routine640 is complete. If, however, a rebalancing is recommended, rebalancing is performed inblock654 to reallocate the slave threads, e.g., to provide additional threads to handle predicted future collisions in particular regions of a scene.
• FIG. 23 next illustrates anexemplary routine660 executed by a slave thread during collision detection.Routine660 begins inblock662 by receiving the stream data from the prior stage in the pipeline (master or slave).Block664 then determines whether the object sweep intersects the region to which the thread is assigned. If not, control passes to block666 to stream the level of detail component, object sweep and any collision data generated by prior slave threads to one or more subsequent slave threads in the pipeline, or alternatively, if this is the last slave thread in the pipeline, back to the master thread for further processing.Routine660 is then complete.
• If the object sweep does intersect the region assigned to the thread, block664 passes control to block668 to determine whether the time at which the intersection occurs (e.g., relative to the time interval) is earlier than a marked collision detected by a prior slave thread. If not, any intersection occurring in the region would only occur after another collision, so there is no reason to perform further collision detection in this thread. Control therefore passes to block666.
• Otherwise, control passes to block670 to perform deep collision detection to determine whether any objects (moving or static) are in the region that intersect with the object in question. Control then passes to block672 to determine whether a collision was detected. If a collision is detected, control passes to block674 to update the collision data to indicate the time and the object with which the object in question has collided. Control then passes to block666 to stream the updated collision data, along with the level of detail component and object sweep, to one or more slave threads, or alternatively, back to the master thread with the results of collision detection.
• If, however, block672 does not detect a collision, control passes to block676 to determine whether a future collision has been detected, based upon the movement of the object (as represented by the object sweep) one or more time intervals in the future. If not, control returns to block666. If, however, a future collision is detected, control passes to block678 to analyze the characteristics of the future collision. While a number of different characteristics of the collision may be analyzed, as noted above, routine660 illustrates two related factors: whether the future collision involves numerous objects, e.g., a number of objects that exceeds a particular threshold (block680), and whether the properties of the colliding objects are likely to require additional processing load (block682). If neither factor is found, control passes to block666. If, however, either determination comes out in the affirmative, control passes to block684 to update the collision data streamed to the next slave threads or to the master thread to recommend a load rebalance. Control then passes to block666, whereby routine660 is complete.
• It should be noted that, in this embodiment, slave threads recommend rebalancing, although the actual rebalancing is managed by the master thread. In other embodiments, however, the determination of when rebalancing is required, and performing the actual rebalancing, may be implemented solely within a master thread, solely within a slave thread, or by an entirely different thread.
• Therefore, by initiating a load balancing operation responsive to predicted future collisions between objects, the allocation of threads within a physics engine may be optimized in advance of events that are likely to significantly alter the workload distribution in the physics engine, and as such, the physics engine is more likely to be optimally configured when such events later occur, i.e., when current collisions corresponding to the future collisions are detected.
• It will be appreciated that implementation of predictive load balancing in the NOC architecture described herein would be within the abilities of one of ordinary skill in the art having the benefit of the instant disclosure. In addition, it will be appreciated that suitable algorithms for allocating and reallocating threads to spatial regions based upon predicted workloads would also be within the abilities of one of ordinary skill in the art having the benefit of the instant disclosure.
• Various modifications may be made to the disclosed embodiments without departing from the spirit and scope of the invention. For example, predictive load balancing may also be used to reallocate other hardware resources, e.g., memory, I/O resources, etc. Other modifications will be apparent to one of ordinary skill in the art. Therefore, the invention lies in the claims hereinafter appended.

Claims (23)

1. A circuit arrangement, comprising:

network on chip hardware logic including a plurality of processing cores defining a plurality of hardware threads and an on chip network coupling the plurality of processing cores to one another;

a memory subsystem coupled to the plurality of processing cores and storing a plurality of level of detail components for a plurality of objects in a scene;

a physics engine executed by at least a portion of the plurality of hardware threads, the physics engine including a multithreaded software pipeline including a plurality of stages configured to detect collisions between objects from among the plurality of objects; and

at least one component loader hardware thread and a plurality of collision detection hardware threads defined among the plurality of stages, the component loader hardware thread configured to retrieve level of detail components for objects in the scene from the memory subsystem and stream each level of detail component to sequences of collision detection hardware threads among the plurality of collision detection hardware threads such that the collision detection hardware threads are able to access the level of detail components streamed thereto without directly accessing the memory subsystem, each collision detection hardware thread allocated to a spatial region of the scene and configured to perform collision detection for the spatial region using the level of detail components streamed thereto, and at least one collision detection hardware thread configured to stream level of detail components to another collision detection hardware disposed later in the multithreaded software pipeline, wherein the plurality of collision detection hardware threads are further configured to detect future collisions between objects in the scene, and wherein the component loader hardware thread is configured to initiate a workload reallocation among the plurality of collision detection hardware threads in response to a detected future collision.

2. A method of load balancing among a plurality of hardware threads in a multithreaded physics engine, the method comprising:

allocating workload among the plurality of hardware threads in the multithreaded physics engine;

detecting a future collision between objects in a scene; and

initiating a workload reallocation among the plurality of hardware threads in response to detecting the future collision.

3. The method ofclaim 2, wherein the plurality of hardware threads includes a plurality of collision detection hardware threads configured to detect collisions between objects in the scene, wherein initiating the workload reallocation includes reallocating the workload among the plurality of collision detection hardware threads.

4. The method ofclaim 2, wherein the plurality of hardware threads includes a plurality of impulse propagation hardware threads configured to propagate impulses between objects in the scene, wherein initiating the workload reallocation includes reallocating the workload among the plurality of impulse propagation hardware threads.

5. The method ofclaim 2, further comprising, after detecting the future collision, detecting a current collision corresponding to the future collision.

6. The method ofclaim 5, wherein initiating the workload reallocation includes completing the workload reallocation prior to detecting the current collision.

7. The method ofclaim 2, further comprising determining a number of objects involved in the future collision, wherein initiating the workload reallocation is selectively performed based upon the determination.

8. The method ofclaim 2, further comprising determining a property of at least one object involved in the future collision, wherein initiating the workload reallocation is selectively performed based upon the determination.

9. The method ofclaim 8, wherein the property is selected from the group consisting of rigidity, deformability, elasticity, speed, mass, spring constant, and combinations thereof.

10. The method ofclaim 2, wherein detecting the future collision includes detecting an intersection with an object sweep projected over multiple time intervals.

11. The method ofclaim 2, wherein the multithreaded physics engine comprises a multithreaded software pipeline utilizing the plurality of hardware threads, the multithreaded software pipeline including a plurality of stages configured to detect collisions between objects in a scene, the plurality of stages including at least one component loader stage and a plurality of collision detection stages assigned to the plurality of hardware threads, the component loader stage configured to retrieve level of detail components for a plurality of objects in the scene from a memory and stream each level of detail component to at least one of the plurality of collision detection hardware threads, and each collision detection stage configured to perform collision detection using the level of detail components streamed thereto, wherein initiating the workload reallocation includes reallocating workload among the plurality of collision detection hardware threads.

12. A circuit arrangement, comprising:

a plurality of hardware threads; and

program code implementing at least a portion of a multithreaded physics engine and executed by the plurality of hardware threads, the program code configured to allocate workload among the plurality of hardware threads, detect a future collision between objects in a scene, and initiate a workload reallocation among the plurality of hardware threads in response to detecting the future collision.

13. The circuit arrangement ofclaim 12, wherein the plurality of hardware threads includes a plurality of collision detection hardware threads configured to detect collisions between objects in the scene, wherein the program code is configured to initiate the workload reallocation by reallocating the workload among the plurality of collision detection hardware threads.

14. The circuit arrangement ofclaim 12, wherein the plurality of hardware threads includes a plurality of impulse propagation hardware threads configured to propagate impulses between objects in the scene, wherein the program code is configured to initiate the workload reallocation by reallocating the workload among the plurality of impulse propagation hardware threads.

15. The circuit arrangement ofclaim 12, wherein the program code is further configured to, after detecting the future collision, detect a current collision corresponding to the future collision.

16. The circuit arrangement ofclaim 15, wherein the program code is further configured to complete the workload reallocation prior to detecting the current collision.

17. The circuit arrangement ofclaim 12, wherein the program code is further configured to determine a number of objects involved in the future collision, and wherein the program code is configured to selectively initiate the workload reallocation based upon the determination.

18. The circuit arrangement ofclaim 12, wherein the program code is further configured to determine a property of at least one object involved in the future collision, and wherein the program code is configured to selectively initiate the workload reallocation based upon the determination.

19. The circuit arrangement ofclaim 18, wherein the property is selected from the group consisting of rigidity, deformability, elasticity, speed, mass, spring constant, and combinations thereof.

20. The circuit arrangement ofclaim 12, wherein the program code is configured to detect the future collision by detecting an intersection with an object sweep projected over multiple time intervals.

21. The circuit arrangement ofclaim 12, further comprising a multithreaded software pipeline utilizing the plurality of hardware threads, the multithreaded software pipeline including a plurality of stages configured to detect collisions between objects in a scene, the plurality of stages including at least one component loader stage and a plurality of collision detection stages assigned to the plurality of hardware threads, the component loader stage configured to retrieve level of detail components for a plurality of objects in the scene from a memory and stream each level of detail component to at least one of the plurality of collision detection hardware threads, and each collision detection stage configured to perform collision detection using the level of detail components streamed thereto, wherein the program code is configured to initiate the workload reallocation by reallocating workload among the plurality of collision detection hardware threads.

22. An integrated circuit device including the circuit arrangement ofclaim 21.

23. A program product comprising a non-transitory computer readable medium and logic definition program code resident on the non-transitory computer readable medium and defining the circuit arrangement ofclaim 21.

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