US20110286258A1

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Info

Publication number: US20110286258A1
Application number: US12/785,978
Authority: US
Inventors: Yi-Chou Chen; Wei-Chih Chien; Feng-Ming Lee
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2010-05-24
Filing date: 2010-05-24
Publication date: 2011-11-24
Also published as: US8331127B2

Abstract

A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Description

BACKGROUND

1. Technical Field

The present invention relates to electronic memory devices, and more particularly, to semiconductor memory devices suitable for use as a nonvolatile memory devices.

Most electronic memory devices can be classified as either volatile or nonvolatile. A volatile electronic memory device is, in general, one which requires power in order to maintain the stored information. An example of a volatile electronic memory device is a Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM) computer memory device, which only retains the stored data while the computer is on, and which loses the stored data when the computer is turned off or otherwise loses power. In contrast, a nonvolatile electronic memory device is, in general, one which is capable of retaining stored data in the absence of an external power source. An example of a nonvolatile memory is a memory card such as those commonly used with digital cameras. Such a memory card can record a picture taken with the camera, and can retain the picture data even while the memory card is removed from the camera.

As the systems that use electronic memory devices become more powerful, the demand for data storage capacity increases as well. For example, more powerful computers and software generally operate better with increased amounts of random access memory (RAM); higher resolution cameras create larger picture and movie files that are better accommodated by memory cards having larger storage capacity. Thus, a trend in the electronic memory device industry has been to find ways of increasing the data storage capacity of memory devices. However, it is not sufficient to simply increase capacity—it is often equally desirable to maintain, or even reduce, the size of a memory device while increasing the data storage capacity. Thus, another trend has been towards increasing the amount of data storage for a given size, in other words towards greater bit density. Still another consideration is cost. For example, it is desirable to maintain or reduce the cost of an electronic memory device as the bit density increases. In other words, it is desirable to reduce the bit cost (cost per bit) of electronic memory devices. Still further considerations are performance related, such as providing faster storage of data and faster access to data stored on an electronic memory device.

One approach to providing increased bit density has been to reduce the size of individual memory cells. For example, as manufacturing processes are improved, smaller structures can be formed, thereby allowing for the manufacture of smaller memory cells. However, some projections indicate that bit cost will begin to increase using this approach in the future, because at some point the process cost will likely begin to increase more rapidly than the memory-cell-reduction rate. Thus, it is desirable to find alternative approaches for increasing the bit density of electronic memory devices.

SUMMARY

Memory devices and methods associated with memory devices are described herein. According to one aspect of the present disclosure, a memory device can comprise an array of memory cells, where each memory cell respectively comprises a transistor and a resistance switching device connected in parallel with the transistor. The transistor and the resistance switching device can each be capable of independently storing one or more bits of data. The transistor can comprise a first terminal, a second terminal, and a gate terminal, and be configured to be switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device can be connected in parallel with the transistor such that the resistance switching device is connected to the first and second terminals of the transistor. The resistance switching device can be configured to be switchable between a plurality of different resistances associated with respective memory states.

According to another aspect of the present disclosure, a memory device can comprise a plurality of bit lines, a plurality of word lines, a first memory string comprising a first group of memory cells, and a second memory string comprising a second group of memory cells. The first and second memory strings can be connected to a common source line and to respective bit lines. The word lines can be connected to respective memory cells of the first group of memory cells and to respective memory cells of the second group of memory cells. Each of the memory cells can respectively comprise a transistor and a resistance switching device connected in parallel with the transistor. The transistor and the resistance switching device can each be capable of independently storing one or more bits of data. The transistor can comprise a first terminal, a second terminal, and a gate terminal. The transistor can be configured to be switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device connected in parallel with the first transistor can be connected to the first and second terminals of the first transistor. The resistance switching device can be configured to be switchable between a plurality of different resistances associated with respective memory states.

According to still further aspects of the present disclosure, methods of reading and writing to a memory cell is provided for reading and writing to a memory cell that comprises a transistor and a resistance switching device connected in parallel with the transistor, where the transistor and the resistance switching device are each capable of independently storing one or more bits of data. For example, according to one aspect of the present disclosure, a reading method can comprise detecting a threshold voltage of the transistor of the memory cell, where the transistor is configured to be switchable between a plurality of threshold voltages associated with respective memory states. The reading method can also comprise detecting a resistance of the resistance switching device of the memory cell, where the resistance switching device is configured to be switchable between a plurality of resistances associated with respective memory states. These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.”

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments of the inventions are described in conjunction with the attached drawings, in which:

FIG. 1 shows a block diagram of a memory device in accordance with an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of a memory string of the memory device shown inFIG. 1;

FIG. 3 shows a schematic diagram of a memory cell of the memory device shown inFIG. 1;

FIGS. 4A and 4B show schematic views of a resistance switching device according to some embodiments of the resistance switching device shown inFIG. 3; and

FIGS. 5A-5E show resistance switching characteristics of a symmetrical two-state embodiment of the resistance switching device shown inFIGS. 4A and 4B;

FIG. 6 shows a graphical representation of relationships between the memory states of, and applied voltages to, a symmetrical two-state embodiment of the resistance switching device shown inFIGS. 4A and 4B;

FIG. 7 shows a flowchart of a reading process for reading the symmetrical two-state embodiment of the resistance switching device shown inFIGS. 4A and 4B;

FIG. 8 shows the switching characteristics of a symmetrical three-state embodiment of the resistance switching device shown inFIGS. 4A and 4B;

FIG. 9 shows the switching characteristics of an asymmetrical two-state embodiment of the resistance switching device shown inFIGS. 4A and 4B;

FIG. 10 shows the switching characteristics of an asymmetrical two/three-state embodiment of the resistance switching device shown inFIGS. 4A and 4B;

FIG. 11 shows a process for reading the resistance switching device according to the asymmetrical embodiment shown inFIG. 9;

FIG. 12 shows a schematic view of a resistance switching device according to some embodiments of the resistance switching device shown inFIG. 3;

FIG. 13 shows a diagram of the voltage and current occurring during programming and read operations of the resistance switching device shown inFIG. 12;

FIG. 14 shows a schematic view of a resistance switching device according to some embodiments of the resistance switching device shown inFIG. 3;

FIG. 15A shows the resistance switching characteristics of the upper PMC structure of a symmetrical, dual-PMC embodiment of the resistance switching device shown inFIG. 14;

FIG. 15B shows the resistance switching characteristics of the lower PMC structure of a symmetrical, dual-PMC embodiment of the resistance switching device shown inFIG. 14;

FIG. 16 shows the resistance switching characteristics of a dual-PMC structure that includes upper and lower PMC structures having the resistance switching characteristics shown inFIGS. 15A and 15B, respectively;

FIG. 17 shows a flowchart of a reading process for a resistance switching device shown according toFIG. 16;

FIG. 18 shows the resistance switching characteristics of the upper PMC structure of an asymmetrical, dual-PMC embodiment of the resistance switching device shown inFIG. 14;

FIG. 19 shows the resistance switching characteristics of the lower PMC structure of an asymmetrical, dual-PMC embodiment of the resistance switching device shown inFIG. 14;

FIG. 20 shows the resistance switching characteristics of a dual-PMC structure that includes upper and lower PMC structures having the resistance switching characteristics shown inFIGS. 18 and 19, respectively;

FIG. 21 shows a flowchart of a reading process for a resistance switching device shown according toFIG. 20;

FIG. 22 shows a schematic view of a resistance switching device according to some embodiments of the resistance switching device shown inFIG. 3;

FIG. 23 shows the resistance switching characteristics of the upper memory structure of an embodiment of the resistance switching device shown inFIG. 22;

FIG. 24 shows the resistance switching characteristics of the lower memory structure of an embodiment of the resistance switching device shown inFIG. 22;

FIG. 25 shows the resistance switching characteristics of a resistance switching device that includes upper and lower memory structures having the resistance switching characteristics shown inFIGS. 23 and 24, respectively;

FIG. 26 shows a flowchart of a reading process for a resistance switching device shown according toFIG. 25;

FIG. 27 shows the resistance switching characteristics of the upper memory structure of an embodiment of the resistance switching device shown inFIG. 22;

FIG. 28 shows the resistance switching characteristics of the lower memory structure of an embodiment of the resistance switching device shown inFIG. 22;

FIG. 29 shows the resistance switching characteristics of a resistance switching device that includes upper and lower memory structures having the resistance switching characteristics shown inFIGS. 27 and 28, respectively;

FIG. 30 shows a flowchart of a reading process for a resistance switching device shown according toFIG. 29;

FIG. 31 shows a flowchart of a reading process for the memory cell shown inFIG. 3; and

FIG. 32 shows a flowchart of a programming process for the memory cell shown inFIG. 3.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of amemory array100 in accordance with an embodiment of the present disclosure. Thememory array100 can include a plurality ofmemory cells102, a plurality of bit lines BL1-BLm, a plurality of word lines WL1-WLn, a string select line SSL, a ground select line GSL, and a common source line SL.

Thememory array100 can be configured such that thememory cells102 are arranged in an array of m×nmemory cells102, where m and n represent respective natural numbers. More specifically, thememory array100 can be configured such that thememory cells102 are arranged into a plurality of memory strings MS1-MSm. Each of the memory strings MS includes a respective string select transistor SST, a respective group ofn memory cells102, and a respective ground select transistor GST connected in series. The memory strings MS1-MSm are connected to respective bit lines BL1-BLm. The memory strings MS1-MSm are all connected to the common source line SL.

FIG. 2 shows a schematic diagram of a memory string MSi, which serves as an example of a memory string that can be used as any of the memory strings MS1-MSm shown inFIG. 1. The memory string MSi includes a string select transistor SST, first throughfourth memory cells102a-102d, and a ground select transistor GST. The string select transistor SST, first throughfourth memory cells102a-102d, and ground select transistor GST are connected in series between bit line BLi and common source line SL. While the memory string MSi includes fourmemory cells102a-102d, actual implementations can include additional memory cells, for example 16, 32, 64 or more memory cells as desired. First throughfourth memory cells102a-102dinclude respectiveresistance switching devices110a-110dandrespective transistors112a-112d. Also, it is preferable for neighboring transistors to share a common source and/or drain in order to minimize the cell size. If neither the source nor the drain are common structures in neighboring transistors, it is difficult to achieve a desired design rule that is not larger than 4F².

The gate of the string select transistor SST is connected to the string select line SSL. The source of the string select transistor SST is connected to the bit line BLi. The drain of the string select transistor SST is connected to thefirst memory cell102a.

The gate of the ground select transistor GST is connected to the ground select line GSL. The source of the ground select transistor GST is connected to thelast memory cell102d. The drain of the ground select transistor GST is connected to the common source line SL.

FIG. 3 shows a schematic diagram of amemory cell102 according to an embodiment of the present disclosure. Thememory cells102a-102dcan be configured as shown inFIG. 3. Thememory cell102 includes plural memory elements connected in parallel. In this embodiment, thememory cell102 includes, as a first memory element, aresistance switching device110 and, as a second memory element, atransistor112, which can be a floating gate transistor, n-type transistor, p-type transistor or Fin-FET.

Thetransistor112 can be configured such that the gate is connected to a word line WL. The source of thetransistor112 is connected to the bit line BL through a string select transistor SST and any interveningmemory cells102 as shown inFIG. 2. The drain of thetransistor112 is connected to the common source line SL through a ground select transistor GST and any interveningmemory cells102 as shown inFIG. 2.

The source and drain of thetransistor112 are also connected to opposite ends of theresistance switching device110 such that theresistance switching device110 and thetransistor112 are connected in parallel. In some embodiments, theresistance switching device110 can be formed above thetransistor112 and word line WL as shown inFIG. 3. In such embodiments, thememory cell102 can be formed by first forming thetransistor112 and word line WL, and then forming theresistance switching device110 above thetransistor112 and word line WL.

Thetransistor112 can be a floating gate transistor, n-type transistor, p-type transistor or Fin-FET that is configured such that the threshold voltage Vt of thetransistor112 is changeable between two or more values, where certain values of Vt are associated with respective memory states. For example, thetransistor112 can be a single-level cell (SLC) floating gate transistor, a multi-level cell (MLC) floating gate transistor, a nano-crystal flash transistor, or a nitride trap device.

Thus, thetransistor112 can be configured to store plural Vt states in one or plural locations. In some embodiments, for example, thetransistor112 can be configured to be a 1-bit memory device capable of being programmed to either one of two distinct threshold voltages Vt. Such embodiments can include embodiments where thetransistor112 is an SLC floating gate transistor. In some embodiments, for example, thetransistor112 can be configured to be a 2-bit memory device capable of being programmed to any one of four distinct threshold voltages Vt. Such embodiments can include embodiments where thetransistor112 is an MLC floating gate transistor. Embodiments of thetransistor112 that include a floating gate device can be programmed by hot electron injection and erased by Fowler-Nordheim (FN) electron tunneling.

Theresistance switching device110 can be configured such that the resistance of theresistance switching device110 is changeable between multiple resistance values, where certain resistance values are associated with respective memory states. For example, theresistance switching device110 can be a resistance type memory device as described in U.S. Pat. No. 7,524,722 to Lee et al., which is hereby incorporated by reference.

Thus, in some embodiments, thememory cell102 can be configured to store one or more bits. For example, in some embodiments, thetransistor112 can be configured to be switched between two memory states and theresistance switching device110 can be configured to be switched between two memory states so that thememory cell102 is a two-bit memory device capable of a total of four memory states. As another example, in some embodiments, thetransistor112 can be configured to be switched between four memory states and theresistance switching device110 can be configured to be switched between four memory states so that thememory cell102 is a 4-bit memory device capable of a total of sixteen memory states. Still further embodiments can include atransistor112 configured to be switched between a selected number N1 threshold voltages associated with respective memory states, and theresistance switching device110 is configured to be switched between a selected number N2 resistances associated with respective memory states, so that thememory cell102 is therefore configured to have a total of N1+N2 memory states.

FIG. 4A shows a schematic view of aresistance switching device110aaccording to some embodiments of theresistance switching device110. Theresistance switching device110aincludes asubstrate122, an intermetal dielectric (IMD)layer124, afirst electrode layer126, atungsten oxide layer128, first and second

dielectric structures

130aand130b, and asecond electrode layer134.

Thesubstrate122 can be a silicon substrate, and theintermetal dielectric layer124 can be an oxide layer or other electrically-insulating layer formed on thesubstrate122 by known methods, for example by chemical vapor deposition (CVD).

Thefirst electrode126 can be formed of titanium nitride (TiN) and disposed on theIMD layer124 by a CVD or physical vapor deposition (PVD) process. Alternatively, the material of thefirst electrode126 can include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).

Thetungsten oxide layer128 is formed over thefirst electrode126. The first and second

dielectric structures

130aand130bflank thetungsten oxide layer128 and are also formed over thefirst electrode126. The

dielectric structures

130aand130bcan contain, for example, SiO₂, Si₃N₄, or similar insulating materials. The structure comprising thetungsten oxide layer128 and the first and second

dielectric structures

130aand130bcan be formed by first forming adielectric layer130 as a continuous dielectric layer over the first electrode, for example by a CVD process. Next, a portion of the continuous dielectric layer is removed, for example by photolithography and etching, thereby resulting in a gap between the first and second

dielectric structures

130aand130b. Next, thetungsten oxide layer128 is formed in the gap between the first and second

dielectric structures

130aand130b. More specifically, thetungsten oxide layer128 can be formed by first depositing tungsten in the gap between the first and second

dielectric structures

130aand130b, then performing an oxidation process so that the tungsten is oxidized. For example, a thermal oxidation process can be used such that oxidation is diffused through most or all of the tungsten layer, thereby resulting in the formation of thetungsten oxide layer128.

Thesecond electrode134 can be formed of titanium nitride (TiN) and disposed over thetungsten oxide layer128 by a CVD or PVD process. Thesecond electrode134 can extend over the

dielectric structures

130aand130bas well. The material of thesecond electrode134 can alternatively include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).

Full oxidation of thetungsten oxide layer128 results in the formation of first and

second interface regions

138 and140 of adjustable resistance.FIG. 4B shows the respective locations of the first and

second interface regions

138 and140. Thefirst interface region138 includes the region at the interface of thefirst electrode126 and thetungsten oxide layer128. Thesecond interface region140 includes the region at the interface of thesecond electrode134 and thetungsten oxide layer128.

FIGS. 5A-5E show the resistance switching characteristics of a symmetrical two-state embodiment of theresistance switching device110a. That is, in the present embodiment, theresistance switching device110aincludes two

interface regions

138 and140, each having two resistance values (memory states), and each being at least substantially symmetrical to the other. Alternative embodiments, including those described herein, can include embodiments that are not symmetric and/or include more than two resistance values per interface region.

The resistance between the first and

second electrodes

126 and134 through thetungsten oxide layer128 can be adjusted between two resistance values R1 and R2. The resistance switching behavior of theresistance switching device110awill occur at either thefirst interface region138 or thesecond interface region140. As will be described in more detail with reference toFIGS. 5A-5E, a voltage pulse can be used to select between the first and

second interface regions

138 and140 as the interface region for controlling the switching behavior of theresistance switching device110a. This is significant because the voltage level required to switch the resistance value from R1 to R2 or vice-versa will depend on whether thefirst interface region138 or thesecond interface region140 is currently controlling the switching behavior of theresistance switching device110a.

Turning first toFIG. 5A, this graph shows the resistance switching characteristics of the present embodiment of theresistance switching device110awhile thesecond interface region140 is controlling the resistance switching characteristics. Here, theresistance switching device110acan be controlled to either have a reset resistance R1 or a set resistance R2. If the resistance of theresistance switching device110ais R1, the resistance can be decreased from R1 to R2 by applying a negative voltage V2 across theresistance switching device110aas shown inFIG. 4B between the voltage supply terminal and ground. Similarly, if the resistance of theresistance switching device110ais R2, the resistance can be increased from R2 to R1 by applying a positive voltage V4 across theresistance switching device110a.

FIG. 5B shows the process for switching control from thesecond interface region140 to thefirst interface region138. Specifically, the control of the resistance switching characteristics of the present embodiment of theresistance switching device110acan be switched from thesecond interface region140 to thefirst interface region138 by applying a negative voltage V1 across theresistance switching device110a.

The result of the switch atFIG. 5B is shown inFIG. 5C, where thefirst interface region138 is now controlling the resistance switching characteristics of the present embodiment of theresistance switching device110a. The behavior illustrated inFIG. 5C can be compared with that ofFIG. 5A in order to observe the difference between the resistance switching characteristics of the present embodiment of theresistance switching device110awhen thefirst interface region138 is controlling and the resistance switching characteristics of the present embodiment of theresistance switching device110awhen the second interface region1440 is controlling. Now, atFIG. 5C, with thefirst interface region138 controlling, the resistance can be decreased from R1 to R2 by applying a positive voltage V3 across theresistance switching device110a, and resistance can be increased from R2 to R1 by applying a negative voltage V1 across theresistance switching device110a.

FIG. 5D shows the process for switching control from thefirst interface region138 to thesecond interface region140. Specifically, the control of the resistance switching characteristics of the present embodiment of theresistance switching device110acan be switched from thefirst interface region138 to thesecond interface region140 by applying a positive voltage V4 across theresistance switching device110a.

The result of the switch atFIG. 5D is shown inFIG. 5E, identical toFIG. 5A, where once again thesecond interface region140 is controlling the resistance switching characteristics of the present embodiment of theresistance switching device110a.

Thus, theresistance switching device110acan be set to any of four states, which can serve as four memory states: (1) first interface controlling and resistance=R1 (state “R_RESET”); (2) first interface controlling and resistance=R2 (state “R_SET”); (3) second interface controlling and resistance=R1 (state “R_RESET”); and (4) second interface controlling and resistance=R2 (state “R_SET”). It is difficult to distinguish between the statesR_SET and R_SET. However, the statesR_RESET and R_RESETcan be reliably distinguished from each other. Also, each of the statesR_RESET and R_RESETcan be reliably distinguished from the statesR_SET and R_SET. Thus, theresistance switching device110aaccording to the present embodiment can be configured to serve as a three-state memory device having states (1)R_RESET; (2) R_RESET; and (3)R_SET or R_SET.

A process for reading theresistance switching device110aaccording to an embodiment as a three-state memory device is next described with reference toFIGS. 6 and 7.FIG. 6 shows a graphical representation of the relationships between the memory states of, and applied voltages to, theresistance switching device110a, andFIG. 7 shows a flowchart of the reading process.

First, atblock200, theresistance switching device110ahas been programmed to one of the memory states (1)R_RESET; (2) R_RESET; and (3)R_SET or R_SET. The remainder of the process will allow for reading theresistance switching device110ain order to determine which of the memory states was written to theresistance switching device110a. Atblock202, the resistance of theresistance switching device110ais determined. As shown inFIG. 6, the resistance can be expected to either be a higher resistanceR_RESET/R_RESETor a lower resistanceR_SET/R_SETregardless of which of the first and

second interface regions

138 and140 is controlling. If the lower resistance valueR_SET/R_SETis detected, the process ends atblock204 with a determination that the memory state of theresistance switching device110aisR_SET/R_SET. Otherwise, if the higher resistanceR_RESET/R_RESETis detected, the process continues in order to distinguish between theR_RESET memory state and the R_RESETmemory state.

The memory stateR_RESET can be distinguished from the R_RESETmemory state by determining which of the first and

second interface regions

138 and140 is controlling. In the process shown inFIG. 7, this is accomplished by applying a voltage V_DETERMINEfor which the behavior of the resistance switching device will differ depending on which of first and

second interface regions

138 and140 is controlling. An example of a voltage level that can be used as the V_DETERMINEis shown inFIG. 6. Here, the voltage level V_DETERMINEis a voltage level between voltage levels V3 and V4 shown inFIGS. 5A-5E. Recalling that atblock206 it is known that the resistance level is high (e.g., R1 inFIGS. 4A-4E), it can be appreciated that the behavior of theresistance memory device110awill differ when the voltage V_DETERMINEis applied across theresistance memory device110adepending on which of the first and

second interface regions

138 and140 is controlling. For example, according toFIG. 5A if thesecond interface region140 is controlling, then the application of voltage V_DETERMINEwill not change the resistance of theresistance memory device110afrom resistance R1. On the other hand, according toFIG. 5D if thefirst interface region138 is controlling, then the application of voltage V_DETERMINEwill change the resistance of theresistance memory device110afrom resistance R1 to resistance R2.

Thus, at block206 a voltage V_DETERMINEis applied across theresistance switching device110a, and then atblock208 the resistance of theresistance switching device110ais measured. If the higher resistance valueR_RESET/R_RESETis still detected, it can be determined that thesecond interface region140 is controlling since the resistance value was not changed by the application of V_DETERMINE. Thus, the process ends atblock210 with a determination that the memory state of theresistance switching device110ais the R_RESETmemory state. Otherwise, if the lower resistance valueR_SET/R_SETis detected, it can be determined that thefirst interface region138 was controlling since the resistance value was changed by the application of V_DETERMINE. Note that in this case, the application of V_DETERMINEswitched control from thefirst interface region138 to thesecond interface region140. Thus, the process continues withblock212, where switching control is switched back to thefirst interface region138 so that the memory state of theresistance memory device110ais not disturbed by the present read process. Then the process ends atblock214 with a determination that the memory state of theresistance switching device110ais theR_SET memory state.

FIGS. 8-10 show the resistance switching characteristics of alternative embodiments of theresistance switching device110a. More specifically,FIG. 8 shows the switching characteristics of a symmetrical three-state embodiment of theresistance switching device110a;FIG. 9 shows the switching characteristics of an asymmetrical two-state embodiment of theresistance switching device110a; andFIG. 10 shows the switching characteristics of an asymmetrical two/three-state embodiment of theresistance switching device110a. These and other such alternative embodiments can be manufactured by varying the composition of the electrode layers126 and134 and/or the composition of thetungsten oxide layer128. For example, where the electrode layers126 and134 are formed of TiN, the resistance associated with the R_RESETorR_RESET state can be increased or decreased depending on the nitrogen content of the TiN. Similarly, the resistance associated with the R_RESETorR_RESET state can be increased or decreased depending on the oxygen content of thetungsten oxide layer128.

The switching characteristics of a symmetrical three-state embodiment of theresistance switching device110asuch as shown inFIG. 8 includes three resistance values (memory states) perinterface region138/140. The memory states for while thefirst interface region138 is controlling areR_SET,R_RESET1, andR_RESET2. The memory states for while thesecond interface region140 is controlling are R_SET, R_RESET1, and R_RESET2. It is difficult to distinguish between the statesR_SET and R_SET. However, the statesR_RESET1,R_RESET2, R_RESET1, and R_RESET2can be reliably distinguished from each other. Also, each of the statesR_RESET1,R_RESET2, R_RESET1, and R_RESET2can be reliably distinguished from the statesR_SET and R_SET. Thus, theresistance switching device110aaccording to the present embodiment can be configured to serve as a five-state memory device having states (1)R_RESET1; (2)R_RESET2; (3) R_RESET1; (4) R_RESET2; and (5)R_SET or R_SET.

The switching characteristics of an asymmetrical two-state embodiment of theresistance switching device110asuch as shown inFIG. 9 includes two resistance values (memory states) perinterface region138/140 where the R_RESETresistance is distinguishably different from theR_RESET resistance. The memory states for while thefirst interface region138 is controlling areR_SET andR_RESET. The memory states for while thesecond interface region140 is controlling are R_SETand R_RESET. It is difficult to distinguish between the statesR_SET and R_SET. However, the statesR_RESET and R_RESETcan be reliably distinguished from each other. Also, each of the statesR_RESET and R_RESETcan be reliably distinguished from the statesR_SET and R_SET. Thus, theresistance switching device110aaccording to the present embodiment can be configured to serve as a three-state memory device having states (1)R_RESET; (2) R_RESET; and (3)R_SET or R_SET.

FIG. 11 shows a process for reading theresistance switching device110aaccording to the asymmetrical embodiment shown inFIG. 9. First, atblock300, theresistance switching device110ahas been programmed to one of the memory states (1)R_RESET; (2) R_RESET; and (3)R_SET or R_SET. The remainder of the process will allow for reading theresistance switching device110ain order to determine which of the memory states was written to theresistance switching device110a. Atblock302, the resistance of theresistance switching device110ais determined. As shown inFIG. 9, the resistance can be expected to be one of a first resistanceR_RESET, a second resistance R_RESET, or a third resistanceR_SET/R_SETregardless of which of the first and

second interface regions

138 and140 is controlling. If the resistance valueR_SET/R_SETis detected, the process ends atblock304 with a determination that the memory state of theresistance switching device110aisR_SET/R_SET. If the resistance value R_RESETis detected, the process ends atblock306 with a determination that the memory state of theresistance switching device110ais R_RESET. If the resistance valueR_RESET is detected, the process ends atblock308 with a determination that the memory state of theresistance switching device110aisR_RESET.

Referring again toFIG. 10, the switching characteristics of an asymmetrical two/three-state embodiment of theresistance switching device110aincludes two resistance values (memory states) associated with thefirst interface region138 and three resistance values (memory states) associated with thesecond interface region140. The memory states for while thefirst interface region138 is controlling areR_SET andR_RESET. The memory states for while thesecond interface region140 is controlling are R_SET, R_RESET1, and R_RESET2. It is difficult to distinguish between the statesR_SET and R_SET. However, the statesR_RESET, R_RESET1, and R_RESET2can be reliably distinguished from each other. Also, each of the statesR_RESET, R_RESET1, and R_RESET2can be reliably distinguished from the statesR_SET and R_SET. Thus, theresistance switching device110aaccording to the present embodiment can be configured to serve as a four-state memory device having states (1)R_RESET, (2) R_RESET1, (3) R_RESET2; and (4)R_SET or R_SET.

FIG. 12 shows a schematic view of aresistance switching device110baccording to some embodiments of theresistance switching device110. Theresistance switching device110bincludes a programmable metallization cell (PMC)400. More specifically, theresistance switching device110bincludes asubstrate402, an intermetal dielectric (IMD)layer404, afirst electrode layer406, aconductive plug layer408, first and second

dielectric layers

410 and412, asolid electrolyte layer414, and asecond electrode layer416.

Thesubstrate402 can be a silicon substrate, and theIMD layer404 can be an oxide layer or other electrically-insulating layer formed on thesubstrate402 by known methods, for example by chemical vapor deposition (CVD).

Thefirst electrode layer406 can be formed of titanium nitride (TiN) and disposed on theIMD layer404 by a CVD or physical vapor deposition (PVD) process. Alternatively, the material of thefirst electrode406 can include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).

Theconductive plug layer408 is formed over thefirst electrode406. The first and second

dielectric layers

410 and412 flank theconductive plug layer408 and are also formed over thefirst electrode406. The

dielectric layers

410 and412 can contain, for example, SiO₂, Si₃N₄, or similar insulating materials. Theconductive plug layer408 can contain tungsten. The structure comprising theconductive plug layer408 and the first and second

dielectric layers

410 and412 can be formed by first forming the

dielectric layers

410 and412 as a continuous dielectric layer over thefirst electrode406, for example by a CVD process. Next, a portion of the continuous dielectric layer is removed, for example by photolithography and etching, thereby resulting in a gap between the first and second

dielectric layer formations

410 and412. Next, theconductive plug layer408 is formed in the gap between the first and second

dielectric layers

410 and412. More specifically, theconductive plug layer408 can be formed by depositing the material of theconductive plug layer408 in the gap between the first and second

dielectric layers

410 and412.

Thesolid electrolyte layer414 can be formed by deposition over theconductive plug layer408. Thesolid electrolyte layer414 can also extend over the

dielectric layers

410 and412. Thesolid electrolyte layer414 can include transition metal oxide or materials that contain at least one chalcogenide element. For example, thesolid electrolyte layer414 can contain GeS/Ag or GeSe/Ag.

Thesecond electrode layer416 can be formed by deposition over thesolid electrolyte layer414. Thesecond electrode layer416 can be an oxidizable electrode. Thesecond electrode layer416 can contain an oxidizable electrode material, for example Ag, Cu, or Zn.

The embodiment of theresistance switching device110bshown inFIG. 12 forms a single PMC structure.FIG. 13 shows a diagram of the voltage and current occurring during programming and read operations of an example of the single PMC embodiment of theresistance switching device110b. The exact voltage and current levels can vary from those shown inFIG. 13.

At the start,resistance switching device110bmay not programmed and may therefore have a high resistance. If a voltage is applied with a higher voltage at thesecond electrode layer416 and a lower voltage at thefirst electrode layer406, no current may flow through theresistance switching device110buntil a set threshold voltage (V1, or programming voltage) is applied. In the illustrated example, the set threshold voltage V1 may be, for example, about 0.7 volts. When the applied voltage rises over the threshold voltage V1, current may flow until a working current I_Wis achieved and may be confined (e.g., limited) by the programming circuit. In one embodiment, the voltage may then be reduced to 0 Volts, whereby the current falls to 0 amps, thereby completing the programming of theresistance switching device110b.

If the cell state is to be sensed or read, a sensing voltage (VS) may be applied to theresistance switching device110b. The sensing voltage VS may be lower than the threshold voltage V1. In the illustrated example, the sensing voltage VS may be, for example, about 0.3 volts. When theresistance switching device110bis programmed (SET) as described above and the sensing voltage VS is applied to theresistance switching device110b, a working current IW may flow through theresistance switching device110b. If theresistance switching device110bis not programmed (RESET), little or no current may flow through theresistance switching device110bwhen the sensing voltage VS is applied.

In one embodiment, a lower voltage, e.g., a negative voltage (also referred to as a reset threshold voltage) may be applied to theresistance switching device110bin order to erase or reset the program status. In the illustrated example, the reset threshold voltage may be, for example, about −0.3 volts. When the reset threshold voltage is applied to theresistance switching device110b, a negative current may flow through theresistance switching device110b. When the negative voltage drops to below the reset threshold voltage, the current may stop flowing (i.e., decrease to 0 Amps). After the reset threshold voltage has been applied to theresistance switching device110b, theresistance switching device110bmay have the same high resistance as prior to the programming operation, thereby erasing or resetting the value stored in theresistance switching device110b.

FIG. 14 shows a schematic view of aresistance switching device110caccording to some embodiments of theresistance switching device110. Theresistance switching device110cincludes a dual PMC structure. Theresistance switching device110cincludes asubstrate452, an intermetal dielectric (IMD)layer454, afirst electrode layer456, aconductive plug layer458, first and second

dielectric layers

460 and462, a firstsolid electrolyte layer464, asecond electrode layer466, a secondsolid electrolyte layer468, and athird electrode layer470.

Thesubstrate452 can be a silicon substrate, and theintermetal dielectric layer454 can be an oxide layer or other electrically-insulating layer formed on thesubstrate452 by known methods, for example by chemical vapor deposition (CVD).

Thefirst electrode layer456 can be formed of titanium nitride (TiN) and disposed on theIMD layer454 by a CVD or physical vapor deposition (PVD) process. Alternatively, the material of thefirst electrode456 can include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).

Theconductive plug layer458 is formed over thefirst electrode456. The first and second

dielectric layers

460 and462 flank theconductive plug layer458 and are also formed over thefirst electrode456. The

dielectric layers

460 and462 can contain, for example, SiO₂, Si₃N₄, or similar insulating materials. Theconductive plug layer458 can contain tungsten. The structure comprising theconductive plug layer458 and the first and second

dielectric layers

460 and462 can be formed by first forming the

dielectric layers

460 and462 as a continuous dielectric layer over thefirst electrode456, for example by a CVD process. Next, a portion of the continuous dielectric layer is removed, for example by photolithography and etching, thereby resulting in a gap between the first and second

dielectric layer formations

460 and462. Next, theconductive plug layer458 is formed in the gap between the first and second

dielectric layers

460 and462. More specifically, theconductive plug layer458 can be formed by depositing the material of theconductive plug layer458 in the gap between the first and second

dielectric layers

460 and462.

The firstsolid electrolyte layer464 can be formed by deposition over theconductive plug layer458. The firstsolid electrolyte layer464 can also extend over the

dielectric layers

460 and462. The firstsolid electrolyte layer464 can include transition metal oxide or materials that contain at least one chalcogenide element. For example, the firstsolid electrolyte layer464 can contain GeS/Ag or GeSe/Ag.

Thesecond electrode layer466 can be formed by deposition over the firstsolid electrolyte layer464. Thesecond electrode layer466 can be an oxidizable electrode. Thesecond electrode layer466 can contain an oxidizable electrode material, for example Ag, Cu, or Zn.

The secondsolid electrolyte layer468 can be formed by deposition over thesecond electrode layer466. The secondsolid electrolyte layer468 can include transition metal oxide or materials that contain at least one chalcogenide element. For example, the secondsolid electrolyte layer468 can contain GeS/Ag or GeSe/Ag.

Thethird electrode layer470 can be formed by deposition over the secondsolid electrolyte layer468. Thethird electrode layer470 can contain a conductive or semiconductive material, for example TiN.

The embodiment of theresistance switching device110cshown inFIG. 14 forms a dual PMC structure, includingupper PMC structure472 andlower PMC structure474. Each of the

PMC structures

472 and474 is capable of being programmed to two respective memory states corresponding to respective resistances. The memory states of theupper PMC structure472 include memory states designated R_RESETand R_SET, which correspond to relatively higher and lower resistance values, respectively. The memory states of thelower PMC structure474 include memory states designatedR_RESET andR_SET, which correspond to relatively higher and lower resistance values, respectively. In some embodiments, the resistance value associated with R_RESETcan be substantially equal to the resistance value associated withR_RESET, while in other embodiments the respective resistance values associated with R_RESETandR_RESET can differ from each other. Similarly, in some embodiments, the resistance value associated with R_SETcan be substantially equal to the resistance value associated withR_SET, while in other embodiments the respective resistance values associated with R_SETandR_SET can differ from each other.

FIGS. 15A,15B, and16 show diagrams of the resistance switching characteristics of a symmetrical, dual-PMC embodiment of theresistance switching device110c. More specifically,FIG. 15A shows the resistance switching characteristics of theupper PMC structure472,FIG. 15B shows the resistance switching characteristics of thelower PMC structure474, andFIG. 16 shows the overall resistance switching characteristics of the symmetrical embodiment of the dual-PMC structure that is formed by the upper and

lower PMC structures

472 and474.

As shown inFIG. 15A, a positive voltage V_S1across theupper PMC structure472 will cause the resistance of theupper PMC structure472 to switch to the resistance value associated with memory state R_RESET. A negative voltage V_S2across theupper PMC structure472 will cause the resistance of theupper PMC structure472 to switch to the resistance value associated with memory state R_SET.

As shown inFIG. 15B, a positive voltage V_S3across thelower PMC structure474 will cause the resistance of thelower PMC structure474 to switch to the resistance value associated with memory stateR_SET. A negative voltage V_S4across thelower PMC structure474 will cause the resistance of thelower PMC structure474 to switch to the resistance value associated with memory stateR_RESET.

The combination of the symmetrical embodiment of the upper and

lower PMC structures

472 and474 as shown inFIGS. 15A and 15B results in a memory device capable of four memory states A-D as shown inFIG. 16. Each of the memory states A-D is associated with a respective sum of resistances of the memory states of the upper and

lower PMC structures

472 and474. The memory state A occurs when the resistance of theupper PMC structure472 has the resistance associated with memory state R_SETand thelower PMC structure474 has the resistance associated with memory stateR_RESET so that the overall resistance of the dual PMC structure for memory state A is R_SET+R_RESET. The memory state D occurs when the resistance of theupper PMC structure472 has the resistance associated with memory state R_RESETand thelower PMC structure474 has the resistance associated with memory stateR_SET so that the overall resistance of the dual PMC structure for memory state D isR_SET+R_RESET. The memory states B and C both occur when the resistance of theupper PMC structure472 has the resistance associated with memory state R_RESETand thelower PMC structure474 has the resistance associated with memory stateR_RESET so that the overall resistance of the dual PMC structure for memory states B and C is R_RESET+R_RESET. Thus, the memory states B and C are difficult to distinguish, so the dual PMC structure of theresistance switching device110ccan be implemented as a three-state memory device having memory states A, B (or C), and D.

A process for reading theresistance switching device110caccording to an embodiment as a three-state, symmetrical, dual-PMC memory device is next described with reference toFIG. 17, which shows a flowchart of the reading process.

First, atblock500, theresistance switching device110chas been programmed to one of the memory states A, B/C, or D. The remainder of the process will allow for reading theresistance switching device110cin order to determine which of the memory states was written to theresistance switching device110c. Atblock502, the resistance of theresistance switching device110cis determined. In the present symmetrical embodiment, the resistance associated with R_SETis substantially equal to the resistance associated withR_SET, and the resistance associated with R_RESETis substantially equal to the resistance associated withR_RESET. Thus, the resistance of theresistance switching device110ccan be expected to either be a higher resistance R=R_RESET+R_RESETor a lower resistance R=(R_RESET+R_SET) or (R_SET+R_RESET). If the higher resistance value R=R_RESET+R_RESETis detected, the process ends atblock504 with a determination that the memory state of theresistance switching device110cis memory state B/C (R_RESET+R_RESET). Otherwise, if the lower resistance is detected, the process continues in order to distinguish between the memory states A (R_SET+R_RESET) and D (R_RESET+R_SET).

Next, at block506 a voltage V_DETERMINEis applied across theresistance switching device110c, and then atblock508 the resistance of theresistance switching device110cis measured. In this embodiment, a voltage for V_DETERMINEis selected that will cause theupper PMC structure472 to switch from R_SETto R_RESETif the memory state is memory state A, but will not result in any change if the memory state is memory state D. Thus, the voltage of V_DETERMINEis a voltage between V_S1and V_S3. Alternatively, a voltage for V_DETERMINEcan be selected between V_S2and V_S4that will cause thelower PMC structure472 to switch fromR_SET toR_RESET if the memory state is memory state D, but will not result in any change if the memory state is memory state A.

If the lower resistance value equal to R_RESET+R_SET (and also equal to R_SET+R_RESET) is detected atblock508, it can be determined that the memory state is memory state D since the resistance value was not changed by the application of V_DETERMINE. Thus, the process ends atblock510 with a determination that the memory state of the resistance switching device122cis the memory state D. Otherwise, if the higher resistance value R_RESET+R_RESET is detected atblock508, it can be determined that the memory state is memory state A since the resistance value was changed by the application of V_DETERMINE. Note that in this case, the application of V_DETERMINEswitched the resistance value of theupper PMC structure472 from R_SETto R_RESET. Thus, the process continues withblock512, where the resistance of theupper PMC structure472 is switched back to R_SET(e.g., by application of V_S2) so that the memory state of the resistance memory device122cis not disturbed by the present read process. Then the process ends atblock514 with a determination that the memory state of the resistance switching device122cis the memory state A.

FIGS. 18-20 show diagrams of the resistance switching characteristics of an asymmetrical, dual-PMC embodiment of theresistance switching device110c. More specifically,FIG. 18 shows the resistance switching characteristics of theupper PMC structure472,FIG. 19 shows the resistance switching characteristics of thelower PMC structure474, andFIG. 20 shows the overall resistance switching characteristics of the asymmetrical embodiment of the dual-PMC structure that is formed by the upper and

lower PMC structures

472 and474.

As shown inFIG. 18, a positive voltage V_S1across theupper PMC structure472 will cause the resistance of theupper PMC structure472 to switch to the resistance value associated with memory state R_RESET. A negative voltage V_S2across theupper PMC structure472 will cause the resistance of theupper PMC structure472 to switch to the resistance value associated with memory state R_SET.

As shown inFIG. 19, a positive voltage V_S3across thelower PMC structure474 will cause the resistance of thelower PMC structure474 to switch to the resistance value associated with memory stateR_SET. A negative voltage V_S4across thelower PMC structure474 will cause the resistance of thelower PMC structure474 to switch to the resistance value associated with memory stateR_RESET.

The combination of the asymmetrical embodiment of the upper and

lower PMC structures

472 and474 as shown inFIGS. 18 and 19 results in a memory device capable of four memory states A-D as shown inFIG. 20. Each of the memory states A-D is associated with a respective sum of resistances of the memory states of the upper and

lower PMC structures

In addition to the foregoing

embodiments

110a,110b, and110cof theresistance switching device110, it will be appreciated that there are many still further embodiments that are possible for theresistance switching device110.FIG. 22 shows a block diagram of a more generalized embodiment, generally referred to asresistance switching device110d. Theresistance switching device110dincludes anupper memory structure652 and alower memory structure654, where each of the

memory structures

652 and654 include a respective semiconductor resistance-switching memory device. For example, theupper memory structure652 can include a PMC, a Resistive Random Access Memory (RRAM), a Magnetoresistive Random Access Memory (MRAM), a phase-change memory (PCM), or a Ferroelectric Random Access Memory (FRAM). Similarly, thelower memory structure654 can include a PMC, an RRAM, an MRAM, or an FRAM. Alternatively, the upper and

lower memory structures

652 and654 can include any electronic memory device capable of switching between two resistance values (corresponding to two memory states).

The memory states of theupper memory structure652 include memory states designated R_RESETand R_SET, which correspond to relatively higher and lower resistance values, respectively. A positive reset voltage (+V_RESET) can switch the resistance of theupper memory structure652 to the resistance R_RESET, and a negative set voltage (−V_SET) can switch the resistance of theupper memory structure652 to the resistance R_SET. The memory states of thelower memory structure654 include memory states designatedR_RESET andR_SET, which correspond to relatively higher and lower resistance values, respectively. A negative reset voltage (−V_RESET) can switch the resistance of theupper memory structure652 to the resistanceR_RESET, and a positive set voltage (+V_SET) can switch the resistance of theupper memory structure652 to the resistanceR_SET. There are two desirable condition sets for theresistance switching device110d. The first condition set satisfies both the following conditions (1a) and (1b):

+V_RESET>+V_SET (1a)

|−V_SET|>|−V_RESET| (1b)

The second condition set satisfies both the following conditions (2a) and (2b):

+V_RESET<+V_SET (2a)

|−V_SET|<|−V_RESET| (2b)

Embodiments of theresistance switching device110dthat satisfy the first condition set are described with reference toFIGS. 23-25. Embodiments of theresistance switching device110dthat satisfy the second condition set are described with reference toFIGS. 27-30.

FIGS. 23-25 show diagrams of the resistance switching characteristics of an embodiment of theresistance switching device110dsatisfying the first set of conditions (1a) and (1b). More specifically,FIG. 23 shows the resistance switching characteristics of theupper memory structure652,FIG. 24 shows the resistance switching characteristics of thelower memory structure654, andFIG. 25 shows the overall resistance switching characteristics of theresistance switching device110daccording to the present embodiment.

As shown inFIG. 23, a positive voltage +V_RESETacross theupper memory structure652 will cause the resistance of theupper memory structure652 to switch to the resistance value associated with memory state R_RESET. A negative voltage −V_SETacross theupper memory structure652 will cause the resistance of theupper memory structure652 to switch to the resistance value associated with memory state R_SET.

As shown inFIG. 24, a positive voltage +V_SET across thelower memory structure654 will cause the resistance of thelower memory structure654 to switch to the resistance value associated with memory stateR_SET. A negative voltage−V_RESET across thelower memory structure654 will cause the resistance of thelower memory structure654 to switch to the resistance value associated with memory stateR_RESET.

The combination of the upper and

lower memory structures

652 and654 as shown inFIGS. 23 and 24 results in aresistance switching device110dcapable of four memory states A-D as shown inFIG. 25. Each of the memory states A-D is associated with a respective sum of resistances of the memory states of the upper and

lower memory structures

A process for reading theresistance switching device110daccording to an embodiment as a four-state memory device satisfying the first set of conditions (1a) and (1b) is next described with reference toFIG. 26, which shows a flowchart of the reading process.

First, atblock700, theresistance switching device110dhas been programmed to one of the memory states A, B, C, or D. The remainder of the process will allow for reading theresistance switching device110din order to determine which of the memory states A-D was written to theresistance switching device110d. Atblock702, the resistance of theresistance switching device110dis determined. The resistance of theresistance switching device110dcan be expected to one of the four resistance values associated with the memory states A-D, respectively. If the resistance value R=R_SET+R_SET is detected, the process ends atblock704 with a determination that the memory state of theresistance switching device110dis memory state C (R_SET+R_SET). If the resistance value R=R_RESET+R_RESET is detected, the process ends atblock705 with a determination that the memory state of theresistance switching device110dis memory state B (R_RESET+R_RESET). In the present embodiment, the resistance associated with R_SETis substantially equal to the resistance associated withR_SET, and the resistance associated with R_RESETis substantially equal to the resistance associated withR_RESET. Thus, a third possibility atblock702 is that the resistance is R=R_RESET+R_SET=R_SET+R_RESET. If this third possibility occurs, then the process continues in order to distinguish between the memory states A (R_SET+R_RESET) and D (R_RESET+R_SET).

Next, at block706 a voltage V_DETERMINEis applied across theresistance switching device110d, and then atblock708 the resistance of theresistance switching device110dis measured. In this embodiment, a voltage for V_DETERMINEis selected that will cause thelower memory structure654 to switch fromR_RESET toR_SET if the memory state is memory state A, but will not result in any change if the memory state is memory state D. Thus, the voltage of V_DETERMINEis a voltage between +V_SET and +V_RESET.

Atblock708, the resistance of theresistance switching device110dis again determined. If the detected resistance atblock708 is R=R_RESET+R_SET, it can be determined that the memory state is memory state D since the resistance value was not changed by the application of V_DETERMINE. Thus, the process ends atblock710 with a determination that the memory state of theresistance switching device110dis the memory state D. Otherwise, if the detected resistance atblock708 is R=R_RESET+R_SET, it can be determined that the memory state is memory state A since the resistance value was changed by the application of V_DETERMINE. Note that in this case, the application of V_DETERMINEswitched the resistance value of thelower memory structure654 fromR_RESET toR_SET. Thus, the process continues withblock712, where the resistance of thelower memory structure654 is switched back toR_RESET (e.g., by application of −V_RESET) so that the memory state of theresistance memory device110dis not disturbed by the present read process. Then the process ends atblock714 with a determination that the memory state of theresistance switching device110dis the memory state A.

FIGS. 27-29 show diagrams of the resistance switching characteristics of an embodiment of theresistance switching device110dsatisfying the above second set of conditions (2a) and (2b). More specifically,FIG. 27 shows the resistance switching characteristics of theupper memory structure652,FIG. 28 shows the resistance switching characteristics of thelower memory structure654, andFIG. 29 shows the overall resistance switching characteristics of theresistance switching device110daccording to the present embodiment.

As shown inFIG. 27, a positive voltage +V_RESETacross theupper memory structure652 will cause the resistance of theupper memory structure652 to switch to the resistance value associated with memory state R_RESET. A negative voltage −V_SETacross theupper memory structure652 will cause the resistance of theupper memory structure652 to switch to the resistance value associated with memory state R_SET.

As shown inFIG. 28, a positive voltage +V_SET across thelower memory structure654 will cause the resistance of thelower memory structure654 to switch to the resistance value associated with memory stateR_SET. A negative voltage −V_RESET across thelower memory structure654 will cause the resistance of thelower memory structure654 to switch to the resistance value associated with memory stateR_RESET.

The combination of the upper and

lower memory structures

652 and654 as shown inFIGS. 27 and 28 results in aresistance switching device110dcapable of four memory states A-D as shown inFIG. 29. Each of the memory states A-D is associated with a respective sum of resistances of the memory states of the upper and

lower memory structures

652 and654. The memory state A occurs when the resistance of theupper memory structure652 has the resistance associated with memory state R_SETand thelower memory structure654 has the resistance associated with memory stateR_RESET so that the overall resistance of theresistance switching device110dfor memory state A is R_SET+R_RESET. The memory state B occurs when the resistance of theupper memory structure652 has the resistance associated with memory state R_SETand thelower memory structure654 has the resistance associated with memory stateR_SET so that the overall resistance of theresistance switching device110dfor memory state B isR_SET+R_SET. The memory state C occurs when the resistance of theupper memory structure652 has the resistance associated with memory state R_RESETand thelower memory structure654 has the resistance associated with memory state RESET so that the overall resistance of theresistance switching device110dfor memory state C isR_RESET+R_RESET. The memory state D occurs when the resistance of theupper memory structure652 has the resistance associated with memory state R_RESETand thelower memory structure654 has the resistance associated with memory stateR_SET so that the overall resistance of theresistance switching device110dfor memory state D isR_SET+R_RESET. Thus, theresistance switching device110dcan be implemented as a four-state memory device having memory states A, B, C, and D.

A process for reading theresistance switching device110daccording to an embodiment as a four-state memory device satisfying the second set of conditions (2a) and (2b) is next described with reference toFIG. 30, which shows a flowchart of the reading process.

First, atblock800, theresistance switching device110dhas been programmed to one of the memory states A, B, C, or D. The remainder of the process will allow for reading theresistance switching device110din order to determine which of the memory states A-D was written to theresistance switching device110d.

Atblock802, the resistance of theresistance switching device110dis determined. The resistance of theresistance switching device110dcan be expected to one of the four resistance values associated with the memory states A-D, respectively. If the resistance value R=R_SET+R_SET is detected, the process ends atblock804 with a determination that the memory state of theresistance switching device110dis memory state B (R_SET+R_SET). If the resistance value R=R_RESET+R_RESET is detected, the process ends atblock805 with a determination that the memory state of theresistance switching device110dis memory state C (R_RESET+R_RESET).

In the present embodiment, the resistance associated with R_SETis substantially equal to the resistance associated withR_SET, and the resistance associated with R_RESETis substantially equal to the resistance associated withR_RESET. Thus, a third possibility atblock802 is that the resistance is R=R_RESET+R_SET=R_SET+R_RESET. If this third possibility occurs, then the process continues in order to distinguish between the memory states A (R_SET+R_RESET) and D (R_RESET+R_SET).

Next, at block806 a voltage V_DETERMINEis applied across theresistance switching device110d, and then atblock808 the resistance of theresistance switching device110dis measured. In this embodiment, a voltage for V_DETERMINEis selected that will cause theupper memory structure652 to switch from R_SETto R_RESETif the memory state is memory state A, but will not result in any change if the memory state is memory state D. Thus, the voltage of V_DETERMINEis a voltage between +V_RESETand +V_SET.

Atblock808, the resistance of theresistance switching device110dis again determined. If the detected resistance atblock808 is R=R_RESET+R_SET, it can be determined that the memory state is memory state D since the resistance value was not changed by the application of V_DETERMINE. Thus, the process ends atblock810 with a determination that the memory state of theresistance switching device110dis the memory state D. Otherwise, if the detected resistance atblock808 is R=R_RESET+R_RESET, it can be determined that the memory state is memory state A since the resistance value was changed by the application of V_DETERMINE. Note that in this case, the application of V_DETERMINEswitched the resistance value of theupper memory structure652 from R_SETto R_RESET. Thus, the process continues withblock812, where the resistance of theupper memory structure652 is switched back to R_SET(e.g., by application of −V_SET) so that the memory state of theresistance memory device110dis not disturbed by the present read process. Then the process ends atblock814 with a determination that the memory state of theresistance switching device110dis the memory state A.

FIG. 31 shows a flowchart of a process for reading a selected one of thememory cells102 shown inFIGS. 1-3. The process is described by way of example for readingmemory cell102dshown inFIG. 2; however, anymemory cell102 can be similarly read using the process described here and shown inFIG. 31.

In short, the reading process can include turning ontransistors112a-112cof thenon-selected memory cells102a-102c(block902), turning on the string select and ground select transistors SST and GST (block904), reading theresistance switching device110d(blocks906-910), and reading thetransistor112d(blocks912-914). Reading theresistance switching device110dcan include turning off thetransistor112dof the selectedmemory cell102d(block906), applying a voltage to the bit line BLi associated with the memory string MSi of the selectedmemory cell102d(block908), and measuring the resistance of theresistance switching device110dof the selectedmemory cell102d(block910). Reading thetransistor112dcan include applying a mid-range voltage (read gate voltage) to word line WL4 (block912) and determining whether the applied threshold voltage turned on thetransistor112d(block914).

Atblock900, the read procedure can be initiated for reading a selected memory cell, for example including the use of a read enable signal.

Atblock902, the word lines WL of the non-selected memory cells, i.e., word lines WL1-WL3, are activated so as to turn on thetransistors112a-112cof thenon-selected memory cells102a-102c. That is, word lines WL1-WL3 are pulled up above the threshold voltage Vt of thetransistors112a-112c. In embodiments where thetransistors112a-112care floating-gate transistors (or other transistors capable of being switched between multiple different threshold voltages Vt), the voltage applied to the word lines WL1-WL3 can be set to a high, but non-programming level voltage (a pass voltage). The application of the pass voltage to thetransistors112a-112callows thetransistors112a-112cto pass current in a manner that is unrestricted by their stored data values.

Atblock904, the string select transistor SST and ground select transistor GST are turned on by applying appropriate threshold voltages to the string select line SSL and ground select line GSL.

Atblock906, the transistor of the selected memory cell is turned off, i.e., the voltage of word line WL4 is set below the threshold voltage Vt of thetransistor112dofmemory cell102d. In embodiments where thetransistor112dis a floating-gate transistor (or other transistor capable of being switched between multiple different threshold voltages Vt), the voltage applied to the word line WL4 can be lower than the lowest of the multiple different threshold voltages so as to turn off thetransistor112d.

Atblock908, an appropriate read voltage is applied between the bit line BLi and the common source line SL, and the remaining bit lines can be floating or zero bias. Atblock910, the resistance of theresistance switching device110dis measured.

Blocks

908 and910 can include read processes described herein, for example as shown inFIGS. 7,11,17,21,26, and30, depending on the type of resistance switching device that is used asresistance switching device110d.

Atblock912, a mid-range voltage (read gate voltage) that is intermediate between the possible threshold voltages is applied to word line WL4. For example, in some embodiments, thetransistor112dcan be a floating-gate transistor capable of being programmed (e.g., logic state “0”) to a first effective threshold voltage V_t-programand erased (e.g., logic state “1”) to a second effective threshold voltage V_t-erase. Typically the program threshold voltage V_t-programwill be higher than the erase threshold voltage V_t-erase. The read gate voltage is selected to be between V_t-programand V_t-eraseso that thetransistor112dwill so turn on if erased (storing logical “1”) or will remain off if programmed (storing logical “0”).

Atblock914 the state of thetransistor112dis detected. Block914 can include applying an appropriate bias to the bit line BLi and detecting the impedance across the memory string MSi through thememory cell102d. If thetransistor112dis programmed, the intermediate-level read gate voltage applied to the gate of thetransistor112datblock912 will not be sufficient to turn on thetransistor112d. Thus, current will flow through theresistance switching device102dand so some increased amount of resistance (i.e., an amount of resistance that is greater than the pass-through resistance oftransistor112dwhen turned on) will be detected through thememory cell102d. On the other hand, if thetransistor112 is erased, the intermediate-level read gate voltage applied to the gate of thetransistor112datblock912 will be sufficient to turn on thetransistor112d. In this case, the current will pass through thetransistor112dsince thetransistor112dwill offer almost no resistance compared to that of theresistance switching device110d.

Atblock916 the read process ends with the data of theresistance switching device110dandtransistor112dhaving thus been read. Block916 can include removing voltages to the bit line BLi, word lines WL1-WL4, string select line SSL, and ground select line GSL.

FIG. 32 shows a flowchart of a process for programming a selected one of thememory cells102 shown inFIGS. 1-3. The process is described by way of example forprogramming memory cell102dshown inFIG. 2; however, anymemory cell102 can be similarly programmed using the process described here and shown inFIG. 32.

In short, the programming process can include turning ontransistors112a-112cof thenon-selected memory cells102a-102c(block952), turning on the string select and ground select transistors SST and GST (block954), programming theresistance switching device110d(blocks956-958), and programming thetransistor112d(blocks960-962). Programming theresistance switching device110dcan include turning off thetransistor112dof the selectedmemory cell102d(block956) and applying a program voltage to the bit line BLi associated with the memory string MSi of the selectedmemory cell102d(block958). Programming thetransistor112dcan include applying a programming gate voltage to word line WL4 (block960) and applying a program voltage to the bit line BLi (block962).

Atblock950, the programming procedure can be initiated for programming a selected memory cell, for example including the use of a write-enable signal.

Atblock952, the word lines WL of the non-selected memory cells, i.e., word lines WL1-WL3, are activated so as to turn on thetransistors112a-112cof thenon-selected memory cells102a-102c. That is, word lines WL1-WL3 are pulled up above the threshold voltage Vt of thetransistors112a-112c. In embodiments where thetransistors112a-112care floating-gate transistors (or other transistors capable of being switched between multiple different threshold voltages Vt), the voltage applied to the word lines WL1-WL3 can be set to a high, but non-programming level voltage (a pass voltage). The application of the pass voltage to thetransistors112a-112callows thetransistors112a-112cto pass current in a manner that is unrestricted by their stored data values.

Atblock954, the string select transistor SST and ground select transistor GST are turned on by applying appropriate threshold voltages to the string select line SSL and ground select line GSL.

Atblock956, the transistor of the selected memory cell is turned off, i.e., the voltage of word line WL4 is set below the threshold voltage Vt of thetransistor112dofmemory cell102d. In embodiments where thetransistor112dis a floating-gate transistor (or other transistor capable of being switched between multiple different threshold voltages Vt), the voltage applied to the word line WL4 can be lower than the lowest of the multiple different threshold voltages so as to turn off thetransistor112d.

Atblock958, an appropriate program voltage is applied between the bit line BLi and the common source line SL according to the data to be written to theresistance switching device110d. The bit line voltage is then removed before programming thetransistor112d.

Atblock960, the process of writing data to thetransistor112dbegins. The word lines WL of the non-selected memory cells, i.e., word lines WL1-WL3, remain activated.

An appropriate program voltage is applied between the bit line BLi and the common source line SL according to the data to be written to thetransistor112d. The bit line program voltage is selected to be a program voltage for writing a logical “0” to thetransistor112d, or a program-inhibit voltage for writing a logical “1” to thetransistor112d. For example, for programming, 0 volts can be applied to the bit line BLi. The string select line SSL is activated, and the ground select line GSL is deactivated.

Atblock962, thetransistor112dcan be programmed/erased using FN current. A high voltage (programming gate voltage) is applied to word line WL4 while 0 volts is applied to the non-selected word lines WL1-WL3. For example, in some embodiments, thetransistor112dcan be a floating-gate transistor capable of being programmed (e.g., logic state “0”) to a first effective threshold voltage V_t-programand erased (e.g., logic state “1”) to a second effective threshold voltage V_t-erase. Typically the program threshold voltage V_t-programwill be higher than the erase threshold voltage V_t-erase. For example, in some embodiments, a program voltage of 20 volts can be applied to thetransistor112din order to program thetransistor112d, while 0 volts is applied to the non-selected word lines WL1-WL3.

Atblock964 the programming process ends with the data of theresistance switching device110dandtransistor112dhaving thus been written. Block964 can include removing voltages to the bit line BLi, word lines WL1-WL4, string select line SSL, and ground select line GSL.

While various embodiments in accordance with the disclosed principles have been described above, it should be understood that they have been presented by way of example only, and are not limiting. Thus, the breadth and scope of the invention(s) should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.

Additionally, the section headings herein are provided for consistency with the suggestions under 37 C.F.R. 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically and by way of example, although the headings refer to a “Technical Field,” such claims should not be limited by the language chosen under this heading to describe the so-called technical field. Further, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Summary” to be considered as a characterization of the invention(s) set forth in issued claims. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings set forth herein.

Claims

1. A memory device comprising an array of memory cells, at least one of the memory cells comprising:

a transistor having a first terminal, a second terminal, and a gate terminal, the transistor being configured to be switchable between a plurality of different threshold voltages associated with respective memory states; and

a resistance switching device connected in parallel with the transistor such that the resistance switching device is connected to the first and second terminals of the transistor, the resistance switching device being configured to be switchable between a plurality of different resistances associated with respective memory states.

2. The memory device ofclaim 1, wherein the resistance switching device includes first and second interface regions having respective different resistance switching characteristics.

3. The memory device ofclaim 2, wherein at least one of the first and second interface regions includes at least a portion of a tungsten oxide layer.

4. The memory device ofclaim 2, wherein the resistance switching characteristics of the first interface region are symmetrical to the resistance switching characteristics of the second interface region.

5. The memory device ofclaim 2, wherein the resistance switching characteristics of the first interface region are asymmetrical to the resistance switching characteristics of the second interface region.

6. The memory device ofclaim 1, wherein the resistance switching device includes a first programmable metallization cell.

7. The memory device ofclaim 6, wherein the resistance switching device includes a second programmable metallization cell.

8. The memory device ofclaim 7, wherein the first programmable metallization cell includes a first solid electrolyte layer and the second programmable metallization cell includes a second solid electrolyte layer.

9. The memory device ofclaim 8, wherein the resistance switching device includes an oxidizable electrode layer disposed between the first and second solid electrolyte layers.

10. The memory device ofclaim 7, wherein the first programmable metallization cell and the second programmable metallization cell have respective different resistance switching characteristics.

11. The memory device ofclaim 10, wherein the resistance switching characteristics of the first programmable metallization cell are symmetrical to the resistance switching characteristics of the second programmable metallization cell.

12. The memory device ofclaim 10, wherein the resistance switching characteristics of the first programmable metallization cell are asymmetrical to the resistance switching characteristics of the second programmable metallization cell.

13. The memory device ofclaim 1, wherein the resistance switching device includes first and second memory structures.

14. The memory device ofclaim 13, wherein the first memory structure includes one of an RRAM, an MRAM, and an FRAM.

15. The memory device ofclaim 1, wherein the transistor includes a floating gate.

16. A memory device comprising:

a plurality of bit lines;

a plurality of word lines;

a first memory string comprising a first group of memory cells;

a second memory string comprising a second group of memory cells; and

a common source line connected to the first and second memory strings;

wherein the first and second memory strings are connected to respective bit lines;

wherein the word lines are connected to respective memory cells of the first group of memory cells and to respective memory cells of the second group of memory cells;

wherein the first group of memory cells includes a first memory cell connected between the common source line and a first bit line of the plurality of bit lines, the first memory cell comprising:

a first transistor having a first terminal, a second terminal, and a gate terminal, the first transistor being configured to be switchable between a plurality of different threshold voltages associated with respective memory states; and

a first resistance switching device connected in parallel with the first transistor such that the first resistance switching device is connected to the first and second terminals of the first transistor, the first resistance switching device being configured to be switchable between a plurality of different resistances associated with respective memory states.

17. The memory device ofclaim 16, wherein the gate terminal of the first transistor is connected to a first word line of the plurality of word lines.

18. The memory device ofclaim 16, wherein the first bit line and the common source line can be controlled for storing data to the first transistor and for storing data to the first resistance switching device.

19. The memory device ofclaim 16, wherein the first bit line and the common source line can be controlled for reading data from the first transistor and for reading data from the first resistance switching device.

20. The memory device ofclaim 16, wherein the first resistance switching device includes first and second interface regions having respective different resistance switching characteristics.

21. The memory device ofclaim 20, wherein at least one of the first and second interface regions includes at least a portion of a tungsten oxide layer.

22. The memory device ofclaim 16, wherein the first resistance switching device includes a first programmable metallization cell.

23. The memory device ofclaim 22, wherein the first resistance switching device includes a second programmable metallization cell.

24. The memory device ofclaim 23, wherein the first programmable metallization cell includes a first solid electrolyte layer and the second programmable metallization cell includes a second solid electrolyte layer.

25. The memory device ofclaim 16, wherein the first resistance switching device includes first and second memory structures.

26. The memory device ofclaim 25, wherein the first memory structure includes one of an RRAM, an MRAM, and an FRAM.

27. The memory device ofclaim 16, wherein the first transistor includes a floating gate.

28. The memory device ofclaim 16, wherein the second group of memory cells includes a second memory cell connected between the common source line and a second bit line of the plurality of bit lines, wherein the second memory cell comprises a second transistor and a second resistance switching device connected in parallel with the second transistor, wherein the second transistor is configured to be switchable between a plurality of different threshold voltages associated with respective memory states, and wherein the second resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

29. The memory device ofclaim 28, wherein the first group of memory cells includes a third memory cell connected between the common source line and the first bit line, wherein the third memory cell comprises a third transistor and a third resistance switching device connected in parallel with the third transistor, wherein the third transistor is configured to be switchable between a plurality of different threshold voltages associated with respective memory states, and wherein the third resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

30. The memory device ofclaim 29, wherein the second transistor is connected in series with the third transistor and the third resistance switching device, and wherein the second resistance switching device is connected in series with the third transistor and the third resistance switching device.

31. A method of reading a memory cell of a semiconductor memory device, the method comprising:

detecting a threshold voltage of a transistor of the memory cell, the transistor being configured to be switchable between a plurality of threshold voltages associated with respective memory states; and

detecting a resistance of a resistance switching device of the memory cell, the resistance switching device being connected in parallel with the transistor and being configured to be switchable between a plurality of resistances associated with respective memory states.

32. The method ofclaim 31, wherein the detecting of the threshold voltage of the transistor includes applying a first voltage to a gate terminal of the transistor and applying a second voltage across a source and drain of the transistor memory cell such that current flows through the resistance switching device if the first voltage is not sufficient to turn on the transistor.

33. The method ofclaim 31, wherein the detecting of the resistance of the resistance switching device includes turning off the transistor.

34. A method of programming a memory array, the memory array comprising a plurality word lines and a plurality bit lines, the method comprising:

applying a first voltage to the plurality of word lines except a selected word line; and

applying a second voltage to one selected bit line, wherein a memory element above the selected word line and coupled to the selected bit line is programmed.

35. The method ofclaim 34, wherein the memory element is one of first and second memory elements of a memory cell of the memory array.

36. The method ofclaim 35, wherein the first memory element comprises a resistance switching device.

37. The method ofclaim 36, wherein the second memory element comprises a transistor.

38. The method ofclaim 37, wherein the first and second memory elements are connected in parallel.